Unified Coverage Report :: Module :: prim_clock_gating

Module : prim_clock_gating

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_abstract_clock_gating_0/prim_clock_gating.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_passthrough.u_pt_sck_cg

---

Module Instance : tb.dut.u_passthrough.u_pt_sck_cg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	94.50	91.49		75.00	92.71	100.00	u_passthrough

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.