Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508123200	2890156	0	0
DataKnown_AKnownEnable	508123200	507991133	0	0
DepthKnown_A	508123200	507991133	0	0
RvalidKnown_A	508123200	507991133	0	0
WreadyKnown_A	508123200	507991133	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	2890156	0	0
T11	3501	1663	0	0
T13	2415	0	0	0
T14	4756	0	0	0
T15	51882	832	0	0
T16	16407	1663	0	0
T17	135126	0	0	0
T18	9552	832	0	0
T19	19411	832	0	0
T20	8263	832	0	0
T21	3098	0	0	0
T22	0	832	0	0
T23	0	1663	0	0
T24	0	832	0	0
T25	0	4218	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508123200	3319577	0	0
DataKnown_AKnownEnable	508123200	507991133	0	0
DepthKnown_A	508123200	507991133	0	0
RvalidKnown_A	508123200	507991133	0	0
WreadyKnown_A	508123200	507991133	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	3319577	0	0
T11	3501	832	0	0
T13	2415	0	0	0
T14	4756	0	0	0
T15	51882	832	0	0
T16	16407	832	0	0
T17	135126	0	0	0
T18	9552	2461	0	0
T19	19411	832	0	0
T20	8263	832	0	0
T21	3098	0	0	0
T22	0	832	0	0
T23	0	832	0	0
T24	0	832	0	0
T25	0	2112	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508123200	188937	0	0
DataKnown_AKnownEnable	508123200	507991133	0	0
DepthKnown_A	508123200	507991133	0	0
RvalidKnown_A	508123200	507991133	0	0
WreadyKnown_A	508123200	507991133	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	188937	0	0
T5	2209	14	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	0	0	0
T12	3439	0	0	0
T13	2415	0	0	0
T14	4756	1	0	0
T26	0	218	0	0
T41	0	64	0	0
T42	0	715	0	0
T43	0	1014	0	0
T46	0	483	0	0
T47	0	16	0	0
T48	0	386	0	0
T49	0	352	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508123200	457554	0	0
DataKnown_AKnownEnable	508123200	507991133	0	0
DepthKnown_A	508123200	507991133	0	0
RvalidKnown_A	508123200	507991133	0	0
WreadyKnown_A	508123200	507991133	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	457554	0	0
T5	2209	14	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	0	0	0
T12	3439	0	0	0
T13	2415	0	0	0
T14	4756	1	0	0
T26	0	218	0	0
T41	0	163	0	0
T42	0	715	0	0
T43	0	3137	0	0
T46	0	2188	0	0
T47	0	16	0	0
T48	0	386	0	0
T49	0	352	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508123200	6635385	0	0
DataKnown_AKnownEnable	508123200	507991133	0	0
DepthKnown_A	508123200	507991133	0	0
RvalidKnown_A	508123200	507991133	0	0
WreadyKnown_A	508123200	507991133	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	6635385	0	0
T1	9378	1	0	0
T2	1547	1	0	0
T3	1633	67	0	0
T4	4740	20	0	0
T5	2209	629	0	0
T6	1339	7	0	0
T7	1300	20	0	0
T8	1043	10	0	0
T9	1754	55	0	0
T10	2086	71	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508123200	14560582	0	0
DataKnown_AKnownEnable	508123200	507991133	0	0
DepthKnown_A	508123200	507991133	0	0
RvalidKnown_A	508123200	507991133	0	0
WreadyKnown_A	508123200	507991133	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	14560582	0	0
T1	9378	7	0	0
T2	1547	1	0	0
T3	1633	311	0	0
T4	4740	20	0	0
T5	2209	629	0	0
T6	1339	7	0	0
T7	1300	20	0	0
T8	1043	10	0	0
T9	1754	252	0	0
T10	2086	225	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508123200	507991133	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0