Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3529437	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4226572

1

T1

9

T3

1

T4

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4232537	1			T1	1		T2	77		T3	1
values[0x0]	1761217	1			T1	2		T4	22		T5	12
values[0x1]	1762255	1			T1	8		T4	15		T5	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2504170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5251839

1

T1

9

T2

30

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28370	1			T7	2		T9	8		T10	5
valid_sources[0x01]	28779	1			T7	5		T9	2		T10	7
valid_sources[0x02]	29843	1			T6	1		T7	4		T10	32
valid_sources[0x03]	28146	1			T2	3		T6	2		T7	3
valid_sources[0x04]	27201	1			T4	1		T7	1		T10	57
valid_sources[0x05]	31297	1			T2	3		T6	1		T7	6
valid_sources[0x06]	27477	1			T2	2		T7	2		T9	3
valid_sources[0x07]	29173	1			T6	1		T7	1		T10	17
valid_sources[0x08]	28156	1			T7	2		T9	14		T10	1
valid_sources[0x09]	29396	1			T6	2		T7	5		T9	4
valid_sources[0x0a]	26190	1			T7	2		T10	5		T11	1
valid_sources[0x0b]	30881	1			T6	1		T10	12		T12	13
valid_sources[0x0c]	31731	1			T6	4		T7	2		T9	5
valid_sources[0x0d]	28308	1			T1	1		T4	1		T6	3
valid_sources[0x0e]	27417	1			T6	10		T9	4		T10	47
valid_sources[0x0f]	30940	1			T6	3		T7	2		T9	12
valid_sources[0x10]	27719	1			T6	4		T7	7		T11	4
valid_sources[0x11]	30077	1			T6	4		T7	1		T9	22
valid_sources[0x12]	25840	1			T6	1		T7	3		T9	7
valid_sources[0x13]	27616	1			T4	1		T6	6		T7	2
valid_sources[0x14]	28181	1			T7	2		T9	5		T10	8
valid_sources[0x15]	27270	1			T2	1		T6	1		T7	1
valid_sources[0x16]	31018	1			T4	1		T7	4		T9	3
valid_sources[0x17]	29144	1			T6	3		T7	4		T10	5
valid_sources[0x18]	28314	1			T2	1		T7	5		T9	3
valid_sources[0x19]	34701	1			T6	1		T7	13		T9	1
valid_sources[0x1a]	30999	1			T2	3		T7	8		T9	1
valid_sources[0x1b]	28737	1			T6	1		T7	7		T9	4
valid_sources[0x1c]	32677	1			T6	1		T9	4		T10	6
valid_sources[0x1d]	31372	1			T2	1		T4	1		T6	2
valid_sources[0x1e]	31759	1			T6	4		T9	10		T10	5
valid_sources[0x1f]	30428	1			T7	1		T9	2		T10	19
valid_sources[0x20]	28526	1			T6	3		T7	3		T9	2
valid_sources[0x21]	28831	1			T7	3		T9	5		T10	11
valid_sources[0x22]	27691	1			T2	1		T4	1		T6	4
valid_sources[0x23]	28381	1			T6	6		T7	5		T9	10
valid_sources[0x24]	29924	1			T1	1		T2	1		T7	5
valid_sources[0x25]	28862	1			T6	2		T7	3		T9	3
valid_sources[0x26]	31968	1			T2	5		T7	3		T9	1
valid_sources[0x27]	28171	1			T6	1		T10	2		T11	6
valid_sources[0x28]	27880	1			T6	1		T7	3		T10	15
valid_sources[0x29]	27528	1			T7	1		T9	2		T10	3
valid_sources[0x2a]	33245	1			T6	1		T7	2		T9	1
valid_sources[0x2b]	26866	1			T2	1		T4	1		T6	6
valid_sources[0x2c]	30948	1			T6	3		T7	2		T9	2
valid_sources[0x2d]	31718	1			T6	5		T7	8		T10	9
valid_sources[0x2e]	28799	1			T6	2		T9	1		T11	16
valid_sources[0x2f]	27481	1			T6	5		T7	3		T12	6
valid_sources[0x30]	29782	1			T4	1		T7	1		T9	12
valid_sources[0x31]	33067	1			T2	1		T4	1		T7	1
valid_sources[0x32]	32208	1			T7	6		T9	8		T10	7
valid_sources[0x33]	48192	1			T6	3		T7	10		T9	8
valid_sources[0x34]	30036	1			T2	1		T7	15		T9	9
valid_sources[0x35]	29598	1			T6	2		T7	1		T9	7
valid_sources[0x36]	28230	1			T2	3		T7	8		T9	1
valid_sources[0x37]	38966	1			T7	3		T9	12		T10	4
valid_sources[0x38]	90373	1			T2	2		T6	5		T7	2
valid_sources[0x39]	30146	1			T7	3		T9	4		T10	6
valid_sources[0x3a]	29237	1			T4	1		T10	4		T11	9
valid_sources[0x3b]	28271	1			T2	1		T6	1		T7	2
valid_sources[0x3c]	31006	1			T2	1		T4	1		T6	7
valid_sources[0x3d]	28366	1			T2	2		T7	2		T9	1
valid_sources[0x3e]	29818	1			T7	1		T9	15		T10	2
valid_sources[0x3f]	31307	1			T7	5		T9	2		T11	8
valid_sources[0x40]	31793	1			T7	12		T11	1		T12	8
valid_sources[0x41]	32243	1			T5	20		T7	1		T10	18
valid_sources[0x42]	27765	1			T7	3		T9	2		T10	13
valid_sources[0x43]	28510	1			T7	1		T10	4		T11	2
valid_sources[0x44]	28426	1			T6	2		T7	1		T9	7
valid_sources[0x45]	31289	1			T9	2		T10	55		T11	5
valid_sources[0x46]	27307	1			T6	3		T7	6		T9	2
valid_sources[0x47]	28089	1			T9	2		T11	11		T12	7
valid_sources[0x48]	29416	1			T6	4		T7	7		T10	5
valid_sources[0x49]	29095	1			T6	3		T7	5		T10	39
valid_sources[0x4a]	29821	1			T4	1		T6	3		T7	1
valid_sources[0x4b]	31285	1			T6	1		T7	1		T10	3
valid_sources[0x4c]	35560	1			T2	1		T6	3		T7	4
valid_sources[0x4d]	28056	1			T9	2		T10	25		T11	2
valid_sources[0x4e]	46475	1			T4	1		T6	1		T7	13
valid_sources[0x4f]	27926	1			T6	3		T10	10		T11	4
valid_sources[0x50]	30977	1			T2	3		T6	3		T7	1
valid_sources[0x51]	28937	1			T1	1		T9	11		T10	4
valid_sources[0x52]	30293	1			T4	1		T6	4		T7	1
valid_sources[0x53]	27237	1			T2	4		T9	14		T11	5
valid_sources[0x54]	27771	1			T6	1		T7	5		T9	2
valid_sources[0x55]	29601	1			T2	1		T7	5		T9	3
valid_sources[0x56]	25691	1			T1	1		T9	6		T10	13
valid_sources[0x57]	29360	1			T7	2		T9	9		T11	11
valid_sources[0x58]	27398	1			T7	8		T9	2		T10	7
valid_sources[0x59]	43799	1			T4	1		T7	2		T9	4
valid_sources[0x5a]	28049	1			T9	6		T11	5		T12	14
valid_sources[0x5b]	29394	1			T4	1		T6	2		T7	2
valid_sources[0x5c]	27647	1			T2	1		T6	4		T7	2
valid_sources[0x5d]	32178	1			T6	7		T7	1		T9	3
valid_sources[0x5e]	31731	1			T6	3		T7	7		T10	1
valid_sources[0x5f]	29652	1			T9	7		T10	8		T11	5
valid_sources[0x60]	35023	1			T6	4		T7	3		T12	8
valid_sources[0x61]	30116	1			T6	3		T7	3		T9	1
valid_sources[0x62]	28174	1			T6	5		T7	1		T9	10
valid_sources[0x63]	28195	1			T7	3		T9	10		T10	26
valid_sources[0x64]	31981	1			T7	8		T9	2		T12	13
valid_sources[0x65]	29849	1			T2	2		T7	1		T9	4
valid_sources[0x66]	30378	1			T6	3		T7	2		T10	7
valid_sources[0x67]	31805	1			T7	2		T9	7		T10	2
valid_sources[0x68]	43433	1			T9	9		T11	2		T12	17
valid_sources[0x69]	26406	1			T7	1		T10	7		T11	3
valid_sources[0x6a]	27006	1			T6	1		T7	5		T9	1
valid_sources[0x6b]	28253	1			T7	1		T9	8		T11	4
valid_sources[0x6c]	26194	1			T6	1		T9	8		T10	53
valid_sources[0x6d]	25708	1			T6	2		T7	2		T9	2
valid_sources[0x6e]	27181	1			T6	4		T7	5		T9	3
valid_sources[0x6f]	27808	1			T2	1		T7	4		T9	4
valid_sources[0x70]	28778	1			T6	3		T7	3		T9	1
valid_sources[0x71]	29397	1			T6	2		T9	2		T10	7
valid_sources[0x72]	27591	1			T6	1		T7	3		T10	16
valid_sources[0x73]	39575	1			T9	7		T10	1		T11	2
valid_sources[0x74]	29389	1			T6	4		T7	10		T9	9
valid_sources[0x75]	29530	1			T9	5		T12	8		T13	10
valid_sources[0x76]	25751	1			T1	1		T7	2		T10	69
valid_sources[0x77]	27587	1			T2	1		T6	4		T7	6
valid_sources[0x78]	26788	1			T2	2		T7	3		T9	2
valid_sources[0x79]	27197	1			T6	1		T7	1		T9	9
valid_sources[0x7a]	27872	1			T7	7		T9	2		T11	2
valid_sources[0x7b]	29206	1			T1	1		T7	7		T9	12
valid_sources[0x7c]	26157	1			T4	1		T6	2		T7	2
valid_sources[0x7d]	27639	1			T4	1		T6	2		T7	3
valid_sources[0x7e]	28364	1			T7	1		T9	7		T10	2
valid_sources[0x7f]	26556	1			T9	2		T10	9		T12	12
valid_sources[0x80]	31638	1			T6	6		T7	3		T9	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1032238

1

T1

1

T3

1

T5

1

values[0x0]

all_enables

biggest_size

1609242

1

T1

2

T4

17

T5

9

values[0x1]

all_enables

biggest_size

1585092

1

T1

6

T4

11

T5

6