Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3555012

1

T1

2

T2

77

T4

10

full_word

4228161

1

T1

9

T3

1

T4

28

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7782763	1			T1	11		T2	77		T3	1
auto[TlIntgErrCmd]	146	1			T109	5		T110	10		T111	12
auto[TlIntgErrData]	152	1			T109	2		T110	11		T111	11
auto[TlIntgErrBoth]	112	1			T109	3		T110	9		T111	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4238006

1

T1

1

T2

77

T3

1

auto[1]

3545167

1

T1

10

T4

37

T5

19

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3205144	1			T2	77		T4	1		T6	413
auto[TlIntgErrNone]	partial	auto[1]	349484	1			T1	2		T4	9		T5	4
auto[TlIntgErrNone]	full_word	auto[0]	1032663	1			T1	1		T3	1		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	3195472	1			T1	8		T4	28		T5	15
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T109	2		T110	6		T111	5
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T109	3		T110	3		T111	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T163	1		T190	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T110	1		T111	2		T163	1
auto[TlIntgErrData]	partial	auto[0]	79	1			T109	1		T110	5		T111	8
auto[TlIntgErrData]	partial	auto[1]	62	1			T109	1		T110	4		T111	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T163	1		T191	1		T192	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T110	2		T111	1		T186	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T109	1		T110	2		T111	5
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T109	2		T110	6		T111	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T186	1		T193	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T110	1		T189	1		T194	1