Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.10	95.20	93.48	97.84		93.55	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	465548306	3631	0	0
addr_swap_data_rd_A	465548306	1985	0	0
addr_swap_mask_rd_A	465548306	1873	0	0
cfg_rd_A	465548306	2316	0	0
cmd_filter_0_rd_A	465548306	6601	0	0
cmd_filter_1_rd_A	465548306	5547	0	0
cmd_filter_2_rd_A	465548306	6472	0	0
cmd_filter_3_rd_A	465548306	6493	0	0
cmd_filter_4_rd_A	465548306	5407	0	0
cmd_filter_5_rd_A	465548306	7773	0	0
cmd_filter_6_rd_A	465548306	5052	0	0
cmd_filter_7_rd_A	465548306	5381	0	0
cmd_info_0_rd_A	465548306	3418	0	0
cmd_info_10_rd_A	465548306	3295	0	0
cmd_info_11_rd_A	465548306	3966	0	0
cmd_info_12_rd_A	465548306	3302	0	0
cmd_info_13_rd_A	465548306	3794	0	0
cmd_info_14_rd_A	465548306	3591	0	0
cmd_info_15_rd_A	465548306	3563	0	0
cmd_info_16_rd_A	465548306	3772	0	0
cmd_info_17_rd_A	465548306	3566	0	0
cmd_info_18_rd_A	465548306	3588	0	0
cmd_info_19_rd_A	465548306	3546	0	0
cmd_info_1_rd_A	465548306	3142	0	0
cmd_info_20_rd_A	465548306	3256	0	0
cmd_info_21_rd_A	465548306	3661	0	0
cmd_info_22_rd_A	465548306	3559	0	0
cmd_info_23_rd_A	465548306	3599	0	0
cmd_info_2_rd_A	465548306	3185	0	0
cmd_info_3_rd_A	465548306	3245	0	0
cmd_info_4_rd_A	465548306	3519	0	0
cmd_info_5_rd_A	465548306	3303	0	0
cmd_info_6_rd_A	465548306	3190	0	0
cmd_info_7_rd_A	465548306	4007	0	0
cmd_info_8_rd_A	465548306	3373	0	0
cmd_info_9_rd_A	465548306	3644	0	0
cmd_info_en4b_rd_A	465548306	2218	0	0
cmd_info_ex4b_rd_A	465548306	2051	0	0
cmd_info_wrdi_rd_A	465548306	2104	0	0
cmd_info_wren_rd_A	465548306	2060	0	0
intercept_en_rd_A	465548306	2596	0	0
intr_enable_rd_A	465548306	3612	0	0
jedec_cc_rd_A	465548306	2095	0	0
jedec_id_rd_A	465548306	2148	0	0
mailbox_addr_rd_A	465548306	1989	0	0
payload_swap_data_rd_A	465548306	2097	0	0
payload_swap_mask_rd_A	465548306	1939	0	0
read_threshold_rd_A	465548306	1958	0	0
tpm_access_0_rd_A	465548306	2467	0	0
tpm_access_1_rd_A	465548306	1938	0	0
tpm_cfg_rd_A	465548306	2314	0	0
tpm_did_vid_rd_A	465548306	2099	0	0
tpm_int_enable_rd_A	465548306	1771	0	0
tpm_int_status_rd_A	465548306	1990	0	0
tpm_int_vector_rd_A	465548306	1855	0	0
tpm_intf_capability_rd_A	465548306	1933	0	0
tpm_rid_rd_A	465548306	1951	0	0
tpm_sts_rd_A	465548306	1984	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3631	0	0
T86	15587	133	0	0
T87	3343	13	0	0
T88	5625	211	0	0
T110	28614	4	0	0
T111	28601	5	0	0
T112	20893	250	0	0
T114	19022	217	0	0
T121	5273	17	0	0
T122	13149	8	0	0
T124	14553	6	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1985	0	0
T122	13149	13	0	0
T124	14553	26	0	0
T127	7374	7	0	0
T134	3612	5	0	0
T135	270315	666	0	0
T136	10606	13	0	0
T153	6986	30	0	0
T154	14561	7	0	0
T161	3917	3	0	0
T162	5310	3	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1873	0	0
T122	13149	16	0	0
T124	14553	18	0	0
T127	7374	4	0	0
T134	3612	17	0	0
T135	270315	625	0	0
T136	10606	5	0	0
T153	6986	7	0	0
T154	14561	57	0	0
T161	3917	4	0	0
T162	5310	16	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2316	0	0
T122	13149	14	0	0
T124	14553	33	0	0
T127	7374	22	0	0
T134	3612	1	0	0
T135	270315	658	0	0
T136	10606	37	0	0
T154	14561	69	0	0
T161	3917	13	0	0
T163	34859	88	0	0
T164	9494	19	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	6601	0	0
T122	13149	232	0	0
T124	14553	162	0	0
T127	7374	2	0	0
T134	3612	13	0	0
T135	270315	756	0	0
T136	10606	256	0	0
T153	6986	51	0	0
T154	14561	68	0	0
T161	3917	4	0	0
T162	5310	9	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	5547	0	0
T122	13149	9	0	0
T124	14553	236	0	0
T127	7374	4	0	0
T134	3612	9	0	0
T135	270315	605	0	0
T136	10606	93	0	0
T153	6986	26	0	0
T154	14561	59	0	0
T161	3917	111	0	0
T162	5310	122	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	6472	0	0
T122	13149	19	0	0
T124	14553	126	0	0
T127	7374	143	0	0
T134	3612	8	0	0
T135	270315	674	0	0
T136	10606	230	0	0
T153	6986	25	0	0
T154	14561	30	0	0
T161	3917	126	0	0
T162	5310	158	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	6493	0	0
T122	13149	79	0	0
T124	14553	194	0	0
T127	7374	132	0	0
T134	3612	13	0	0
T135	270315	667	0	0
T136	10606	101	0	0
T154	14561	44	0	0
T161	3917	5	0	0
T162	5310	150	0	0
T163	34859	841	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	5407	0	0
T122	13149	86	0	0
T124	14553	250	0	0
T127	7374	117	0	0
T134	3612	8	0	0
T135	270315	643	0	0
T136	10606	109	0	0
T154	14561	65	0	0
T161	3917	4	0	0
T162	5310	11	0	0
T163	34859	589	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	7773	0	0
T116	18266	3	0	0
T122	13149	133	0	0
T124	14553	394	0	0
T127	7374	102	0	0
T134	3612	9	0	0
T135	270315	696	0	0
T136	10606	262	0	0
T153	6986	28	0	0
T154	14561	75	0	0
T161	3917	4	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	5052	0	0
T122	13149	9	0	0
T124	14553	21	0	0
T127	7374	225	0	0
T134	3612	6	0	0
T135	270315	706	0	0
T136	10606	203	0	0
T153	6986	12	0	0
T154	14561	36	0	0
T161	3917	128	0	0
T162	5310	8	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	5381	0	0
T122	13149	151	0	0
T124	14553	124	0	0
T127	7374	302	0	0
T135	270315	657	0	0
T136	10606	140	0	0
T153	6986	23	0	0
T154	14561	60	0	0
T161	3917	1	0	0
T162	5310	137	0	0
T163	34859	770	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3418	0	0
T122	13149	62	0	0
T124	14553	124	0	0
T127	7374	76	0	0
T134	3612	11	0	0
T135	270315	653	0	0
T136	10606	7	0	0
T153	6986	68	0	0
T154	14561	68	0	0
T161	3917	55	0	0
T162	5310	10	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3295	0	0
T122	13149	31	0	0
T124	14553	86	0	0
T134	3612	14	0	0
T135	270315	634	0	0
T136	10606	60	0	0
T153	6986	33	0	0
T154	14561	49	0	0
T161	3917	2	0	0
T162	5310	14	0	0
T163	34859	150	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3966	0	0
T122	13149	90	0	0
T124	14553	67	0	0
T127	7374	117	0	0
T134	3612	1	0	0
T135	270315	667	0	0
T136	10606	94	0	0
T153	6986	14	0	0
T154	14561	66	0	0
T161	3917	40	0	0
T162	5310	64	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3302	0	0
T122	13149	1	0	0
T124	14553	96	0	0
T127	7374	65	0	0
T134	3612	3	0	0
T135	270315	623	0	0
T136	10606	100	0	0
T153	6986	11	0	0
T154	14561	58	0	0
T161	3917	9	0	0
T162	5310	48	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3794	0	0
T122	13149	44	0	0
T124	14553	54	0	0
T127	7374	46	0	0
T134	3612	10	0	0
T135	270315	686	0	0
T136	10606	1	0	0
T153	6986	33	0	0
T154	14561	54	0	0
T161	3917	8	0	0
T162	5310	9	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3591	0	0
T122	13149	100	0	0
T124	14553	93	0	0
T127	7374	53	0	0
T134	3612	4	0	0
T135	270315	682	0	0
T136	10606	112	0	0
T153	6986	15	0	0
T154	14561	69	0	0
T161	3917	44	0	0
T162	5310	2	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3563	0	0
T122	13149	38	0	0
T124	14553	85	0	0
T127	7374	44	0	0
T134	3612	16	0	0
T135	270315	656	0	0
T136	10606	97	0	0
T153	6986	33	0	0
T154	14561	46	0	0
T161	3917	34	0	0
T162	5310	9	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3772	0	0
T122	13149	35	0	0
T124	14553	48	0	0
T127	7374	84	0	0
T135	270315	677	0	0
T136	10606	6	0	0
T153	6986	12	0	0
T154	14561	36	0	0
T161	3917	54	0	0
T162	5310	38	0	0
T163	34859	331	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3566	0	0
T122	13149	77	0	0
T124	14553	103	0	0
T127	7374	49	0	0
T134	3612	5	0	0
T135	270315	726	0	0
T136	10606	13	0	0
T153	6986	21	0	0
T154	14561	52	0	0
T161	3917	58	0	0
T162	5310	10	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3588	0	0
T122	13149	68	0	0
T124	14553	111	0	0
T127	7374	44	0	0
T134	3612	2	0	0
T135	270315	671	0	0
T136	10606	143	0	0
T154	14561	64	0	0
T161	3917	26	0	0
T162	5310	9	0	0
T163	34859	351	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3546	0	0
T122	13149	64	0	0
T124	14553	109	0	0
T127	7374	66	0	0
T134	3612	8	0	0
T135	270315	637	0	0
T136	10606	88	0	0
T153	6986	8	0	0
T154	14561	23	0	0
T161	3917	3	0	0
T162	5310	54	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3142	0	0
T122	13149	63	0	0
T124	14553	96	0	0
T127	7374	77	0	0
T134	3612	8	0	0
T135	270315	681	0	0
T136	10606	8	0	0
T153	6986	52	0	0
T154	14561	36	0	0
T161	3917	54	0	0
T162	5310	6	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3256	0	0
T122	13149	68	0	0
T124	14553	13	0	0
T127	7374	6	0	0
T134	3612	9	0	0
T135	270315	707	0	0
T136	10606	13	0	0
T153	6986	33	0	0
T154	14561	31	0	0
T161	3917	55	0	0
T162	5310	6	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3661	0	0
T122	13149	45	0	0
T124	14553	123	0	0
T127	7374	7	0	0
T134	3612	2	0	0
T135	270315	693	0	0
T136	10606	63	0	0
T153	6986	18	0	0
T154	14561	52	0	0
T161	3917	7	0	0
T162	5310	80	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3559	0	0
T122	13149	61	0	0
T124	14553	86	0	0
T127	7374	7	0	0
T134	3612	14	0	0
T135	270315	711	0	0
T136	10606	48	0	0
T153	6986	20	0	0
T154	14561	55	0	0
T161	3917	5	0	0
T162	5310	46	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3599	0	0
T122	13149	49	0	0
T124	14553	97	0	0
T127	7374	55	0	0
T134	3612	2	0	0
T135	270315	669	0	0
T136	10606	13	0	0
T153	6986	49	0	0
T154	14561	57	0	0
T161	3917	5	0	0
T162	5310	6	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3185	0	0
T122	13149	47	0	0
T124	14553	72	0	0
T127	7374	55	0	0
T134	3612	14	0	0
T135	270315	641	0	0
T136	10606	122	0	0
T153	6986	10	0	0
T154	14561	16	0	0
T161	3917	5	0	0
T162	5310	76	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3245	0	0
T122	13149	68	0	0
T124	14553	10	0	0
T127	7374	68	0	0
T134	3612	1	0	0
T135	270315	646	0	0
T136	10606	119	0	0
T153	6986	20	0	0
T154	14561	12	0	0
T162	5310	17	0	0
T163	34859	257	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3519	0	0
T122	13149	29	0	0
T124	14553	66	0	0
T127	7374	127	0	0
T134	3612	1	0	0
T135	270315	699	0	0
T136	10606	137	0	0
T153	6986	41	0	0
T154	14561	63	0	0
T161	3917	55	0	0
T162	5310	8	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3303	0	0
T122	13149	36	0	0
T124	14553	100	0	0
T127	7374	98	0	0
T135	270315	684	0	0
T136	10606	69	0	0
T153	6986	30	0	0
T154	14561	36	0	0
T161	3917	1	0	0
T162	5310	6	0	0
T163	34859	268	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3190	0	0
T122	13149	44	0	0
T124	14553	123	0	0
T127	7374	10	0	0
T134	3612	4	0	0
T135	270315	651	0	0
T136	10606	84	0	0
T153	6986	26	0	0
T154	14561	17	0	0
T162	5310	57	0	0
T163	34859	255	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	4007	0	0
T114	19022	4	0	0
T122	13149	53	0	0
T124	14553	114	0	0
T127	7374	2	0	0
T134	3612	1	0	0
T135	270315	703	0	0
T136	10606	116	0	0
T153	6986	64	0	0
T154	14561	12	0	0
T161	3917	2	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3373	0	0
T122	13149	10	0	0
T124	14553	81	0	0
T127	7374	43	0	0
T134	3612	5	0	0
T135	270315	683	0	0
T136	10606	15	0	0
T153	6986	3	0	0
T154	14561	56	0	0
T161	3917	32	0	0
T165	8885	9	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3644	0	0
T122	13149	55	0	0
T124	14553	106	0	0
T127	7374	45	0	0
T134	3612	10	0	0
T135	270315	725	0	0
T136	10606	82	0	0
T154	14561	17	0	0
T162	5310	6	0	0
T163	34859	254	0	0
T164	9494	98	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2218	0	0
T122	13149	35	0	0
T124	14553	39	0	0
T127	7374	2	0	0
T134	3612	10	0	0
T135	270315	717	0	0
T136	10606	15	0	0
T153	6986	7	0	0
T154	14561	58	0	0
T161	3917	5	0	0
T162	5310	12	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2051	0	0
T114	19022	3	0	0
T122	13149	14	0	0
T124	14553	30	0	0
T127	7374	22	0	0
T134	3612	13	0	0
T135	270315	660	0	0
T136	10606	8	0	0
T153	6986	9	0	0
T154	14561	20	0	0
T161	3917	1	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2104	0	0
T114	19022	8	0	0
T122	13149	20	0	0
T124	14553	39	0	0
T127	7374	7	0	0
T134	3612	12	0	0
T135	270315	673	0	0
T136	10606	13	0	0
T153	6986	21	0	0
T154	14561	37	0	0
T161	3917	2	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2060	0	0
T122	13149	17	0	0
T124	14553	27	0	0
T127	7374	28	0	0
T134	3612	1	0	0
T135	270315	682	0	0
T136	10606	22	0	0
T153	6986	44	0	0
T154	14561	37	0	0
T161	3917	5	0	0
T162	5310	15	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2596	0	0
T122	13149	17	0	0
T124	14553	30	0	0
T127	7374	20	0	0
T134	3612	9	0	0
T135	270315	650	0	0
T136	10606	44	0	0
T153	6986	37	0	0
T154	14561	148	0	0
T162	5310	10	0	0
T163	34859	113	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	3612	0	0
T22	921505	15	0	0
T29	9565	0	0	0
T34	0	13	0	0
T40	519564	0	0	0
T42	301549	0	0	0
T46	31317	0	0	0
T50	102682	0	0	0
T64	678948	0	0	0
T65	1520	0	0	0
T85	907	0	0	0
T166	0	60	0	0
T167	0	6	0	0
T168	0	37	0	0
T169	0	101	0	0
T170	0	22	0	0
T171	0	6	0	0
T172	0	13	0	0
T173	0	11	0	0
T174	1437	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2095	0	0
T122	13149	4	0	0
T124	14553	39	0	0
T127	7374	10	0	0
T134	3612	12	0	0
T135	270315	688	0	0
T136	10606	12	0	0
T153	6986	15	0	0
T154	14561	40	0	0
T162	5310	13	0	0
T163	34859	77	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2148	0	0
T122	13149	20	0	0
T124	14553	29	0	0
T127	7374	18	0	0
T134	3612	11	0	0
T135	270315	707	0	0
T136	10606	19	0	0
T154	14561	57	0	0
T161	3917	3	0	0
T162	5310	9	0	0
T163	34859	43	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1989	0	0
T122	13149	8	0	0
T124	14553	16	0	0
T127	7374	9	0	0
T134	3612	9	0	0
T135	270315	741	0	0
T136	10606	7	0	0
T153	6986	10	0	0
T154	14561	59	0	0
T161	3917	1	0	0
T162	5310	6	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2097	0	0
T122	13149	13	0	0
T124	14553	21	0	0
T127	7374	12	0	0
T134	3612	1	0	0
T135	270315	702	0	0
T136	10606	14	0	0
T153	6986	33	0	0
T154	14561	35	0	0
T161	3917	4	0	0
T162	5310	9	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1939	0	0
T122	13149	12	0	0
T124	14553	21	0	0
T127	7374	3	0	0
T134	3612	15	0	0
T135	270315	656	0	0
T136	10606	16	0	0
T153	6986	24	0	0
T154	14561	24	0	0
T161	3917	4	0	0
T162	5310	12	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1958	0	0
T122	13149	15	0	0
T124	14553	21	0	0
T127	7374	10	0	0
T134	3612	7	0	0
T135	270315	596	0	0
T136	10606	11	0	0
T153	6986	15	0	0
T154	14561	57	0	0
T161	3917	1	0	0
T162	5310	3	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2467	0	0
T122	13149	16	0	0
T124	14553	34	0	0
T127	7374	29	0	0
T134	3612	13	0	0
T135	270315	693	0	0
T136	10606	30	0	0
T153	6986	3	0	0
T154	14561	19	0	0
T161	3917	21	0	0
T162	5310	15	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1938	0	0
T122	13149	19	0	0
T124	14553	12	0	0
T127	7374	6	0	0
T134	3612	7	0	0
T135	270315	641	0	0
T136	10606	14	0	0
T153	6986	18	0	0
T154	14561	38	0	0
T161	3917	2	0	0
T162	5310	11	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2314	0	0
T122	13149	41	0	0
T124	14553	29	0	0
T127	7374	8	0	0
T134	3612	4	0	0
T135	270315	639	0	0
T136	10606	44	0	0
T153	6986	13	0	0
T154	14561	19	0	0
T161	3917	1	0	0
T162	5310	8	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	2099	0	0
T122	13149	10	0	0
T124	14553	18	0	0
T127	7374	18	0	0
T134	3612	4	0	0
T135	270315	610	0	0
T136	10606	26	0	0
T153	6986	15	0	0
T154	14561	57	0	0
T161	3917	11	0	0
T162	5310	4	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1771	0	0
T122	13149	13	0	0
T124	14553	24	0	0
T127	7374	13	0	0
T134	3612	2	0	0
T135	270315	595	0	0
T136	10606	14	0	0
T154	14561	29	0	0
T161	3917	4	0	0
T162	5310	5	0	0
T163	34859	29	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1990	0	0
T122	13149	15	0	0
T124	14553	21	0	0
T127	7374	11	0	0
T134	3612	6	0	0
T135	270315	705	0	0
T136	10606	4	0	0
T153	6986	26	0	0
T154	14561	19	0	0
T161	3917	4	0	0
T162	5310	3	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1855	0	0
T122	13149	12	0	0
T124	14553	14	0	0
T127	7374	9	0	0
T134	3612	6	0	0
T135	270315	642	0	0
T136	10606	6	0	0
T153	6986	23	0	0
T154	14561	23	0	0
T162	5310	16	0	0
T163	34859	42	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1933	0	0
T122	13149	11	0	0
T124	14553	33	0	0
T127	7374	8	0	0
T134	3612	4	0	0
T135	270315	660	0	0
T136	10606	15	0	0
T153	6986	24	0	0
T154	14561	35	0	0
T161	3917	5	0	0
T162	5310	10	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1951	0	0
T122	13149	7	0	0
T124	14553	26	0	0
T127	7374	10	0	0
T134	3612	9	0	0
T135	270315	671	0	0
T136	10606	9	0	0
T153	6986	4	0	0
T154	14561	45	0	0
T161	3917	3	0	0
T162	5310	9	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465548306	1984	0	0
T114	19022	3	0	0
T122	13149	16	0	0
T124	14553	19	0	0
T127	7374	11	0	0
T134	3612	13	0	0
T135	270315	691	0	0
T136	10606	16	0	0
T153	6986	14	0	0
T154	14561	78	0	0
T161	3917	5	0	0