Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2710782	1			T1	1		T2	1		T3	1
all_values[1]	2710782	1			T1	1		T2	1		T3	1
all_values[2]	2710782	1			T1	1		T2	1		T3	1
all_values[3]	2710782	1			T1	1		T2	1		T3	1
all_values[4]	2710782	1			T1	1		T2	1		T3	1
all_values[5]	2710782	1			T1	1		T2	1		T3	1
all_values[6]	2710782	1			T1	1		T2	1		T3	1
all_values[7]	2710782	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21171108

1

T1

8

T2

8

T3

8

auto[1]

515148

1

T21

60

T87

87

T33

74

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21656070

1

T1

8

T2

8

T3

8

auto[1]

30186

1

T21

153

T48

231

T63

468

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2661200	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	14406	1			T21	53		T48	91		T63	201
all_values[0]	auto[1]	auto[0]	34781	1			T21	3		T87	8		T33	3
all_values[0]	auto[1]	auto[1]	395	1			T21	3		T87	6		T33	2
all_values[1]	auto[0]	auto[0]	2621444	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	9115	1			T21	53		T48	85		T63	184
all_values[1]	auto[1]	auto[0]	79703	1			T21	4		T87	2		T33	11
all_values[1]	auto[1]	auto[1]	520	1			T21	5		T87	5		T33	6
all_values[2]	auto[0]	auto[0]	2615121	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3373	1			T21	2		T48	55		T63	83
all_values[2]	auto[1]	auto[0]	91853	1			T21	7		T87	7		T33	6
all_values[2]	auto[1]	auto[1]	435	1			T21	5		T87	7		T33	5
all_values[3]	auto[0]	auto[0]	2635517	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	201	1			T21	2		T87	6		T33	5
all_values[3]	auto[1]	auto[0]	74870	1			T21	5		T87	4		T33	5
all_values[3]	auto[1]	auto[1]	194	1			T21	4		T87	7		T33	4
all_values[4]	auto[0]	auto[0]	2643345	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	201	1			T21	5		T87	3		T33	7
all_values[4]	auto[1]	auto[0]	67026	1			T21	2		T87	10		T33	2
all_values[4]	auto[1]	auto[1]	210	1			T21	3		T87	4		T33	2
all_values[5]	auto[0]	auto[0]	2675551	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	171	1			T21	1		T87	5		T33	1
all_values[5]	auto[1]	auto[0]	34889	1			T21	3		T87	9		T33	11
all_values[5]	auto[1]	auto[1]	171	1			T21	6		T87	4		T33	3
all_values[6]	auto[0]	auto[0]	2662331	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	179	1			T21	3		T87	5		T33	3
all_values[6]	auto[1]	auto[0]	48061	1			T21	2		T87	6		T33	2
all_values[6]	auto[1]	auto[1]	211	1			T21	2		T87	2		T33	1
all_values[7]	auto[0]	auto[0]	2628747	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	206	1			T21	4		T87	7		T33	1
all_values[7]	auto[1]	auto[0]	81631	1			T21	4		T87	5		T33	6
all_values[7]	auto[1]	auto[1]	198	1			T21	2		T87	1		T33	5