Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2677279	1			T1	542		T2	1		T3	1
all_values[1]	2677279	1			T1	542		T2	1		T3	1
all_values[2]	2677279	1			T1	542		T2	1		T3	1
all_values[3]	2677279	1			T1	542		T2	1		T3	1
all_values[4]	2677279	1			T1	542		T2	1		T3	1
all_values[5]	2677279	1			T1	542		T2	1		T3	1
all_values[6]	2677279	1			T1	542		T2	1		T3	1
all_values[7]	2677279	1			T1	542		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20654215

1

T1

4336

T2

8

T3

8

auto[1]

764017

1

T37

27

T38

14448

T39

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21388784

1

T1

4336

T2

8

T3

8

auto[1]

29448

1

T129

3

T37

157

T209

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2577337	1			T1	542		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13464	1			T37	56		T44	14		T115	15
all_values[0]	auto[1]	auto[0]	85621	1			T37	1		T38	2		T40	5
all_values[0]	auto[1]	auto[1]	857	1			T37	1		T38	1		T39	5
all_values[1]	auto[0]	auto[0]	2599435	1			T1	542		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	9165	1			T37	54		T44	14		T115	15
all_values[1]	auto[1]	auto[0]	68142	1			T37	4		T38	1		T39	6
all_values[1]	auto[1]	auto[1]	537	1			T38	2		T39	2		T101	6
all_values[2]	auto[0]	auto[0]	2583718	1			T1	542		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3450	1			T37	36		T44	3		T69	25
all_values[2]	auto[1]	auto[0]	89868	1			T38	2		T101	9		T105	3
all_values[2]	auto[1]	auto[1]	243	1			T39	6		T101	1		T102	6
all_values[3]	auto[0]	auto[0]	2590793	1			T1	542		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	157	1			T129	3		T37	1		T209	2
all_values[3]	auto[1]	auto[0]	86152	1			T37	2		T38	4		T39	3
all_values[3]	auto[1]	auto[1]	177	1			T37	2		T39	3		T40	1
all_values[4]	auto[0]	auto[0]	2582633	1			T1	542		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	173	1			T38	4		T39	1		T101	3
all_values[4]	auto[1]	auto[0]	94290	1			T39	1		T40	7		T101	3
all_values[4]	auto[1]	auto[1]	183	1			T37	1		T38	2		T39	4
all_values[5]	auto[0]	auto[0]	2553229	1			T1	542		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	158	1			T37	1		T38	1		T39	3
all_values[5]	auto[1]	auto[0]	123723	1			T37	3		T38	7215		T39	10
all_values[5]	auto[1]	auto[1]	169	1			T37	1		T38	1		T39	3
all_values[6]	auto[0]	auto[0]	2540919	1			T1	542		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	190	1			T38	2		T39	4		T40	1
all_values[6]	auto[1]	auto[0]	135993	1			T37	4		T38	1		T39	2
all_values[6]	auto[1]	auto[1]	177	1			T37	2		T38	1		T39	4
all_values[7]	auto[0]	auto[0]	2599225	1			T1	542		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	169	1			T38	2		T39	5		T101	6
all_values[7]	auto[1]	auto[0]	77706	1			T37	4		T38	7212		T39	8
all_values[7]	auto[1]	auto[1]	179	1			T37	2		T38	4		T39	3