Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.InterceptLevel_M	0	0	155718586	0	0	0
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.SyncReqAckAckNeedsReq	0	0	155717645	0	0	0
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.SyncReqAckHoldReq	0	0	485027186	0	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	155717645	0	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	155717645	0	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	155717645	0	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	155717645	0	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.gen_assert_data_src2dst.SyncReqAckDataHoldSrc2Dst	0	0	485027186	0	0	0
tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	485027186	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	485027186	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	485027186	0	0	0
tb.dut.u_tlul2sram_egress.rvalidHighReqFifoEmpty	0	0	485027186	0	0	0
tb.dut.u_tlul2sram_egress.rvalidHighWhenRspFifoFull	0	0	485027186	0	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.DataKnown_A	0	0	485027186	0	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	485027186	0	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.DataKnown_A	0	0	485027186	0	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	485027186	0	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	155717645	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	155717645	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	155717645	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	155717645	0	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.DataKnown_A	0	0	155717645	0	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	155717645	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnownO_A	0	0	485027186	484937895	0	0
tb.dut.CioSdoEnOKnown	0	0	485027186	484937895	0	0
tb.dut.CioSdoEnOffWhenInactive	0	0	485027186	484937895	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	485027186	110	0	0
tb.dut.IntrReadbufFlipOKnown	0	0	485027186	484937895	0	0
tb.dut.IntrReadbufWatermarkOKnown	0	0	485027186	484937895	0	0
tb.dut.IntrTpmHeaderNotEmptyOKnown	0	0	485027186	484937895	0	0
tb.dut.IntrTpmRdfifoCmdEndOKnown	0	0	485027186	484937895	0	0
tb.dut.IntrTpmRdfifoDropOKnown	0	0	485027186	484937895	0	0
tb.dut.IntrUploadCmdfifoNotEmptyOKnown	0	0	485027186	484937895	0	0
tb.dut.IntrUploadPayloadNotEmptyOKnown	0	0	485027186	484937895	0	0
tb.dut.IntrUploadPayloadOverflowOKnown	0	0	485027186	484937895	0	0
tb.dut.PayloadStartIdxWidthMatch_A	0	0	956	956	0	0
tb.dut.SpiModeKnown_A	0	0	485027186	484937895	0	0
tb.dut.TpmEnableWhenTpmCsbIdle_M	0	0	485027186	350	0	0
tb.dut.g_sram_connect[0].ReqAlwaysAccepted_A	0	0	485027186	1942272	0	0
tb.dut.g_sram_connect[1].ReqAlwaysAccepted_A	0	0	485027186	182799	0	0
tb.dut.g_sram_connect[2].ReqAlwaysAccepted_A	0	0	485027186	2467	0	0
tb.dut.g_sram_connect[3].ReqAlwaysAccepted_A	0	0	485027186	1844	0	0
tb.dut.g_sram_connect[4].ReqAlwaysAccepted_A	0	0	485027186	193745	0	0
tb.dut.scanmodeKnown	0	0	485027186	485027186	0	0
tb.dut.spi_device_csr_assert.TlulOOBAddrErr_A	0	0	487100895	3290	0	0
tb.dut.spi_device_csr_assert.addr_swap_data_rd_A	0	0	487100895	1133	0	0
tb.dut.spi_device_csr_assert.addr_swap_mask_rd_A	0	0	487100895	1142	0	0
tb.dut.spi_device_csr_assert.cfg_rd_A	0	0	487100895	1600	0	0
tb.dut.spi_device_csr_assert.cmd_filter_0_rd_A	0	0	487100895	8695	0	0
tb.dut.spi_device_csr_assert.cmd_filter_1_rd_A	0	0	487100895	8682	0	0
tb.dut.spi_device_csr_assert.cmd_filter_2_rd_A	0	0	487100895	7930	0	0
tb.dut.spi_device_csr_assert.cmd_filter_3_rd_A	0	0	487100895	8792	0	0
tb.dut.spi_device_csr_assert.cmd_filter_4_rd_A	0	0	487100895	8671	0	0
tb.dut.spi_device_csr_assert.cmd_filter_5_rd_A	0	0	487100895	7737	0	0
tb.dut.spi_device_csr_assert.cmd_filter_6_rd_A	0	0	487100895	9036	0	0
tb.dut.spi_device_csr_assert.cmd_filter_7_rd_A	0	0	487100895	8129	0	0
tb.dut.spi_device_csr_assert.cmd_info_0_rd_A	0	0	487100895	3801	0	0
tb.dut.spi_device_csr_assert.cmd_info_10_rd_A	0	0	487100895	3574	0	0
tb.dut.spi_device_csr_assert.cmd_info_11_rd_A	0	0	487100895	3885	0	0
tb.dut.spi_device_csr_assert.cmd_info_12_rd_A	0	0	487100895	3838	0	0
tb.dut.spi_device_csr_assert.cmd_info_13_rd_A	0	0	487100895	3523	0	0
tb.dut.spi_device_csr_assert.cmd_info_14_rd_A	0	0	487100895	4259	0	0
tb.dut.spi_device_csr_assert.cmd_info_15_rd_A	0	0	487100895	4011	0	0
tb.dut.spi_device_csr_assert.cmd_info_16_rd_A	0	0	487100895	3954	0	0
tb.dut.spi_device_csr_assert.cmd_info_17_rd_A	0	0	487100895	4134	0	0
tb.dut.spi_device_csr_assert.cmd_info_18_rd_A	0	0	487100895	3967	0	0
tb.dut.spi_device_csr_assert.cmd_info_19_rd_A	0	0	487100895	3924	0	0
tb.dut.spi_device_csr_assert.cmd_info_1_rd_A	0	0	487100895	3937	0	0
tb.dut.spi_device_csr_assert.cmd_info_20_rd_A	0	0	487100895	3700	0	0
tb.dut.spi_device_csr_assert.cmd_info_21_rd_A	0	0	487100895	4184	0	0
tb.dut.spi_device_csr_assert.cmd_info_22_rd_A	0	0	487100895	4212	0	0
tb.dut.spi_device_csr_assert.cmd_info_23_rd_A	0	0	487100895	3778	0	0
tb.dut.spi_device_csr_assert.cmd_info_2_rd_A	0	0	487100895	3986	0	0
tb.dut.spi_device_csr_assert.cmd_info_3_rd_A	0	0	487100895	3931	0	0
tb.dut.spi_device_csr_assert.cmd_info_4_rd_A	0	0	487100895	3766	0	0
tb.dut.spi_device_csr_assert.cmd_info_5_rd_A	0	0	487100895	4087	0	0
tb.dut.spi_device_csr_assert.cmd_info_6_rd_A	0	0	487100895	3697	0	0
tb.dut.spi_device_csr_assert.cmd_info_7_rd_A	0	0	487100895	4202	0	0
tb.dut.spi_device_csr_assert.cmd_info_8_rd_A	0	0	487100895	3661	0	0
tb.dut.spi_device_csr_assert.cmd_info_9_rd_A	0	0	487100895	3837	0	0
tb.dut.spi_device_csr_assert.cmd_info_en4b_rd_A	0	0	487100895	1428	0	0
tb.dut.spi_device_csr_assert.cmd_info_ex4b_rd_A	0	0	487100895	1320	0	0
tb.dut.spi_device_csr_assert.cmd_info_wrdi_rd_A	0	0	487100895	1259	0	0
tb.dut.spi_device_csr_assert.cmd_info_wren_rd_A	0	0	487100895	1233	0	0
tb.dut.spi_device_csr_assert.intercept_en_rd_A	0	0	487100895	1796	0	0
tb.dut.spi_device_csr_assert.intr_enable_rd_A	0	0	487100895	3519	0	0
tb.dut.spi_device_csr_assert.jedec_cc_rd_A	0	0	487100895	1266	0	0
tb.dut.spi_device_csr_assert.jedec_id_rd_A	0	0	487100895	1222	0	0
tb.dut.spi_device_csr_assert.mailbox_addr_rd_A	0	0	487100895	1134	0	0
tb.dut.spi_device_csr_assert.payload_swap_data_rd_A	0	0	487100895	1044	0	0
tb.dut.spi_device_csr_assert.payload_swap_mask_rd_A	0	0	487100895	1098	0	0
tb.dut.spi_device_csr_assert.read_threshold_rd_A	0	0	487100895	1023	0	0
tb.dut.spi_device_csr_assert.tpm_access_0_rd_A	0	0	487100895	1780	0	0
tb.dut.spi_device_csr_assert.tpm_access_1_rd_A	0	0	487100895	1116	0	0
tb.dut.spi_device_csr_assert.tpm_cfg_rd_A	0	0	487100895	2209	0	0
tb.dut.spi_device_csr_assert.tpm_did_vid_rd_A	0	0	487100895	1282	0	0
tb.dut.spi_device_csr_assert.tpm_int_enable_rd_A	0	0	487100895	1004	0	0
tb.dut.spi_device_csr_assert.tpm_int_status_rd_A	0	0	487100895	1039	0	0
tb.dut.spi_device_csr_assert.tpm_int_vector_rd_A	0	0	487100895	1056	0	0
tb.dut.spi_device_csr_assert.tpm_intf_capability_rd_A	0	0	487100895	1107	0	0
tb.dut.spi_device_csr_assert.tpm_rid_rd_A	0	0	487100895	1079	0	0
tb.dut.spi_device_csr_assert.tpm_sts_rd_A	0	0	487100895	1067	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	487100895	9609395	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	487100895	486965968	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	487100895	486965968	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	487100895	16500373	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	487100895	486965968	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	487100895	486965968	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
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tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1131	1131	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	487101605	4859866	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	487100895	9072	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	487101605	6797119	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	487101605	9231476	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	487100895	6961	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	487101605	9609395	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	487101605	16500373	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	487101605	9609395	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	487101605	16500373	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	487101605	16500373	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	487101605	16500373	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	487100895	6622	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	487100895	6129	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1131	1131	0	0
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown0	0	0	66557	65601	0	0
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown0	0	0	155718586	155717630	0	0
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown1	0	0	155717645	155716838	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown0	0	0	155717645	155716838	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown0	0	0	155718586	155717630	0	0
tb.dut.u_cmdparse.CmdOnlySelDpKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_cmdparse.OnlyOneDatapath_A	0	0	155717645	64702	0	0
tb.dut.u_cmdparse.SelDpKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_cmdparse.StKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	64704	64089	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	65601	64930	0	0
tb.dut.u_flash_readbuf_flip_pulse_sync.DstPulseCheck_A	0	0	485027186	323	0	0
tb.dut.u_flash_readbuf_flip_pulse_sync.SrcPulseCheck_M	0	0	155717645	323	0	0
tb.dut.u_flash_readbuf_watermark_pulse_sync.DstPulseCheck_A	0	0	485027186	188	0	0
tb.dut.u_flash_readbuf_watermark_pulse_sync.SrcPulseCheck_M	0	0	155717645	188	0	0
tb.dut.u_intr_cmdfifo_not_empty.IntrTKind_A	0	0	956	956	0	0
tb.dut.u_intr_payload_not_empty.IntrTKind_A	0	0	956	956	0	0
tb.dut.u_intr_payload_overflow.IntrTKind_A	0	0	956	956	0	0
tb.dut.u_intr_readbuf_flip.IntrTKind_A	0	0	956	956	0	0
tb.dut.u_intr_readbuf_watermark.IntrTKind_A	0	0	956	956	0	0
tb.dut.u_intr_tpm_cmdaddr_notempty.IntrTKind_A	0	0	956	956	0	0
tb.dut.u_intr_tpm_rdfifo_cmd_end.IntrTKind_A	0	0	956	956	0	0
tb.dut.u_intr_tpm_rdfifo_drop.IntrTKind_A	0	0	956	956	0	0
tb.dut.u_jedec.JedecStKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_p2s.IoModeChangeValid_A	0	0	155718586	7813	0	0
tb.dut.u_p2s.IoModeDefault_A	0	0	155718586	20853	0	0
tb.dut.u_passthrough.PassThroughStKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_passthrough.PayloadSwapConstraint_M	0	0	155717645	2536144	0	0
tb.dut.u_readcmd.AddrIncNotAssertInAddressState_A	0	0	155717645	4818437	0	0
tb.dut.u_readcmd.MailboxSizeMatch_M	0	0	155717645	126037864	0	0
tb.dut.u_readcmd.ValidCmdConfig_A	0	0	155717645	217006	0	0
tb.dut.u_readcmd.u_readbuffer.StartWithAddressUpdate_A	0	0	155717645	8210	0	0
tb.dut.u_readcmd.u_readsram.AddrLatchedPulse_M	0	0	155717645	72880	0	0
tb.dut.u_readcmd.u_readsram.FifoNotEmpty_A	0	0	155717645	4818437	0	0
tb.dut.u_readcmd.u_readsram.NotOverflow_A	0	0	155717645	1214802	0	0
tb.dut.u_readcmd.u_readsram.ReqStrbRelation_M	0	0	155717645	8210	0	0
tb.dut.u_readcmd.u_readsram.SramDataReturnRequirement_M	0	0	155717645	1214298	0	0
tb.dut.u_readcmd.u_readsram.SramReadOnly_A	0	0	155717645	1214802	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.DataKnown_A	0	0	155717645	24325223	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.DepthKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.RvalidKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.WreadyKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	155717645	24325223	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A	0	0	155717645	23135051	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DepthKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.RvalidKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.WreadyKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	155717645	23135051	0	0
tb.dut.u_reg.en2addrHit	0	0	487100895	5843016	0	0
tb.dut.u_reg.reAfterRv	0	0	487100895	5843016	0	0
tb.dut.u_reg.rePulse	0	0	487100895	4243743	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1131	1131	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1131	1131	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1131	1131	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1131	1131	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1131	1131	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1131	1131	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1131	1131	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.NotOverflowed_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	487100895	9609395	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	487100895	16500373	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	487100895	2980511	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	487100895	3251292	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	487100895	200889	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	487100895	476139	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	487100895	6254429	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	487100895	12772942	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	487100895	486965968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1131	1131	0	0
tb.dut.u_reg.u_socket.maxN	0	0	1131	1131	0	0
tb.dut.u_reg.wePulse	0	0	487100895	1599273	0	0
tb.dut.u_s2p.IoModeDefault_A	0	0	155717645	20853	0	0
tb.dut.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	956	956	0	0
tb.dut.u_scanmode_sync.OutputsKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	485027186	484937895	0	0
tb.dut.u_spi_tpm.CmdAddrAvailable_A	0	0	155717645	49940	0	0
tb.dut.u_spi_tpm.CmdAddrBitCntInAddrSt_A	0	0	155717645	542136	0	0
tb.dut.u_spi_tpm.CmdAddrInfo_A	0	0	155717645	54196	0	0
tb.dut.u_spi_tpm.CmdPowerof2_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.DataFifoLessThan64_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.DataSelKnown_A	0	0	155718586	28290599	0	0
tb.dut.u_spi_tpm.HwRegCondition2_a	0	0	155717645	10946	0	0
tb.dut.u_spi_tpm.HwRegCondition_A	0	0	155717645	67767	0	0
tb.dut.u_spi_tpm.HwRegIdxKnown_A	0	0	155718586	28290599	0	0
tb.dut.u_spi_tpm.LocalityLatchCondition_A	0	0	155717645	67767	0	0
tb.dut.u_spi_tpm.RdFifoDepthPoT_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.RdFifoNumBytesPoT_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.RdPowerof2_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.SckFifoAddrLatchCondition_A	0	0	155717645	67767	0	0
tb.dut.u_spi_tpm.TpmRegSizeMatch_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.WrDepthSpec_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.WrFifoAvailable_A	0	0	155717645	430202	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	155717645	28290599	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	155717645	642375	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	155717645	642375	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	155717645	28290599	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	155717645	28290599	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	155717645	642375	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	155717645	642375	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	155717645	642375	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	155717645	642375	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	155717645	28290599	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	155717645	642375	0	0
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.DataKnown_A	0	0	155717645	193745	0	0
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.DepthKnown_A	0	0	155717645	28290599	0	0
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.RvalidKnown_A	0	0	155717645	28290599	0	0
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.WreadyKnown_A	0	0	155717645	28290599	0	0
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	155717645	193745	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayRptr_A	0	0	485027186	484936714	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayWptr_A	0	0	155717645	155716815	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.ParamCheckDepth_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.u_hw_reg_slice.ValidWidth_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.u_sram_fifo.DataKnown_A	0	0	155717645	6029907	0	0
tb.dut.u_spi_tpm.u_sram_fifo.DepthKnown_A	0	0	155717645	28290599	0	0
tb.dut.u_spi_tpm.u_sram_fifo.RvalidKnown_A	0	0	155717645	28290599	0	0
tb.dut.u_spi_tpm.u_sram_fifo.WreadyKnown_A	0	0	155717645	28290599	0	0
tb.dut.u_spi_tpm.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	155717645	6029907	0	0
tb.dut.u_spi_tpm.u_tpm_wr_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.u_tpm_wr_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A	0	0	956	956	0	0
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.SyncReqAckAckNeedsReq	0	0	155717645	83116	0	0
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.SyncReqAckHoldReq	0	0	485027186	79772	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.gen_assert_data_src2dst.SyncReqAckDataReg	0	0	956	956	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	155717645	633	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	485027186	633	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.CannotHaveEccAndParity_A	0	0	956	956	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.gen_byte_parity.ParityNeedsByteWriteMask_A	0	0	956	956	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.gen_byte_parity.WidthNeedsToBeByteAligned_A	0	0	956	956	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortA_A	0	0	155717645	1427043	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortA_A	0	0	155717645	1427043	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortA_A	0	0	155717645	1427043	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortA_A	0	0	155717645	1427043	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.CannotHaveEccAndParity_A	0	0	956	956	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.gen_byte_parity.ParityNeedsByteWriteMask_A	0	0	956	956	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.gen_byte_parity.WidthNeedsToBeByteAligned_A	0	0	956	956	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortA_A	0	0	485027186	2136017	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortA_A	0	0	485027186	2136017	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortA_A	0	0	485027186	2136017	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortA_A	0	0	485027186	2136017	0	0
tb.dut.u_spid_status.BusyBitZero_A	0	0	956	956	0	0
tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	1181	225	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.GrayRptr_A	0	0	155717645	155716815	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.GrayWptr_A	0	0	485027186	484936714	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.ParamCheckDepth_A	0	0	956	956	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	485027186	484937895	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	956	956	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	485027186	2323127	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	485027186	2323127	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	485027186	2323127	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	485027186	2323127	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	485027186	2323127	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	485027186	2323127	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	485027186	5	0	956
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	485027186	2323127	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.DataKnown_A	0	0	485027186	187110	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.DepthKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.RvalidKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.WreadyKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	485027186	187110	0	0
tb.dut.u_tlul2sram_egress.AddrOutKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.DataIntgOptions_A	0	0	956	956	0	0
tb.dut.u_tlul2sram_egress.ReqOutKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.SramDwHasByteGranularity_A	0	0	956	956	0	0
tb.dut.u_tlul2sram_egress.SramDwIsMultipleOfTlulWidth_A	0	0	956	956	0	0
tb.dut.u_tlul2sram_egress.TlOutKnownIfFifoKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.TlOutValidKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.WdataOutKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.WeOutKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.WmaskOutKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.adapterNoReadOrWrite	0	0	956	956	0	0
tb.dut.u_tlul2sram_egress.u_err.dataWidthOnly32_A	0	0	956	956	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.DataKnown_A	0	0	485027186	3215469	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.DepthKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.RvalidKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.WreadyKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	485027186	3215469	0	0
tb.dut.u_tlul2sram_egress.u_rsp_gen.DataWidthCheck_A	0	0	956	956	0	0
tb.dut.u_tlul2sram_egress.u_rsp_gen.PayLoadWidthCheck	0	0	956	956	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.DepthKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.RvalidKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.WreadyKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.u_sram_byte.SramReadbackAndIntg	0	0	956	956	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.DepthKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.RvalidKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.WreadyKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.AddrOutKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.DataIntgOptions_A	0	0	956	956	0	0
tb.dut.u_tlul2sram_ingress.ReqOutKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.SramDwHasByteGranularity_A	0	0	956	956	0	0
tb.dut.u_tlul2sram_ingress.SramDwIsMultipleOfTlulWidth_A	0	0	956	956	0	0
tb.dut.u_tlul2sram_ingress.TlOutKnownIfFifoKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.TlOutValidKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.WdataOutKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.WeOutKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.WmaskOutKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.adapterNoReadOrWrite	0	0	956	956	0	0
tb.dut.u_tlul2sram_ingress.rvalidHighReqFifoEmpty	0	0	485027186	182799	0	0
tb.dut.u_tlul2sram_ingress.rvalidHighWhenRspFifoFull	0	0	485027186	182799	0	0
tb.dut.u_tlul2sram_ingress.u_err.dataWidthOnly32_A	0	0	956	956	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.DataKnown_A	0	0	485027186	459062	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.DepthKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.RvalidKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.WreadyKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	485027186	459062	0	0
tb.dut.u_tlul2sram_ingress.u_rsp_gen.DataWidthCheck_A	0	0	956	956	0	0
tb.dut.u_tlul2sram_ingress.u_rsp_gen.PayLoadWidthCheck	0	0	956	956	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.DataKnown_A	0	0	485027186	459062	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.DepthKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.RvalidKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.WreadyKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	485027186	459062	0	0
tb.dut.u_tlul2sram_ingress.u_sram_byte.SramReadbackAndIntg	0	0	956	956	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.DataKnown_A	0	0	485027186	182799	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.DepthKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.RvalidKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.WreadyKnown_A	0	0	485027186	484937895	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	485027186	182799	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	68655	68278	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	68655	68278	0	0
tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	67770	67448	0	0
tb.dut.u_upload.AddrFifoNeverFull_M	0	0	155717645	1844	0	0
tb.dut.u_upload.CmdFifoNeverFull_M	0	0	155717645	2467	0	0
tb.dut.u_upload.CmdFifoPush_A	0	0	155717645	2467	0	0
tb.dut.u_upload.FifosOnlyOneValid_A	0	0	155717645	126037864	0	0
tb.dut.u_upload.PayloadNeverFull_M	0	0	155717645	992530	0	0
tb.dut.u_upload.u_addrfifo.MinDepth_A	0	0	956	956	0	0
tb.dut.u_upload.u_addrfifo.NoRAckInEmpty_A	0	0	485027186	1844	0	0
tb.dut.u_upload.u_addrfifo.NoWAckInFull_A	0	0	155717645	1844	0	0
tb.dut.u_upload.u_addrfifo.ParamCheckDepth_A	0	0	956	956	0	0
tb.dut.u_upload.u_addrfifo.RSramRvalidOneCycle_M	0	0	485027186	1844	0	0
tb.dut.u_upload.u_addrfifo.RptrGrayOneBitAtATime_A	0	0	485027186	1844	0	0
tb.dut.u_upload.u_addrfifo.RptrIncDataValid_A	0	0	485027186	1844	0	0
tb.dut.u_upload.u_addrfifo.RptrIncrease_A	0	0	485027186	1844	0	0
tb.dut.u_upload.u_addrfifo.SramRvalid_A	0	0	485027186	1844	0	0
tb.dut.u_upload.u_addrfifo.WSramRvalid_A	0	0	155717645	155717645	0	0
tb.dut.u_upload.u_addrfifo.WidthMatch_A	0	0	956	956	0	0
tb.dut.u_upload.u_addrfifo.WptrGrayOneBitAtATime_A	0	0	155717645	1844	0	0
tb.dut.u_upload.u_addrfifo.WptrIncrease_A	0	0	155717645	1844	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	155717645	126037864	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	956	956	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	155717645	996841	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	155717645	996841	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	155717645	996841	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	155717645	996841	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	155717645	996841	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	155717645	996841	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	155717645	996841	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.DepthKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.RvalidKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.WreadyKnown_A	0	0	155717645	126037864	0	0
tb.dut.u_upload.u_cmdfifo.MinDepth_A	0	0	956	956	0	0
tb.dut.u_upload.u_cmdfifo.NoRAckInEmpty_A	0	0	485027186	2467	0	0
tb.dut.u_upload.u_cmdfifo.NoWAckInFull_A	0	0	155717645	2467	0	0
tb.dut.u_upload.u_cmdfifo.ParamCheckDepth_A	0	0	956	956	0	0
tb.dut.u_upload.u_cmdfifo.RSramRvalidOneCycle_M	0	0	485027186	2467	0	0
tb.dut.u_upload.u_cmdfifo.RptrGrayOneBitAtATime_A	0	0	485027186	2467	0	0
tb.dut.u_upload.u_cmdfifo.RptrIncDataValid_A	0	0	485027186	2467	0	0
tb.dut.u_upload.u_cmdfifo.RptrIncrease_A	0	0	485027186	2467	0	0
tb.dut.u_upload.u_cmdfifo.SramRvalid_A	0	0	485027186	2467	0	0
tb.dut.u_upload.u_cmdfifo.WSramRvalid_A	0	0	155717645	155717645	0	0
tb.dut.u_upload.u_cmdfifo.WidthMatch_A	0	0	956	956	0	0
tb.dut.u_upload.u_cmdfifo.WptrGrayOneBitAtATime_A	0	0	155717645	2467	0	0
tb.dut.u_upload.u_cmdfifo.WptrIncrease_A	0	0	155717645	2467	0	0
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	0	0	956	956	0	0
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A	0	0	956	956	0	0
tb.dut.u_upload.u_payloadptr_clr_psync.DstPulseCheck_A	0	0	485027186	2467	0	0
tb.dut.u_upload.u_payloadptr_clr_psync.SrcPulseCheck_M	0	0	155717645	2467	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	485027186	5	0	956

Assertions Without Attempts:

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	487101605	78061	78061	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	487101605	1287	1287	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	487101605	1357	1357	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	487101605	901	901	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	487101605	193	193	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	487101605	719	719	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	487101605	563	563	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	487101605	21187	21187	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	487101605	1091422	1091422	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	487101605	3737210	3737210	1111

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	487101605	78061	78061	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	487101605	1287	1287	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	487101605	1357	1357	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	487101605	901	901	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	487101605	193	193	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	487101605	719	719	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	487101605	563	563	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	487101605	21187	21187	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	487101605	1091422	1091422	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	487101605	3737210	3737210	1111

	ASSERT	PROPERTIES	SEQUENCES
Total	693	0	10
Category 0	693	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	693	0	10
Severity 0	693	0	10

	NUMBER	PERCENT
Total Number	693	100.00
Uncovered	32	4.62
Success	661	95.38
Failure	0	0.00
Incomplete	1	0.14
Without Attempts	9	1.30

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	0	0.00
All Matches	10	100.00
First Matches	10	100.00