Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.74 98.65 96.80 99.01 89.36 98.51 95.57 99.26


Total tests in report: 1131
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
65.40 65.40 92.12 92.12 82.26 82.26 80.43 80.43 28.89 28.89 89.72 89.72 72.34 72.34 12.03 12.03 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2357482345
83.22 17.83 97.32 5.21 93.07 10.81 87.85 7.41 82.22 53.33 96.95 7.22 85.06 12.72 40.10 28.07 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.786166724
86.53 3.30 97.69 0.36 93.43 0.36 88.34 0.49 93.33 11.11 97.36 0.41 85.20 0.14 50.35 10.25 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.773218858
88.54 2.01 98.12 0.44 93.57 0.14 89.92 1.58 93.33 0.00 97.67 0.31 85.20 0.00 61.98 11.63 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.1903094891
90.12 1.58 98.12 0.00 93.75 0.18 90.71 0.79 93.33 0.00 97.70 0.03 93.50 8.30 63.71 1.73 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1120474996
91.22 1.10 98.12 0.00 93.75 0.00 90.71 0.00 93.33 0.00 97.70 0.00 93.50 0.00 71.44 7.72 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1076213763
91.98 0.75 98.12 0.00 94.77 1.02 90.71 0.00 93.33 0.00 97.70 0.00 93.50 0.00 75.69 4.26 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.313916303
92.66 0.68 98.15 0.03 94.77 0.00 95.45 4.74 93.33 0.00 97.72 0.02 93.50 0.00 75.69 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.2753462080
93.24 0.58 98.18 0.03 94.83 0.05 95.45 0.00 93.33 0.00 97.80 0.09 93.50 0.00 79.55 3.86 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3836266102
93.69 0.45 98.44 0.26 95.27 0.45 97.04 1.58 93.33 0.00 98.22 0.41 93.50 0.00 80.00 0.45 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1315468503
94.09 0.40 98.44 0.00 95.27 0.00 97.04 0.00 93.33 0.00 98.22 0.00 93.50 0.00 82.82 2.82 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.660252095
94.41 0.33 98.44 0.00 95.27 0.00 97.04 0.00 93.33 0.00 98.22 0.00 93.50 0.00 85.10 2.28 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.2015453408
94.73 0.32 98.45 0.01 95.31 0.04 98.81 1.78 93.33 0.00 98.23 0.02 93.64 0.14 85.35 0.25 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.3446634546
95.01 0.27 98.45 0.00 95.31 0.00 98.81 0.00 93.33 0.00 98.23 0.00 93.78 0.14 87.13 1.78 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.367624369
95.22 0.22 98.56 0.11 95.66 0.35 98.81 0.00 93.33 0.00 98.39 0.15 94.33 0.55 87.48 0.35 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.1360418388
95.43 0.21 98.56 0.00 95.68 0.03 98.81 0.00 93.33 0.00 98.40 0.02 94.33 0.00 88.91 1.44 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.3157493898
95.60 0.17 98.56 0.00 95.68 0.00 98.81 0.00 93.33 0.00 98.40 0.00 94.33 0.00 90.10 1.19 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1496234044
95.77 0.16 98.59 0.03 95.71 0.03 98.81 0.00 93.33 0.00 98.46 0.05 94.33 0.00 91.14 1.04 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.361160609
95.93 0.16 98.60 0.01 95.80 0.09 98.81 0.00 93.33 0.00 98.47 0.02 94.33 0.00 92.13 0.99 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.675092746
96.06 0.14 98.60 0.00 95.80 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.30 0.97 92.13 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3540013361
96.18 0.11 98.60 0.00 95.80 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.30 0.00 92.92 0.79 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2018764266
96.28 0.11 98.60 0.00 95.82 0.03 98.81 0.00 93.33 0.00 98.49 0.02 95.30 0.00 93.61 0.69 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.468179374
96.38 0.10 98.60 0.00 96.52 0.69 98.81 0.00 93.33 0.00 98.49 0.00 95.30 0.00 93.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1472552744
96.48 0.10 98.60 0.00 96.52 0.00 98.81 0.00 93.33 0.00 98.49 0.00 95.57 0.28 94.01 0.40 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1803671052
96.56 0.08 98.60 0.00 96.52 0.00 98.81 0.00 93.33 0.00 98.49 0.00 95.57 0.00 94.60 0.59 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.1609553604
96.64 0.08 98.60 0.00 96.52 0.00 98.81 0.00 93.33 0.00 98.49 0.00 95.57 0.00 95.15 0.54 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2908635148
96.70 0.06 98.60 0.00 96.52 0.00 98.81 0.00 93.33 0.00 98.49 0.00 95.57 0.00 95.59 0.45 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3859489106
96.76 0.06 98.60 0.00 96.52 0.00 98.81 0.00 93.33 0.00 98.49 0.00 95.57 0.00 95.99 0.40 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1985386313
96.82 0.06 98.60 0.00 96.52 0.00 98.81 0.00 93.33 0.00 98.49 0.00 95.57 0.00 96.39 0.40 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.252855034
96.87 0.05 98.60 0.00 96.52 0.00 98.81 0.00 93.33 0.00 98.49 0.00 95.57 0.00 96.73 0.35 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.4161263168
96.91 0.04 98.60 0.00 96.52 0.00 98.81 0.00 93.33 0.00 98.49 0.00 95.57 0.00 97.03 0.30 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.115071640
96.95 0.04 98.60 0.00 96.66 0.14 98.81 0.00 93.33 0.00 98.49 0.00 95.57 0.00 97.18 0.15 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.541392192
96.99 0.04 98.61 0.01 96.67 0.01 98.81 0.00 93.33 0.00 98.49 0.00 95.57 0.00 97.43 0.25 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1439724407
97.03 0.04 98.64 0.03 96.71 0.04 99.01 0.20 93.33 0.00 98.49 0.00 95.57 0.00 97.43 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.2659141861
97.06 0.03 98.64 0.00 96.73 0.03 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 97.62 0.20 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.193929019
97.09 0.03 98.64 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 97.82 0.20 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3842754283
97.11 0.02 98.64 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 97.97 0.15 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.494057643
97.13 0.02 98.64 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.12 0.15 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1896300757
97.14 0.01 98.64 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.22 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.192309652
97.16 0.01 98.64 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.32 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.2925602248
97.17 0.01 98.64 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.42 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.831243741
97.19 0.01 98.64 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.1492668475
97.20 0.01 98.64 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.159307880
97.21 0.01 98.64 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3274401980
97.23 0.01 98.64 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.81 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.4251693871
97.24 0.01 98.64 0.00 96.75 0.01 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.2478262731
97.24 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.1120402146
97.25 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.1072612923
97.26 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.1975802113
97.26 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.245481301
97.27 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.1872330893
97.28 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1523514149
97.29 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2448068568
97.29 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.1747798974
97.30 0.01 98.65 0.01 96.76 0.01 99.01 0.00 93.33 0.00 98.51 0.02 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.893746429
97.30 0.01 98.65 0.00 96.79 0.03 99.01 0.00 93.33 0.00 98.51 0.00 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3280587610
97.30 0.01 98.65 0.00 96.80 0.01 99.01 0.00 93.33 0.00 98.51 0.00 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.994360018

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2776883317
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2378503189
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.640525617
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2558261070
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2030634697
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2140667453
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2290298584
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.382797254
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.275268290
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.1696938994
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3599867104
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1061879621
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4219776429
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3904482466
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.927936055
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1136060874
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1537303142
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3225868190
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2914787312
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4176467095
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1666498404
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1624365019
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.374876319
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.366493779
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1834355427
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.4205431707
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.134481310
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.952477741
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/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.710262480
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/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.1804413846



Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.852612089 Oct 15 05:55:31 AM UTC 24 Oct 15 05:55:33 AM UTC 24 43962763 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.2753462080 Oct 15 05:55:37 AM UTC 24 Oct 15 05:55:40 AM UTC 24 72033331 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2235040263 Oct 15 05:55:40 AM UTC 24 Oct 15 05:55:43 AM UTC 24 32617312 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.4063704814 Oct 15 05:55:44 AM UTC 24 Oct 15 05:55:48 AM UTC 24 291102237 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.193929019 Oct 15 05:55:37 AM UTC 24 Oct 15 05:55:49 AM UTC 24 2447963324 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.612508102 Oct 15 05:55:42 AM UTC 24 Oct 15 05:55:50 AM UTC 24 213775432 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.893746429 Oct 15 05:55:50 AM UTC 24 Oct 15 05:56:00 AM UTC 24 233857766 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2357482345 Oct 15 05:55:49 AM UTC 24 Oct 15 05:56:02 AM UTC 24 4050200550 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.295611563 Oct 15 05:56:03 AM UTC 24 Oct 15 05:56:10 AM UTC 24 1068739209 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.743585184 Oct 15 05:56:09 AM UTC 24 Oct 15 05:56:15 AM UTC 24 217812941 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.4046627722 Oct 15 05:55:51 AM UTC 24 Oct 15 05:56:25 AM UTC 24 16301333777 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.1903094891 Oct 15 05:55:40 AM UTC 24 Oct 15 05:56:44 AM UTC 24 5180923362 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.42796440 Oct 15 05:56:00 AM UTC 24 Oct 15 05:56:45 AM UTC 24 7450697224 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3774072094 Oct 15 05:56:15 AM UTC 24 Oct 15 05:56:46 AM UTC 24 3844561763 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.3446634546 Oct 15 05:56:46 AM UTC 24 Oct 15 05:56:49 AM UTC 24 328678649 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2030304395 Oct 15 05:56:47 AM UTC 24 Oct 15 05:56:49 AM UTC 24 13006056 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.993101044 Oct 15 05:56:47 AM UTC 24 Oct 15 05:56:49 AM UTC 24 20873580 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3513913211 Oct 15 05:56:53 AM UTC 24 Oct 15 05:56:56 AM UTC 24 37917791 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.215656118 Oct 15 05:56:55 AM UTC 24 Oct 15 05:56:57 AM UTC 24 10866247 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.2705450620 Oct 15 05:56:57 AM UTC 24 Oct 15 05:57:04 AM UTC 24 2092225783 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.2642073335 Oct 15 05:57:05 AM UTC 24 Oct 15 05:57:13 AM UTC 24 747431893 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.2616131027 Oct 15 05:56:50 AM UTC 24 Oct 15 05:57:15 AM UTC 24 2072877873 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1315468503 Oct 15 05:57:15 AM UTC 24 Oct 15 05:57:21 AM UTC 24 291210260 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.2164617557 Oct 15 05:57:14 AM UTC 24 Oct 15 05:57:24 AM UTC 24 812358095 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3000814977 Oct 15 05:56:58 AM UTC 24 Oct 15 05:57:31 AM UTC 24 23410548708 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3667812048 Oct 15 05:57:25 AM UTC 24 Oct 15 05:57:35 AM UTC 24 613951737 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.1153609767 Oct 15 05:57:22 AM UTC 24 Oct 15 05:57:36 AM UTC 24 1733374501 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3465499895 Oct 15 05:57:24 AM UTC 24 Oct 15 05:57:38 AM UTC 24 3101607711 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.3092178585 Oct 15 05:57:37 AM UTC 24 Oct 15 05:57:40 AM UTC 24 733414910 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.786166724 Oct 15 05:56:45 AM UTC 24 Oct 15 05:57:41 AM UTC 24 6387000716 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.2659141861 Oct 15 05:57:39 AM UTC 24 Oct 15 05:57:41 AM UTC 24 14014411 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1437065833 Oct 15 05:56:50 AM UTC 24 Oct 15 05:57:42 AM UTC 24 8948424851 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.1362462051 Oct 15 05:57:41 AM UTC 24 Oct 15 05:57:43 AM UTC 24 15096698 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2767388003 Oct 15 05:57:44 AM UTC 24 Oct 15 05:57:47 AM UTC 24 39988538 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3122870702 Oct 15 05:57:46 AM UTC 24 Oct 15 05:57:48 AM UTC 24 155918199 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2791673246 Oct 15 05:57:42 AM UTC 24 Oct 15 05:57:51 AM UTC 24 3120123950 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1439724407 Oct 15 05:56:11 AM UTC 24 Oct 15 05:57:52 AM UTC 24 6183438686 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.866549693 Oct 15 05:57:10 AM UTC 24 Oct 15 05:57:53 AM UTC 24 2031969338 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2510572328 Oct 15 05:57:48 AM UTC 24 Oct 15 05:57:55 AM UTC 24 287818674 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.1061955641 Oct 15 05:57:53 AM UTC 24 Oct 15 05:57:58 AM UTC 24 735578364 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.152993352 Oct 15 05:57:53 AM UTC 24 Oct 15 05:58:01 AM UTC 24 3251979000 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.688806804 Oct 15 05:57:56 AM UTC 24 Oct 15 05:58:01 AM UTC 24 119090715 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3509325458 Oct 15 05:57:43 AM UTC 24 Oct 15 05:58:02 AM UTC 24 3231776337 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.3478489351 Oct 15 05:57:52 AM UTC 24 Oct 15 05:58:06 AM UTC 24 6316689968 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.1629265217 Oct 15 05:57:48 AM UTC 24 Oct 15 05:58:07 AM UTC 24 5462700777 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.551401127 Oct 15 05:57:49 AM UTC 24 Oct 15 05:58:13 AM UTC 24 2885273667 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.915868220 Oct 15 05:58:11 AM UTC 24 Oct 15 05:58:13 AM UTC 24 132690100 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2879964779 Oct 15 05:58:01 AM UTC 24 Oct 15 05:58:15 AM UTC 24 589114811 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1798756643 Oct 15 05:58:14 AM UTC 24 Oct 15 05:58:16 AM UTC 24 76503591 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.745686860 Oct 15 05:58:14 AM UTC 24 Oct 15 05:58:16 AM UTC 24 34382273 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.484985021 Oct 15 05:58:19 AM UTC 24 Oct 15 05:58:22 AM UTC 24 51282224 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.1812085356 Oct 15 05:58:20 AM UTC 24 Oct 15 05:58:26 AM UTC 24 821657399 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.3600365976 Oct 15 05:58:17 AM UTC 24 Oct 15 05:58:28 AM UTC 24 2204679233 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.824432408 Oct 15 05:58:29 AM UTC 24 Oct 15 05:58:33 AM UTC 24 65430847 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2821427854 Oct 15 05:58:23 AM UTC 24 Oct 15 05:58:36 AM UTC 24 1036323989 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.794863758 Oct 15 05:58:27 AM UTC 24 Oct 15 05:58:38 AM UTC 24 1717585286 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2312472207 Oct 15 05:57:32 AM UTC 24 Oct 15 05:58:42 AM UTC 24 10494329082 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1464424060 Oct 15 05:58:17 AM UTC 24 Oct 15 05:58:46 AM UTC 24 12181972072 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.1952107828 Oct 15 05:58:39 AM UTC 24 Oct 15 05:58:47 AM UTC 24 2012689479 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1166733510 Oct 15 05:58:37 AM UTC 24 Oct 15 05:58:48 AM UTC 24 442260197 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.101194744 Oct 15 05:58:34 AM UTC 24 Oct 15 05:58:52 AM UTC 24 2232511615 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2318751166 Oct 15 05:58:47 AM UTC 24 Oct 15 05:58:55 AM UTC 24 183078324 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.1525275834 Oct 15 05:58:56 AM UTC 24 Oct 15 05:58:59 AM UTC 24 118289948 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.152643354 Oct 15 05:59:00 AM UTC 24 Oct 15 05:59:02 AM UTC 24 25030662 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.264897266 Oct 15 05:59:00 AM UTC 24 Oct 15 05:59:02 AM UTC 24 40096680 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1985386313 Oct 15 05:56:34 AM UTC 24 Oct 15 05:59:05 AM UTC 24 7020408178 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2807559733 Oct 15 05:59:06 AM UTC 24 Oct 15 05:59:09 AM UTC 24 199491111 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.895114962 Oct 15 05:59:03 AM UTC 24 Oct 15 05:59:12 AM UTC 24 1630772064 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.3607162061 Oct 15 05:59:09 AM UTC 24 Oct 15 05:59:13 AM UTC 24 77684265 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1690147335 Oct 15 05:58:02 AM UTC 24 Oct 15 05:59:15 AM UTC 24 12831014262 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2923095313 Oct 15 05:59:14 AM UTC 24 Oct 15 05:59:21 AM UTC 24 127366188 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.3704605531 Oct 15 05:59:13 AM UTC 24 Oct 15 05:59:26 AM UTC 24 1852543976 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2880272549 Oct 15 05:59:22 AM UTC 24 Oct 15 05:59:26 AM UTC 24 32399578 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.773218858 Oct 15 05:57:58 AM UTC 24 Oct 15 05:59:29 AM UTC 24 5045323443 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1343083036 Oct 15 05:59:17 AM UTC 24 Oct 15 05:59:33 AM UTC 24 962981005 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.2715339539 Oct 15 05:59:14 AM UTC 24 Oct 15 05:59:37 AM UTC 24 5759226370 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1496234044 Oct 15 05:57:36 AM UTC 24 Oct 15 05:59:40 AM UTC 24 13498811877 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.3631140192 Oct 15 05:59:16 AM UTC 24 Oct 15 05:59:44 AM UTC 24 11393344952 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.1360418388 Oct 15 05:59:26 AM UTC 24 Oct 15 05:59:45 AM UTC 24 2784915368 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.2694234390 Oct 15 05:59:46 AM UTC 24 Oct 15 05:59:49 AM UTC 24 270819526 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.2577385410 Oct 15 05:59:49 AM UTC 24 Oct 15 05:59:51 AM UTC 24 13774194 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.3343203017 Oct 15 05:59:52 AM UTC 24 Oct 15 05:59:54 AM UTC 24 63444846 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3051892607 Oct 15 05:59:30 AM UTC 24 Oct 15 05:59:56 AM UTC 24 13801556469 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2588184475 Oct 15 05:59:05 AM UTC 24 Oct 15 05:59:56 AM UTC 24 14922877607 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.4000683141 Oct 15 05:59:58 AM UTC 24 Oct 15 06:00:01 AM UTC 24 87502714 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.1124529451 Oct 15 06:00:01 AM UTC 24 Oct 15 06:00:08 AM UTC 24 33521408 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2552575891 Oct 15 05:59:57 AM UTC 24 Oct 15 06:00:10 AM UTC 24 2177830020 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.156962997 Oct 15 05:59:27 AM UTC 24 Oct 15 06:00:11 AM UTC 24 12691330233 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.313916303 Oct 15 05:58:07 AM UTC 24 Oct 15 06:00:12 AM UTC 24 25005155773 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.2846605828 Oct 15 05:59:57 AM UTC 24 Oct 15 06:00:13 AM UTC 24 1056875039 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.839678032 Oct 15 06:00:11 AM UTC 24 Oct 15 06:00:15 AM UTC 24 563481397 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3167147580 Oct 15 06:00:12 AM UTC 24 Oct 15 06:00:18 AM UTC 24 298823891 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.218410695 Oct 15 06:00:15 AM UTC 24 Oct 15 06:00:19 AM UTC 24 248422398 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.751934247 Oct 15 06:00:17 AM UTC 24 Oct 15 06:00:23 AM UTC 24 482826074 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.1206701029 Oct 15 06:00:16 AM UTC 24 Oct 15 06:00:24 AM UTC 24 183475951 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1468978649 Oct 15 06:00:20 AM UTC 24 Oct 15 06:00:28 AM UTC 24 148007279 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.1120402146 Oct 15 05:56:16 AM UTC 24 Oct 15 06:00:39 AM UTC 24 38682008004 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2634013352 Oct 15 06:00:37 AM UTC 24 Oct 15 06:00:40 AM UTC 24 43761335 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.367624369 Oct 15 05:58:49 AM UTC 24 Oct 15 06:00:40 AM UTC 24 17465734974 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2172867817 Oct 15 06:00:39 AM UTC 24 Oct 15 06:00:41 AM UTC 24 15046350 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1964951181 Oct 15 06:02:31 AM UTC 24 Oct 15 06:02:33 AM UTC 24 81139292 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.3923735295 Oct 15 06:00:40 AM UTC 24 Oct 15 06:00:43 AM UTC 24 58550778 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.1382338824 Oct 15 06:00:43 AM UTC 24 Oct 15 06:00:46 AM UTC 24 68341714 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1206630228 Oct 15 06:00:09 AM UTC 24 Oct 15 06:00:49 AM UTC 24 8785030221 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2742567275 Oct 15 06:00:42 AM UTC 24 Oct 15 06:00:49 AM UTC 24 412731592 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2882379134 Oct 15 06:00:47 AM UTC 24 Oct 15 06:00:49 AM UTC 24 23339842 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.4273344279 Oct 15 05:59:38 AM UTC 24 Oct 15 06:00:56 AM UTC 24 7976140378 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.1607367334 Oct 15 06:00:43 AM UTC 24 Oct 15 06:00:57 AM UTC 24 866563166 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.3053341550 Oct 15 06:00:50 AM UTC 24 Oct 15 06:00:59 AM UTC 24 293044522 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1471351597 Oct 15 06:00:50 AM UTC 24 Oct 15 06:01:00 AM UTC 24 12252415646 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2275045022 Oct 15 06:01:00 AM UTC 24 Oct 15 06:01:02 AM UTC 24 21462867 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1357316304 Oct 15 06:00:50 AM UTC 24 Oct 15 06:01:03 AM UTC 24 445164755 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3274401980 Oct 15 05:58:02 AM UTC 24 Oct 15 06:01:04 AM UTC 24 78114148772 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.2936834874 Oct 15 06:00:57 AM UTC 24 Oct 15 06:01:04 AM UTC 24 244136194 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.544515834 Oct 15 05:57:27 AM UTC 24 Oct 15 06:01:05 AM UTC 24 286016235907 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1629290664 Oct 15 06:01:00 AM UTC 24 Oct 15 06:01:08 AM UTC 24 507275682 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.660252095 Oct 15 05:57:37 AM UTC 24 Oct 15 06:01:08 AM UTC 24 21223212590 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1124660484 Oct 15 06:00:57 AM UTC 24 Oct 15 06:01:10 AM UTC 24 1828027628 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.4150284995 Oct 15 06:01:09 AM UTC 24 Oct 15 06:01:11 AM UTC 24 36663121 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.1346765319 Oct 15 06:01:09 AM UTC 24 Oct 15 06:01:11 AM UTC 24 64364562 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.4204165977 Oct 15 06:00:53 AM UTC 24 Oct 15 06:01:13 AM UTC 24 868498448 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3530001235 Oct 15 06:01:13 AM UTC 24 Oct 15 06:01:15 AM UTC 24 24990555 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2036994011 Oct 15 06:01:14 AM UTC 24 Oct 15 06:01:16 AM UTC 24 34315985 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.553563519 Oct 15 06:01:12 AM UTC 24 Oct 15 06:01:17 AM UTC 24 173790436 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.3070683526 Oct 15 05:58:47 AM UTC 24 Oct 15 06:01:20 AM UTC 24 14353164263 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3909010806 Oct 15 06:01:03 AM UTC 24 Oct 15 06:01:20 AM UTC 24 5392657607 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.2831645851 Oct 15 06:01:17 AM UTC 24 Oct 15 06:01:23 AM UTC 24 135981515 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.723887380 Oct 15 06:01:12 AM UTC 24 Oct 15 06:01:26 AM UTC 24 1514534983 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.2912017433 Oct 15 06:01:21 AM UTC 24 Oct 15 06:01:28 AM UTC 24 3169988043 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.258445551 Oct 15 06:01:17 AM UTC 24 Oct 15 06:01:28 AM UTC 24 1403859931 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.952880229 Oct 15 06:01:24 AM UTC 24 Oct 15 06:01:29 AM UTC 24 57824357 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3871551644 Oct 15 05:58:43 AM UTC 24 Oct 15 06:01:35 AM UTC 24 61919461331 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1238255028 Oct 15 06:01:29 AM UTC 24 Oct 15 06:01:43 AM UTC 24 864410006 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.819741072 Oct 15 05:58:32 AM UTC 24 Oct 15 06:01:43 AM UTC 24 77867195815 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2223076972 Oct 15 06:00:13 AM UTC 24 Oct 15 06:01:46 AM UTC 24 52331899134 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.240413525 Oct 15 06:01:21 AM UTC 24 Oct 15 06:01:47 AM UTC 24 6373984741 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.2698169927 Oct 15 06:01:27 AM UTC 24 Oct 15 06:01:48 AM UTC 24 1275283097 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.2627592549 Oct 15 06:01:48 AM UTC 24 Oct 15 06:01:50 AM UTC 24 18093217 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.710262480 Oct 15 06:01:48 AM UTC 24 Oct 15 06:01:50 AM UTC 24 22290838 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3373544581 Oct 15 05:59:41 AM UTC 24 Oct 15 06:01:53 AM UTC 24 145296379021 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3621906312 Oct 15 06:01:04 AM UTC 24 Oct 15 06:01:54 AM UTC 24 13538106272 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3838464861 Oct 15 06:01:52 AM UTC 24 Oct 15 06:01:54 AM UTC 24 22696237 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.316734310 Oct 15 06:01:51 AM UTC 24 Oct 15 06:01:56 AM UTC 24 142836189 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.1971520351 Oct 15 06:01:54 AM UTC 24 Oct 15 06:01:56 AM UTC 24 69085238 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3617224229 Oct 15 06:01:51 AM UTC 24 Oct 15 06:02:06 AM UTC 24 11306042884 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.571696483 Oct 15 06:01:16 AM UTC 24 Oct 15 06:02:07 AM UTC 24 8403766593 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1227760786 Oct 15 06:01:55 AM UTC 24 Oct 15 06:02:09 AM UTC 24 568493948 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2538022713 Oct 15 06:01:55 AM UTC 24 Oct 15 06:02:13 AM UTC 24 2013058813 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.2704349841 Oct 15 06:01:57 AM UTC 24 Oct 15 06:02:15 AM UTC 24 10135875582 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1411904374 Oct 15 06:02:01 AM UTC 24 Oct 15 06:02:20 AM UTC 24 10826521490 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3194765459 Oct 15 06:02:10 AM UTC 24 Oct 15 06:02:20 AM UTC 24 484909434 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.768329127 Oct 15 06:02:20 AM UTC 24 Oct 15 06:02:22 AM UTC 24 24049888 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.4087348739 Oct 15 06:02:23 AM UTC 24 Oct 15 06:02:26 AM UTC 24 19813775 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1076213763 Oct 15 05:58:56 AM UTC 24 Oct 15 06:02:30 AM UTC 24 125582645455 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.47751932 Oct 15 06:01:55 AM UTC 24 Oct 15 06:02:31 AM UTC 24 8030572157 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.785764595 Oct 15 06:02:28 AM UTC 24 Oct 15 06:02:33 AM UTC 24 570473041 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3548745964 Oct 15 06:02:30 AM UTC 24 Oct 15 06:02:36 AM UTC 24 1930500431 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1877111543 Oct 15 06:02:32 AM UTC 24 Oct 15 06:02:36 AM UTC 24 111286774 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.3022670978 Oct 15 06:00:23 AM UTC 24 Oct 15 06:02:38 AM UTC 24 11425686423 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.4039979179 Oct 15 06:02:37 AM UTC 24 Oct 15 06:02:42 AM UTC 24 355684652 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3006493375 Oct 15 06:02:36 AM UTC 24 Oct 15 06:02:44 AM UTC 24 525872821 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1764601467 Oct 15 06:02:34 AM UTC 24 Oct 15 06:02:46 AM UTC 24 1143294284 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.2931181360 Oct 15 05:58:08 AM UTC 24 Oct 15 06:02:47 AM UTC 24 116557286085 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.2480580000 Oct 15 06:02:39 AM UTC 24 Oct 15 06:02:49 AM UTC 24 686107301 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2753991947 Oct 15 06:02:34 AM UTC 24 Oct 15 06:02:49 AM UTC 24 3499174281 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.78346705 Oct 15 06:02:45 AM UTC 24 Oct 15 06:02:52 AM UTC 24 219919189 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.2960448101 Oct 15 06:00:19 AM UTC 24 Oct 15 06:02:55 AM UTC 24 57439730973 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3360817569 Oct 15 06:02:53 AM UTC 24 Oct 15 06:02:55 AM UTC 24 18279512 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.1804413846 Oct 15 06:02:37 AM UTC 24 Oct 15 06:02:56 AM UTC 24 983605504 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.3909679350 Oct 15 06:02:55 AM UTC 24 Oct 15 06:02:58 AM UTC 24 16042478 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2052056812 Oct 15 06:01:06 AM UTC 24 Oct 15 06:03:02 AM UTC 24 6817885759 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.143466849 Oct 15 06:03:00 AM UTC 24 Oct 15 06:03:02 AM UTC 24 21962045 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.711356800 Oct 15 06:02:07 AM UTC 24 Oct 15 06:03:03 AM UTC 24 6744886930 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.255515959 Oct 15 06:02:56 AM UTC 24 Oct 15 06:03:03 AM UTC 24 592317003 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.2809653361 Oct 15 06:02:59 AM UTC 24 Oct 15 06:03:03 AM UTC 24 157201846 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2505603533 Oct 15 06:03:01 AM UTC 24 Oct 15 06:03:04 AM UTC 24 130836495 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1026831471 Oct 15 06:03:03 AM UTC 24 Oct 15 06:03:08 AM UTC 24 142734018 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1464129113 Oct 15 06:01:36 AM UTC 24 Oct 15 06:03:08 AM UTC 24 5912268945 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.2224278801 Oct 15 06:03:04 AM UTC 24 Oct 15 06:03:08 AM UTC 24 56199555 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.3646892390 Oct 15 06:03:04 AM UTC 24 Oct 15 06:03:12 AM UTC 24 102595211 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.3779755785 Oct 15 06:02:44 AM UTC 24 Oct 15 06:03:12 AM UTC 24 8271075155 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.2453849672 Oct 15 06:03:05 AM UTC 24 Oct 15 06:03:12 AM UTC 24 3485951524 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3697964502 Oct 15 06:01:56 AM UTC 24 Oct 15 06:03:18 AM UTC 24 7398385795 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.848891782 Oct 15 06:03:09 AM UTC 24 Oct 15 06:03:23 AM UTC 24 4999118985 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.3138221939 Oct 15 06:03:13 AM UTC 24 Oct 15 06:03:24 AM UTC 24 2397479084 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.2187430031 Oct 15 06:03:22 AM UTC 24 Oct 15 06:03:24 AM UTC 24 11897925 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.48311365 Oct 15 06:02:08 AM UTC 24 Oct 15 06:03:25 AM UTC 24 14923354616 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.235057265 Oct 15 06:03:24 AM UTC 24 Oct 15 06:03:26 AM UTC 24 21776772 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.3646493080 Oct 15 06:03:26 AM UTC 24 Oct 15 06:03:28 AM UTC 24 58035708 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2340468758 Oct 15 06:03:03 AM UTC 24 Oct 15 06:03:29 AM UTC 24 9682673671 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.2650664562 Oct 15 05:59:33 AM UTC 24 Oct 15 06:03:29 AM UTC 24 77747934299 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.3525722113 Oct 15 06:03:27 AM UTC 24 Oct 15 06:03:30 AM UTC 24 86289624 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1348578603 Oct 15 06:02:16 AM UTC 24 Oct 15 06:03:32 AM UTC 24 43489320034 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.899832725 Oct 15 06:03:28 AM UTC 24 Oct 15 06:03:32 AM UTC 24 194924315 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.2400252896 Oct 15 06:03:25 AM UTC 24 Oct 15 06:03:32 AM UTC 24 1732658866 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1279536095 Oct 15 06:03:30 AM UTC 24 Oct 15 06:03:35 AM UTC 24 583209882 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2477686087 Oct 15 06:03:30 AM UTC 24 Oct 15 06:03:37 AM UTC 24 3108833439 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.3325486285 Oct 15 06:03:08 AM UTC 24 Oct 15 06:03:38 AM UTC 24 953333046 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.140144522 Oct 15 06:03:33 AM UTC 24 Oct 15 06:03:43 AM UTC 24 903254540 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.2051699863 Oct 15 06:03:33 AM UTC 24 Oct 15 06:03:43 AM UTC 24 295593945 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.2573486026 Oct 15 06:02:14 AM UTC 24 Oct 15 06:03:44 AM UTC 24 5485016511 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.808878437 Oct 15 06:03:36 AM UTC 24 Oct 15 06:03:44 AM UTC 24 878064829 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.2853924943 Oct 15 06:03:44 AM UTC 24 Oct 15 06:03:46 AM UTC 24 116292259 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.1675211791 Oct 15 06:03:44 AM UTC 24 Oct 15 06:03:46 AM UTC 24 44874407 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3301783680 Oct 15 06:02:50 AM UTC 24 Oct 15 06:03:46 AM UTC 24 28932809041 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.2825251765 Oct 15 06:03:51 AM UTC 24 Oct 15 06:04:18 AM UTC 24 3220799771 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.3853800983 Oct 15 06:03:04 AM UTC 24 Oct 15 06:03:47 AM UTC 24 11249334139 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.1581779259 Oct 15 06:03:33 AM UTC 24 Oct 15 06:03:49 AM UTC 24 2166204065 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.1658188602 Oct 15 06:03:30 AM UTC 24 Oct 15 06:03:49 AM UTC 24 1534600225 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.1942472127 Oct 15 06:03:47 AM UTC 24 Oct 15 06:03:49 AM UTC 24 23356405 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.4173195692 Oct 15 06:03:47 AM UTC 24 Oct 15 06:03:49 AM UTC 24 204884344 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2565394814 Oct 15 06:03:48 AM UTC 24 Oct 15 06:03:53 AM UTC 24 273532960 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.649881062 Oct 15 06:03:45 AM UTC 24 Oct 15 06:03:55 AM UTC 24 1582950257 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.3010877021 Oct 15 06:01:43 AM UTC 24 Oct 15 06:03:55 AM UTC 24 23543267463 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.3978609421 Oct 15 06:03:31 AM UTC 24 Oct 15 06:03:55 AM UTC 24 5586745702 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1075097728 Oct 15 06:03:48 AM UTC 24 Oct 15 06:03:57 AM UTC 24 485659371 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.338086377 Oct 15 06:03:51 AM UTC 24 Oct 15 06:03:58 AM UTC 24 695554994 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.44934253 Oct 15 06:03:51 AM UTC 24 Oct 15 06:04:01 AM UTC 24 4683522011 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2362054353 Oct 15 05:58:53 AM UTC 24 Oct 15 06:04:01 AM UTC 24 141404233806 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.147377342 Oct 15 06:03:56 AM UTC 24 Oct 15 06:04:04 AM UTC 24 6815750001 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.2517196547 Oct 15 06:03:33 AM UTC 24 Oct 15 06:04:04 AM UTC 24 20514915690 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.2012300665 Oct 15 06:04:02 AM UTC 24 Oct 15 06:04:04 AM UTC 24 12538986 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1461782817 Oct 15 06:03:54 AM UTC 24 Oct 15 06:04:06 AM UTC 24 1055620178 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.2330381980 Oct 15 06:03:51 AM UTC 24 Oct 15 06:04:06 AM UTC 24 892910285 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.751306322 Oct 15 06:04:05 AM UTC 24 Oct 15 06:04:08 AM UTC 24 126497165 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.1841140200 Oct 15 06:04:09 AM UTC 24 Oct 15 06:04:16 AM UTC 24 424273572 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1055418330 Oct 15 06:02:50 AM UTC 24 Oct 15 06:04:08 AM UTC 24 38464118879 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.1535329089 Oct 15 06:04:07 AM UTC 24 Oct 15 06:04:09 AM UTC 24 38242368 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.1730838946 Oct 15 06:04:07 AM UTC 24 Oct 15 06:04:10 AM UTC 24 20037247 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.468179374 Oct 15 06:03:09 AM UTC 24 Oct 15 06:04:10 AM UTC 24 4875273350 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3553036972 Oct 15 06:04:06 AM UTC 24 Oct 15 06:04:12 AM UTC 24 3265484481 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.2382683129 Oct 15 06:04:10 AM UTC 24 Oct 15 06:04:14 AM UTC 24 146140713 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.1764109380 Oct 15 06:04:09 AM UTC 24 Oct 15 06:04:19 AM UTC 24 394099641 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.1310583877 Oct 15 06:04:07 AM UTC 24 Oct 15 06:04:19 AM UTC 24 4555013503 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.2886066868 Oct 15 06:04:10 AM UTC 24 Oct 15 06:04:26 AM UTC 24 3969665296 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.844515486 Oct 15 06:04:17 AM UTC 24 Oct 15 06:04:30 AM UTC 24 2849861613 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.2021922828 Oct 15 06:03:47 AM UTC 24 Oct 15 06:04:30 AM UTC 24 1786568545 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.20605565 Oct 15 06:01:29 AM UTC 24 Oct 15 06:04:30 AM UTC 24 93874940972 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.605150438 Oct 15 06:04:30 AM UTC 24 Oct 15 06:04:32 AM UTC 24 10214653 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.1481656734 Oct 15 06:06:40 AM UTC 24 Oct 15 06:06:47 AM UTC 24 604380497 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.1663964147 Oct 15 06:04:31 AM UTC 24 Oct 15 06:04:34 AM UTC 24 73491272 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.126618022 Oct 15 06:04:10 AM UTC 24 Oct 15 06:04:34 AM UTC 24 5959267014 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1401635357 Oct 15 06:04:20 AM UTC 24 Oct 15 06:04:35 AM UTC 24 4898130291 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.3271785976 Oct 15 06:04:34 AM UTC 24 Oct 15 06:04:37 AM UTC 24 47605007 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.598932057 Oct 15 06:04:35 AM UTC 24 Oct 15 06:04:38 AM UTC 24 18392202 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.1560872595 Oct 15 06:04:34 AM UTC 24 Oct 15 06:04:42 AM UTC 24 680397100 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.3067314589 Oct 15 06:04:38 AM UTC 24 Oct 15 06:04:43 AM UTC 24 79193673 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.905344520 Oct 15 06:01:30 AM UTC 24 Oct 15 06:04:44 AM UTC 24 10251422108 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.1975802113 Oct 15 06:04:44 AM UTC 24 Oct 15 06:04:52 AM UTC 24 125415032 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.4175561300 Oct 15 06:04:45 AM UTC 24 Oct 15 06:04:52 AM UTC 24 1385823559 ps
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