Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total tests in report: 1131
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
52.87 52.87 88.97 88.97 75.35 75.35 53.44 53.44 0.00 0.00 84.53 84.53 64.58 64.58 3.22 3.22 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.453428210
65.08 12.21 91.92 2.96 80.41 5.06 61.32 7.87 48.89 48.89 88.10 3.57 71.98 7.40 12.92 9.70 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3252637297
74.49 9.41 95.20 3.27 86.83 6.42 72.05 10.73 66.67 17.78 92.98 4.89 80.09 8.11 27.62 14.70 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.1844001260
80.00 5.51 97.10 1.91 89.18 2.35 88.88 16.83 75.56 8.89 95.40 2.42 84.35 4.27 29.50 1.88 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3837180774
83.55 3.55 97.75 0.65 90.77 1.59 90.75 1.87 84.44 8.89 96.18 0.78 84.50 0.14 40.45 10.94 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.1629657708
85.71 2.16 97.83 0.08 91.01 0.24 90.75 0.00 84.44 0.00 96.35 0.17 84.64 0.14 54.95 14.50 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1673767987
87.27 1.56 97.85 0.02 91.16 0.15 91.73 0.98 84.44 0.00 96.38 0.03 93.03 8.39 56.29 1.34 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2167032930
88.58 1.31 98.01 0.16 91.44 0.29 91.73 0.00 91.11 6.67 96.55 0.17 93.17 0.14 58.07 1.78 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.2774335227
89.86 1.27 98.04 0.03 91.49 0.05 91.73 0.00 93.33 2.22 96.62 0.07 93.17 0.00 64.60 6.53 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2016766801
90.80 0.94 98.04 0.00 91.49 0.00 91.73 0.00 93.33 0.00 96.62 0.00 93.17 0.00 71.19 6.58 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1366732885
91.48 0.68 98.06 0.02 91.52 0.02 96.46 4.72 93.33 0.00 96.62 0.00 93.17 0.00 71.19 0.00 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.3905376779
92.12 0.64 98.06 0.00 91.53 0.01 96.46 0.00 93.33 0.00 96.62 0.00 93.17 0.00 75.64 4.46 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3213895561
92.69 0.57 98.06 0.00 91.61 0.07 96.85 0.39 93.33 0.00 96.62 0.00 93.17 0.00 79.16 3.51 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.3918115283
93.09 0.41 98.06 0.00 91.61 0.00 96.85 0.00 93.33 0.00 96.62 0.00 93.31 0.14 81.88 2.72 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.724062855
93.49 0.39 98.06 0.00 92.30 0.70 97.24 0.39 93.33 0.00 96.65 0.03 93.60 0.28 83.22 1.34 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3359870807
93.84 0.35 98.06 0.00 92.30 0.00 97.24 0.00 93.33 0.00 96.65 0.00 93.60 0.00 85.69 2.48 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.3305999356
94.19 0.35 98.18 0.12 93.00 0.70 97.24 0.00 93.33 0.00 96.82 0.17 94.31 0.71 86.44 0.74 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.255382291
94.45 0.27 98.34 0.16 93.22 0.22 97.24 0.00 93.33 0.00 97.11 0.29 94.31 0.00 87.62 1.19 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.1801717000
94.68 0.23 98.34 0.00 93.25 0.02 98.43 1.18 93.33 0.00 97.11 0.00 94.45 0.14 87.87 0.25 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1566593341
94.91 0.23 98.34 0.00 93.25 0.00 98.43 0.00 93.33 0.00 97.11 0.00 94.45 0.00 89.46 1.58 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.1542857080
95.10 0.20 98.35 0.01 93.28 0.04 98.43 0.00 93.33 0.00 97.14 0.03 94.45 0.00 90.74 1.29 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.429145169
95.28 0.18 98.35 0.00 93.28 0.00 98.43 0.00 93.33 0.00 97.14 0.00 94.45 0.00 91.98 1.24 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2372901693
95.45 0.17 98.35 0.00 93.28 0.00 98.43 0.00 93.33 0.00 97.14 0.00 94.45 0.00 93.17 1.19 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.3235193146
95.58 0.13 98.35 0.00 93.31 0.02 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.85 93.17 0.00 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3823241394
95.67 0.09 98.35 0.00 93.31 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.00 93.81 0.64 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.611473944
95.76 0.09 98.35 0.00 93.48 0.17 98.43 0.00 93.33 0.00 97.14 0.00 95.31 0.00 94.26 0.45 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2918604981
95.84 0.08 98.35 0.00 93.48 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.45 0.14 94.70 0.45 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.2176193409
95.91 0.07 98.35 0.00 93.48 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.45 0.00 95.20 0.50 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2434252852
95.98 0.07 98.35 0.00 93.48 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.45 0.00 95.69 0.50 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1660286099
96.04 0.06 98.35 0.00 93.48 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.45 0.00 96.09 0.40 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.451609898
96.08 0.04 98.35 0.00 93.48 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.45 0.00 96.39 0.30 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1452324848
96.12 0.04 98.37 0.03 93.52 0.04 98.62 0.20 93.33 0.00 97.14 0.00 95.45 0.00 96.39 0.00 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.4223948616
96.16 0.04 98.37 0.00 93.63 0.11 98.62 0.00 93.33 0.00 97.14 0.00 95.45 0.00 96.53 0.15 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2219972501
96.19 0.04 98.37 0.00 93.65 0.01 98.62 0.00 93.33 0.00 97.14 0.00 95.45 0.00 96.78 0.25 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3374544124
96.23 0.04 98.37 0.00 93.84 0.20 98.62 0.00 93.33 0.00 97.14 0.00 95.45 0.00 96.83 0.05 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3752015530
96.26 0.04 98.37 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.14 0.00 95.45 0.00 97.08 0.25 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1603932899
96.30 0.04 98.37 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.14 0.00 95.45 0.00 97.33 0.25 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.938798591
96.33 0.04 98.37 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.14 0.00 95.45 0.00 97.57 0.25 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2352260357
96.36 0.03 98.37 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.14 0.00 95.45 0.00 97.77 0.20 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.2496764338
96.39 0.03 98.37 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.14 0.00 95.45 0.00 97.97 0.20 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.2542270994
96.41 0.02 98.38 0.01 93.88 0.04 98.62 0.00 93.33 0.00 97.16 0.02 95.45 0.00 98.07 0.10 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3449864698
96.43 0.02 98.38 0.00 93.88 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.22 0.15 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2624029112
96.46 0.02 98.38 0.00 93.91 0.02 98.62 0.00 93.33 0.00 97.18 0.02 95.45 0.00 98.32 0.10 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.4076247069
96.47 0.01 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.42 0.10 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2997516306
96.48 0.01 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.1537817791
96.50 0.01 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1266466033
96.51 0.01 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1758372641
96.53 0.01 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.81 0.10 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.2982520861
96.54 0.01 98.38 0.00 93.93 0.02 98.62 0.00 93.33 0.00 97.19 0.02 95.45 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1246032152
96.55 0.01 98.38 0.00 93.98 0.05 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.86 0.00 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2718938507
96.55 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.513489337
96.56 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.702906161
96.57 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2542025872
96.57 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.3731086407
96.58 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.611055164
96.59 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.1534303575
96.60 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.265674111
96.60 0.01 98.38 0.00 93.98 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.4007221583
96.60 0.01 98.38 0.00 93.99 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.624059182

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.4104031312
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.532489589
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2524841070
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3442538648
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2690236997
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1863703653
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1861341904
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1832513532
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1747523892
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3729395750
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1395607230
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3916464131
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3679426913
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1966818447
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3329973556
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1305220891
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1330703449
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4272284334
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1733480621
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1902122902
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4063160627
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2249549991
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.201668473
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1765698075
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1067117469
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3031115664
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2939177179
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4144650993
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3368151010
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1758789056
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.931817044
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.795795849
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2690096040
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.110388874
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4023409426
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/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1411300617
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.1835584843
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3374708735
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.1552022327
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.860332448
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.3972318600
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.3933237411
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.4190852542
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.176293375
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2269517949
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3235559423
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2423305752
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.2501278625
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1061904805
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.4211321034
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.1473072191
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3124305700
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.638040314
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.820612226
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2042726063
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.518315871
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.1686420407
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.130071344
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2831390394
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.2456064216
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.2676305453
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1220622260
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.1565911853
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.967216858
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1612339182
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3973070307
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1851714234
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.1374853418
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.1961749358
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.2614196601
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2052129614
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2306078885
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.2943615674
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1374509259
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.1314783406
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.391177376
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1468813678
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.2358311260
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3355683663
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2081700463
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1788217462
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.997154993
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.259951137
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.1921274870
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.2437100387
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3874528192
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1707648196
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2349793555
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3081255464
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.1114942183
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2104321467
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.793318494
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2533394050
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1089153293
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.3245192082
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.3262106971
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.905149281
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.3008523331
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1814715261
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3466752561
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2497019429
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.492115001
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.321227359
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2016107218
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.279391358
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2909110137
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2497729293
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.727012785
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.703505196
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3483321028
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.867229436
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2679955317
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.159410158
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.1744839663
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3676734622
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.328457116
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.3577920082
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2567025689
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.1032611264
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2599215291
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2304236494
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2663052391
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1117558599
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1238741961
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.4038014804
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3692752535
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1143606404
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3963098177
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.1074103100



Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.338409322 Feb 08 06:48:00 PM UTC 25 Feb 08 06:48:16 PM UTC 25 2606735644 ps
T2 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.3905376779 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:44 PM UTC 25 34974414 ps
T3 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.3329759668 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:44 PM UTC 25 54086085 ps
T4 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.3351090748 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:44 PM UTC 25 22960603 ps
T5 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.4054693933 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:44 PM UTC 25 280292789 ps
T6 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.386363452 Feb 08 06:48:05 PM UTC 25 Feb 08 06:48:07 PM UTC 25 18022004 ps
T7 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.453428210 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:45 PM UTC 25 31242033 ps
T8 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.3720063640 Feb 08 06:47:43 PM UTC 25 Feb 08 06:47:45 PM UTC 25 22386762 ps
T9 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.4223948616 Feb 08 06:47:43 PM UTC 25 Feb 08 06:47:46 PM UTC 25 36941311 ps
T10 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.1844001260 Feb 08 06:47:43 PM UTC 25 Feb 08 06:48:15 PM UTC 25 3322159507 ps
T11 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.854308231 Feb 08 06:47:43 PM UTC 25 Feb 08 06:47:46 PM UTC 25 64996157 ps
T12 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3195597042 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:46 PM UTC 25 5522054562 ps
T13 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1566593341 Feb 08 06:47:43 PM UTC 25 Feb 08 06:47:46 PM UTC 25 102092905 ps
T14 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.4053147797 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:46 PM UTC 25 144319143 ps
T15 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.2190646768 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:46 PM UTC 25 135707056 ps
T16 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.1801717000 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:47 PM UTC 25 111162998 ps
T41 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.2866363598 Feb 08 06:47:43 PM UTC 25 Feb 08 06:47:47 PM UTC 25 36794642 ps
T17 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.2980818984 Feb 08 06:47:45 PM UTC 25 Feb 08 06:47:47 PM UTC 25 59122778 ps
T18 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.3128738687 Feb 08 06:47:44 PM UTC 25 Feb 08 06:47:48 PM UTC 25 119571123 ps
T19 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.2122224477 Feb 08 06:47:43 PM UTC 25 Feb 08 06:47:48 PM UTC 25 287674364 ps
T27 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.29934191 Feb 08 06:47:43 PM UTC 25 Feb 08 06:47:48 PM UTC 25 130568670 ps
T42 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.2930932450 Feb 08 06:47:46 PM UTC 25 Feb 08 06:47:48 PM UTC 25 24691707 ps
T28 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.130071344 Feb 08 06:48:11 PM UTC 25 Feb 08 06:48:15 PM UTC 25 114532797 ps
T20 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.2453746490 Feb 08 06:47:46 PM UTC 25 Feb 08 06:47:48 PM UTC 25 50133390 ps
T32 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.3860598004 Feb 08 06:47:46 PM UTC 25 Feb 08 06:47:49 PM UTC 25 13138772 ps
T29 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.394766156 Feb 08 06:47:46 PM UTC 25 Feb 08 06:47:49 PM UTC 25 97050853 ps
T21 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1794238213 Feb 08 06:47:45 PM UTC 25 Feb 08 06:47:51 PM UTC 25 205630866 ps
T30 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.3660059199 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:51 PM UTC 25 262822623 ps
T22 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3837180774 Feb 08 06:47:48 PM UTC 25 Feb 08 06:47:51 PM UTC 25 41484664 ps
T23 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2219972501 Feb 08 06:47:44 PM UTC 25 Feb 08 06:47:51 PM UTC 25 2413539429 ps
T31 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.2774335227 Feb 08 06:47:43 PM UTC 25 Feb 08 06:47:53 PM UTC 25 4681584228 ps
T33 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.2288358211 Feb 08 06:47:50 PM UTC 25 Feb 08 06:47:53 PM UTC 25 216884567 ps
T24 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.154876742 Feb 08 06:47:43 PM UTC 25 Feb 08 06:47:53 PM UTC 25 893932809 ps
T97 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.271414162 Feb 08 06:47:51 PM UTC 25 Feb 08 06:47:53 PM UTC 25 35790365 ps
T103 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.1882432641 Feb 08 06:47:51 PM UTC 25 Feb 08 06:47:54 PM UTC 25 18832766 ps
T25 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3449864698 Feb 08 06:47:44 PM UTC 25 Feb 08 06:47:54 PM UTC 25 450640415 ps
T26 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2691502018 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:54 PM UTC 25 1829511918 ps
T43 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.1936724574 Feb 08 06:47:55 PM UTC 25 Feb 08 06:48:18 PM UTC 25 1292642951 ps
T73 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.2720872962 Feb 08 06:47:49 PM UTC 25 Feb 08 06:47:54 PM UTC 25 71454644 ps
T74 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2150114448 Feb 08 06:48:04 PM UTC 25 Feb 08 06:48:20 PM UTC 25 1548015841 ps
T52 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3252637297 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:55 PM UTC 25 891428183 ps
T62 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.3972957460 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:55 PM UTC 25 409726286 ps
T75 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3379126287 Feb 08 06:47:48 PM UTC 25 Feb 08 06:47:56 PM UTC 25 245716299 ps
T64 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3671374601 Feb 08 06:47:44 PM UTC 25 Feb 08 06:47:56 PM UTC 25 380976539 ps
T76 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3291276970 Feb 08 06:47:46 PM UTC 25 Feb 08 06:47:56 PM UTC 25 8173953570 ps
T77 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2880484544 Feb 08 06:47:54 PM UTC 25 Feb 08 06:47:56 PM UTC 25 35245121 ps
T49 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.855517974 Feb 08 06:47:54 PM UTC 25 Feb 08 06:47:56 PM UTC 25 62607301 ps
T188 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.4211321034 Feb 08 06:48:13 PM UTC 25 Feb 08 06:48:21 PM UTC 25 706614074 ps
T95 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.228657188 Feb 08 06:47:48 PM UTC 25 Feb 08 06:47:57 PM UTC 25 2435537350 ps
T53 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1879686750 Feb 08 06:47:49 PM UTC 25 Feb 08 06:47:57 PM UTC 25 1003132163 ps
T54 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.624059182 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:58 PM UTC 25 2243113780 ps
T397 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.1012599936 Feb 08 06:47:57 PM UTC 25 Feb 08 06:47:59 PM UTC 25 264071992 ps
T34 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.4071255438 Feb 08 06:47:57 PM UTC 25 Feb 08 06:48:00 PM UTC 25 251292919 ps
T398 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.867487963 Feb 08 06:47:58 PM UTC 25 Feb 08 06:48:00 PM UTC 25 142625122 ps
T399 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.735340369 Feb 08 06:47:58 PM UTC 25 Feb 08 06:48:00 PM UTC 25 49139068 ps
T128 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.4190852542 Feb 08 06:48:15 PM UTC 25 Feb 08 06:48:21 PM UTC 25 329554468 ps
T65 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.3800785138 Feb 08 06:47:54 PM UTC 25 Feb 08 06:48:01 PM UTC 25 796721355 ps
T145 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3368158858 Feb 08 06:47:48 PM UTC 25 Feb 08 06:48:02 PM UTC 25 3461274660 ps
T96 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2275009975 Feb 08 06:47:55 PM UTC 25 Feb 08 06:48:02 PM UTC 25 471104317 ps
T113 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3875059547 Feb 08 06:48:00 PM UTC 25 Feb 08 06:48:02 PM UTC 25 128840327 ps
T35 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.759454261 Feb 08 06:47:42 PM UTC 25 Feb 08 06:48:03 PM UTC 25 13944461401 ps
T50 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2905461425 Feb 08 06:48:01 PM UTC 25 Feb 08 06:48:04 PM UTC 25 55476521 ps
T51 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.3500014413 Feb 08 06:47:42 PM UTC 25 Feb 08 06:48:04 PM UTC 25 23270789615 ps
T61 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3609573105 Feb 08 06:47:49 PM UTC 25 Feb 08 06:48:04 PM UTC 25 4139143177 ps
T67 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2572957515 Feb 08 06:47:54 PM UTC 25 Feb 08 06:48:05 PM UTC 25 606741114 ps
T129 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.255382291 Feb 08 06:47:49 PM UTC 25 Feb 08 06:48:06 PM UTC 25 792297842 ps
T400 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2519892412 Feb 08 06:48:02 PM UTC 25 Feb 08 06:48:07 PM UTC 25 294174512 ps
T131 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.419984855 Feb 08 06:48:02 PM UTC 25 Feb 08 06:48:07 PM UTC 25 307470034 ps
T114 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2697894825 Feb 08 06:47:52 PM UTC 25 Feb 08 06:48:07 PM UTC 25 2275843245 ps
T170 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3292451201 Feb 08 06:47:56 PM UTC 25 Feb 08 06:48:08 PM UTC 25 1214153218 ps
T36 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3822321239 Feb 08 06:48:07 PM UTC 25 Feb 08 06:48:10 PM UTC 25 682468494 ps
T401 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.536839160 Feb 08 06:47:59 PM UTC 25 Feb 08 06:48:10 PM UTC 25 1973820139 ps
T402 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.2038475585 Feb 08 06:48:08 PM UTC 25 Feb 08 06:48:10 PM UTC 25 39693536 ps
T403 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.176293375 Feb 08 06:48:08 PM UTC 25 Feb 08 06:48:10 PM UTC 25 62338341 ps
T120 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1127385460 Feb 08 06:48:04 PM UTC 25 Feb 08 06:48:11 PM UTC 25 1676830355 ps
T404 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.3519992144 Feb 08 06:48:04 PM UTC 25 Feb 08 06:48:12 PM UTC 25 728064929 ps
T171 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3289650697 Feb 08 06:48:05 PM UTC 25 Feb 08 06:48:13 PM UTC 25 292483367 ps
T203 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3164122034 Feb 08 06:48:01 PM UTC 25 Feb 08 06:48:13 PM UTC 25 1474409076 ps
T405 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2831390394 Feb 08 06:48:11 PM UTC 25 Feb 08 06:48:14 PM UTC 25 78181867 ps
T130 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.2501278625 Feb 08 06:48:16 PM UTC 25 Feb 08 06:48:21 PM UTC 25 246416698 ps
T205 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2545905170 Feb 08 06:47:54 PM UTC 25 Feb 08 06:48:21 PM UTC 25 35245059459 ps
T260 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.2456064216 Feb 08 06:48:14 PM UTC 25 Feb 08 06:48:21 PM UTC 25 1977273391 ps
T78 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2335423417 Feb 08 06:47:54 PM UTC 25 Feb 08 06:48:21 PM UTC 25 6028126448 ps
T93 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.2893323027 Feb 08 06:47:46 PM UTC 25 Feb 08 06:48:22 PM UTC 25 11030749611 ps
T58 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2875783290 Feb 08 06:47:49 PM UTC 25 Feb 08 06:48:23 PM UTC 25 4062364754 ps
T172 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.820612226 Feb 08 06:48:17 PM UTC 25 Feb 08 06:48:23 PM UTC 25 4436258246 ps
T406 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.3933237411 Feb 08 06:48:21 PM UTC 25 Feb 08 06:48:24 PM UTC 25 18933633 ps
T66 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3124305700 Feb 08 06:48:13 PM UTC 25 Feb 08 06:48:24 PM UTC 25 1360412872 ps
T407 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.1744839663 Feb 08 06:49:35 PM UTC 25 Feb 08 06:49:37 PM UTC 25 11187583 ps
T408 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.1565911853 Feb 08 06:48:22 PM UTC 25 Feb 08 06:48:25 PM UTC 25 15239426 ps
T119 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2269517949 Feb 08 06:48:19 PM UTC 25 Feb 08 06:48:26 PM UTC 25 272350538 ps
T392 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1068426532 Feb 08 06:48:06 PM UTC 25 Feb 08 06:48:27 PM UTC 25 4893412966 ps
T409 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.391177376 Feb 08 06:48:25 PM UTC 25 Feb 08 06:48:27 PM UTC 25 92830014 ps
T410 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.1314783406 Feb 08 06:48:25 PM UTC 25 Feb 08 06:48:28 PM UTC 25 48660067 ps
T63 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.4218265023 Feb 08 06:48:01 PM UTC 25 Feb 08 06:48:30 PM UTC 25 21521913269 ps
T411 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1374509259 Feb 08 06:48:22 PM UTC 25 Feb 08 06:48:30 PM UTC 25 1039861572 ps
T133 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1220622260 Feb 08 06:48:27 PM UTC 25 Feb 08 06:48:32 PM UTC 25 145173041 ps
T94 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.1374853418 Feb 08 06:48:26 PM UTC 25 Feb 08 06:48:33 PM UTC 25 589769200 ps
T121 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.2759413588 Feb 08 06:47:55 PM UTC 25 Feb 08 06:48:34 PM UTC 25 8454149993 ps
T197 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.1904988611 Feb 08 06:47:55 PM UTC 25 Feb 08 06:48:34 PM UTC 25 3809259877 ps
T132 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3973070307 Feb 08 06:48:27 PM UTC 25 Feb 08 06:48:34 PM UTC 25 121429014 ps
T267 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.1961749358 Feb 08 06:48:26 PM UTC 25 Feb 08 06:48:37 PM UTC 25 1091803391 ps
T47 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1618355169 Feb 08 06:47:45 PM UTC 25 Feb 08 06:48:37 PM UTC 25 40221172143 ps
T412 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.2676305453 Feb 08 06:48:35 PM UTC 25 Feb 08 06:48:37 PM UTC 25 13788006 ps
T413 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2081700463 Feb 08 06:48:35 PM UTC 25 Feb 08 06:48:37 PM UTC 25 18511585 ps
T207 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.576501819 Feb 08 06:47:48 PM UTC 25 Feb 08 06:49:37 PM UTC 25 12418235920 ps
T414 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.2614196601 Feb 08 06:48:25 PM UTC 25 Feb 08 06:48:37 PM UTC 25 915192506 ps
T48 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.2943615674 Feb 08 06:48:23 PM UTC 25 Feb 08 06:48:38 PM UTC 25 4485704959 ps
T173 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2306078885 Feb 08 06:48:28 PM UTC 25 Feb 08 06:48:38 PM UTC 25 2515436187 ps
T415 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1089153293 Feb 08 06:48:38 PM UTC 25 Feb 08 06:48:41 PM UTC 25 41174476 ps
T122 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.638040314 Feb 08 06:48:12 PM UTC 25 Feb 08 06:48:41 PM UTC 25 76641737730 ps
T416 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.1686420407 Feb 08 06:48:10 PM UTC 25 Feb 08 06:48:42 PM UTC 25 5750338359 ps
T417 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2533394050 Feb 08 06:48:38 PM UTC 25 Feb 08 06:48:43 PM UTC 25 92968098 ps
T265 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.2437100387 Feb 08 06:48:39 PM UTC 25 Feb 08 06:48:46 PM UTC 25 1639434138 ps
T314 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2349793555 Feb 08 06:48:38 PM UTC 25 Feb 08 06:48:46 PM UTC 25 882163179 ps
T287 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3355683663 Feb 08 06:48:43 PM UTC 25 Feb 08 06:48:47 PM UTC 25 38257096 ps
T389 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.518315871 Feb 08 06:48:11 PM UTC 25 Feb 08 06:48:51 PM UTC 25 13281657859 ps
T37 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.1629657708 Feb 08 06:48:07 PM UTC 25 Feb 08 06:48:53 PM UTC 25 2791397087 ps
T174 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3081255464 Feb 08 06:48:44 PM UTC 25 Feb 08 06:48:54 PM UTC 25 1445322375 ps
T209 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.259951137 Feb 08 06:48:43 PM UTC 25 Feb 08 06:48:55 PM UTC 25 923660043 ps
T418 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.2358311260 Feb 08 06:48:53 PM UTC 25 Feb 08 06:48:55 PM UTC 25 33045352 ps
T419 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.3008523331 Feb 08 06:48:54 PM UTC 25 Feb 08 06:48:56 PM UTC 25 101860560 ps
T296 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1468813678 Feb 08 06:48:26 PM UTC 25 Feb 08 06:48:57 PM UTC 25 16155400788 ps
T420 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2679955317 Feb 08 06:48:57 PM UTC 25 Feb 08 06:48:59 PM UTC 25 49081662 ps
T59 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.1921274870 Feb 08 06:48:43 PM UTC 25 Feb 08 06:49:02 PM UTC 25 2506315564 ps
T309 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2052129614 Feb 08 06:48:25 PM UTC 25 Feb 08 06:49:03 PM UTC 25 62856984913 ps
T68 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2497729293 Feb 08 06:48:58 PM UTC 25 Feb 08 06:49:06 PM UTC 25 764350073 ps
T421 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3483321028 Feb 08 06:48:56 PM UTC 25 Feb 08 06:49:08 PM UTC 25 4618425787 ps
T55 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1707648196 Feb 08 06:48:38 PM UTC 25 Feb 08 06:49:09 PM UTC 25 32891613895 ps
T60 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2918604981 Feb 08 06:47:42 PM UTC 25 Feb 08 06:49:09 PM UTC 25 7275956260 ps
T44 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.1694431861 Feb 08 06:47:57 PM UTC 25 Feb 08 06:49:11 PM UTC 25 13857081565 ps
T204 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.159410158 Feb 08 06:49:06 PM UTC 25 Feb 08 06:49:12 PM UTC 25 280017558 ps
T422 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.867229436 Feb 08 06:48:58 PM UTC 25 Feb 08 06:49:12 PM UTC 25 1213725640 ps
T423 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.793318494 Feb 08 06:48:38 PM UTC 25 Feb 08 06:49:13 PM UTC 25 8607465589 ps
T390 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.703505196 Feb 08 06:48:56 PM UTC 25 Feb 08 06:49:14 PM UTC 25 6551410359 ps
T424 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1814715261 Feb 08 06:49:13 PM UTC 25 Feb 08 06:49:15 PM UTC 25 76278064 ps
T199 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1061904805 Feb 08 06:48:16 PM UTC 25 Feb 08 06:49:16 PM UTC 25 9067216298 ps
T425 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.3262106971 Feb 08 06:49:16 PM UTC 25 Feb 08 06:49:18 PM UTC 25 10450219 ps
T426 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.905149281 Feb 08 06:49:09 PM UTC 25 Feb 08 06:49:18 PM UTC 25 2227211364 ps
T112 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2104321467 Feb 08 06:48:38 PM UTC 25 Feb 08 06:49:19 PM UTC 25 26864929406 ps
T206 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2909110137 Feb 08 06:49:00 PM UTC 25 Feb 08 06:49:19 PM UTC 25 532950910 ps
T427 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.727012785 Feb 08 06:49:12 PM UTC 25 Feb 08 06:49:19 PM UTC 25 445347794 ps
T428 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.328457116 Feb 08 06:49:17 PM UTC 25 Feb 08 06:49:19 PM UTC 25 22904166 ps
T116 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3874528192 Feb 08 06:48:39 PM UTC 25 Feb 08 06:49:20 PM UTC 25 7106929072 ps
T429 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.4165690659 Feb 08 06:49:35 PM UTC 25 Feb 08 06:49:37 PM UTC 25 30354405 ps
T430 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3963098177 Feb 08 06:49:19 PM UTC 25 Feb 08 06:49:22 PM UTC 25 15879942 ps
T394 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1143606404 Feb 08 06:49:20 PM UTC 25 Feb 08 06:49:23 PM UTC 25 148829593 ps
T327 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2663052391 Feb 08 06:49:20 PM UTC 25 Feb 08 06:49:24 PM UTC 25 130868833 ps
T275 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2016107218 Feb 08 06:49:03 PM UTC 25 Feb 08 06:49:25 PM UTC 25 8827945463 ps
T115 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1612339182 Feb 08 06:48:33 PM UTC 25 Feb 08 06:49:26 PM UTC 25 3048419381 ps
T318 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1117558599 Feb 08 06:49:20 PM UTC 25 Feb 08 06:49:26 PM UTC 25 1076195820 ps
T431 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3676734622 Feb 08 06:49:25 PM UTC 25 Feb 08 06:49:30 PM UTC 25 62529971 ps
T432 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.1032611264 Feb 08 06:49:26 PM UTC 25 Feb 08 06:49:33 PM UTC 25 72007198 ps
T433 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3692752535 Feb 08 06:49:19 PM UTC 25 Feb 08 06:49:33 PM UTC 25 3470406625 ps
T208 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.492115001 Feb 08 06:49:10 PM UTC 25 Feb 08 06:49:33 PM UTC 25 4686182498 ps
T117 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1238741961 Feb 08 06:49:27 PM UTC 25 Feb 08 06:49:34 PM UTC 25 213786697 ps
T69 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.429145169 Feb 08 06:48:07 PM UTC 25 Feb 08 06:49:38 PM UTC 25 6769209211 ps
T304 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.91064915 Feb 08 06:50:08 PM UTC 25 Feb 08 06:51:02 PM UTC 25 7223077432 ps
T244 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.1473072191 Feb 08 06:48:14 PM UTC 25 Feb 08 06:49:40 PM UTC 25 16453416585 ps
T434 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1599387234 Feb 08 06:49:39 PM UTC 25 Feb 08 06:49:42 PM UTC 25 134055832 ps
T56 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1851714234 Feb 08 06:48:28 PM UTC 25 Feb 08 06:49:42 PM UTC 25 11584492821 ps
T195 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2497019429 Feb 08 06:49:14 PM UTC 25 Feb 08 06:49:42 PM UTC 25 1356281753 ps
T57 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3213895561 Feb 08 06:48:05 PM UTC 25 Feb 08 06:49:43 PM UTC 25 5060844482 ps
T435 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.1520201636 Feb 08 06:49:41 PM UTC 25 Feb 08 06:49:43 PM UTC 25 24253599 ps
T191 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.3245192082 Feb 08 06:48:41 PM UTC 25 Feb 08 06:49:47 PM UTC 25 14506550013 ps
T261 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2779383183 Feb 08 06:49:41 PM UTC 25 Feb 08 06:49:47 PM UTC 25 1583455444 ps
T436 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.773937541 Feb 08 06:49:43 PM UTC 25 Feb 08 06:49:48 PM UTC 25 72948570 ps
T393 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.4038014804 Feb 08 06:49:19 PM UTC 25 Feb 08 06:49:48 PM UTC 25 13228030969 ps
T70 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.2626094629 Feb 08 06:47:45 PM UTC 25 Feb 08 06:49:49 PM UTC 25 56611064309 ps
T307 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2599215291 Feb 08 06:49:22 PM UTC 25 Feb 08 06:49:51 PM UTC 25 3452783784 ps
T193 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2016766801 Feb 08 06:48:32 PM UTC 25 Feb 08 06:49:53 PM UTC 25 6906535755 ps
T268 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.702906161 Feb 08 06:49:47 PM UTC 25 Feb 08 06:49:53 PM UTC 25 90094890 ps
T437 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3021161558 Feb 08 06:49:48 PM UTC 25 Feb 08 06:49:54 PM UTC 25 623497288 ps
T198 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.997154993 Feb 08 06:48:46 PM UTC 25 Feb 08 06:49:55 PM UTC 25 2526517364 ps
T438 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.660584487 Feb 08 06:49:54 PM UTC 25 Feb 08 06:49:56 PM UTC 25 42642655 ps
T439 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.516585280 Feb 08 06:49:55 PM UTC 25 Feb 08 06:49:57 PM UTC 25 16214083 ps
T440 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.4202156765 Feb 08 06:49:38 PM UTC 25 Feb 08 06:49:58 PM UTC 25 2791582848 ps
T441 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.529514868 Feb 08 06:49:59 PM UTC 25 Feb 08 06:50:01 PM UTC 25 62821574 ps
T442 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3001909145 Feb 08 06:49:57 PM UTC 25 Feb 08 06:50:02 PM UTC 25 571505731 ps
T190 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2624029112 Feb 08 06:47:49 PM UTC 25 Feb 08 06:50:06 PM UTC 25 65282110299 ps
T233 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.3227253053 Feb 08 06:49:43 PM UTC 25 Feb 08 06:50:06 PM UTC 25 9864366277 ps
T189 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.1074103100 Feb 08 06:49:24 PM UTC 25 Feb 08 06:50:07 PM UTC 25 9204095407 ps
T299 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2787429139 Feb 08 06:50:02 PM UTC 25 Feb 08 06:50:08 PM UTC 25 1137798166 ps
T245 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1584473934 Feb 08 06:50:02 PM UTC 25 Feb 08 06:50:08 PM UTC 25 263376251 ps
T443 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.553142567 Feb 08 06:49:59 PM UTC 25 Feb 08 06:50:10 PM UTC 25 374539264 ps
T444 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1925165198 Feb 08 06:50:06 PM UTC 25 Feb 08 06:50:11 PM UTC 25 112657742 ps
T305 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2653517171 Feb 08 06:50:09 PM UTC 25 Feb 08 06:50:13 PM UTC 25 162956945 ps
T194 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.321227359 Feb 08 06:49:10 PM UTC 25 Feb 08 06:50:18 PM UTC 25 24574544196 ps
T312 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.4196395033 Feb 08 06:50:06 PM UTC 25 Feb 08 06:50:20 PM UTC 25 580052189 ps
T445 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3634151216 Feb 08 06:50:12 PM UTC 25 Feb 08 06:50:21 PM UTC 25 323949714 ps
T71 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2343527387 Feb 08 06:47:57 PM UTC 25 Feb 08 06:50:21 PM UTC 25 27591078917 ps
T446 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.1490134512 Feb 08 06:50:21 PM UTC 25 Feb 08 06:50:23 PM UTC 25 35470121 ps
T447 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1575507053 Feb 08 06:49:44 PM UTC 25 Feb 08 06:50:24 PM UTC 25 2850548770 ps
T337 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.3789706437 Feb 08 06:49:43 PM UTC 25 Feb 08 06:51:03 PM UTC 25 23198289871 ps
T448 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.3914818571 Feb 08 06:50:22 PM UTC 25 Feb 08 06:50:24 PM UTC 25 56852745 ps
T391 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1963569209 Feb 08 06:49:38 PM UTC 25 Feb 08 06:50:26 PM UTC 25 2497623536 ps
T449 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2334317026 Feb 08 06:50:25 PM UTC 25 Feb 08 06:50:27 PM UTC 25 54566964 ps
T196 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2372901693 Feb 08 06:49:33 PM UTC 25 Feb 08 06:50:28 PM UTC 25 2140207901 ps
T450 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.3681832218 Feb 08 06:50:25 PM UTC 25 Feb 08 06:50:28 PM UTC 25 22198393 ps
T451 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.3799027293 Feb 08 06:50:24 PM UTC 25 Feb 08 06:50:29 PM UTC 25 734377991 ps
T452 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.3887619144 Feb 08 06:50:09 PM UTC 25 Feb 08 06:50:29 PM UTC 25 888272291 ps
T72 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1673767987 Feb 08 06:47:42 PM UTC 25 Feb 08 06:50:29 PM UTC 25 29125672025 ps
T38 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1660286099 Feb 08 06:47:57 PM UTC 25 Feb 08 06:50:29 PM UTC 25 10924617641 ps
T156 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.1609104192 Feb 08 06:49:43 PM UTC 25 Feb 08 06:50:33 PM UTC 25 7726157747 ps
T157 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.4136559574 Feb 08 06:50:30 PM UTC 25 Feb 08 06:50:35 PM UTC 25 345962975 ps
T158 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1375033229 Feb 08 06:50:27 PM UTC 25 Feb 08 06:50:36 PM UTC 25 1629455018 ps
T159 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.214567015 Feb 08 06:50:28 PM UTC 25 Feb 08 06:50:38 PM UTC 25 1754815218 ps
T160 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3798343318 Feb 08 06:50:30 PM UTC 25 Feb 08 06:50:38 PM UTC 25 230828799 ps
T39 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.3959153945 Feb 08 06:50:39 PM UTC 25 Feb 08 06:50:41 PM UTC 25 75525415 ps
T161 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.279391358 Feb 08 06:49:04 PM UTC 25 Feb 08 06:50:43 PM UTC 25 32216753598 ps
T162 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.3176282353 Feb 08 06:50:14 PM UTC 25 Feb 08 06:50:43 PM UTC 25 1127144455 ps
T185 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.1142013179 Feb 08 06:50:42 PM UTC 25 Feb 08 06:50:44 PM UTC 25 17207968 ps
T453 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3250280186 Feb 08 06:50:34 PM UTC 25 Feb 08 06:50:45 PM UTC 25 1537195003 ps
T380 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.1243695559 Feb 08 06:50:24 PM UTC 25 Feb 08 06:50:45 PM UTC 25 1834894043 ps
T313 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.4159885445 Feb 08 06:50:53 PM UTC 25 Feb 08 06:51:04 PM UTC 25 382000684 ps
T454 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3026169096 Feb 08 06:50:44 PM UTC 25 Feb 08 06:50:46 PM UTC 25 129766987 ps
T285 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.2496764338 Feb 08 06:50:30 PM UTC 25 Feb 08 06:50:47 PM UTC 25 1588214515 ps
T455 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.1290808521 Feb 08 06:50:46 PM UTC 25 Feb 08 06:50:49 PM UTC 25 417582411 ps
T278 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.272194924 Feb 08 06:50:28 PM UTC 25 Feb 08 06:50:49 PM UTC 25 8141572794 ps
T234 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2688691989 Feb 08 06:50:28 PM UTC 25 Feb 08 06:50:51 PM UTC 25 11042065517 ps
T456 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.3707880056 Feb 08 06:50:47 PM UTC 25 Feb 08 06:50:52 PM UTC 25 677998852 ps
T457 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3153571246 Feb 08 06:50:45 PM UTC 25 Feb 08 06:50:53 PM UTC 25 1810021135 ps
T319 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.828626854 Feb 08 06:50:47 PM UTC 25 Feb 08 06:50:53 PM UTC 25 188577616 ps
T200 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1072338477 Feb 08 06:47:45 PM UTC 25 Feb 08 06:50:53 PM UTC 25 81480456233 ps
T328 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2403434159 Feb 08 06:50:49 PM UTC 25 Feb 08 06:50:53 PM UTC 25 82710661 ps
T236 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1366732885 Feb 08 06:47:50 PM UTC 25 Feb 08 06:50:54 PM UTC 25 11088243034 ps
T192 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.407388227 Feb 08 06:50:11 PM UTC 25 Feb 08 06:50:57 PM UTC 25 4803274892 ps
T286 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3124439725 Feb 08 06:50:54 PM UTC 25 Feb 08 06:51:00 PM UTC 25 276668654 ps
T281 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.3664510029 Feb 08 06:50:50 PM UTC 25 Feb 08 06:51:01 PM UTC 25 923573195 ps
T257 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2954852230 Feb 08 06:50:18 PM UTC 25 Feb 08 06:51:01 PM UTC 25 12142070439 ps
T386 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2542025872 Feb 08 06:50:39 PM UTC 25 Feb 08 06:51:01 PM UTC 25 5441197279 ps
T458 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3757918736 Feb 08 06:51:02 PM UTC 25 Feb 08 06:51:05 PM UTC 25 47921320 ps
T459 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.3592484147 Feb 08 06:52:18 PM UTC 25 Feb 08 06:52:27 PM UTC 25 1141916960 ps
T460 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.3808607507 Feb 08 06:51:02 PM UTC 25 Feb 08 06:51:05 PM UTC 25 14910732 ps
T249 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2042726063 Feb 08 06:48:21 PM UTC 25 Feb 08 06:51:07 PM UTC 25 16963226061 ps
T461 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.3508207368 Feb 08 06:51:06 PM UTC 25 Feb 08 06:51:08 PM UTC 25 50078505 ps
T462 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.645427108 Feb 08 06:51:06 PM UTC 25 Feb 08 06:51:09 PM UTC 25 195460140 ps
T463 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.1498344362 Feb 08 06:50:46 PM UTC 25 Feb 08 06:51:10 PM UTC 25 2238025091 ps
T235 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2567025689 Feb 08 06:49:33 PM UTC 25 Feb 08 06:51:10 PM UTC 25 8268305508 ps
T246 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2304236494 Feb 08 06:49:23 PM UTC 25 Feb 08 06:51:11 PM UTC 25 47240371587 ps
T291 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2517775980 Feb 08 06:50:37 PM UTC 25 Feb 08 06:51:11 PM UTC 25 1516278049 ps
T464 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2681013553 Feb 08 06:51:03 PM UTC 25 Feb 08 06:51:12 PM UTC 25 837091066 ps
T465 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2352260357 Feb 08 06:49:58 PM UTC 25 Feb 08 06:51:12 PM UTC 25 17746001541 ps
T297 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.4095936790 Feb 08 06:50:53 PM UTC 25 Feb 08 06:51:15 PM UTC 25 5666150733 ps
T338 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.882374442 Feb 08 06:51:08 PM UTC 25 Feb 08 06:51:15 PM UTC 25 105861084 ps
T385 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.2859855530 Feb 08 06:51:03 PM UTC 25 Feb 08 06:51:15 PM UTC 25 1219828296 ps
T302 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3275890379 Feb 08 06:51:11 PM UTC 25 Feb 08 06:51:16 PM UTC 25 86226879 ps
T292 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.2774330503 Feb 08 06:51:06 PM UTC 25 Feb 08 06:51:18 PM UTC 25 2392482105 ps
T466 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.2479034209 Feb 08 06:51:16 PM UTC 25 Feb 08 06:51:19 PM UTC 25 14492268 ps
T467 /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.1803624127 Feb 08 06:51:17 PM UTC 25 Feb 08 06:51:19 PM UTC 25 115689270 ps
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