Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg

Group : spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	4	6	60.00
Crosses	4	3	1	25.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mailbox_en	2	0	2	100.00	100	1	1	2
cp_rx_order	2	1	1	50.00	100	1	1	2
cp_tx_order	2	1	1	50.00	100	1	1	2
rx_order	2	1	1	50.00	100	1	1	2
tx_order	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_order	4	3	1	25.00	100	1	1	0

Summary for Variable cp_mailbox_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_mailbox_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57391

1

T3

8

T4

2

T5

515

auto[1]

75601

1

T7

26

T8

16

T10

1

---

Summary for Variable cp_rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_rx_order

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132992

1

T3

8

T4

2

T5

515

---

Summary for Variable cp_tx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_tx_order

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132992

1

T3

8

T4

2

T5

515

---

Summary for Variable rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for rx_order

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132992

1

T3

8

T4

2

T5

515

---

Summary for Variable tx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for tx_order

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132992

1

T3

8

T4

2

T5

515

---

Summary for Cross cr_order

Samples crossed: tx_order rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	3	1	25.00	3

Automatically Generated Cross Bins for cr_order

Element holes

tx_order	rx_order	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	2

Uncovered bins

tx_order	rx_order	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	0	1	1

Covered bins

tx_order

rx_order

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

132992

1

T3

8

T4

2

T5

515