Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36422	1			T7	6		T8	6		T13	29
auto[SpiFlashAddrCfg]	8017	1			T13	6		T17	6		T38	8
auto[SpiFlashAddr3b]	9698	1			T7	6		T10	1		T11	2
auto[SpiFlashAddr4b]	8092	1			T8	6		T36	2		T49	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35344

1

T7

12

T10

1

T11

2

auto[1]

26885

1

T8

12

T49

14

T38

11

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33187

1

T8

6

T11

2

T13

10

auto[1]

29042

1

T7

12

T8

6

T10

1

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41522	1			T7	6		T8	10		T13	33
values[1]	1115	1			T21	4		T43	1		T112	2
values[2]	1515	1			T7	6		T10	1		T11	2
values[3]	1502	1			T21	4		T43	2		T50	2
values[4]	1587	1			T21	2		T43	10		T109	2
values[5]	1580	1			T38	1		T21	4		T43	2
values[6]	1509	1			T38	3		T21	5		T43	10
values[7]	1664	1			T13	4		T38	1		T21	5
values[8]	10235	1			T8	2		T13	4		T17	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31726

1

T7

12

T8

12

T11

2

auto[1]

30503

1

T10

1

T38

20

T21

113

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58769

1

T7

12

T8

12

T10

1

write

3460

1

T36

4

T49

6

T38

3

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20532

1

T7

6

T8

2

T11

2

valids[0x1]

41697

1

T7

6

T8

10

T10

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1572	1			T7	2		T8	2		T49	2
internal_process_ops[0x5a]	1665	1			T13	4		T18	4		T49	2
internal_process_ops[0x05]	21745	1			T7	4		T13	29		T18	2
internal_process_ops[0x35]	1684	1			T21	7		T43	3		T61	6
internal_process_ops[0x15]	1634	1			T21	1		T109	2		T48	6
internal_process_ops[0x03]	1084	1			T10	1		T21	1		T43	6
internal_process_ops[0x0b]	1126	1			T8	4		T17	2		T36	2
internal_process_ops[0x3b]	1128	1			T7	6		T11	2		T21	4
internal_process_ops[0x6b]	1048	1			T38	1		T21	2		T43	3
internal_process_ops[0xbb]	1082	1			T36	2		T38	2		T43	9
internal_process_ops[0xeb]	1124	1			T21	1		T43	7		T51	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60537

1

T7

12

T8

12

T10

1

auto[1]

1692

1

T49

6

T38

3

T21

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59664

1

T7

12

T8

12

T10

1

auto[1]

2565

1

T13

2

T36

4

T38

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10384

1

T7

6

T13

29

T18

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6645

1

T8

6

T49

4

T43

11

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2185

1

T13

6

T17

6

T43

23

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1849

1

T43

9

T51

4

T52

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2588

1

T7

6

T11

2

T13

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2245

1

T49

2

T43

9

T52

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2095

1

T36

2

T43

14

T50

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2077

1

T8

6

T49

2

T43

22

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

96

1

T78

1

T54

2

T47

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

97

1

T57

1

T175

2

T176

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

114

1

T55

2

T54

3

T47

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

121

1

T49

6

T43

1

T55

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

113

1

T53

2

T54

2

T147

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T55

1

T54

1

T47

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

125

1

T55

4

T175

1

T177

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

116

1

T56

4

T54

1

T175

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

162

1

T36

4

T50

4

T78

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

86

1

T43

2

T58

1

T175

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

87

1

T54

1

T147

1

T178

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

84

1

T43

1

T58

4

T33

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

100

1

T55

4

T54

3

T58

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

91

1

T43

1

T54

2

T57

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

76

1

T43

3

T54

4

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T43

1

T51

2

T54

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11172

1

T38

2

T21

37

T48

81

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7346

1

T21

19

T48

237

T63

126

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1531

1

T38

1

T21

5

T48

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1575

1

T38

7

T21

8

T48

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2014

1

T10

1

T38

3

T21

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1960

1

T38

1

T21

4

T48

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1645

1

T38

3

T21

7

T48

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1458

1

T21

5

T48

4

T63

13

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

128

1

T21

1

T48

2

T63

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

111

1

T32

2

T98

1

T179

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

107

1

T32

1

T98

3

T34

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

101

1

T38

3

T21

1

T63

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

99

1

T48

1

T63

2

T32

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

109

1

T48

1

T32

3

T179

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

110

1

T63

2

T32

2

T179

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

116

1

T21

1

T32

1

T98

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

114

1

T21

5

T48

1

T63

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

119

1

T21

2

T48

2

T63

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

119

1

T98

2

T34

2

T89

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

120

1

T48

4

T63

2

T180

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

106

1

T21

1

T32

1

T181

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

110

1

T63

4

T32

1

T179

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

112

1

T48

1

T98

1

T179

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

121

1

T21

1

T48

2

T98

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4079	1			T8	2		T13	2		T17	4
auto[0]	values[0]	valids[0x1]	16007	1			T7	6		T8	8		T13	31
auto[0]	values[1]	valids[0x1]	554	1			T43	1		T112	2		T55	5
auto[0]	values[2]	valids[0x0]	602	1			T7	6		T11	2		T43	3
auto[0]	values[2]	valids[0x1]	277	1			T43	4		T78	2		T55	1
auto[0]	values[3]	valids[0x0]	561	1			T43	1		T55	8		T54	9
auto[0]	values[3]	valids[0x1]	281	1			T43	1		T50	2		T55	3
auto[0]	values[4]	valids[0x0]	587	1			T43	6		T109	2		T52	2
auto[0]	values[4]	valids[0x1]	348	1			T43	4		T55	2		T54	3
auto[0]	values[5]	valids[0x0]	601	1			T43	1		T109	6		T55	7
auto[0]	values[5]	valids[0x1]	260	1			T43	1		T50	2		T124	2
auto[0]	values[6]	valids[0x0]	580	1			T43	7		T46	6		T55	3
auto[0]	values[6]	valids[0x1]	283	1			T43	3		T55	5		T54	2
auto[0]	values[7]	valids[0x0]	593	1			T43	3		T112	2		T51	8
auto[0]	values[7]	valids[0x1]	350	1			T13	4		T43	1		T50	2
auto[0]	values[8]	valids[0x0]	3679	1			T17	2		T36	4		T49	2
auto[0]	values[8]	valids[0x1]	2084	1			T8	2		T13	4		T17	2
auto[1]	values[0]	valids[0x0]	4257	1			T38	1		T21	22		T48	46
auto[1]	values[0]	valids[0x1]	17179	1			T38	5		T21	49		T48	283
auto[1]	values[1]	valids[0x1]	561	1			T21	4		T48	5		T111	1
auto[1]	values[2]	valids[0x0]	386	1			T21	1		T48	5		T63	3
auto[1]	values[2]	valids[0x1]	250	1			T10	1		T21	1		T48	4
auto[1]	values[3]	valids[0x0]	376	1			T21	2		T63	3		T182	1
auto[1]	values[3]	valids[0x1]	284	1			T21	2		T48	3		T63	4
auto[1]	values[4]	valids[0x0]	373	1			T48	1		T63	9		T32	4
auto[1]	values[4]	valids[0x1]	279	1			T21	2		T48	4		T63	1
auto[1]	values[5]	valids[0x0]	431	1			T38	1		T21	4		T48	6
auto[1]	values[5]	valids[0x1]	288	1			T48	4		T63	7		T32	1
auto[1]	values[6]	valids[0x0]	377	1			T63	4		T154	1		T32	9
auto[1]	values[6]	valids[0x1]	269	1			T38	3		T21	5		T48	4
auto[1]	values[7]	valids[0x0]	437	1			T38	1		T21	1		T63	8
auto[1]	values[7]	valids[0x1]	284	1			T21	4		T48	2		T63	6
auto[1]	values[8]	valids[0x0]	2613	1			T38	6		T21	11		T48	14
auto[1]	values[8]	valids[0x1]	1859	1			T38	3		T21	5		T48	27