Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37853	1			T14	14		T16	8		T19	2
auto[SpiFlashAddrCfg]	7725	1			T18	2		T19	2		T22	2
auto[SpiFlashAddr3b]	9565	1			T15	1		T16	8		T18	1
auto[SpiFlashAddr4b]	7659	1			T16	2		T19	4		T24	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35574

1

T14

14

T15

1

T16

18

auto[1]

27228

1

T24

12

T26

10

T52

7

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33898

1

T14

14

T15

1

T16

10

auto[1]

28904

1

T16

8

T19

2

T22

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42685	1			T14	14		T16	8		T19	2
values[1]	1107	1			T25	4		T58	2		T66	4
values[2]	1441	1			T15	1		T16	2		T75	4
values[3]	1436	1			T19	2		T51	2		T130	3
values[4]	1484	1			T24	2		T43	2		T64	4
values[5]	1452	1			T62	4		T95	2		T65	2
values[6]	1507	1			T16	4		T19	4		T25	2
values[7]	1547	1			T62	12		T75	4		T61	1
values[8]	10143	1			T16	4		T18	3		T24	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34425

1

T14

14

T16

18

T19

8

auto[1]

28377

1

T15

1

T18

3

T61

119

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

59398

1

T14

14

T15

1

T16

18

write

3404

1

T25

8

T26

2

T52

1

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19886

1

T14

14

T15

1

T16

2

valids[0x1]

42916

1

T16

16

T18

1

T19

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1694	1			T16	4		T25	2		T26	2
internal_process_ops[0x5a]	1705	1			T65	2		T120	4		T58	1
internal_process_ops[0x05]	23124	1			T22	4		T25	146		T26	2
internal_process_ops[0x35]	1664	1			T16	4		T52	2		T188	2
internal_process_ops[0x15]	1670	1			T19	2		T26	2		T52	3
internal_process_ops[0x03]	1077	1			T16	2		T24	2		T62	4
internal_process_ops[0x0b]	1112	1			T16	4		T18	1		T24	2
internal_process_ops[0x3b]	1116	1			T62	4		T61	1		T129	2
internal_process_ops[0x6b]	1089	1			T16	2		T43	6		T52	1
internal_process_ops[0xbb]	1103	1			T15	1		T16	2		T18	2
internal_process_ops[0xeb]	1119	1			T19	2		T52	1		T65	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61179

1

T14

14

T15

1

T16

18

auto[1]

1623

1

T26

2

T52

1

T61

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60264

1

T14

14

T15

1

T16

18

auto[1]

2538

1

T22

2

T25

8

T52

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12156

1

T14

14

T16

8

T19

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7588

1

T26

6

T52

3

T67

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2174

1

T19

2

T22

2

T25

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1825

1

T24

6

T52

2

T75

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2721

1

T16

8

T25

2

T43

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2202

1

T67

4

T37

4

T55

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2050

1

T16

2

T19

4

T43

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1975

1

T24

6

T26

2

T52

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

139

1

T37

2

T189

2

T72

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

109

1

T69

3

T57

2

T72

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

99

1

T37

2

T44

1

T69

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

129

1

T67

10

T190

2

T72

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

127

1

T44

1

T57

3

T70

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

91

1

T52

1

T37

1

T57

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

98

1

T57

1

T72

3

T162

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

110

1

T26

2

T37

1

T55

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

134

1

T25

8

T51

2

T122

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

104

1

T57

1

T70

4

T190

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

93

1

T44

1

T72

6

T162

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

83

1

T69

1

T190

1

T38

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

114

1

T37

2

T57

2

T191

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

98

1

T57

5

T70

2

T72

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

106

1

T190

2

T72

2

T38

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T44

1

T57

1

T71

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9827

1

T61

13

T58

12

T119

6

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7395

1

T61

88

T58

6

T119

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1526

1

T18

2

T61

2

T129

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1362

1

T61

1

T58

2

T119

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1923

1

T15

1

T18

1

T61

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1849

1

T61

7

T58

4

T59

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1413

1

T61

2

T129

2

T130

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1412

1

T61

2

T58

2

T119

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

108

1

T60

3

T115

1

T192

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

118

1

T115

1

T56

1

T193

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

93

1

T115

1

T56

5

T194

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

92

1

T60

1

T195

1

T196

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

117

1

T197

2

T198

3

T196

6

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

88

1

T60

4

T198

1

T196

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

111

1

T60

1

T193

2

T194

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

96

1

T61

1

T60

2

T115

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

114

1

T59

1

T60

1

T199

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

116

1

T60

2

T115

1

T56

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

116

1

T199

1

T115

2

T196

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T196

1

T200

3

T201

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T61

2

T60

1

T56

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

96

1

T200

1

T202

1

T201

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

101

1

T60

2

T56

2

T194

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

83

1

T58

2

T59

3

T108

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4172	1			T14	14		T22	4		T23	2
auto[0]	values[0]	valids[0x1]	18675	1			T16	8		T19	2		T22	4
auto[0]	values[1]	valids[0x1]	598	1			T25	4		T66	4		T121	8
auto[0]	values[2]	valids[0x0]	494	1			T131	2		T203	6		T37	2
auto[0]	values[2]	valids[0x1]	314	1			T16	2		T75	4		T57	1
auto[0]	values[3]	valids[0x0]	577	1			T19	2		T51	2		T94	4
auto[0]	values[3]	valids[0x1]	283	1			T44	3		T204	4		T69	2
auto[0]	values[4]	valids[0x0]	563	1			T43	2		T64	4		T203	4
auto[0]	values[4]	valids[0x1]	295	1			T24	2		T51	4		T37	1
auto[0]	values[5]	valids[0x0]	553	1			T62	4		T95	2		T65	2
auto[0]	values[5]	valids[0x1]	312	1			T205	2		T206	2		T69	2
auto[0]	values[6]	valids[0x0]	593	1			T19	4		T25	2		T52	3
auto[0]	values[6]	valids[0x1]	324	1			T16	4		T55	6		T204	2
auto[0]	values[7]	valids[0x0]	587	1			T62	8		T75	4		T207	2
auto[0]	values[7]	valids[0x1]	289	1			T62	4		T44	1		T69	1
auto[0]	values[8]	valids[0x0]	3569	1			T16	2		T24	2		T43	6
auto[0]	values[8]	valids[0x1]	2227	1			T16	2		T24	4		T25	4
auto[1]	values[0]	valids[0x0]	4018	1			T61	12		T58	7		T119	5
auto[1]	values[0]	valids[0x1]	15820	1			T61	91		T58	13		T119	3
auto[1]	values[1]	valids[0x1]	509	1			T58	2		T119	1		T60	4
auto[1]	values[2]	valids[0x0]	370	1			T15	1		T61	3		T59	2
auto[1]	values[2]	valids[0x1]	263	1			T60	4		T199	1		T115	2
auto[1]	values[3]	valids[0x0]	351	1			T130	3		T58	1		T132	1
auto[1]	values[3]	valids[0x1]	225	1			T58	1		T59	2		T60	5
auto[1]	values[4]	valids[0x0]	404	1			T60	6		T115	1		T208	3
auto[1]	values[4]	valids[0x1]	222	1			T60	1		T193	6		T198	4
auto[1]	values[5]	valids[0x0]	334	1			T132	1		T59	1		T60	3
auto[1]	values[5]	valids[0x1]	253	1			T59	3		T60	4		T199	1
auto[1]	values[6]	valids[0x0]	359	1			T60	2		T199	4		T56	2
auto[1]	values[6]	valids[0x1]	231	1			T58	3		T209	1		T59	2
auto[1]	values[7]	valids[0x0]	409	1			T58	3		T59	5		T60	1
auto[1]	values[7]	valids[0x1]	262	1			T61	1		T59	1		T60	2
auto[1]	values[8]	valids[0x0]	2533	1			T18	2		T61	9		T129	6
auto[1]	values[8]	valids[0x1]	1814	1			T18	1		T61	3		T58	2