Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3476846

1

T4

1

T7

381

T8

1

auto[1]

34780

1

T13

25

T36

64

T38

7

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

941453

1

T4

1

T7

381

T8

1

auto[1]

2570173

1

T13

4507

T36

64

T21

5096

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	657336	1			T4	1		T7	110		T8	1
auto[524288:1048575]	400803	1			T7	187		T18	29		T19	1
auto[1048576:1572863]	394905	1			T7	70		T18	137		T19	134
auto[1572864:2097151]	467569	1			T18	1		T19	113		T21	6
auto[2097152:2621439]	431539	1			T10	2		T11	3672		T18	77
auto[2621440:3145727]	384888	1			T9	3		T11	4		T18	116
auto[3145728:3670015]	348176	1			T7	11		T18	2		T19	1
auto[3670016:4194303]	426410	1			T7	3		T18	58		T60	661

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2607025

1

T4

1

T7

27

T8

1

auto[1]

904601

1

T7

354

T9

495

T10

30

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3023231

1

T4

1

T7

381

T8

1

auto[1]

488395

1

T21

562

T43

334

T80

35

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	198184	1			T4	1		T7	110		T8	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	388041	1			T13	4484		T36	4		T21	512
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	88234	1			T7	187		T18	29		T19	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	259199	1			T21	1432		T63	129		T78	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	100591	1			T7	70		T18	137		T19	134
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	236047	1			T21	512		T43	512		T48	260
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	105082	1			T18	1		T19	113		T21	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	280437	1			T21	4		T43	694		T48	770
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	125313	1			T10	2		T11	3672		T18	77
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	257420	1			T21	1823		T43	15		T48	512
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	103789	1			T9	3		T11	4		T18	116
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	223825	1			T43	2641		T48	695		T78	2880
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	98495	1			T7	11		T18	2		T19	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	196204	1			T48	260		T63	2717		T55	256
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	105630	1			T7	3		T18	58		T60	661
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	227161	1			T21	261		T48	4081		T63	440
auto[0]	auto[1]	auto[0:524287]	auto[0]	2610	1			T21	1		T48	5		T63	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	63082	1			T21	408		T48	421		T54	3360
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	869	1			T21	1		T43	19		T48	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	48430	1			T48	512		T54	516		T57	520
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1285	1			T43	18		T48	6		T63	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	52008	1			T48	2		T63	642		T47	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1531	1			T43	4		T48	1		T63	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	76021	1			T43	256		T63	129		T78	1559
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1431	1			T21	3		T43	22		T80	26
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	43851	1			T21	6		T48	512		T63	1645
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	904	1			T43	6		T80	9		T48	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	51384	1			T48	484		T58	4		T32	262
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1574	1			T21	2		T48	2		T55	6
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	49884	1			T21	128		T48	19		T63	768
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1314	1			T21	1		T48	4		T63	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	87016	1			T21	1		T48	1		T63	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	713	1			T13	2		T36	4		T38	7
auto[1]	auto[0]	auto[0:524287]	auto[1]	3985	1			T13	23		T36	60		T50	5
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	440	1			T63	1		T78	1		T54	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3337	1			T63	7		T78	3		T54	56
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	430	1			T43	5		T48	1		T63	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3739	1			T43	5		T48	1		T63	11
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	428	1			T43	15		T48	2		T63	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2820	1			T48	28		T63	21		T58	15
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	486	1			T21	1		T63	3		T54	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2442	1			T21	1		T63	4		T54	19
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	459	1			T55	5		T58	2		T204	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	4191	1			T55	1513		T58	8		T204	61
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	426	1			T48	3		T63	1		T55	28
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1220	1			T48	63		T63	1		T57	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	448	1			T63	3		T55	12		T57	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	4015	1			T63	31		T55	1681		T175	40
auto[1]	auto[1]	auto[0:524287]	auto[0]	99	1			T21	1		T48	4		T57	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	622	1			T48	14		T57	1		T32	25
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	65	1			T43	6		T54	2		T57	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	229	1			T54	32		T57	5		T98	20
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	106	1			T48	2		T63	2		T47	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	699	1			T48	105		T63	23		T47	36
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	143	1			T63	1		T58	1		T177	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1107	1			T63	5		T58	3		T177	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	92	1			T21	1		T209	1		T260	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	504	1			T21	1		T209	6		T227	11
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	51	1			T43	3		T32	1		T209	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	285	1			T32	7		T209	7		T71	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	112	1			T32	1		T98	5		T181	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	261	1			T32	2		T181	13		T246	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	119	1			T21	1		T48	1		T63	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	707	1			T21	7		T63	17		T47	72

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2096082	1			T4	1		T7	27		T8	1
auto[0]	auto[0]	auto[1]	897570	1			T7	354		T9	495		T10	30
auto[0]	auto[1]	auto[0]	476877	1			T21	551		T43	325		T80	28
auto[0]	auto[1]	auto[1]	6317	1			T80	7		T54	1		T57	2
auto[1]	auto[0]	auto[0]	28996	1			T13	23		T36	63		T38	5
auto[1]	auto[0]	auto[1]	583	1			T13	2		T36	1		T38	2
auto[1]	auto[1]	auto[0]	5070	1			T21	11		T43	8		T48	126
auto[1]	auto[1]	auto[1]	131	1			T43	1		T47	1		T57	2