Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3650261

1

T6

1

T7

1

T14

162

auto[1]

33701

1

T22

4

T25

144

T52

56

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022749

1

T6

1

T7

1

T14

162

auto[1]

2661213

1

T22

4

T25

144

T52

4748

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	687420	1			T6	1		T7	1		T14	95
auto[524288:1048575]	420050	1			T14	67		T16	12		T23	1
auto[1048576:1572863]	385066	1			T16	70		T23	1		T43	516
auto[1572864:2097151]	431408	1			T18	1		T43	243		T73	61
auto[2097152:2621439]	413330	1			T16	8		T18	1		T23	1596
auto[2621440:3145727]	507825	1			T15	3		T16	2		T18	25
auto[3145728:3670015]	448541	1			T16	4		T73	5		T74	747
auto[3670016:4194303]	390322	1			T16	199		T43	317		T73	27

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2695186

1

T6

1

T7

1

T14

162

auto[1]

988776

1

T15

186

T16

320

T18

37

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3158567

1

T6

1

T7

1

T14

94

auto[1]

525395

1

T14

68

T74

1514

T61

541

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	242251	1			T6	1		T7	1		T14	93
auto[0]	auto[0]	auto[0:524287]	auto[1]	378532	1			T22	2		T25	8		T52	386
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	87367	1			T14	1		T16	12		T23	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	245994	1			T61	2		T37	128		T60	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	122837	1			T16	70		T23	1		T43	516
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	195342	1			T52	1946		T95	68		T58	1049
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	108802	1			T18	1		T43	243		T73	61
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	260084	1			T52	2364		T37	3307		T59	819
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	116817	1			T16	8		T18	1		T23	1596
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	230599	1			T59	512		T60	22		T44	512
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	116813	1			T15	3		T16	2		T18	25
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	308128	1			T60	256		T275	7		T115	870
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	123824	1			T16	4		T73	5		T74	747
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	262643	1			T61	512		T119	640		T37	3153
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	89114	1			T16	199		T43	317		T73	27
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	240720	1			T37	512		T59	256		T60	768
auto[0]	auto[1]	auto[0:524287]	auto[0]	598	1			T14	2		T74	5		T60	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	61251	1			T44	1		T57	1202		T193	533
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2021	1			T14	66		T61	5		T60	29
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	80138	1			T61	1		T199	1257		T57	1810
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2276	1			T74	1509		T59	8		T57	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	61013	1			T190	2674		T71	1		T38	512
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	878	1			T61	3		T60	3		T115	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	57716	1			T61	512		T115	128		T57	3341
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	737	1			T58	7		T287	2		T59	26
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	61750	1			T58	1		T59	798		T60	259
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1460	1			T58	10		T60	4		T115	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	76481	1			T115	5		T69	132		T70	1286
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1597	1			T58	13		T59	16		T44	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	55798	1			T115	2336		T56	520		T196	385
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1151	1			T58	9		T60	2		T57	10
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	55529	1			T193	1611		T198	256		T71	384
auto[1]	auto[0]	auto[0:524287]	auto[0]	511	1			T22	2		T25	8		T52	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3653	1			T22	2		T25	136		T52	34
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	440	1			T61	2		T44	1		T115	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3411	1			T61	57		T44	34		T115	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	376	1			T52	2		T58	3		T37	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2263	1			T52	18		T58	103		T37	25
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	416	1			T37	3		T59	12		T56	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2538	1			T37	63		T193	29		T71	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	357	1			T69	1		T193	1		T190	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2731	1			T69	2		T190	13		T71	36
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	541	1			T59	3		T115	1		T57	8
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3968	1			T193	6		T196	24		T72	12
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	429	1			T60	5		T56	9		T57	9
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3550	1			T56	4		T57	161		T70	26
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	360	1			T60	2		T56	3		T195	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3156	1			T195	5		T70	1		T198	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	68	1			T44	1		T288	4		T102	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	556	1			T44	2		T102	6		T289	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	101	1			T61	1		T57	12		T193	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	578	1			T61	19		T193	2		T162	100
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	100	1			T71	1		T236	2		T235	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	859	1			T71	3		T236	8		T235	46
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	130	1			T60	4		T57	11		T249	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	844	1			T249	15		T104	13		T202	34
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	81	1			T59	11		T190	1		T71	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	258	1			T190	7		T236	14		T105	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	119	1			T198	1		T290	12		T101	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	315	1			T198	2		T290	2		T101	8
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	78	1			T56	9		T196	1		T38	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	622	1			T196	6		T38	63		T104	32
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	99	1			T57	6		T257	1		T249	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	193	1			T257	2		T249	10		T263	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2147596	1			T6	1		T7	1		T14	94
auto[0]	auto[0]	auto[1]	982271	1			T15	186		T16	320		T18	37
auto[0]	auto[1]	auto[0]	514619	1			T14	68		T74	4		T61	521
auto[0]	auto[1]	auto[1]	5775	1			T74	1510		T196	1		T38	2
auto[1]	auto[0]	auto[0]	28103	1			T22	3		T25	143		T52	56
auto[1]	auto[0]	auto[1]	597	1			T22	1		T25	1		T51	2
auto[1]	auto[1]	auto[0]	4868	1			T61	20		T59	10		T60	3
auto[1]	auto[1]	auto[1]	133	1			T59	1		T60	1		T56	1