Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2677279	1			T1	542		T2	1		T3	1
all_pins[1]	2677279	1			T1	542		T2	1		T3	1
all_pins[2]	2677279	1			T1	542		T2	1		T3	1
all_pins[3]	2677279	1			T1	542		T2	1		T3	1
all_pins[4]	2677279	1			T1	542		T2	1		T3	1
all_pins[5]	2677279	1			T1	542		T2	1		T3	1
all_pins[6]	2677279	1			T1	542		T2	1		T3	1
all_pins[7]	2677279	1			T1	542		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21278310	1			T1	4336		T2	8		T3	8
values[0x1]	139922	1			T37	9		T38	115		T39	30
transitions[0x0=>0x1]	138287	1			T37	9		T38	113		T39	23
transitions[0x1=>0x0]	138296	1			T37	9		T38	113		T39	23

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2676357	1			T1	542		T2	1		T3	1
all_pins[0]	values[0x1]	922	1			T37	1		T38	1		T39	5
all_pins[0]	transitions[0x0=>0x1]	524	1			T37	1		T39	5		T101	5
all_pins[0]	transitions[0x1=>0x0]	178	1			T38	1		T39	2		T101	5
all_pins[1]	values[0x0]	2676703	1			T1	542		T2	1		T3	1
all_pins[1]	values[0x1]	576	1			T38	2		T39	2		T101	6
all_pins[1]	transitions[0x0=>0x1]	485	1			T38	2		T39	1		T101	6
all_pins[1]	transitions[0x1=>0x0]	166	1			T39	5		T101	1		T102	6
all_pins[2]	values[0x0]	2677022	1			T1	542		T2	1		T3	1
all_pins[2]	values[0x1]	257	1			T39	6		T101	1		T102	6
all_pins[2]	transitions[0x0=>0x1]	214	1			T39	5		T101	1		T102	4
all_pins[2]	transitions[0x1=>0x0]	134	1			T37	2		T39	2		T40	1
all_pins[3]	values[0x0]	2677102	1			T1	542		T2	1		T3	1
all_pins[3]	values[0x1]	177	1			T37	2		T39	3		T40	1
all_pins[3]	transitions[0x0=>0x1]	134	1			T37	2		T39	2		T40	1
all_pins[3]	transitions[0x1=>0x0]	140	1			T37	1		T38	2		T39	3
all_pins[4]	values[0x0]	2677096	1			T1	542		T2	1		T3	1
all_pins[4]	values[0x1]	183	1			T37	1		T38	2		T39	4
all_pins[4]	transitions[0x0=>0x1]	145	1			T37	1		T38	2		T39	4
all_pins[4]	transitions[0x1=>0x0]	1822	1			T37	1		T38	105		T39	3
all_pins[5]	values[0x0]	2675419	1			T1	542		T2	1		T3	1
all_pins[5]	values[0x1]	1860	1			T37	1		T38	105		T39	3
all_pins[5]	transitions[0x0=>0x1]	923	1			T37	1		T38	105		T39	1
all_pins[5]	transitions[0x1=>0x0]	134831	1			T37	2		T38	1		T39	2
all_pins[6]	values[0x0]	2541511	1			T1	542		T2	1		T3	1
all_pins[6]	values[0x1]	135768	1			T37	2		T38	1		T39	4
all_pins[6]	transitions[0x0=>0x1]	135732	1			T37	2		T39	4		T101	2
all_pins[6]	transitions[0x1=>0x0]	143	1			T37	2		T38	3		T39	3
all_pins[7]	values[0x0]	2677100	1			T1	542		T2	1		T3	1
all_pins[7]	values[0x1]	179	1			T37	2		T38	4		T39	3
all_pins[7]	transitions[0x0=>0x1]	130	1			T37	2		T38	4		T39	1
all_pins[7]	transitions[0x1=>0x0]	882	1			T37	1		T38	1		T39	3