Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20017

1

T14

14

T16

18

T19

8

auto[1]

14408

1

T24

12

T26

10

T52

7

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4472	1			T14	14		T22	8		T23	2
values[1]	4405	1			T73	18		T120	4		T55	26
values[2]	4204	1			T43	16		T74	6		T75	16
values[3]	4554	1			T62	20		T205	10		T204	24
values[4]	4137	1			T19	8		T24	12		T95	4
values[5]	4976	1			T16	18		T25	166		T52	76
values[6]	3981	1			T64	14		T145	2		T122	18
values[7]	3696	1			T26	10		T67	22		T44	55

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4737	1			T25	166		T26	10		T205	10
values[1]	3363	1			T24	12		T67	22		T121	20
values[2]	4814	1			T75	16		T95	4		T203	22
values[3]	4044	1			T19	8		T22	8		T62	20
values[4]	4865	1			T188	4		T94	10		T265	4
values[5]	3856	1			T43	16		T52	76		T96	4
values[6]	4073	1			T16	18		T23	2		T73	18
values[7]	4673	1			T14	14		T74	6		T64	14

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	342	1			T236	12		T102	21		T283	11
auto[0]	values[0]	values[1]	141	1			T121	20		T292	18		T293	20
auto[0]	values[0]	values[2]	281	1			T294	12		T273	20		T295	11
auto[0]	values[0]	values[3]	369	1			T22	8		T296	8		T190	53
auto[0]	values[0]	values[4]	372	1			T94	10		T44	10		T162	8
auto[0]	values[0]	values[5]	317	1			T207	12		T69	8		T236	25
auto[0]	values[0]	values[6]	231	1			T23	2		T131	4		T190	26
auto[0]	values[0]	values[7]	466	1			T14	14		T51	49		T260	8
auto[0]	values[1]	values[0]	447	1			T57	17		T261	4		T70	16
auto[0]	values[1]	values[1]	311	1			T249	16		T256	12		T101	14
auto[0]	values[1]	values[2]	278	1			T72	12		T297	20		T298	14
auto[0]	values[1]	values[3]	236	1			T120	4		T57	13		T71	12
auto[0]	values[1]	values[4]	217	1			T162	7		T266	10		T280	14
auto[0]	values[1]	values[5]	349	1			T244	10		T156	16		T229	10
auto[0]	values[1]	values[6]	400	1			T73	18		T57	11		T72	12
auto[0]	values[1]	values[7]	345	1			T70	14		T38	12		T251	10
auto[0]	values[2]	values[0]	195	1			T57	12		T236	14		T249	9
auto[0]	values[2]	values[1]	202	1			T299	6		T72	6		T300	6
auto[0]	values[2]	values[2]	286	1			T235	10		T223	11		T301	16
auto[0]	values[2]	values[3]	342	1			T72	13		T159	4		T235	11
auto[0]	values[2]	values[4]	295	1			T188	4		T37	8		T44	11
auto[0]	values[2]	values[5]	264	1			T43	16		T190	16		T71	16
auto[0]	values[2]	values[6]	261	1			T236	8		T235	14		T293	12
auto[0]	values[2]	values[7]	524	1			T74	6		T37	80		T69	22
auto[0]	values[3]	values[0]	257	1			T205	10		T101	12		T252	8
auto[0]	values[3]	values[1]	340	1			T237	8		T105	6		T263	11
auto[0]	values[3]	values[2]	270	1			T38	13		T302	4		T303	6
auto[0]	values[3]	values[3]	461	1			T62	20		T304	22		T190	7
auto[0]	values[3]	values[4]	405	1			T57	12		T305	18		T249	46
auto[0]	values[3]	values[5]	361	1			T204	24		T57	15		T189	63
auto[0]	values[3]	values[6]	155	1			T235	13		T246	12		T306	4
auto[0]	values[3]	values[7]	502	1			T307	4		T71	23		T72	7
auto[0]	values[4]	values[0]	513	1			T57	12		T104	11		T308	10
auto[0]	values[4]	values[1]	284	1			T70	24		T104	12		T229	6
auto[0]	values[4]	values[2]	391	1			T95	4		T309	10		T57	16
auto[0]	values[4]	values[3]	275	1			T19	8		T65	8		T267	2
auto[0]	values[4]	values[4]	268	1			T72	14		T236	12		T101	20
auto[0]	values[4]	values[5]	268	1			T280	23		T179	9		T224	22
auto[0]	values[4]	values[6]	304	1			T63	18		T116	4		T69	13
auto[0]	values[4]	values[7]	343	1			T104	21		T223	16		T310	23
auto[0]	values[5]	values[0]	586	1			T25	166		T57	7		T190	18
auto[0]	values[5]	values[1]	161	1			T187	13		T311	4		T80	13
auto[0]	values[5]	values[2]	634	1			T312	6		T71	39		T38	13
auto[0]	values[5]	values[3]	286	1			T37	8		T72	9		T235	16
auto[0]	values[5]	values[4]	232	1			T265	4		T69	12		T38	8
auto[0]	values[5]	values[5]	342	1			T52	69		T96	4		T287	8
auto[0]	values[5]	values[6]	602	1			T16	18		T68	8		T57	10
auto[0]	values[5]	values[7]	276	1			T72	14		T313	6		T228	24
auto[0]	values[6]	values[0]	170	1			T238	29		T230	2		T179	10
auto[0]	values[6]	values[1]	316	1			T229	14		T105	103		T280	10
auto[0]	values[6]	values[2]	217	1			T314	6		T249	9		T263	8
auto[0]	values[6]	values[3]	250	1			T315	10		T238	13		T316	4
auto[0]	values[6]	values[4]	280	1			T249	13		T229	17		T277	18
auto[0]	values[6]	values[5]	274	1			T236	15		T229	11		T101	9
auto[0]	values[6]	values[6]	333	1			T122	18		T38	78		T317	14
auto[0]	values[6]	values[7]	214	1			T64	14		T145	2		T318	2
auto[0]	values[7]	values[0]	305	1			T319	4		T236	9		T281	4
auto[0]	values[7]	values[1]	162	1			T320	8		T271	22		T90	2
auto[0]	values[7]	values[2]	247	1			T235	36		T104	16		T293	7
auto[0]	values[7]	values[3]	305	1			T236	12		T238	31		T266	9
auto[0]	values[7]	values[4]	288	1			T69	9		T190	10		T72	8
auto[0]	values[7]	values[5]	252	1			T44	44		T277	13		T321	6
auto[0]	values[7]	values[6]	223	1			T236	15		T229	13		T322	18
auto[0]	values[7]	values[7]	194	1			T71	11		T308	12		T323	24
auto[1]	values[0]	values[0]	265	1			T236	20		T102	8		T283	9
auto[1]	values[0]	values[1]	148	1			T293	5		T179	10		T80	65
auto[1]	values[0]	values[2]	306	1			T203	22		T273	91		T295	9
auto[1]	values[0]	values[3]	223	1			T190	6		T236	20		T223	7
auto[1]	values[0]	values[4]	527	1			T44	14		T162	125		T235	10
auto[1]	values[0]	values[5]	263	1			T69	12		T236	5		T238	58
auto[1]	values[0]	values[6]	119	1			T190	12		T308	24		T243	9
auto[1]	values[0]	values[7]	102	1			T38	8		T235	8		T324	8
auto[1]	values[1]	values[0]	331	1			T206	16		T57	23		T70	56
auto[1]	values[1]	values[1]	178	1			T249	11		T101	11		T102	15
auto[1]	values[1]	values[2]	374	1			T72	97		T179	7		T80	8
auto[1]	values[1]	values[3]	149	1			T57	7		T71	8		T266	5
auto[1]	values[1]	values[4]	258	1			T162	13		T266	15		T280	6
auto[1]	values[1]	values[5]	123	1			T229	10		T238	12		T230	12
auto[1]	values[1]	values[6]	171	1			T57	9		T72	9		T266	12
auto[1]	values[1]	values[7]	238	1			T55	26		T70	6		T38	10
auto[1]	values[2]	values[0]	152	1			T57	8		T236	16		T249	11
auto[1]	values[2]	values[1]	235	1			T72	17		T263	15		T243	8
auto[1]	values[2]	values[2]	208	1			T75	16		T235	20		T223	9
auto[1]	values[2]	values[3]	234	1			T72	7		T235	9		T101	18
auto[1]	values[2]	values[4]	402	1			T37	12		T44	9		T72	33
auto[1]	values[2]	values[5]	173	1			T190	4		T71	4		T72	14
auto[1]	values[2]	values[6]	231	1			T236	12		T235	6		T284	6
auto[1]	values[2]	values[7]	200	1			T37	7		T69	9		T71	6
auto[1]	values[3]	values[0]	264	1			T101	8		T252	12		T179	3
auto[1]	values[3]	values[1]	245	1			T105	42		T263	9		T280	44
auto[1]	values[3]	values[2]	261	1			T38	7		T104	10		T105	66
auto[1]	values[3]	values[3]	212	1			T190	18		T72	10		T104	7
auto[1]	values[3]	values[4]	278	1			T57	8		T249	12		T105	8
auto[1]	values[3]	values[5]	185	1			T57	5		T162	5		T325	8
auto[1]	values[3]	values[6]	157	1			T234	22		T235	7		T80	5
auto[1]	values[3]	values[7]	201	1			T71	12		T72	13		T229	7
auto[1]	values[4]	values[0]	289	1			T57	8		T104	71		T308	23
auto[1]	values[4]	values[1]	195	1			T24	12		T70	16		T104	53
auto[1]	values[4]	values[2]	238	1			T57	4		T229	7		T243	7
auto[1]	values[4]	values[3]	120	1			T69	5		T236	10		T105	4
auto[1]	values[4]	values[4]	166	1			T72	25		T236	21		T101	5
auto[1]	values[4]	values[5]	145	1			T233	22		T280	6		T179	11
auto[1]	values[4]	values[6]	94	1			T69	7		T38	22		T104	7
auto[1]	values[4]	values[7]	244	1			T326	20		T104	110		T223	4
auto[1]	values[5]	values[0]	218	1			T57	13		T190	2		T104	76
auto[1]	values[5]	values[1]	103	1			T187	18		T80	7		T46	13
auto[1]	values[5]	values[2]	297	1			T66	10		T327	4		T71	2
auto[1]	values[5]	values[3]	246	1			T37	38		T72	20		T328	2
auto[1]	values[5]	values[4]	191	1			T69	8		T38	38		T162	9
auto[1]	values[5]	values[5]	166	1			T52	7		T71	7		T223	17
auto[1]	values[5]	values[6]	381	1			T57	10		T70	8		T162	6
auto[1]	values[5]	values[7]	255	1			T72	24		T105	8		T252	10
auto[1]	values[6]	values[0]	207	1			T238	12		T230	18		T179	10
auto[1]	values[6]	values[1]	150	1			T229	6		T105	19		T280	10
auto[1]	values[6]	values[2]	216	1			T249	27		T263	12		T266	65
auto[1]	values[6]	values[3]	188	1			T245	2		T238	90		T271	13
auto[1]	values[6]	values[4]	490	1			T249	7		T229	3		T277	6
auto[1]	values[6]	values[5]	273	1			T236	5		T229	9		T101	11
auto[1]	values[6]	values[6]	184	1			T38	7		T229	9		T293	23
auto[1]	values[6]	values[7]	219	1			T235	3		T251	7		T277	23
auto[1]	values[7]	values[0]	196	1			T26	10		T236	11		T229	6
auto[1]	values[7]	values[1]	192	1			T67	22		T329	6		T271	6
auto[1]	values[7]	values[2]	310	1			T235	9		T104	85		T293	17
auto[1]	values[7]	values[3]	148	1			T236	13		T238	12		T266	11
auto[1]	values[7]	values[4]	196	1			T69	11		T190	10		T72	22
auto[1]	values[7]	values[5]	101	1			T44	11		T277	7		T243	9
auto[1]	values[7]	values[6]	227	1			T236	5		T229	7		T330	20
auto[1]	values[7]	values[7]	350	1			T71	9		T308	8		T323	16