Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	438	1			T16	6		T62	6		T64	2
auto[ReadAddrCrossIntoMailbox]	330	1			T43	6		T62	4		T37	1
auto[ReadAddrCrossOutOfMailbox]	337	1			T43	2		T62	4		T131	2
auto[ReadAddrCrossAllMailbox]	241	1			T43	4		T62	2		T37	1
auto[ReadAddrOutsideMailbox]	3656	1			T16	2		T19	2		T24	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2386

1

T16

4

T19

1

T24

3

auto[1]

2616

1

T16

4

T19

1

T24

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	816	1			T16	2		T24	2		T62	4
read_ops[0x0b]	867	1			T16	4		T24	2		T43	8
read_ops[0x3b]	833	1			T62	4		T63	6		T314	2
read_ops[0x6b]	825	1			T43	6		T52	1		T64	4
read_ops[0xbb]	831	1			T16	2		T24	2		T25	2
read_ops[0xeb]	830	1			T19	2		T52	1		T65	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T62	2		T64	1		T37	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T62	2		T64	1		T44	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T57	1		T71	1		T235	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T235	2		T101	1		T105	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T131	1		T69	1		T38	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T131	1		T44	1		T57	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T308	3		T263	1		T331	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T190	1		T101	1		T105	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	282	1			T16	1		T24	1		T64	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T16	1		T24	1		T64	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T16	2		T190	1		T312	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T16	2		T37	1		T44	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T43	2		T62	1		T57	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T43	2		T62	1		T69	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T62	1		T71	1		T72	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T62	1		T57	1		T71	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T43	1		T72	1		T235	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	29	1			T43	1		T57	1		T71	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	298	1			T24	1		T43	1		T75	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T24	1		T43	1		T75	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T275	1		T69	1		T57	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T275	1		T57	2		T312	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T62	1		T69	1		T190	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T62	1		T37	1		T57	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T62	1		T190	1		T236	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T62	1		T235	1		T105	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T236	1		T104	1		T308	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T57	1		T235	1		T252	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T63	3		T314	1		T55	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T63	3		T314	1		T37	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T275	1		T72	1		T278	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T44	1		T275	1		T69	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T43	1		T69	1		T236	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T43	1		T44	1		T236	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T43	1		T69	2		T57	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T43	1		T44	1		T71	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T43	1		T236	1		T263	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T43	1		T57	1		T190	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T64	2		T51	2		T131	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	322	1			T52	1		T64	2		T51	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T16	1		T62	1		T207	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T16	1		T62	1		T207	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T57	1		T71	1		T72	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T38	1		T236	1		T249	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T57	1		T72	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T44	1		T38	2		T236	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T62	1		T37	1		T57	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T62	1		T236	1		T279	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	318	1			T24	1		T25	1		T43	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T24	1		T25	1		T43	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T275	1		T38	1		T263	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T275	1		T69	1		T71	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T57	2		T72	1		T236	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T236	1		T249	1		T104	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T71	1		T236	1		T105	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T37	1		T190	1		T71	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T44	2		T70	1		T236	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T162	1		T332	1		T178	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T19	1		T65	1		T203	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	339	1			T19	1		T52	1		T65	1