Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	458	1			T43	9		T78	1		T55	5
auto[ReadAddrCrossIntoMailbox]	315	1			T55	2		T54	1		T221	2
auto[ReadAddrCrossOutOfMailbox]	337	1			T43	2		T78	1		T55	3
auto[ReadAddrCrossAllMailbox]	215	1			T43	4		T78	2		T55	2
auto[ReadAddrOutsideMailbox]	3586	1			T7	6		T8	4		T11	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2445

1

T7

3

T8

2

T11

1

auto[1]

2466

1

T7

3

T8

2

T11

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	801	1			T43	6		T50	4		T79	2
read_ops[0x0b]	812	1			T8	4		T36	2		T43	4
read_ops[0x3b]	860	1			T7	6		T11	2		T43	9
read_ops[0x6b]	772	1			T43	3		T52	2		T78	1
read_ops[0xbb]	828	1			T36	2		T43	9		T79	2
read_ops[0xeb]	838	1			T43	7		T51	8		T52	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T221	1		T244	1		T241	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T244	1		T204	1		T33	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T47	1		T176	1		T246	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T221	1		T204	1		T101	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T244	1		T176	1		T263	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T43	1		T54	1		T244	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T176	1		T101	1		T238	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T57	1		T71	1		T194	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T43	3		T50	2		T79	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T43	2		T50	2		T79	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T55	3		T33	1		T233	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T43	1		T55	1		T57	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T221	1		T244	1		T246	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T55	1		T47	2		T244	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T54	1		T175	1		T246	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T78	1		T33	1		T290	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T43	1		T55	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T47	2		T57	2		T263	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T8	2		T36	1		T43	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T8	2		T36	1		T50	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T43	3		T54	1		T244	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T43	1		T47	1		T244	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T57	1		T101	1		T213	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T55	1		T178	1		T65	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T57	1		T175	1		T177	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T176	1		T193	1		T263	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T33	1		T176	1		T246	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T47	1		T101	1		T213	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	321	1			T7	3		T11	1		T43	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T7	3		T11	1		T43	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T175	1		T244	1		T39	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T244	1		T204	1		T264	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T175	1		T33	2		T246	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T54	1		T47	2		T58	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T33	1		T178	1		T246	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	38	1			T55	1		T54	2		T101	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T43	1		T55	1		T47	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T43	1		T78	1		T47	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T52	1		T55	7		T54	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	266	1			T43	1		T52	1		T55	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T43	1		T78	1		T221	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T43	2		T55	1		T47	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T57	1		T204	1		T33	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T74	1		T219	1		T149	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T221	1		T175	1		T204	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T54	2		T39	2		T213	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T43	1		T78	1		T244	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T244	1		T204	2		T259	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T36	1		T43	1		T79	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	289	1			T36	1		T43	4		T79	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T43	1		T54	1		T57	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T58	2		T175	1		T33	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T251	1		T291	1		T213	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T58	1		T33	1		T251	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T55	1		T101	1		T227	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T43	1		T55	1		T54	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T219	1		T292	1		T272	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T54	1		T57	1		T33	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T43	3		T51	4		T52	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T43	2		T51	4		T52	1