Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3898	1			T73	18		T95	4		T51	49
values[1]	4615	1			T62	20		T75	16		T65	8
values[2]	4593	1			T19	8		T67	22		T94	10
values[3]	5171	1			T22	8		T24	12		T327	4
values[4]	4299	1			T16	18		T43	16		T52	76
values[5]	3246	1			T25	166		T64	14		T96	4
values[6]	4186	1			T26	10		T188	4		T37	107
values[7]	4417	1			T14	14		T23	2		T74	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3836	1			T52	76		T265	4		T314	6
values[1]	4301	1			T16	18		T64	14		T188	4
values[2]	3929	1			T19	8		T75	16		T65	8
values[3]	4172	1			T43	16		T74	6		T205	10
values[4]	4292	1			T62	20		T96	4		T66	10
values[5]	4272	1			T26	10		T95	4		T287	8
values[6]	5151	1			T22	8		T23	2		T25	166
values[7]	4472	1			T14	14		T24	12		T73	18

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33601

1

T14

14

T16

18

T19

8

auto[1]

824

1

T26

2

T52

1

T67

10

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	179	1			T314	6		T309	10		T105	22
auto[0]	values[0]	values[1]	389	1			T223	19		T230	25		T283	20
auto[0]	values[0]	values[2]	408	1			T51	49		T71	33		T277	31
auto[0]	values[0]	values[3]	467	1			T63	18		T72	23		T282	22
auto[0]	values[0]	values[4]	466	1			T281	4		T235	45		T326	20
auto[0]	values[0]	values[5]	620	1			T95	4		T239	18		T101	20
auto[0]	values[0]	values[6]	720	1			T71	20		T235	140		T308	32
auto[0]	values[0]	values[7]	563	1			T73	18		T236	17		T104	20
auto[0]	values[1]	values[0]	563	1			T236	20		T252	20		T333	113
auto[0]	values[1]	values[1]	530	1			T145	2		T69	17		T57	19
auto[0]	values[1]	values[2]	820	1			T75	16		T65	8		T68	8
auto[0]	values[1]	values[3]	392	1			T236	20		T105	20		T316	4
auto[0]	values[1]	values[4]	434	1			T62	20		T71	20		T236	20
auto[0]	values[1]	values[5]	666	1			T44	20		T72	109		T105	68
auto[0]	values[1]	values[6]	583	1			T57	15		T158	20		T104	17
auto[0]	values[1]	values[7]	524	1			T207	12		T307	4		T189	63
auto[0]	values[2]	values[0]	446	1			T305	18		T266	24		T280	20
auto[0]	values[2]	values[1]	650	1			T308	32		T101	24		T102	27
auto[0]	values[2]	values[2]	450	1			T19	8		T312	6		T319	4
auto[0]	values[2]	values[3]	714	1			T190	20		T229	18		T105	20
auto[0]	values[2]	values[4]	603	1			T71	20		T246	12		T104	80
auto[0]	values[2]	values[5]	456	1			T162	20		T334	20		T229	19
auto[0]	values[2]	values[6]	476	1			T67	12		T122	18		T296	8
auto[0]	values[2]	values[7]	680	1			T94	10		T69	19		T71	20
auto[0]	values[3]	values[0]	560	1			T236	28		T235	19		T229	17
auto[0]	values[3]	values[1]	443	1			T318	2		T38	71		T238	20
auto[0]	values[3]	values[2]	647	1			T69	20		T101	62		T298	14
auto[0]	values[3]	values[3]	570	1			T57	20		T229	19		T101	19
auto[0]	values[3]	values[4]	703	1			T304	22		T190	20		T72	109
auto[0]	values[3]	values[5]	870	1			T190	58		T104	90		T335	2
auto[0]	values[3]	values[6]	791	1			T22	8		T72	39		T236	29
auto[0]	values[3]	values[7]	458	1			T24	12		T327	4		T162	94
auto[0]	values[4]	values[0]	548	1			T52	75		T69	20		T72	19
auto[0]	values[4]	values[1]	484	1			T16	18		T57	20		T235	20
auto[0]	values[4]	values[2]	277	1			T121	20		T38	22		T328	2
auto[0]	values[4]	values[3]	580	1			T43	16		T205	10		T267	2
auto[0]	values[4]	values[4]	567	1			T70	20		T313	6		T236	25
auto[0]	values[4]	values[5]	557	1			T287	8		T57	19		T223	19
auto[0]	values[4]	values[6]	426	1			T57	40		T249	18		T235	29
auto[0]	values[4]	values[7]	754	1			T104	104		T105	22		T266	76
auto[0]	values[5]	values[0]	495	1			T265	4		T274	28		T263	28
auto[0]	values[5]	values[1]	239	1			T64	14		T37	45		T162	20
auto[0]	values[5]	values[2]	269	1			T159	4		T104	27		T228	24
auto[0]	values[5]	values[3]	401	1			T57	35		T156	16		T104	19
auto[0]	values[5]	values[4]	411	1			T96	4		T191	26		T336	4
auto[0]	values[5]	values[5]	339	1			T71	20		T236	25		T223	20
auto[0]	values[5]	values[6]	513	1			T25	166		T72	28		T278	4
auto[0]	values[5]	values[7]	483	1			T70	20		T337	12		T236	40
auto[0]	values[6]	values[0]	456	1			T72	29		T105	78		T321	6
auto[0]	values[6]	values[1]	605	1			T188	4		T245	2		T38	22
auto[0]	values[6]	values[2]	761	1			T37	86		T70	20		T72	45
auto[0]	values[6]	values[3]	526	1			T116	4		T229	20		T101	29
auto[0]	values[6]	values[4]	556	1			T69	31		T57	40		T38	85
auto[0]	values[6]	values[5]	197	1			T26	8		T37	20		T38	26
auto[0]	values[6]	values[6]	677	1			T38	46		T104	100		T101	44
auto[0]	values[6]	values[7]	308	1			T338	8		T237	8		T277	45
auto[0]	values[7]	values[0]	500	1			T233	22		T38	20		T317	14
auto[0]	values[7]	values[1]	841	1			T261	4		T190	23		T71	43
auto[0]	values[7]	values[2]	210	1			T120	4		T249	27		T339	12
auto[0]	values[7]	values[3]	399	1			T74	6		T260	8		T72	18
auto[0]	values[7]	values[4]	454	1			T66	10		T206	16		T275	14
auto[0]	values[7]	values[5]	482	1			T71	41		T263	28		T340	16
auto[0]	values[7]	values[6]	840	1			T23	2		T131	4		T203	22
auto[0]	values[7]	values[7]	605	1			T14	14		T72	21		T238	64
auto[1]	values[0]	values[0]	4	1			T105	1		T273	1		T341	1
auto[1]	values[0]	values[1]	7	1			T223	1		T230	3		T181	1
auto[1]	values[0]	values[2]	12	1			T71	2		T277	1		T266	3
auto[1]	values[0]	values[3]	19	1			T230	1		T342	1		T343	3
auto[1]	values[0]	values[4]	11	1			T46	2		T344	1		T345	5
auto[1]	values[0]	values[5]	8	1			T293	1		T333	1		T179	1
auto[1]	values[0]	values[6]	15	1			T308	1		T238	1		T254	2
auto[1]	values[0]	values[7]	10	1			T236	3		T346	2		T347	1
auto[1]	values[1]	values[0]	5	1			T333	1		T348	2		T349	1
auto[1]	values[1]	values[1]	15	1			T69	3		T57	1		T102	1
auto[1]	values[1]	values[2]	17	1			T70	4		T190	1		T254	2
auto[1]	values[1]	values[3]	7	1			T280	2		T179	1		T46	1
auto[1]	values[1]	values[4]	7	1			T179	1		T272	1		T350	1
auto[1]	values[1]	values[5]	9	1			T105	1		T263	2		T230	1
auto[1]	values[1]	values[6]	23	1			T57	5		T104	3		T229	2
auto[1]	values[1]	values[7]	20	1			T236	5		T229	1		T266	1
auto[1]	values[2]	values[0]	11	1			T266	1		T179	1		T295	1
auto[1]	values[2]	values[1]	18	1			T308	2		T101	1		T102	2
auto[1]	values[2]	values[2]	8	1			T254	1		T351	2		T352	4
auto[1]	values[2]	values[3]	13	1			T229	2		T353	1		T179	4
auto[1]	values[2]	values[4]	26	1			T104	2		T310	1		T254	5
auto[1]	values[2]	values[5]	10	1			T229	1		T308	2		T263	1
auto[1]	values[2]	values[6]	22	1			T67	10		T55	4		T44	1
auto[1]	values[2]	values[7]	10	1			T69	1		T266	1		T273	1
auto[1]	values[3]	values[0]	18	1			T236	2		T235	1		T229	3
auto[1]	values[3]	values[1]	18	1			T38	2		T293	1		T333	1
auto[1]	values[3]	values[2]	12	1			T101	2		T333	2		T46	1
auto[1]	values[3]	values[3]	20	1			T229	1		T101	2		T293	2
auto[1]	values[3]	values[4]	23	1			T72	5		T249	4		T104	2
auto[1]	values[3]	values[5]	14	1			T190	1		T354	1		T355	1
auto[1]	values[3]	values[6]	17	1			T236	1		T253	4		T179	1
auto[1]	values[3]	values[7]	7	1			T235	4		T104	2		T179	1
auto[1]	values[4]	values[0]	14	1			T52	1		T72	1		T236	4
auto[1]	values[4]	values[1]	14	1			T280	1		T272	1		T356	3
auto[1]	values[4]	values[2]	5	1			T38	2		T357	2		T266	1
auto[1]	values[4]	values[3]	23	1			T70	2		T190	2		T238	2
auto[1]	values[4]	values[4]	9	1			T333	3		T273	2		T254	1
auto[1]	values[4]	values[5]	12	1			T57	1		T223	1		T358	1
auto[1]	values[4]	values[6]	8	1			T249	2		T235	1		T308	1
auto[1]	values[4]	values[7]	21	1			T104	2		T266	7		T331	1
auto[1]	values[5]	values[0]	15	1			T263	1		T266	1		T253	3
auto[1]	values[5]	values[1]	11	1			T37	1		T253	1		T272	1
auto[1]	values[5]	values[2]	8	1			T359	1		T360	2		T361	1
auto[1]	values[5]	values[3]	17	1			T57	5		T104	1		T80	3
auto[1]	values[5]	values[4]	4	1			T280	1		T362	2		T363	1
auto[1]	values[5]	values[5]	17	1			T266	4		T273	1		T358	1
auto[1]	values[5]	values[6]	12	1			T72	1		T179	1		T364	4
auto[1]	values[5]	values[7]	12	1			T330	2		T266	1		T331	3
auto[1]	values[6]	values[0]	12	1			T72	1		T105	1		T295	2
auto[1]	values[6]	values[1]	27	1			T249	3		T365	8		T181	2
auto[1]	values[6]	values[2]	18	1			T37	1		T72	1		T238	3
auto[1]	values[6]	values[3]	7	1			T46	3		T366	2		T232	1
auto[1]	values[6]	values[4]	15	1			T104	1		T251	3		T347	3
auto[1]	values[6]	values[5]	4	1			T26	2		T358	2		-	-
auto[1]	values[6]	values[6]	14	1			T104	1		T101	1		T105	1
auto[1]	values[6]	values[7]	3	1			T277	1		T350	2		-	-
auto[1]	values[7]	values[0]	10	1			T367	2		T368	3		T369	1
auto[1]	values[7]	values[1]	10	1			T190	2		T229	2		T263	1
auto[1]	values[7]	values[2]	7	1			T249	3		T370	1		T371	3
auto[1]	values[7]	values[3]	17	1			T72	2		T372	4		T252	1
auto[1]	values[7]	values[4]	3	1			T38	1		T323	1		T359	1
auto[1]	values[7]	values[5]	11	1			T271	1		T373	1		T370	1
auto[1]	values[7]	values[6]	14	1			T162	1		T280	1		T283	2
auto[1]	values[7]	values[7]	14	1			T238	2		T333	1		T271	1