Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4127	1			T43	20		T195	10		T55	20
values[1]	4183	1			T49	14		T61	6		T46	10
values[2]	4042	1			T7	12		T11	2		T13	41
values[3]	4023	1			T36	76		T43	20		T52	16
values[4]	3687	1			T18	6		T43	20		T79	4
values[5]	3535	1			T50	25		T51	18		T78	24
values[6]	4003	1			T8	12		T17	8		T112	4
values[7]	4126	1			T19	10		T43	20		T55	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4209	1			T7	12		T43	20		T55	20
values[1]	4358	1			T18	6		T19	10		T43	20
values[2]	4033	1			T43	20		T80	20		T55	80
values[3]	3901	1			T8	12		T43	20		T112	4
values[4]	3593	1			T11	2		T13	41		T17	8
values[5]	3663	1			T43	20		T47	117		T58	40
values[6]	4510	1			T36	76		T79	4		T52	16
values[7]	3459	1			T50	25		T195	10		T46	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30941

1

T7

12

T8

12

T11

2

auto[1]

785

1

T49

6

T43

6

T51

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	555	1			T43	20		T33	23		T233	18
auto[0]	values[0]	values[1]	847	1			T55	19		T57	20		T175	20
auto[0]	values[0]	values[2]	372	1			T57	29		T293	20		T178	20
auto[0]	values[0]	values[3]	513	1			T54	95		T177	20		T231	19
auto[0]	values[0]	values[4]	331	1			T221	20		T294	2		T194	19
auto[0]	values[0]	values[5]	423	1			T177	41		T176	60		T213	18
auto[0]	values[0]	values[6]	633	1			T204	45		T99	20		T193	20
auto[0]	values[0]	values[7]	352	1			T195	10		T194	20		T65	21
auto[0]	values[1]	values[0]	624	1			T204	76		T33	29		T265	26
auto[0]	values[1]	values[1]	483	1			T61	6		T233	63		T246	20
auto[0]	values[1]	values[2]	484	1			T176	41		T218	18		T246	18
auto[0]	values[1]	values[3]	444	1			T54	40		T204	52		T246	37
auto[0]	values[1]	values[4]	437	1			T49	8		T147	22		T243	14
auto[0]	values[1]	values[5]	698	1			T204	58		T295	4		T209	197
auto[0]	values[1]	values[6]	556	1			T47	66		T253	16		T222	18
auto[0]	values[1]	values[7]	356	1			T46	10		T258	4		T296	2
auto[0]	values[2]	values[0]	583	1			T7	12		T55	19		T57	27
auto[0]	values[2]	values[1]	545	1			T78	20		T47	20		T144	8
auto[0]	values[2]	values[2]	563	1			T43	20		T55	20		T233	19
auto[0]	values[2]	values[3]	654	1			T54	101		T57	20		T147	20
auto[0]	values[2]	values[4]	260	1			T11	2		T13	41		T43	18
auto[0]	values[2]	values[5]	192	1			T43	18		T47	20		T76	18
auto[0]	values[2]	values[6]	497	1			T147	20		T204	20		T149	26
auto[0]	values[2]	values[7]	642	1			T193	39		T276	10		T297	6
auto[0]	values[3]	values[0]	463	1			T57	39		T32	18		T246	19
auto[0]	values[3]	values[1]	459	1			T282	20		T298	2		T75	26
auto[0]	values[3]	values[2]	482	1			T55	20		T248	16		T246	21
auto[0]	values[3]	values[3]	262	1			T299	2		T225	23		T234	20
auto[0]	values[3]	values[4]	513	1			T43	20		T59	18		T300	16
auto[0]	values[3]	values[5]	794	1			T257	24		T216	317		T234	40
auto[0]	values[3]	values[6]	592	1			T36	76		T52	16		T33	20
auto[0]	values[3]	values[7]	360	1			T288	4		T177	109		T246	20
auto[0]	values[4]	values[0]	391	1			T246	23		T216	20		T65	19
auto[0]	values[4]	values[1]	296	1			T18	6		T54	20		T58	24
auto[0]	values[4]	values[2]	603	1			T202	22		T203	21		T235	21
auto[0]	values[4]	values[3]	713	1			T43	19		T275	6		T198	10
auto[0]	values[4]	values[4]	362	1			T47	25		T175	36		T264	12
auto[0]	values[4]	values[5]	279	1			T58	20		T176	20		T71	23
auto[0]	values[4]	values[6]	485	1			T79	4		T177	36		T209	39
auto[0]	values[4]	values[7]	480	1			T177	42		T233	33		T75	20
auto[0]	values[5]	values[0]	379	1			T101	18		T71	20		T225	20
auto[0]	values[5]	values[1]	341	1			T78	24		T55	20		T219	20
auto[0]	values[5]	values[2]	470	1			T221	20		T47	20		T58	41
auto[0]	values[5]	values[3]	331	1			T53	36		T39	21		T273	2
auto[0]	values[5]	values[4]	621	1			T51	16		T56	8		T54	20
auto[0]	values[5]	values[5]	376	1			T47	97		T259	6		T301	20
auto[0]	values[5]	values[6]	531	1			T55	20		T57	39		T175	20
auto[0]	values[5]	values[7]	381	1			T50	25		T54	20		T302	10
auto[0]	values[6]	values[0]	616	1			T58	24		T175	20		T204	59
auto[0]	values[6]	values[1]	804	1			T54	52		T32	84		T33	20
auto[0]	values[6]	values[2]	398	1			T80	20		T55	20		T285	2
auto[0]	values[6]	values[3]	406	1			T8	12		T112	4		T55	18
auto[0]	values[6]	values[4]	404	1			T17	8		T109	14		T124	6
auto[0]	values[6]	values[5]	367	1			T267	2		T251	4		T71	19
auto[0]	values[6]	values[6]	564	1			T55	20		T221	20		T241	57
auto[0]	values[6]	values[7]	340	1			T219	20		T235	21		T303	82
auto[0]	values[7]	values[0]	487	1			T47	43		T193	19		T233	30
auto[0]	values[7]	values[1]	461	1			T19	10		T43	19		T255	18
auto[0]	values[7]	values[2]	569	1			T55	20		T33	35		T304	2
auto[0]	values[7]	values[3]	485	1			T245	6		T269	10		T74	20
auto[0]	values[7]	values[4]	558	1			T54	40		T57	20		T204	20
auto[0]	values[7]	values[5]	467	1			T58	20		T207	18		T305	26
auto[0]	values[7]	values[6]	552	1			T47	92		T147	20		T175	102
auto[0]	values[7]	values[7]	455	1			T223	6		T58	31		T233	38
auto[1]	values[0]	values[0]	15	1			T233	2		T213	1		T238	1
auto[1]	values[0]	values[1]	14	1			T55	1		T203	1		T306	1
auto[1]	values[0]	values[2]	8	1			T57	1		T307	2		T306	2
auto[1]	values[0]	values[3]	18	1			T231	1		T281	3		T308	1
auto[1]	values[0]	values[4]	2	1			T194	1		T309	1		-	-
auto[1]	values[0]	values[5]	8	1			T176	3		T213	2		T216	1
auto[1]	values[0]	values[6]	21	1			T241	4		T207	1		T202	1
auto[1]	values[0]	values[7]	15	1			T65	3		T280	1		T303	2
auto[1]	values[1]	values[0]	18	1			T204	3		T33	1		T246	2
auto[1]	values[1]	values[1]	19	1			T225	1		T207	3		T231	3
auto[1]	values[1]	values[2]	11	1			T176	1		T246	2		T210	2
auto[1]	values[1]	values[3]	15	1			T204	3		T194	1		T229	4
auto[1]	values[1]	values[4]	11	1			T49	6		T310	3		T287	1
auto[1]	values[1]	values[5]	13	1			T209	3		T234	1		T151	3
auto[1]	values[1]	values[6]	11	1			T74	2		T227	2		T281	1
auto[1]	values[1]	values[7]	3	1			T202	1		T308	1		T311	1
auto[1]	values[2]	values[0]	11	1			T55	1		T272	4		T235	1
auto[1]	values[2]	values[1]	14	1			T177	1		T65	3		T234	2
auto[1]	values[2]	values[2]	12	1			T233	1		T71	2		T216	2
auto[1]	values[2]	values[3]	17	1			T54	2		T175	2		T238	1
auto[1]	values[2]	values[4]	17	1			T43	2		T235	1		T312	6
auto[1]	values[2]	values[5]	5	1			T43	2		T313	2		T314	1
auto[1]	values[2]	values[6]	14	1			T207	2		T226	2		T315	2
auto[1]	values[2]	values[7]	16	1			T193	1		T71	3		T271	5
auto[1]	values[3]	values[0]	21	1			T57	2		T32	2		T246	3
auto[1]	values[3]	values[1]	12	1			T282	2		T75	1		T234	1
auto[1]	values[3]	values[2]	10	1			T66	2		T240	4		T316	3
auto[1]	values[3]	values[3]	6	1			T225	4		T203	1		T317	1
auto[1]	values[3]	values[4]	12	1			T59	4		T202	1		T150	1
auto[1]	values[3]	values[5]	9	1			T216	1		T287	1		T318	3
auto[1]	values[3]	values[6]	14	1			T71	2		T219	1		T202	3
auto[1]	values[3]	values[7]	14	1			T194	2		T219	4		T149	3
auto[1]	values[4]	values[0]	11	1			T246	4		T65	1		T310	3
auto[1]	values[4]	values[1]	10	1			T219	1		T202	2		T41	3
auto[1]	values[4]	values[2]	12	1			T202	2		T203	1		T235	2
auto[1]	values[4]	values[3]	14	1			T43	1		T33	2		T281	1
auto[1]	values[4]	values[4]	5	1			T175	2		T319	1		T320	1
auto[1]	values[4]	values[5]	9	1			T219	3		T234	1		T321	2
auto[1]	values[4]	values[6]	9	1			T209	1		T216	1		T219	1
auto[1]	values[4]	values[7]	8	1			T177	1		T231	1		T208	1
auto[1]	values[5]	values[0]	6	1			T101	2		T308	1		T41	2
auto[1]	values[5]	values[1]	12	1			T272	1		T207	3		T322	3
auto[1]	values[5]	values[2]	20	1			T58	4		T175	1		T240	2
auto[1]	values[5]	values[3]	4	1			T228	1		T322	3		-	-
auto[1]	values[5]	values[4]	32	1			T51	2		T56	4		T303	2
auto[1]	values[5]	values[5]	3	1			T323	1		T236	2		-	-
auto[1]	values[5]	values[6]	12	1			T213	1		T75	1		T194	1
auto[1]	values[5]	values[7]	16	1			T227	2		T271	1		T210	3
auto[1]	values[6]	values[0]	16	1			T234	7		T149	2		T324	2
auto[1]	values[6]	values[1]	24	1			T54	2		T32	1		T231	2
auto[1]	values[6]	values[2]	11	1			T176	3		T238	1		T210	2
auto[1]	values[6]	values[3]	14	1			T55	2		T210	2		T325	2
auto[1]	values[6]	values[4]	11	1			T202	1		T324	3		T326	2
auto[1]	values[6]	values[5]	13	1			T71	1		T219	1		T280	1
auto[1]	values[6]	values[6]	11	1			T71	1		T227	1		T272	2
auto[1]	values[6]	values[7]	4	1			T303	3		T277	1		-	-
auto[1]	values[7]	values[0]	13	1			T193	1		T213	1		T194	3
auto[1]	values[7]	values[1]	17	1			T43	1		T71	3		T289	2
auto[1]	values[7]	values[2]	8	1			T33	3		T228	1		T327	2
auto[1]	values[7]	values[3]	5	1			T328	1		T320	2		T329	1
auto[1]	values[7]	values[4]	17	1			T54	1		T209	1		T71	1
auto[1]	values[7]	values[5]	7	1			T207	2		T41	1		T330	2
auto[1]	values[7]	values[6]	8	1			T47	1		T175	2		T227	1
auto[1]	values[7]	values[7]	17	1			T58	1		T233	1		T331	6