Group : spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
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Group : spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_prev_wr_en 2 0 2 100.00 100 1 1 2
cp_wr_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 4 0 4 100.00 100 1 1 0


Summary for Variable cp_prev_wr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_prev_wr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2494 1 T14 6 T23 2 T73 16
auto[1] 755 1 T14 2 T74 1 T61 2


Summary for Variable cp_wr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_wr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1641 1 T14 4 T23 2 T73 16
auto[1] 1608 1 T14 4 T74 2 T61 2


Summary for Cross cr_all

Samples crossed: cp_wr_en cp_prev_wr_en
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_wr_en   cp_prev_wr_en   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 1298 1 T14 4 T23 2 T73 16
auto[0] auto[1] 343 1 T61 1 T287 1 T59 1
auto[1] auto[0] 1196 1 T14 2 T74 1 T61 1
auto[1] auto[1] 412 1 T14 2 T74 1 T61 1