Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	754	1			T37	4		T38	7		T39	14
all_values[1]	754	1			T37	4		T38	7		T39	14
all_values[2]	754	1			T37	4		T38	7		T39	14
all_values[3]	754	1			T37	4		T38	7		T39	14
all_values[4]	754	1			T37	4		T38	7		T39	14
all_values[5]	754	1			T37	4		T38	7		T39	14
all_values[6]	754	1			T37	4		T38	7		T39	14
all_values[7]	754	1			T37	4		T38	7		T39	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3266

1

T37

18

T38

36

T39

71

auto[1]

2766

1

T37

14

T38

20

T39

41

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2392

1

T37

12

T38

22

T39

40

auto[1]

3640

1

T37

20

T38

34

T39

72

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3439

1

T37

18

T38

33

T39

62

auto[1]

2593

1

T37

14

T38

23

T39

50

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	146	1			T38	1		T39	4		T40	2
all_values[0]	auto[0]	auto[0]	auto[1]	67	1			T37	1		T38	2		T39	3
all_values[0]	auto[0]	auto[1]	auto[0]	148	1			T37	1		T38	1		T40	1
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T39	2		T101	4		T105	1
all_values[0]	auto[1]	auto[0]	auto[1]	166	1			T37	2		T38	2		T39	2
all_values[0]	auto[1]	auto[1]	auto[1]	147	1			T38	1		T39	3		T101	3
all_values[1]	auto[0]	auto[0]	auto[0]	143	1			T37	2		T38	3		T39	2
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T39	2		T40	1		T101	2
all_values[1]	auto[0]	auto[1]	auto[0]	112	1			T37	2		T39	4		T102	4
all_values[1]	auto[0]	auto[1]	auto[1]	75	1			T101	2		T102	1		T186	6
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T38	2		T39	5		T40	3
all_values[1]	auto[1]	auto[1]	auto[1]	152	1			T38	2		T39	1		T101	4
all_values[2]	auto[0]	auto[0]	auto[0]	152	1			T37	1		T38	3		T39	1
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T38	1		T39	3		T101	1
all_values[2]	auto[0]	auto[1]	auto[0]	138	1			T38	1		T101	5		T105	2
all_values[2]	auto[0]	auto[1]	auto[1]	59	1			T102	1		T186	3		T187	1
all_values[2]	auto[1]	auto[0]	auto[1]	194	1			T37	3		T38	2		T39	3
all_values[2]	auto[1]	auto[1]	auto[1]	132	1			T39	7		T102	6		T186	3
all_values[3]	auto[0]	auto[0]	auto[0]	168	1			T38	1		T39	5		T40	2
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T38	1		T39	3		T101	3
all_values[3]	auto[0]	auto[1]	auto[0]	140	1			T38	3		T101	1		T105	2
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T37	2		T39	1		T40	1
all_values[3]	auto[1]	auto[0]	auto[1]	172	1			T37	2		T38	1		T39	5
all_values[3]	auto[1]	auto[1]	auto[1]	140	1			T38	1		T101	5		T102	3
all_values[4]	auto[0]	auto[0]	auto[0]	169	1			T37	1		T39	6		T101	4
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T37	1		T38	2		T39	1
all_values[4]	auto[0]	auto[1]	auto[0]	107	1			T39	2		T40	3		T102	2
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T38	1		T39	2		T101	4
all_values[4]	auto[1]	auto[0]	auto[1]	182	1			T37	1		T38	3		T39	1
all_values[4]	auto[1]	auto[1]	auto[1]	146	1			T37	1		T38	1		T39	2
all_values[5]	auto[0]	auto[0]	auto[0]	206	1			T37	1		T38	2		T39	4
all_values[5]	auto[0]	auto[1]	auto[0]	221	1			T37	1		T38	3		T39	4
all_values[5]	auto[1]	auto[0]	auto[1]	175	1			T37	1		T38	2		T39	3
all_values[5]	auto[1]	auto[1]	auto[1]	152	1			T37	1		T39	3		T101	4
all_values[6]	auto[0]	auto[0]	auto[0]	152	1			T38	3		T39	1		T40	1
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T38	1		T101	3		T105	1
all_values[6]	auto[0]	auto[1]	auto[0]	108	1			T37	1		T38	1		T39	2
all_values[6]	auto[0]	auto[1]	auto[1]	89	1			T37	1		T39	1		T101	1
all_values[6]	auto[1]	auto[0]	auto[1]	197	1			T37	1		T38	1		T39	7
all_values[6]	auto[1]	auto[1]	auto[1]	133	1			T37	1		T38	1		T39	3
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T37	1		T39	1		T101	4
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T38	1		T39	4		T101	3
all_values[7]	auto[0]	auto[1]	auto[0]	122	1			T37	1		T39	4		T101	1
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T37	1		T38	2		T40	1
all_values[7]	auto[1]	auto[0]	auto[1]	174	1			T38	2		T39	5		T40	1
all_values[7]	auto[1]	auto[1]	auto[1]	145	1			T37	1		T38	2		T40	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal