Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1869

1

T3

5

T5

25

T12

12

auto[1]

1932

1

T3

3

T5

20

T12

18

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2086

1

T12

30

T26

5

T21

7

auto[1]

1715

1

T3

8

T5

45

T24

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3033

1

T3

8

T5

45

T12

22

auto[1]

768

1

T12

8

T26

3

T21

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	767	1			T5	7		T12	8		T24	4
valid[1]	743	1			T3	3		T5	6		T12	8
valid[2]	756	1			T3	1		T5	9		T12	8
valid[3]	773	1			T3	2		T5	10		T12	3
valid[4]	762	1			T3	2		T5	13		T12	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	121	1			T12	3		T26	1		T21	1
auto[0]	auto[0]	valid[0]	auto[1]	152	1			T5	4		T24	2		T27	3
auto[0]	auto[0]	valid[1]	auto[0]	125	1			T12	3		T62	2		T63	1
auto[0]	auto[0]	valid[1]	auto[1]	160	1			T3	2		T5	1		T29	1
auto[0]	auto[0]	valid[2]	auto[0]	141	1			T12	2		T63	3		T78	1
auto[0]	auto[0]	valid[2]	auto[1]	171	1			T3	1		T5	6		T24	3
auto[0]	auto[0]	valid[3]	auto[0]	117	1			T42	1		T63	2		T32	1
auto[0]	auto[0]	valid[3]	auto[1]	193	1			T3	1		T5	4		T24	2
auto[0]	auto[0]	valid[4]	auto[0]	115	1			T12	1		T42	1		T63	1
auto[0]	auto[0]	valid[4]	auto[1]	170	1			T3	1		T5	10		T27	2
auto[0]	auto[1]	valid[0]	auto[0]	135	1			T12	4		T48	2		T62	4
auto[0]	auto[1]	valid[0]	auto[1]	190	1			T5	3		T24	2		T27	3
auto[0]	auto[1]	valid[1]	auto[0]	133	1			T12	4		T62	3		T78	1
auto[0]	auto[1]	valid[1]	auto[1]	177	1			T3	1		T5	5		T24	1
auto[0]	auto[1]	valid[2]	auto[0]	124	1			T12	1		T26	1		T62	1
auto[0]	auto[1]	valid[2]	auto[1]	155	1			T5	3		T24	1		T27	1
auto[0]	auto[1]	valid[3]	auto[0]	154	1			T12	3		T21	2		T62	3
auto[0]	auto[1]	valid[3]	auto[1]	162	1			T3	1		T5	6		T24	1
auto[0]	auto[1]	valid[4]	auto[0]	153	1			T12	1		T21	1		T42	1
auto[0]	auto[1]	valid[4]	auto[1]	185	1			T3	1		T5	3		T27	2
auto[1]	auto[0]	valid[0]	auto[0]	92	1			T62	1		T63	1		T348	4
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T21	1		T62	1		T63	2
auto[1]	auto[0]	valid[2]	auto[0]	92	1			T12	3		T26	1		T21	1
auto[1]	auto[0]	valid[3]	auto[0]	69	1			T62	1		T63	2		T348	1
auto[1]	auto[0]	valid[4]	auto[0]	73	1			T62	2		T32	1		T347	1
auto[1]	auto[1]	valid[0]	auto[0]	77	1			T12	1		T48	1		T147	1
auto[1]	auto[1]	valid[1]	auto[0]	70	1			T12	1		T26	1		T21	1
auto[1]	auto[1]	valid[2]	auto[0]	73	1			T12	2		T48	3		T62	1
auto[1]	auto[1]	valid[3]	auto[0]	78	1			T26	1		T62	1		T63	2
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T12	1		T342	1		T343	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal