Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1783

1

T1

6

T5

7

T10

15

auto[1]

1852

1

T1

7

T5

7

T10

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1970

1

T1

13

T10

25

T35

1

auto[1]

1665

1

T5

14

T11

6

T12

20

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2886

1

T1

7

T5

14

T10

14

auto[1]

749

1

T1

6

T10

11

T78

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	690	1			T1	4		T10	5		T12	4
valid[1]	730	1			T1	3		T5	4		T10	4
valid[2]	780	1			T1	1		T5	3		T10	7
valid[3]	704	1			T1	1		T5	4		T10	5
valid[4]	731	1			T1	4		T5	3		T10	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	133	1			T1	1		T10	3		T78	1
auto[0]	auto[0]	valid[0]	auto[1]	145	1			T12	4		T31	3		T76	1
auto[0]	auto[0]	valid[1]	auto[0]	124	1			T1	1		T10	1		T93	2
auto[0]	auto[0]	valid[1]	auto[1]	179	1			T5	2		T12	2		T31	3
auto[0]	auto[0]	valid[2]	auto[0]	126	1			T10	2		T35	1		T78	1
auto[0]	auto[0]	valid[2]	auto[1]	167	1			T5	1		T12	2		T32	1
auto[0]	auto[0]	valid[3]	auto[0]	107	1			T10	1		T93	3		T47	2
auto[0]	auto[0]	valid[3]	auto[1]	167	1			T5	3		T11	1		T31	3
auto[0]	auto[0]	valid[4]	auto[0]	118	1			T1	1		T10	1		T47	1
auto[0]	auto[0]	valid[4]	auto[1]	169	1			T5	1		T11	1		T12	4
auto[0]	auto[1]	valid[0]	auto[0]	109	1			T1	2		T78	1		T392	1
auto[0]	auto[1]	valid[0]	auto[1]	169	1			T31	4		T76	2		T35	1
auto[0]	auto[1]	valid[1]	auto[0]	119	1			T10	1		T78	1		T47	1
auto[0]	auto[1]	valid[1]	auto[1]	163	1			T5	2		T11	1		T12	1
auto[0]	auto[1]	valid[2]	auto[0]	136	1			T10	3		T392	1		T47	1
auto[0]	auto[1]	valid[2]	auto[1]	183	1			T5	2		T11	3		T12	3
auto[0]	auto[1]	valid[3]	auto[0]	119	1			T10	1		T93	1		T392	1
auto[0]	auto[1]	valid[3]	auto[1]	165	1			T5	1		T12	2		T31	2
auto[0]	auto[1]	valid[4]	auto[0]	130	1			T1	2		T10	1		T78	3
auto[0]	auto[1]	valid[4]	auto[1]	158	1			T5	2		T12	2		T31	7
auto[1]	auto[0]	valid[0]	auto[0]	52	1			T10	1		T93	1		T47	2
auto[1]	auto[0]	valid[1]	auto[0]	68	1			T10	2		T390	2		T391	2
auto[1]	auto[0]	valid[2]	auto[0]	76	1			T1	1		T10	1		T78	1
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T1	1		T10	2		T93	1
auto[1]	auto[0]	valid[4]	auto[0]	76	1			T1	1		T10	1		T93	1
auto[1]	auto[1]	valid[0]	auto[0]	82	1			T1	1		T10	1		T47	1
auto[1]	auto[1]	valid[1]	auto[0]	77	1			T1	2		T112	1		T195	1
auto[1]	auto[1]	valid[2]	auto[0]	92	1			T10	1		T392	1		T47	2
auto[1]	auto[1]	valid[3]	auto[0]	70	1			T10	1		T93	2		T47	1
auto[1]	auto[1]	valid[4]	auto[0]	80	1			T10	1		T93	1		T48	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal