Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51376

1

T6

6

T12

561

T26

141

auto[1]

17805

1

T3

8

T5

515

T24

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50467

1

T3

8

T5

515

T6

2

auto[1]

18714

1

T6

4

T12

190

T26

49

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35722	1			T3	8		T5	282		T6	4
others[1]	5878	1			T5	37		T12	46		T26	6
others[2]	5761	1			T5	40		T6	1		T12	44
others[3]	6590	1			T5	55		T6	1		T12	52
interest[1]	3886	1			T5	26		T12	37		T26	7
interest[4]	23425	1			T3	8		T5	179		T6	3
interest[64]	11344	1			T5	75		T12	94		T26	21

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16839	1			T6	2		T12	199		T26	51
auto[0]	auto[0]	others[1]	2741	1			T12	26		T26	2		T21	9
auto[0]	auto[0]	others[2]	2724	1			T12	29		T26	6		T21	11
auto[0]	auto[0]	others[3]	3120	1			T12	31		T26	13		T21	22
auto[0]	auto[0]	interest[1]	1807	1			T12	25		T26	5		T21	8
auto[0]	auto[0]	interest[4]	10968	1			T6	1		T12	121		T26	30
auto[0]	auto[0]	interest[64]	5431	1			T12	61		T26	15		T21	28
auto[0]	auto[1]	others[0]	9302	1			T3	8		T5	282		T24	12
auto[0]	auto[1]	others[1]	1558	1			T5	37		T21	8		T27	47
auto[0]	auto[1]	others[2]	1445	1			T5	40		T21	11		T27	37
auto[0]	auto[1]	others[3]	1678	1			T5	55		T21	3		T27	51
auto[0]	auto[1]	interest[1]	1013	1			T5	26		T21	6		T27	23
auto[0]	auto[1]	interest[4]	6207	1			T3	8		T5	179		T24	12
auto[0]	auto[1]	interest[64]	2809	1			T5	75		T21	11		T27	59
auto[1]	auto[0]	others[0]	9581	1			T6	2		T12	89		T26	24
auto[1]	auto[0]	others[1]	1579	1			T12	20		T26	4		T21	12
auto[1]	auto[0]	others[2]	1592	1			T6	1		T12	15		T26	4
auto[1]	auto[0]	others[3]	1792	1			T6	1		T12	21		T26	9
auto[1]	auto[0]	interest[1]	1066	1			T12	12		T26	2		T21	8
auto[1]	auto[0]	interest[4]	6250	1			T6	2		T12	60		T26	15
auto[1]	auto[0]	interest[64]	3104	1			T12	33		T26	6		T21	16

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal