Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49940

1

T1

227

T10

437

T27

6

auto[1]

17827

1

T5

14

T11

6

T12

135

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49442

1

T1

145

T5

14

T10

281

auto[1]

18325

1

T1

82

T10

156

T27

3

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34889	1			T1	127		T5	14		T10	232
others[1]	5612	1			T1	12		T10	32		T12	15
others[2]	5666	1			T1	23		T10	33		T12	4
others[3]	6483	1			T1	23		T10	47		T12	15
interest[1]	3817	1			T1	14		T10	24		T12	13
interest[4]	22784	1			T1	87		T5	14		T10	149
interest[64]	11300	1			T1	28		T10	69		T12	20

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16191	1			T1	84		T10	144		T27	1
auto[0]	auto[0]	others[1]	2657	1			T1	8		T10	19		T30	1
auto[0]	auto[0]	others[2]	2712	1			T1	14		T10	15		T28	1
auto[0]	auto[0]	others[3]	3016	1			T1	15		T10	32		T49	2
auto[0]	auto[0]	interest[1]	1755	1			T1	11		T10	18		T49	1
auto[0]	auto[0]	interest[4]	10570	1			T1	62		T10	96		T29	1
auto[0]	auto[0]	interest[64]	5284	1			T1	13		T10	53		T27	2
auto[0]	auto[1]	others[0]	9248	1			T5	14		T11	6		T12	68
auto[0]	auto[1]	others[1]	1438	1			T12	15		T31	31		T76	17
auto[0]	auto[1]	others[2]	1447	1			T12	4		T31	40		T76	4
auto[0]	auto[1]	others[3]	1730	1			T12	15		T31	49		T76	13
auto[0]	auto[1]	interest[1]	995	1			T12	13		T31	27		T76	5
auto[0]	auto[1]	interest[4]	6114	1			T5	14		T11	6		T12	41
auto[0]	auto[1]	interest[64]	2969	1			T12	20		T31	61		T76	13
auto[1]	auto[0]	others[0]	9450	1			T1	43		T10	88		T27	1
auto[1]	auto[0]	others[1]	1517	1			T1	4		T10	13		T27	1
auto[1]	auto[0]	others[2]	1507	1			T1	9		T10	18		T28	1
auto[1]	auto[0]	others[3]	1737	1			T1	8		T10	15		T35	4
auto[1]	auto[0]	interest[1]	1067	1			T1	3		T10	6		T27	1
auto[1]	auto[0]	interest[4]	6100	1			T1	25		T10	53		T27	1
auto[1]	auto[0]	interest[64]	3047	1			T1	15		T10	16		T30	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal