SPI_DEVICE/2P Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.809m	90.801ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.250s	177.400us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.900s	328.188us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.700s	11.310ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.680s	1.793ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.230s	308.190us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.900s	328.188us	20	20	100.00
		spi_device_csr_aliasing	21.680s	1.793ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.740s	36.592us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.190s	126.966us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.010s	17.288us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	64.659us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	18.469us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	10.820s	236.055us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.820s	236.055us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	31.740s	11.526ms	50	50	100.00
		spi_device_tpm_sts_read	1.290s	222.522us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.376m	15.068ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	49.480s	76.873ms	50	50	100.00
		spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.122m	48.346ms	50	50	100.00
		spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.122m	48.346ms	50	50	100.00
		spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	cmd_info_slots	spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	cmd_read_status	spi_device_intercept	16.330s	18.071ms	50	50	100.00
		spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	cmd_read_jedec	spi_device_intercept	16.330s	18.071ms	50	50	100.00
		spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	cmd_read_sfdp	spi_device_intercept	16.330s	18.071ms	50	50	100.00
		spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	cmd_fast_read	spi_device_intercept	16.330s	18.071ms	50	50	100.00
		spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	cmd_read_pipeline	spi_device_intercept	16.330s	18.071ms	50	50	100.00
		spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	flash_cmd_upload	spi_device_upload	35.670s	10.443ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	43.550s	16.269ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	43.550s	16.269ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	43.550s	16.269ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.347m	18.731ms	49	50	98.00
		spi_device_read_buffer_direct	6.830s	1.651ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	43.550s	16.269ms	50	50	100.00
		spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	quad_spi	spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	dual_spi	spi_device_flash_all	8.705m	103.113ms	47	50	94.00
V2	4b_3b_feature	spi_device_cfg_cmd	14.960s	14.530ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	14.960s	14.530ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.809m	90.801ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.425m	374.975ms	49	50	98.00
V2	stress_all	spi_device_stress_all	19.061m	1.321s	48	50	96.00
V2	alert_test	spi_device_alert_test	0.780s	12.250us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	68.745us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.310s	909.719us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.310s	909.719us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.250s	177.400us	5	5	100.00
		spi_device_csr_rw	2.900s	328.188us	20	20	100.00
		spi_device_csr_aliasing	21.680s	1.793ms	5	5	100.00
		spi_device_same_csr_outstanding	4.590s	917.004us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.250s	177.400us	5	5	100.00
		spi_device_csr_rw	2.900s	328.188us	20	20	100.00
		spi_device_csr_aliasing	21.680s	1.793ms	5	5	100.00
		spi_device_same_csr_outstanding	4.590s	917.004us	20	20	100.00
V2		TOTAL			973	980	99.29
V2S	tl_intg_err	spi_device_sec_cm	1.210s	169.281us	5	5	100.00
		spi_device_tl_intg_err	22.400s	2.095ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.400s	2.095ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1113	1120	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	18	81.82
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.36	94.45	98.61	89.36	97.09	95.82	98.22

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

4.spi_device_flash_and_tpm_min_idle.30476841338433285827140882024356176779304530503605895872702106320328339861695
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 628144201 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 673755110 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 1/10
  UVM_INFO @ 1221044651 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/10
  UVM_INFO @ 1546032210 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/10
  UVM_INFO @ 1960924201 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/10

Test spi_device_stress_all has 1 failures.

8.spi_device_stress_all.103622041579774195809243228830487325971476073057247264696146922132982924755463
Line 288, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 13989449792 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 13997279896 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 14/18
  UVM_INFO @ 14973574322 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 15/18
  UVM_INFO @ 15732931838 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 16/18
  UVM_INFO @ 16620868786 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 17/18

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_flash_all has 2 failures.

5.spi_device_flash_all.51450852125164845047454653318501576802249193414212506706008904643258425130119
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 7486722895 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 7670853787 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 14/18
  UVM_INFO @ 7987218077 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 15/18
  UVM_INFO @ 8542500548 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 16/18
  UVM_INFO @ 8839071899 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 17/18

31.spi_device_flash_all.12527891338883077926153888954993333346336221338819121291837493873324572298289
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 1021299607 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 1032858022 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/9
  UVM_INFO @ 1180003983 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/9
  UVM_INFO @ 1322213606 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/9
  UVM_INFO @ 1385582097 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/9

UVM_ERROR (spi_device_scoreboard.sv:862) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 1 failures:

Test spi_device_flash_all has 1 failures.

11.spi_device_flash_all.70266137526341551224666486437404345836581086957253762017617097736961642130672
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 5396367287 ps: (spi_device_scoreboard.sv:862) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_FATAL @ 5396367288 ps: (spi_device_scoreboard.sv:825) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 5396367288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1070) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_stress_all has 1 failures.

26.spi_device_stress_all.89171022342597769220713494619342150555373300150408619463239005836897371636095
Line 288, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 168117017463 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe2d50c) != exp '{'{other_status:'h3adbaf, wel:'h1, busy:'h0}}
  UVM_INFO @ 169848739650 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/14
  UVM_INFO @ 179255477902 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/14
  UVM_INFO @ 183825232122 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/14
  UVM_INFO @ 188619621480 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/14

UVM_FATAL (spi_device_scoreboard.sv:921) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 39.spi_device_flash_mode.88468843067690572063022984753041190485068110287916894453597108191886779293971
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 67130886884 ps: (spi_device_scoreboard.sv:921) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 67130886884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```