Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5529377	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6020870

1

T1

27122

T2

2996

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7266580	1			T1	18641		T2	3023		T3	75
values[0x0]	2143069	1			T1	11210		T2	1484		T4	18499
values[0x1]	2140598	1			T1	11122		T2	1415		T4	18790

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4001299	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

7548948

1

T1

30892

T2

3876

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	45080	1			T1	386		T2	26		T3	2
valid_sources[0x01]	44784	1			T1	450		T2	24		T3	1
valid_sources[0x02]	45400	1			T1	101		T2	29		T4	56
valid_sources[0x03]	44259	1			T1	25		T2	16		T3	1
valid_sources[0x04]	41853	1			T1	44		T2	20		T3	1
valid_sources[0x05]	44071	1			T1	132		T2	18		T4	123
valid_sources[0x06]	43031	1			T1	430		T2	14		T4	251
valid_sources[0x07]	43523	1			T1	664		T2	24		T4	190
valid_sources[0x08]	45347	1			T1	61		T2	17		T3	2
valid_sources[0x09]	40691	1			T1	32		T2	18		T4	90
valid_sources[0x0a]	48136	1			T1	73		T2	25		T4	184
valid_sources[0x0b]	47773	1			T1	31		T2	28		T4	431
valid_sources[0x0c]	43902	1			T1	64		T2	23		T4	132
valid_sources[0x0d]	44073	1			T1	106		T2	29		T3	1
valid_sources[0x0e]	44621	1			T1	132		T2	27		T4	824
valid_sources[0x0f]	44148	1			T1	83		T2	27		T4	346
valid_sources[0x10]	44922	1			T1	122		T2	26		T3	1
valid_sources[0x11]	44222	1			T1	84		T2	24		T3	3
valid_sources[0x12]	44892	1			T1	204		T2	21		T4	225
valid_sources[0x13]	51275	1			T1	163		T2	39		T4	781
valid_sources[0x14]	43383	1			T1	32		T2	24		T4	146
valid_sources[0x15]	44649	1			T1	263		T2	19		T4	1094
valid_sources[0x16]	43596	1			T1	81		T2	23		T4	269
valid_sources[0x17]	49517	1			T1	179		T2	27		T4	346
valid_sources[0x18]	45087	1			T1	121		T2	27		T3	1
valid_sources[0x19]	44101	1			T1	308		T2	18		T4	273
valid_sources[0x1a]	43800	1			T1	16		T2	25		T4	495
valid_sources[0x1b]	44213	1			T1	659		T2	18		T3	1
valid_sources[0x1c]	47875	1			T1	235		T2	22		T4	284
valid_sources[0x1d]	58557	1			T1	82		T2	26		T4	280
valid_sources[0x1e]	43136	1			T1	246		T2	25		T4	446
valid_sources[0x1f]	42917	1			T1	72		T2	33		T4	560
valid_sources[0x20]	45140	1			T1	85		T2	24		T4	378
valid_sources[0x21]	42536	1			T1	702		T2	22		T4	332
valid_sources[0x22]	45843	1			T1	44		T2	26		T4	501
valid_sources[0x23]	40700	1			T1	579		T2	25		T4	94
valid_sources[0x24]	48740	1			T1	99		T2	17		T4	234
valid_sources[0x25]	43114	1			T1	74		T2	31		T4	403
valid_sources[0x26]	41969	1			T1	15		T2	25		T3	1
valid_sources[0x27]	45112	1			T1	70		T2	17		T4	115
valid_sources[0x28]	43622	1			T1	65		T2	24		T3	1
valid_sources[0x29]	48014	1			T1	583		T2	28		T4	1414
valid_sources[0x2a]	44760	1			T1	82		T2	24		T4	241
valid_sources[0x2b]	45718	1			T1	61		T2	29		T3	1
valid_sources[0x2c]	42959	1			T1	6		T2	29		T3	1
valid_sources[0x2d]	44514	1			T1	234		T2	22		T3	1
valid_sources[0x2e]	42175	1			T1	15		T2	20		T3	1
valid_sources[0x2f]	48511	1			T1	273		T2	15		T4	347
valid_sources[0x30]	45136	1			T1	55		T2	20		T4	275
valid_sources[0x31]	45051	1			T1	49		T2	27		T3	1
valid_sources[0x32]	46911	1			T1	462		T2	24		T4	1862
valid_sources[0x33]	43139	1			T1	61		T2	21		T3	1
valid_sources[0x34]	43992	1			T1	42		T2	29		T4	321
valid_sources[0x35]	44833	1			T1	386		T2	26		T4	184
valid_sources[0x36]	47008	1			T1	419		T2	22		T4	245
valid_sources[0x37]	42600	1			T1	68		T2	15		T3	1
valid_sources[0x38]	42470	1			T1	135		T2	27		T4	1011
valid_sources[0x39]	46766	1			T1	155		T2	15		T4	256
valid_sources[0x3a]	41229	1			T1	8		T2	26		T3	1
valid_sources[0x3b]	44536	1			T1	92		T2	17		T4	370
valid_sources[0x3c]	46681	1			T1	246		T2	20		T4	1244
valid_sources[0x3d]	43639	1			T1	153		T2	29		T4	243
valid_sources[0x3e]	41227	1			T1	250		T2	20		T4	67
valid_sources[0x3f]	44637	1			T1	124		T2	19		T3	1
valid_sources[0x40]	43099	1			T1	70		T2	22		T4	76
valid_sources[0x41]	46469	1			T1	103		T2	22		T3	1
valid_sources[0x42]	45154	1			T1	101		T2	32		T4	55
valid_sources[0x43]	46147	1			T1	26		T2	35		T4	352
valid_sources[0x44]	50597	1			T1	3		T2	14		T4	1555
valid_sources[0x45]	43395	1			T1	6		T2	23		T4	287
valid_sources[0x46]	41716	1			T1	143		T2	21		T4	281
valid_sources[0x47]	44426	1			T1	208		T2	20		T4	142
valid_sources[0x48]	52499	1			T1	291		T2	14		T4	744
valid_sources[0x49]	46693	1			T1	189		T2	30		T4	108
valid_sources[0x4a]	42340	1			T1	225		T2	19		T4	86
valid_sources[0x4b]	43055	1			T1	547		T2	29		T4	15
valid_sources[0x4c]	46744	1			T1	121		T2	40		T4	363
valid_sources[0x4d]	44787	1			T1	78		T2	18		T4	225
valid_sources[0x4e]	43596	1			T1	222		T2	29		T3	1
valid_sources[0x4f]	43806	1			T1	159		T2	22		T4	612
valid_sources[0x50]	48787	1			T1	118		T2	26		T3	1
valid_sources[0x51]	47025	1			T1	240		T2	19		T4	635
valid_sources[0x52]	43736	1			T1	66		T2	12		T4	159
valid_sources[0x53]	42419	1			T1	218		T2	22		T3	1
valid_sources[0x54]	44148	1			T1	3		T2	25		T4	578
valid_sources[0x55]	44297	1			T1	4		T2	30		T4	433
valid_sources[0x56]	47970	1			T1	30		T2	22		T4	1174
valid_sources[0x57]	45270	1			T1	61		T2	29		T3	1
valid_sources[0x58]	45343	1			T1	198		T2	18		T4	445
valid_sources[0x59]	42105	1			T1	539		T2	16		T4	668
valid_sources[0x5a]	44063	1			T1	517		T2	19		T4	118
valid_sources[0x5b]	45271	1			T1	27		T2	16		T4	81
valid_sources[0x5c]	46674	1			T1	585		T2	15		T3	1
valid_sources[0x5d]	44647	1			T1	85		T2	26		T3	1
valid_sources[0x5e]	46656	1			T1	130		T2	28		T4	70
valid_sources[0x5f]	44025	1			T1	4		T2	24		T3	3
valid_sources[0x60]	43753	1			T1	110		T2	30		T4	668
valid_sources[0x61]	45072	1			T1	159		T2	17		T4	35
valid_sources[0x62]	41793	1			T1	50		T2	22		T4	150
valid_sources[0x63]	42859	1			T1	97		T2	25		T4	626
valid_sources[0x64]	44222	1			T1	171		T2	18		T4	318
valid_sources[0x65]	43573	1			T1	4		T2	28		T4	108
valid_sources[0x66]	46173	1			T1	45		T2	23		T4	228
valid_sources[0x67]	43004	1			T1	46		T2	21		T4	171
valid_sources[0x68]	43469	1			T1	172		T2	24		T3	3
valid_sources[0x69]	46886	1			T1	193		T2	18		T4	879
valid_sources[0x6a]	43880	1			T1	295		T2	16		T3	1
valid_sources[0x6b]	45357	1			T1	996		T2	20		T4	391
valid_sources[0x6c]	43584	1			T1	22		T2	22		T4	546
valid_sources[0x6d]	44366	1			T1	42		T2	26		T4	239
valid_sources[0x6e]	46033	1			T1	192		T2	19		T3	2
valid_sources[0x6f]	44207	1			T1	81		T2	29		T4	206
valid_sources[0x70]	43200	1			T1	94		T2	21		T4	928
valid_sources[0x71]	43479	1			T1	269		T2	29		T4	133
valid_sources[0x72]	48055	1			T1	36		T2	14		T4	261
valid_sources[0x73]	44788	1			T1	205		T2	30		T4	138
valid_sources[0x74]	46244	1			T1	69		T2	12		T4	218
valid_sources[0x75]	44844	1			T1	116		T2	26		T4	124
valid_sources[0x76]	48722	1			T1	63		T2	23		T3	1
valid_sources[0x77]	45946	1			T1	561		T2	24		T4	110
valid_sources[0x78]	43816	1			T1	34		T2	26		T4	127
valid_sources[0x79]	44347	1			T1	96		T2	24		T4	79
valid_sources[0x7a]	44953	1			T1	111		T2	30		T4	214
valid_sources[0x7b]	43248	1			T1	28		T2	19		T4	95
valid_sources[0x7c]	45229	1			T1	110		T2	26		T3	1
valid_sources[0x7d]	55709	1			T1	21		T2	25		T4	621
valid_sources[0x7e]	46001	1			T1	73		T2	34		T3	2
valid_sources[0x7f]	43988	1			T1	120		T2	24		T4	267
valid_sources[0x80]	43885	1			T1	14		T2	14		T4	81

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2177879

1

T1

6391

T2

749

T3

1

values[0x0]

all_enables

biggest_size

1938261

1

T1

10493

T2

1159

T4

16780

values[0x1]

all_enables

biggest_size

1904730

1

T1

10238

T2

1088

T4

16711