Unified Coverage Report :: Group :: cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg

Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_errors_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_errors_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_errors_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group Instance tl_errors_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_csr_size_err	2	0	2	100.00	100	1	1	2
cp_instr_type_err	2	0	2	100.00	100	1	1	2
cp_mem_byte_access_err	2	0	2	100.00	100	1	1	2
cp_mem_ro_err	2	0	2	100.00	100	1	1	2
cp_mem_wo_err	2	0	2	100.00	100	1	1	2
cp_tl_protocol_err	1	0	1	100.00	100	1	1	0
cp_unmapped_err	2	0	2	100.00	100	1	1	2
cp_write_w_instr_type_err	2	0	2	100.00	100	1	1	2

Summary for Variable cp_csr_size_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_csr_size_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4044

1

T79

119

T80

1

T82

7

auto[1]

1215

1

T79

29

T81

1

T84

1

---

Summary for Variable cp_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_instr_type_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4465

1

T79

109

T80

1

T81

1

auto[1]

794

1

T79

39

T82

2

T84

2

---

Summary for Variable cp_mem_byte_access_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_mem_byte_access_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4829

1

T79

131

T80

1

T81

1

auto[1]

430

1

T79

17

T82

1

T83

15

---

Summary for Variable cp_mem_ro_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_mem_ro_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5257

1

T79

148

T80

1

T81

1

auto[1]

2

1

T160

1

T161

1

-

-

---

Summary for Variable cp_mem_wo_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_mem_wo_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5013

1

T79

148

T80

1

T81

1

auto[1]

246

1

T83

17

T87

12

T92

18

---

Summary for Variable cp_tl_protocol_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_tl_protocol_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

covered

967

1

T79

20

T83

17

T87

27

---

Summary for Variable cp_unmapped_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_unmapped_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5067

1

T79

144

T80

1

T81

1

auto[1]

192

1

T79

4

T84

1

T83

12

---

Summary for Variable cp_write_w_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write_w_instr_type_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3881

1

T79

109

T80

1

T81

1

auto[1]

1378

1

T79

39

T82

4

T84

4