Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5549743

1

T1

13851

T2

2926

T3

74

full_word

6019980

1

T1

27122

T2

2996

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	11569333	1			T1	40973		T2	5922		T3	75
auto[TlIntgErrCmd]	131	1			T80	8		T85	11		T86	7
auto[TlIntgErrData]	126	1			T80	4		T85	7		T86	10
auto[TlIntgErrBoth]	133	1			T80	8		T85	12		T86	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7267961

1

T1

18641

T2

3023

T3

75

auto[1]

4301762

1

T1

22332

T2

2899

T4

37289

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5089848	1			T1	12250		T2	2274		T3	74
auto[TlIntgErrNone]	partial	auto[1]	459538	1			T1	1601		T2	652		T4	3798
auto[TlIntgErrNone]	full_word	auto[0]	2177955	1			T1	6391		T2	749		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3841992	1			T1	20731		T2	2247		T4	33491
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T80	3		T85	1		T86	2
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T80	4		T85	9		T86	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T80	1		T86	1		T162	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T85	1		T86	1		T164	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T80	2		T85	2		T86	4
auto[TlIntgErrData]	partial	auto[1]	71	1			T80	2		T85	3		T86	6
auto[TlIntgErrData]	full_word	auto[0]	4	1			T85	1		T165	1		T166	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T85	1		T133	2		T166	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T80	3		T85	3		T86	4
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T80	5		T85	7		T86	9
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T85	1		T165	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T85	1		T130	3		T164	1