Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T4,T8

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T4,T8

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1551593271	3361	0	0
SrcPulseCheck_M	531748941	3361	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551593271	3361	0	0
T1	952391	26	0	0
T2	194435	0	0	0
T3	1786	0	0	0
T4	437635	17	0	0
T5	47484	0	0	0
T6	611136	0	0	0
T7	82746	0	0	0
T8	876138	24	0	0
T9	11569	0	0	0
T10	1284	0	0	0
T11	0	14	0	0
T13	0	14	0	0
T14	116666	13	0	0
T17	1387980	0	0	0
T24	349080	0	0	0
T25	774918	2	0	0
T26	0	3	0	0
T27	0	1	0	0
T34	0	7	0	0
T35	0	7	0	0
T36	0	18	0	0
T38	111762	0	0	0
T39	1093862	0	0	0
T40	1128722	19	0	0
T50	2292	0	0	0
T117	0	7	0	0
T118	0	3	0	0
T119	0	22	0	0
T120	0	7	0	0
T121	0	17	0	0
T122	0	7	0	0
T123	0	7	0	0
T124	0	2	0	0
T125	259902	0	0	0
T126	2652	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	531748941	3361	0	0
T1	890453	26	0	0
T2	162853	0	0	0
T4	211662	17	0	0
T5	79536	0	0	0
T6	184281	0	0	0
T7	76580	0	0	0
T8	108470	24	0	0
T9	4880	0	0	0
T11	804480	14	0	0
T13	0	14	0	0
T14	200246	13	0	0
T15	102409	0	0	0
T17	169956	0	0	0
T24	305296	0	0	0
T25	1464310	2	0	0
T26	0	3	0	0
T27	0	1	0	0
T34	0	7	0	0
T35	0	7	0	0
T36	0	18	0	0
T38	99520	0	0	0
T39	180372	0	0	0
T40	226390	19	0	0
T73	235514	0	0	0
T117	0	7	0	0
T118	0	3	0	0
T119	0	22	0	0
T120	0	7	0	0
T121	0	17	0	0
T122	0	7	0	0
T123	0	7	0	0
T124	0	2	0	0
T125	518680	0	0	0
T127	109864	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T14,T34,T35
1	0	Covered	T14,T34,T35
1	1	Covered	T14,T34,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T34,T35
1	0	Covered	T14,T34,T35
1	1	Covered	T14,T34,T35

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	517197757	474	0	0
SrcPulseCheck_M	177249647	474	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	474	0	0
T14	58333	7	0	0
T17	693990	0	0	0
T24	174540	0	0	0
T25	387459	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T38	55881	0	0	0
T39	546931	0	0	0
T40	564361	0	0	0
T50	1146	0	0	0
T117	0	2	0	0
T119	0	11	0	0
T120	0	2	0	0
T121	0	9	0	0
T122	0	2	0	0
T123	0	2	0	0
T124	0	2	0	0
T125	129951	0	0	0
T126	1326	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	474	0	0
T14	100123	7	0	0
T17	84978	0	0	0
T24	152648	0	0	0
T25	732155	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T38	49760	0	0	0
T39	90186	0	0	0
T40	113195	0	0	0
T73	117757	0	0	0
T117	0	2	0	0
T119	0	11	0	0
T120	0	2	0	0
T121	0	9	0	0
T122	0	2	0	0
T123	0	2	0	0
T124	0	2	0	0
T125	259340	0	0	0
T127	54932	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T14,T34,T35
1	0	Covered	T14,T34,T35
1	1	Covered	T14,T34,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T34,T35
1	0	Covered	T14,T34,T35
1	1	Covered	T14,T34,T35

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	517197757	637	0	0
SrcPulseCheck_M	177249647	637	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	637	0	0
T14	58333	6	0	0
T17	693990	0	0	0
T24	174540	0	0	0
T25	387459	0	0	0
T34	0	5	0	0
T35	0	5	0	0
T38	55881	0	0	0
T39	546931	0	0	0
T40	564361	0	0	0
T50	1146	0	0	0
T117	0	5	0	0
T118	0	3	0	0
T119	0	11	0	0
T120	0	5	0	0
T121	0	8	0	0
T122	0	5	0	0
T123	0	5	0	0
T125	129951	0	0	0
T126	1326	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	637	0	0
T14	100123	6	0	0
T17	84978	0	0	0
T24	152648	0	0	0
T25	732155	0	0	0
T34	0	5	0	0
T35	0	5	0	0
T38	49760	0	0	0
T39	90186	0	0	0
T40	113195	0	0	0
T73	117757	0	0	0
T117	0	5	0	0
T118	0	3	0	0
T119	0	11	0	0
T120	0	5	0	0
T121	0	8	0	0
T122	0	5	0	0
T123	0	5	0	0
T125	259340	0	0	0
T127	54932	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T4,T8

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T4,T8

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	517197757	2250	0	0
SrcPulseCheck_M	177249647	2250	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	2250	0	0
T1	952391	26	0	0
T2	194435	0	0	0
T3	1786	0	0	0
T4	437635	17	0	0
T5	47484	0	0	0
T6	611136	0	0	0
T7	82746	0	0	0
T8	876138	24	0	0
T9	11569	0	0	0
T10	1284	0	0	0
T11	0	14	0	0
T13	0	14	0	0
T25	0	2	0	0
T26	0	3	0	0
T27	0	1	0	0
T36	0	18	0	0
T40	0	19	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	2250	0	0
T1	890453	26	0	0
T2	162853	0	0	0
T4	211662	17	0	0
T5	79536	0	0	0
T6	184281	0	0	0
T7	76580	0	0	0
T8	108470	24	0	0
T9	4880	0	0	0
T11	804480	14	0	0
T13	0	14	0	0
T15	102409	0	0	0
T25	0	2	0	0
T26	0	3	0	0
T27	0	1	0	0
T36	0	18	0	0
T40	0	19	0	0