Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	871697051	692555353	0	0
CheckNGreaterZero_A	2823	2823	0	0
GntImpliesReady_A	871697051	4063467	0	0
GntImpliesValid_A	871697051	4063467	0	0
GrantKnown_A	871697051	692555353	0	0
IdxKnown_A	871697051	692555353	0	0
IndexIsCorrect_A	871697051	4063467	0	0
LockArbDecision_A	871697051	0	0	0
NoReadyValidNoGrant_A	871697051	0	0	0
ReadyAndValidImplyGrant_A	871697051	4063467	0	0
ReqAndReadyImplyGrant_A	871697051	4063467	0	0
ReqImpliesValid_A	871697051	4063467	0	0
ReqStaysHighUntilGranted0_M	871697051	0	0	0
RoundRobin_A	871697051	3	0	941
ValidKnown_A	871697051	692555353	0	0
gen_data_port_assertion.DataFlow_A	871697051	4063467	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	692555353	0	0
T1	2733297	1833723	0	0
T2	520141	354215	0	0
T3	1786	1710	0	0
T4	860959	857251	0	0
T5	206556	126555	0	0
T6	979698	785860	0	0
T7	235906	158973	0	0
T8	1093078	984152	0	0
T9	21329	16350	0	0
T10	1284	1211	0	0
T11	1608960	803553	0	0
T12	0	124976	0	0
T13	0	761258	0	0
T14	0	99676	0	0
T15	204818	99256	0	0
T16	0	576	0	0
T17	0	82088	0	0
T24	0	148800	0	0
T25	0	160144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2823	2823	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	4063467	0	0
T1	2733297	27342	0	0
T2	520141	5784	0	0
T3	1786	0	0	0
T4	860959	38296	0	0
T5	206556	832	0	0
T6	979698	9686	0	0
T7	235906	832	0	0
T8	1093078	20611	0	0
T9	21329	832	0	0
T10	1284	0	0	0
T11	1608960	12766	0	0
T12	0	832	0	0
T13	0	9684	0	0
T15	204818	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2785	0	0
T26	0	5113	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	15446	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	4063467	0	0
T1	2733297	27342	0	0
T2	520141	5784	0	0
T3	1786	0	0	0
T4	860959	38296	0	0
T5	206556	832	0	0
T6	979698	9686	0	0
T7	235906	832	0	0
T8	1093078	20611	0	0
T9	21329	832	0	0
T10	1284	0	0	0
T11	1608960	12766	0	0
T12	0	832	0	0
T13	0	9684	0	0
T15	204818	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2785	0	0
T26	0	5113	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	15446	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	692555353	0	0
T1	2733297	1833723	0	0
T2	520141	354215	0	0
T3	1786	1710	0	0
T4	860959	857251	0	0
T5	206556	126555	0	0
T6	979698	785860	0	0
T7	235906	158973	0	0
T8	1093078	984152	0	0
T9	21329	16350	0	0
T10	1284	1211	0	0
T11	1608960	803553	0	0
T12	0	124976	0	0
T13	0	761258	0	0
T14	0	99676	0	0
T15	204818	99256	0	0
T16	0	576	0	0
T17	0	82088	0	0
T24	0	148800	0	0
T25	0	160144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	692555353	0	0
T1	2733297	1833723	0	0
T2	520141	354215	0	0
T3	1786	1710	0	0
T4	860959	857251	0	0
T5	206556	126555	0	0
T6	979698	785860	0	0
T7	235906	158973	0	0
T8	1093078	984152	0	0
T9	21329	16350	0	0
T10	1284	1211	0	0
T11	1608960	803553	0	0
T12	0	124976	0	0
T13	0	761258	0	0
T14	0	99676	0	0
T15	204818	99256	0	0
T16	0	576	0	0
T17	0	82088	0	0
T24	0	148800	0	0
T25	0	160144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	4063467	0	0
T1	2733297	27342	0	0
T2	520141	5784	0	0
T3	1786	0	0	0
T4	860959	38296	0	0
T5	206556	832	0	0
T6	979698	9686	0	0
T7	235906	832	0	0
T8	1093078	20611	0	0
T9	21329	832	0	0
T10	1284	0	0	0
T11	1608960	12766	0	0
T12	0	832	0	0
T13	0	9684	0	0
T15	204818	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2785	0	0
T26	0	5113	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	15446	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	4063467	0	0
T1	2733297	27342	0	0
T2	520141	5784	0	0
T3	1786	0	0	0
T4	860959	38296	0	0
T5	206556	832	0	0
T6	979698	9686	0	0
T7	235906	832	0	0
T8	1093078	20611	0	0
T9	21329	832	0	0
T10	1284	0	0	0
T11	1608960	12766	0	0
T12	0	832	0	0
T13	0	9684	0	0
T15	204818	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2785	0	0
T26	0	5113	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	15446	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	4063467	0	0
T1	2733297	27342	0	0
T2	520141	5784	0	0
T3	1786	0	0	0
T4	860959	38296	0	0
T5	206556	832	0	0
T6	979698	9686	0	0
T7	235906	832	0	0
T8	1093078	20611	0	0
T9	21329	832	0	0
T10	1284	0	0	0
T11	1608960	12766	0	0
T12	0	832	0	0
T13	0	9684	0	0
T15	204818	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2785	0	0
T26	0	5113	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	15446	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	4063467	0	0
T1	2733297	27342	0	0
T2	520141	5784	0	0
T3	1786	0	0	0
T4	860959	38296	0	0
T5	206556	832	0	0
T6	979698	9686	0	0
T7	235906	832	0	0
T8	1093078	20611	0	0
T9	21329	832	0	0
T10	1284	0	0	0
T11	1608960	12766	0	0
T12	0	832	0	0
T13	0	9684	0	0
T15	204818	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2785	0	0
T26	0	5113	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	15446	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	3	0	941
T30	438073	1	0	1
T31	874190	0	0	1
T32	172163	0	0	1
T41	0	1	0	0
T42	0	1	0	0
T43	186083	0	0	1
T44	656522	0	0	1
T45	34889	0	0	1
T46	1170	0	0	1
T47	97551	0	0	1
T48	109382	0	0	1
T49	9054	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	692555353	0	0
T1	2733297	1833723	0	0
T2	520141	354215	0	0
T3	1786	1710	0	0
T4	860959	857251	0	0
T5	206556	126555	0	0
T6	979698	785860	0	0
T7	235906	158973	0	0
T8	1093078	984152	0	0
T9	21329	16350	0	0
T10	1284	1211	0	0
T11	1608960	803553	0	0
T12	0	124976	0	0
T13	0	761258	0	0
T14	0	99676	0	0
T15	204818	99256	0	0
T16	0	576	0	0
T17	0	82088	0	0
T24	0	148800	0	0
T25	0	160144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871697051	4063467	0	0
T1	2733297	27342	0	0
T2	520141	5784	0	0
T3	1786	0	0	0
T4	860959	38296	0	0
T5	206556	832	0	0
T6	979698	9686	0	0
T7	235906	832	0	0
T8	1093078	20611	0	0
T9	21329	832	0	0
T10	1284	0	0	0
T11	1608960	12766	0	0
T12	0	832	0	0
T13	0	9684	0	0
T15	204818	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2785	0	0
T26	0	5113	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	15446	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	177249647	40268723	0	0
CheckNGreaterZero_A	941	941	0	0
GntImpliesReady_A	177249647	869967	0	0
GntImpliesValid_A	177249647	869967	0	0
GrantKnown_A	177249647	40268723	0	0
IdxKnown_A	177249647	40268723	0	0
IndexIsCorrect_A	177249647	869967	0	0
LockArbDecision_A	177249647	0	0	0
NoReadyValidNoGrant_A	177249647	0	0	0
ReadyAndValidImplyGrant_A	177249647	869967	0	0
ReqAndReadyImplyGrant_A	177249647	869967	0	0
ReqImpliesValid_A	177249647	869967	0	0
ReqStaysHighUntilGranted0_M	177249647	0	0	0
RoundRobin_A	177249647	0	0	0
ValidKnown_A	177249647	40268723	0	0
gen_data_port_assertion.DataFlow_A	177249647	869967	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	40268723	0	0
T1	890453	208296	0	0
T2	162853	159880	0	0
T4	211662	232608	0	0
T5	79536	0	0	0
T6	184281	174784	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	80848	0	0
T15	102409	99256	0	0
T16	0	576	0	0
T17	0	82088	0	0
T24	0	148800	0	0
T25	0	160144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	941	941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	869967	0	0
T1	890453	4719	0	0
T2	162853	3812	0	0
T4	211662	7752	0	0
T5	79536	0	0	0
T6	184281	6530	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	3420	0	0
T15	102409	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2522	0	0
T26	0	4468	0	0
T40	0	8059	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	869967	0	0
T1	890453	4719	0	0
T2	162853	3812	0	0
T4	211662	7752	0	0
T5	79536	0	0	0
T6	184281	6530	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	3420	0	0
T15	102409	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2522	0	0
T26	0	4468	0	0
T40	0	8059	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	40268723	0	0
T1	890453	208296	0	0
T2	162853	159880	0	0
T4	211662	232608	0	0
T5	79536	0	0	0
T6	184281	174784	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	80848	0	0
T15	102409	99256	0	0
T16	0	576	0	0
T17	0	82088	0	0
T24	0	148800	0	0
T25	0	160144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	40268723	0	0
T1	890453	208296	0	0
T2	162853	159880	0	0
T4	211662	232608	0	0
T5	79536	0	0	0
T6	184281	174784	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	80848	0	0
T15	102409	99256	0	0
T16	0	576	0	0
T17	0	82088	0	0
T24	0	148800	0	0
T25	0	160144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	869967	0	0
T1	890453	4719	0	0
T2	162853	3812	0	0
T4	211662	7752	0	0
T5	79536	0	0	0
T6	184281	6530	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	3420	0	0
T15	102409	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2522	0	0
T26	0	4468	0	0
T40	0	8059	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	869967	0	0
T1	890453	4719	0	0
T2	162853	3812	0	0
T4	211662	7752	0	0
T5	79536	0	0	0
T6	184281	6530	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	3420	0	0
T15	102409	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2522	0	0
T26	0	4468	0	0
T40	0	8059	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	869967	0	0
T1	890453	4719	0	0
T2	162853	3812	0	0
T4	211662	7752	0	0
T5	79536	0	0	0
T6	184281	6530	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	3420	0	0
T15	102409	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2522	0	0
T26	0	4468	0	0
T40	0	8059	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	869967	0	0
T1	890453	4719	0	0
T2	162853	3812	0	0
T4	211662	7752	0	0
T5	79536	0	0	0
T6	184281	6530	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	3420	0	0
T15	102409	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2522	0	0
T26	0	4468	0	0
T40	0	8059	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	40268723	0	0
T1	890453	208296	0	0
T2	162853	159880	0	0
T4	211662	232608	0	0
T5	79536	0	0	0
T6	184281	174784	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	80848	0	0
T15	102409	99256	0	0
T16	0	576	0	0
T17	0	82088	0	0
T24	0	148800	0	0
T25	0	160144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	869967	0	0
T1	890453	4719	0	0
T2	162853	3812	0	0
T4	211662	7752	0	0
T5	79536	0	0	0
T6	184281	6530	0	0
T7	76580	0	0	0
T8	108470	0	0	0
T9	4880	0	0	0
T11	804480	0	0	0
T13	0	3420	0	0
T15	102409	0	0	0
T17	0	4121	0	0
T24	0	3706	0	0
T25	0	2522	0	0
T26	0	4468	0	0
T40	0	8059	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	177249647	135171707	0	0
CheckNGreaterZero_A	941	941	0	0
GntImpliesReady_A	177249647	575341	0	0
GntImpliesValid_A	177249647	575341	0	0
GrantKnown_A	177249647	135171707	0	0
IdxKnown_A	177249647	135171707	0	0
IndexIsCorrect_A	177249647	575341	0	0
LockArbDecision_A	177249647	0	0	0
NoReadyValidNoGrant_A	177249647	0	0	0
ReadyAndValidImplyGrant_A	177249647	575341	0	0
ReqAndReadyImplyGrant_A	177249647	575341	0	0
ReqImpliesValid_A	177249647	575341	0	0
ReqStaysHighUntilGranted0_M	177249647	0	0	0
RoundRobin_A	177249647	0	0	0
ValidKnown_A	177249647	135171707	0	0
gen_data_port_assertion.DataFlow_A	177249647	575341	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	135171707	0	0
T1	890453	673131	0	0
T2	162853	0	0	0
T4	211662	187019	0	0
T5	79536	79162	0	0
T6	184281	0	0	0
T7	76580	76320	0	0
T8	108470	108022	0	0
T9	4880	4880	0	0
T11	804480	803553	0	0
T12	0	124976	0	0
T13	0	680410	0	0
T14	0	99676	0	0
T15	102409	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	941	941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	575341	0	0
T1	890453	4735	0	0
T2	162853	0	0	0
T4	211662	6322	0	0
T5	79536	0	0	0
T6	184281	0	0	0
T7	76580	0	0	0
T8	108470	8542	0	0
T9	4880	0	0	0
T11	804480	930	0	0
T13	0	6264	0	0
T15	102409	0	0	0
T25	0	263	0	0
T26	0	645	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	7387	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	575341	0	0
T1	890453	4735	0	0
T2	162853	0	0	0
T4	211662	6322	0	0
T5	79536	0	0	0
T6	184281	0	0	0
T7	76580	0	0	0
T8	108470	8542	0	0
T9	4880	0	0	0
T11	804480	930	0	0
T13	0	6264	0	0
T15	102409	0	0	0
T25	0	263	0	0
T26	0	645	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	7387	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	135171707	0	0
T1	890453	673131	0	0
T2	162853	0	0	0
T4	211662	187019	0	0
T5	79536	79162	0	0
T6	184281	0	0	0
T7	76580	76320	0	0
T8	108470	108022	0	0
T9	4880	4880	0	0
T11	804480	803553	0	0
T12	0	124976	0	0
T13	0	680410	0	0
T14	0	99676	0	0
T15	102409	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	135171707	0	0
T1	890453	673131	0	0
T2	162853	0	0	0
T4	211662	187019	0	0
T5	79536	79162	0	0
T6	184281	0	0	0
T7	76580	76320	0	0
T8	108470	108022	0	0
T9	4880	4880	0	0
T11	804480	803553	0	0
T12	0	124976	0	0
T13	0	680410	0	0
T14	0	99676	0	0
T15	102409	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	575341	0	0
T1	890453	4735	0	0
T2	162853	0	0	0
T4	211662	6322	0	0
T5	79536	0	0	0
T6	184281	0	0	0
T7	76580	0	0	0
T8	108470	8542	0	0
T9	4880	0	0	0
T11	804480	930	0	0
T13	0	6264	0	0
T15	102409	0	0	0
T25	0	263	0	0
T26	0	645	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	7387	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	575341	0	0
T1	890453	4735	0	0
T2	162853	0	0	0
T4	211662	6322	0	0
T5	79536	0	0	0
T6	184281	0	0	0
T7	76580	0	0	0
T8	108470	8542	0	0
T9	4880	0	0	0
T11	804480	930	0	0
T13	0	6264	0	0
T15	102409	0	0	0
T25	0	263	0	0
T26	0	645	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	7387	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	575341	0	0
T1	890453	4735	0	0
T2	162853	0	0	0
T4	211662	6322	0	0
T5	79536	0	0	0
T6	184281	0	0	0
T7	76580	0	0	0
T8	108470	8542	0	0
T9	4880	0	0	0
T11	804480	930	0	0
T13	0	6264	0	0
T15	102409	0	0	0
T25	0	263	0	0
T26	0	645	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	7387	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	575341	0	0
T1	890453	4735	0	0
T2	162853	0	0	0
T4	211662	6322	0	0
T5	79536	0	0	0
T6	184281	0	0	0
T7	76580	0	0	0
T8	108470	8542	0	0
T9	4880	0	0	0
T11	804480	930	0	0
T13	0	6264	0	0
T15	102409	0	0	0
T25	0	263	0	0
T26	0	645	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	7387	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	135171707	0	0
T1	890453	673131	0	0
T2	162853	0	0	0
T4	211662	187019	0	0
T5	79536	79162	0	0
T6	184281	0	0	0
T7	76580	76320	0	0
T8	108470	108022	0	0
T9	4880	4880	0	0
T11	804480	803553	0	0
T12	0	124976	0	0
T13	0	680410	0	0
T14	0	99676	0	0
T15	102409	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177249647	575341	0	0
T1	890453	4735	0	0
T2	162853	0	0	0
T4	211662	6322	0	0
T5	79536	0	0	0
T6	184281	0	0	0
T7	76580	0	0	0
T8	108470	8542	0	0
T9	4880	0	0	0
T11	804480	930	0	0
T13	0	6264	0	0
T15	102409	0	0	0
T25	0	263	0	0
T26	0	645	0	0
T27	0	3	0	0
T36	0	2075	0	0
T40	0	7387	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	517197757	517114923	0	0
CheckNGreaterZero_A	941	941	0	0
GntImpliesReady_A	517197757	2618159	0	0
GntImpliesValid_A	517197757	2618159	0	0
GrantKnown_A	517197757	517114923	0	0
IdxKnown_A	517197757	517114923	0	0
IndexIsCorrect_A	517197757	2618159	0	0
LockArbDecision_A	517197757	0	0	0
NoReadyValidNoGrant_A	517197757	0	0	0
ReadyAndValidImplyGrant_A	517197757	2618159	0	0
ReqAndReadyImplyGrant_A	517197757	2618159	0	0
ReqImpliesValid_A	517197757	2618159	0	0
ReqStaysHighUntilGranted0_M	517197757	0	0	0
RoundRobin_A	517197757	3	0	941
ValidKnown_A	517197757	517114923	0	0
gen_data_port_assertion.DataFlow_A	517197757	2618159	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	517114923	0	0
T1	952391	952296	0	0
T2	194435	194335	0	0
T3	1786	1710	0	0
T4	437635	437624	0	0
T5	47484	47393	0	0
T6	611136	611076	0	0
T7	82746	82653	0	0
T8	876138	876130	0	0
T9	11569	11470	0	0
T10	1284	1211	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	941	941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	2618159	0	0
T1	952391	17888	0	0
T2	194435	1972	0	0
T3	1786	0	0	0
T4	437635	24222	0	0
T5	47484	832	0	0
T6	611136	3156	0	0
T7	82746	832	0	0
T8	876138	12069	0	0
T9	11569	832	0	0
T10	1284	0	0	0
T11	0	11836	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	2618159	0	0
T1	952391	17888	0	0
T2	194435	1972	0	0
T3	1786	0	0	0
T4	437635	24222	0	0
T5	47484	832	0	0
T6	611136	3156	0	0
T7	82746	832	0	0
T8	876138	12069	0	0
T9	11569	832	0	0
T10	1284	0	0	0
T11	0	11836	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	517114923	0	0
T1	952391	952296	0	0
T2	194435	194335	0	0
T3	1786	1710	0	0
T4	437635	437624	0	0
T5	47484	47393	0	0
T6	611136	611076	0	0
T7	82746	82653	0	0
T8	876138	876130	0	0
T9	11569	11470	0	0
T10	1284	1211	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	517114923	0	0
T1	952391	952296	0	0
T2	194435	194335	0	0
T3	1786	1710	0	0
T4	437635	437624	0	0
T5	47484	47393	0	0
T6	611136	611076	0	0
T7	82746	82653	0	0
T8	876138	876130	0	0
T9	11569	11470	0	0
T10	1284	1211	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	2618159	0	0
T1	952391	17888	0	0
T2	194435	1972	0	0
T3	1786	0	0	0
T4	437635	24222	0	0
T5	47484	832	0	0
T6	611136	3156	0	0
T7	82746	832	0	0
T8	876138	12069	0	0
T9	11569	832	0	0
T10	1284	0	0	0
T11	0	11836	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	2618159	0	0
T1	952391	17888	0	0
T2	194435	1972	0	0
T3	1786	0	0	0
T4	437635	24222	0	0
T5	47484	832	0	0
T6	611136	3156	0	0
T7	82746	832	0	0
T8	876138	12069	0	0
T9	11569	832	0	0
T10	1284	0	0	0
T11	0	11836	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	2618159	0	0
T1	952391	17888	0	0
T2	194435	1972	0	0
T3	1786	0	0	0
T4	437635	24222	0	0
T5	47484	832	0	0
T6	611136	3156	0	0
T7	82746	832	0	0
T8	876138	12069	0	0
T9	11569	832	0	0
T10	1284	0	0	0
T11	0	11836	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	2618159	0	0
T1	952391	17888	0	0
T2	194435	1972	0	0
T3	1786	0	0	0
T4	437635	24222	0	0
T5	47484	832	0	0
T6	611136	3156	0	0
T7	82746	832	0	0
T8	876138	12069	0	0
T9	11569	832	0	0
T10	1284	0	0	0
T11	0	11836	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	3	0	941
T30	438073	1	0	1
T31	874190	0	0	1
T32	172163	0	0	1
T41	0	1	0	0
T42	0	1	0	0
T43	186083	0	0	1
T44	656522	0	0	1
T45	34889	0	0	1
T46	1170	0	0	1
T47	97551	0	0	1
T48	109382	0	0	1
T49	9054	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	517114923	0	0
T1	952391	952296	0	0
T2	194435	194335	0	0
T3	1786	1710	0	0
T4	437635	437624	0	0
T5	47484	47393	0	0
T6	611136	611076	0	0
T7	82746	82653	0	0
T8	876138	876130	0	0
T9	11569	11470	0	0
T10	1284	1211	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517197757	2618159	0	0
T1	952391	17888	0	0
T2	194435	1972	0	0
T3	1786	0	0	0
T4	437635	24222	0	0
T5	47484	832	0	0
T6	611136	3156	0	0
T7	82746	832	0	0
T8	876138	12069	0	0
T9	11569	832	0	0
T10	1284	0	0	0
T11	0	11836	0	0
T12	0	832	0	0