Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
4122 |
0 |
0 |
T79 |
7931 |
129 |
0 |
0 |
T80 |
56752 |
5 |
0 |
0 |
T81 |
4861 |
4 |
0 |
0 |
T82 |
3405 |
3 |
0 |
0 |
T83 |
3677 |
160 |
0 |
0 |
T84 |
5261 |
13 |
0 |
0 |
T85 |
79784 |
3 |
0 |
0 |
T87 |
11778 |
230 |
0 |
0 |
T92 |
16584 |
284 |
0 |
0 |
T94 |
8191 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1422 |
0 |
0 |
T81 |
4861 |
7 |
0 |
0 |
T104 |
37339 |
242 |
0 |
0 |
T128 |
7794 |
36 |
0 |
0 |
T129 |
7711 |
21 |
0 |
0 |
T130 |
61402 |
32 |
0 |
0 |
T131 |
15356 |
16 |
0 |
0 |
T132 |
70932 |
109 |
0 |
0 |
T133 |
72450 |
97 |
0 |
0 |
T134 |
10440 |
8 |
0 |
0 |
T135 |
7377 |
19 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1269 |
0 |
0 |
T81 |
4861 |
3 |
0 |
0 |
T104 |
37339 |
240 |
0 |
0 |
T128 |
7794 |
18 |
0 |
0 |
T129 |
7711 |
20 |
0 |
0 |
T130 |
61402 |
41 |
0 |
0 |
T131 |
15356 |
30 |
0 |
0 |
T132 |
70932 |
61 |
0 |
0 |
T133 |
72450 |
70 |
0 |
0 |
T134 |
10440 |
5 |
0 |
0 |
T136 |
5431 |
5 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1701 |
0 |
0 |
T81 |
4861 |
17 |
0 |
0 |
T104 |
37339 |
279 |
0 |
0 |
T128 |
7794 |
23 |
0 |
0 |
T129 |
7711 |
18 |
0 |
0 |
T130 |
61402 |
85 |
0 |
0 |
T131 |
15356 |
34 |
0 |
0 |
T132 |
70932 |
129 |
0 |
0 |
T133 |
72450 |
203 |
0 |
0 |
T134 |
10440 |
5 |
0 |
0 |
T135 |
7377 |
22 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
6496 |
0 |
0 |
T92 |
16584 |
1 |
0 |
0 |
T104 |
37339 |
268 |
0 |
0 |
T128 |
7794 |
48 |
0 |
0 |
T129 |
7711 |
29 |
0 |
0 |
T130 |
61402 |
719 |
0 |
0 |
T131 |
15356 |
234 |
0 |
0 |
T132 |
70932 |
907 |
0 |
0 |
T133 |
72450 |
1871 |
0 |
0 |
T134 |
10440 |
135 |
0 |
0 |
T136 |
5431 |
44 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
6485 |
0 |
0 |
T81 |
4861 |
6 |
0 |
0 |
T104 |
37339 |
236 |
0 |
0 |
T108 |
3014 |
6 |
0 |
0 |
T129 |
7711 |
29 |
0 |
0 |
T130 |
61402 |
462 |
0 |
0 |
T131 |
15356 |
390 |
0 |
0 |
T132 |
70932 |
1512 |
0 |
0 |
T133 |
72450 |
1265 |
0 |
0 |
T134 |
10440 |
422 |
0 |
0 |
T136 |
5431 |
84 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
6608 |
0 |
0 |
T104 |
37339 |
223 |
0 |
0 |
T108 |
3014 |
6 |
0 |
0 |
T128 |
7794 |
13 |
0 |
0 |
T129 |
7711 |
12 |
0 |
0 |
T130 |
61402 |
823 |
0 |
0 |
T131 |
15356 |
370 |
0 |
0 |
T132 |
70932 |
1477 |
0 |
0 |
T133 |
72450 |
1152 |
0 |
0 |
T134 |
10440 |
155 |
0 |
0 |
T135 |
7377 |
15 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
5112 |
0 |
0 |
T81 |
4861 |
43 |
0 |
0 |
T104 |
37339 |
272 |
0 |
0 |
T128 |
7794 |
11 |
0 |
0 |
T129 |
7711 |
21 |
0 |
0 |
T130 |
61402 |
562 |
0 |
0 |
T131 |
15356 |
19 |
0 |
0 |
T132 |
70932 |
1213 |
0 |
0 |
T133 |
72450 |
985 |
0 |
0 |
T134 |
10440 |
119 |
0 |
0 |
T135 |
7377 |
12 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
5005 |
0 |
0 |
T104 |
37339 |
221 |
0 |
0 |
T128 |
7794 |
24 |
0 |
0 |
T129 |
7711 |
2 |
0 |
0 |
T130 |
61402 |
511 |
0 |
0 |
T131 |
15356 |
38 |
0 |
0 |
T132 |
70932 |
983 |
0 |
0 |
T133 |
72450 |
1017 |
0 |
0 |
T134 |
10440 |
12 |
0 |
0 |
T135 |
7377 |
5 |
0 |
0 |
T136 |
5431 |
81 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
6348 |
0 |
0 |
T81 |
4861 |
10 |
0 |
0 |
T104 |
37339 |
245 |
0 |
0 |
T128 |
7794 |
41 |
0 |
0 |
T129 |
7711 |
32 |
0 |
0 |
T130 |
61402 |
684 |
0 |
0 |
T131 |
15356 |
16 |
0 |
0 |
T132 |
70932 |
1360 |
0 |
0 |
T133 |
72450 |
1020 |
0 |
0 |
T134 |
10440 |
254 |
0 |
0 |
T136 |
5431 |
90 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
6259 |
0 |
0 |
T81 |
4861 |
110 |
0 |
0 |
T104 |
37339 |
208 |
0 |
0 |
T128 |
7794 |
8 |
0 |
0 |
T129 |
7711 |
24 |
0 |
0 |
T130 |
61402 |
718 |
0 |
0 |
T131 |
15356 |
141 |
0 |
0 |
T132 |
70932 |
1248 |
0 |
0 |
T133 |
72450 |
1334 |
0 |
0 |
T134 |
10440 |
13 |
0 |
0 |
T136 |
5431 |
74 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
6905 |
0 |
0 |
T81 |
4861 |
52 |
0 |
0 |
T104 |
37339 |
254 |
0 |
0 |
T128 |
7794 |
1 |
0 |
0 |
T129 |
7711 |
9 |
0 |
0 |
T130 |
61402 |
1067 |
0 |
0 |
T131 |
15356 |
275 |
0 |
0 |
T132 |
70932 |
1293 |
0 |
0 |
T133 |
72450 |
1320 |
0 |
0 |
T134 |
10440 |
122 |
0 |
0 |
T136 |
5431 |
83 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3181 |
0 |
0 |
T81 |
4861 |
37 |
0 |
0 |
T104 |
37339 |
268 |
0 |
0 |
T128 |
7794 |
35 |
0 |
0 |
T129 |
7711 |
53 |
0 |
0 |
T130 |
61402 |
172 |
0 |
0 |
T131 |
15356 |
109 |
0 |
0 |
T132 |
70932 |
681 |
0 |
0 |
T133 |
72450 |
488 |
0 |
0 |
T134 |
10440 |
100 |
0 |
0 |
T136 |
5431 |
16 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
2726 |
0 |
0 |
T81 |
4861 |
4 |
0 |
0 |
T104 |
37339 |
242 |
0 |
0 |
T128 |
7794 |
18 |
0 |
0 |
T129 |
7711 |
10 |
0 |
0 |
T130 |
61402 |
182 |
0 |
0 |
T131 |
15356 |
67 |
0 |
0 |
T132 |
70932 |
416 |
0 |
0 |
T133 |
72450 |
394 |
0 |
0 |
T134 |
10440 |
5 |
0 |
0 |
T135 |
7377 |
37 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3018 |
0 |
0 |
T81 |
4861 |
3 |
0 |
0 |
T104 |
37339 |
207 |
0 |
0 |
T128 |
7794 |
20 |
0 |
0 |
T129 |
7711 |
31 |
0 |
0 |
T130 |
61402 |
179 |
0 |
0 |
T131 |
15356 |
118 |
0 |
0 |
T132 |
70932 |
580 |
0 |
0 |
T133 |
72450 |
527 |
0 |
0 |
T134 |
10440 |
103 |
0 |
0 |
T136 |
5431 |
2 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3452 |
0 |
0 |
T81 |
4861 |
2 |
0 |
0 |
T104 |
37339 |
257 |
0 |
0 |
T128 |
7794 |
33 |
0 |
0 |
T129 |
7711 |
31 |
0 |
0 |
T130 |
61402 |
256 |
0 |
0 |
T131 |
15356 |
76 |
0 |
0 |
T132 |
70932 |
579 |
0 |
0 |
T133 |
72450 |
657 |
0 |
0 |
T134 |
10440 |
119 |
0 |
0 |
T136 |
5431 |
1 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3229 |
0 |
0 |
T81 |
4861 |
18 |
0 |
0 |
T104 |
37339 |
255 |
0 |
0 |
T128 |
7794 |
15 |
0 |
0 |
T129 |
7711 |
33 |
0 |
0 |
T130 |
61402 |
203 |
0 |
0 |
T131 |
15356 |
92 |
0 |
0 |
T132 |
70932 |
611 |
0 |
0 |
T133 |
72450 |
650 |
0 |
0 |
T134 |
10440 |
66 |
0 |
0 |
T136 |
5431 |
3 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3092 |
0 |
0 |
T81 |
4861 |
10 |
0 |
0 |
T104 |
37339 |
237 |
0 |
0 |
T128 |
7794 |
38 |
0 |
0 |
T129 |
7711 |
16 |
0 |
0 |
T130 |
61402 |
382 |
0 |
0 |
T131 |
15356 |
151 |
0 |
0 |
T132 |
70932 |
545 |
0 |
0 |
T133 |
72450 |
485 |
0 |
0 |
T134 |
10440 |
100 |
0 |
0 |
T136 |
5431 |
1 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3601 |
0 |
0 |
T81 |
4861 |
7 |
0 |
0 |
T104 |
37339 |
214 |
0 |
0 |
T128 |
7794 |
10 |
0 |
0 |
T129 |
7711 |
12 |
0 |
0 |
T130 |
61402 |
218 |
0 |
0 |
T131 |
15356 |
134 |
0 |
0 |
T132 |
70932 |
452 |
0 |
0 |
T133 |
72450 |
728 |
0 |
0 |
T134 |
10440 |
112 |
0 |
0 |
T136 |
5431 |
5 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3413 |
0 |
0 |
T81 |
4861 |
42 |
0 |
0 |
T104 |
37339 |
233 |
0 |
0 |
T128 |
7794 |
11 |
0 |
0 |
T130 |
61402 |
448 |
0 |
0 |
T131 |
15356 |
132 |
0 |
0 |
T132 |
70932 |
596 |
0 |
0 |
T133 |
72450 |
540 |
0 |
0 |
T134 |
10440 |
115 |
0 |
0 |
T135 |
7377 |
18 |
0 |
0 |
T136 |
5431 |
33 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3208 |
0 |
0 |
T81 |
4861 |
16 |
0 |
0 |
T104 |
37339 |
227 |
0 |
0 |
T128 |
7794 |
29 |
0 |
0 |
T129 |
7711 |
9 |
0 |
0 |
T130 |
61402 |
183 |
0 |
0 |
T131 |
15356 |
110 |
0 |
0 |
T132 |
70932 |
485 |
0 |
0 |
T133 |
72450 |
473 |
0 |
0 |
T134 |
10440 |
46 |
0 |
0 |
T136 |
5431 |
1 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3252 |
0 |
0 |
T81 |
4861 |
9 |
0 |
0 |
T104 |
37339 |
236 |
0 |
0 |
T128 |
7794 |
4 |
0 |
0 |
T129 |
7711 |
57 |
0 |
0 |
T130 |
61402 |
384 |
0 |
0 |
T131 |
15356 |
96 |
0 |
0 |
T132 |
70932 |
530 |
0 |
0 |
T133 |
72450 |
393 |
0 |
0 |
T134 |
10440 |
181 |
0 |
0 |
T136 |
5431 |
11 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3258 |
0 |
0 |
T81 |
4861 |
31 |
0 |
0 |
T87 |
11778 |
8 |
0 |
0 |
T104 |
37339 |
257 |
0 |
0 |
T128 |
7794 |
32 |
0 |
0 |
T129 |
7711 |
15 |
0 |
0 |
T130 |
61402 |
279 |
0 |
0 |
T131 |
15356 |
73 |
0 |
0 |
T132 |
70932 |
619 |
0 |
0 |
T133 |
72450 |
547 |
0 |
0 |
T136 |
5431 |
14 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3212 |
0 |
0 |
T81 |
4861 |
9 |
0 |
0 |
T104 |
37339 |
255 |
0 |
0 |
T128 |
7794 |
31 |
0 |
0 |
T129 |
7711 |
15 |
0 |
0 |
T130 |
61402 |
325 |
0 |
0 |
T131 |
15356 |
82 |
0 |
0 |
T132 |
70932 |
530 |
0 |
0 |
T133 |
72450 |
717 |
0 |
0 |
T134 |
10440 |
79 |
0 |
0 |
T135 |
7377 |
44 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3221 |
0 |
0 |
T81 |
4861 |
26 |
0 |
0 |
T104 |
37339 |
272 |
0 |
0 |
T128 |
7794 |
46 |
0 |
0 |
T129 |
7711 |
15 |
0 |
0 |
T130 |
61402 |
272 |
0 |
0 |
T131 |
15356 |
60 |
0 |
0 |
T132 |
70932 |
672 |
0 |
0 |
T133 |
72450 |
547 |
0 |
0 |
T134 |
10440 |
6 |
0 |
0 |
T136 |
5431 |
21 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3129 |
0 |
0 |
T81 |
4861 |
7 |
0 |
0 |
T104 |
37339 |
276 |
0 |
0 |
T128 |
7794 |
53 |
0 |
0 |
T129 |
7711 |
26 |
0 |
0 |
T130 |
61402 |
298 |
0 |
0 |
T131 |
15356 |
124 |
0 |
0 |
T132 |
70932 |
392 |
0 |
0 |
T133 |
72450 |
577 |
0 |
0 |
T134 |
10440 |
48 |
0 |
0 |
T136 |
5431 |
5 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
2965 |
0 |
0 |
T81 |
4861 |
6 |
0 |
0 |
T104 |
37339 |
264 |
0 |
0 |
T128 |
7794 |
11 |
0 |
0 |
T129 |
7711 |
20 |
0 |
0 |
T130 |
61402 |
343 |
0 |
0 |
T131 |
15356 |
113 |
0 |
0 |
T132 |
70932 |
453 |
0 |
0 |
T133 |
72450 |
468 |
0 |
0 |
T134 |
10440 |
54 |
0 |
0 |
T136 |
5431 |
8 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3123 |
0 |
0 |
T104 |
37339 |
263 |
0 |
0 |
T128 |
7794 |
33 |
0 |
0 |
T129 |
7711 |
32 |
0 |
0 |
T130 |
61402 |
234 |
0 |
0 |
T131 |
15356 |
43 |
0 |
0 |
T132 |
70932 |
454 |
0 |
0 |
T133 |
72450 |
483 |
0 |
0 |
T134 |
10440 |
105 |
0 |
0 |
T135 |
7377 |
5 |
0 |
0 |
T136 |
5431 |
20 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
2805 |
0 |
0 |
T104 |
37339 |
231 |
0 |
0 |
T128 |
7794 |
32 |
0 |
0 |
T129 |
7711 |
16 |
0 |
0 |
T130 |
61402 |
291 |
0 |
0 |
T131 |
15356 |
68 |
0 |
0 |
T132 |
70932 |
588 |
0 |
0 |
T133 |
72450 |
280 |
0 |
0 |
T134 |
10440 |
50 |
0 |
0 |
T135 |
7377 |
20 |
0 |
0 |
T136 |
5431 |
7 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3226 |
0 |
0 |
T81 |
4861 |
34 |
0 |
0 |
T104 |
37339 |
247 |
0 |
0 |
T128 |
7794 |
12 |
0 |
0 |
T129 |
7711 |
22 |
0 |
0 |
T130 |
61402 |
237 |
0 |
0 |
T131 |
15356 |
62 |
0 |
0 |
T132 |
70932 |
406 |
0 |
0 |
T133 |
72450 |
706 |
0 |
0 |
T134 |
10440 |
127 |
0 |
0 |
T136 |
5431 |
32 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
2862 |
0 |
0 |
T81 |
4861 |
19 |
0 |
0 |
T104 |
37339 |
228 |
0 |
0 |
T108 |
3014 |
55 |
0 |
0 |
T128 |
7794 |
4 |
0 |
0 |
T130 |
61402 |
291 |
0 |
0 |
T131 |
15356 |
112 |
0 |
0 |
T132 |
70932 |
414 |
0 |
0 |
T133 |
72450 |
418 |
0 |
0 |
T134 |
10440 |
124 |
0 |
0 |
T135 |
7377 |
4 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3174 |
0 |
0 |
T81 |
4861 |
28 |
0 |
0 |
T104 |
37339 |
242 |
0 |
0 |
T128 |
7794 |
16 |
0 |
0 |
T129 |
7711 |
42 |
0 |
0 |
T130 |
61402 |
422 |
0 |
0 |
T131 |
15356 |
94 |
0 |
0 |
T132 |
70932 |
540 |
0 |
0 |
T133 |
72450 |
505 |
0 |
0 |
T134 |
10440 |
10 |
0 |
0 |
T136 |
5431 |
7 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3210 |
0 |
0 |
T81 |
4861 |
4 |
0 |
0 |
T104 |
37339 |
270 |
0 |
0 |
T128 |
7794 |
1 |
0 |
0 |
T129 |
7711 |
31 |
0 |
0 |
T130 |
61402 |
380 |
0 |
0 |
T131 |
15356 |
76 |
0 |
0 |
T132 |
70932 |
524 |
0 |
0 |
T133 |
72450 |
592 |
0 |
0 |
T134 |
10440 |
81 |
0 |
0 |
T136 |
5431 |
33 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3142 |
0 |
0 |
T81 |
4861 |
17 |
0 |
0 |
T104 |
37339 |
250 |
0 |
0 |
T128 |
7794 |
26 |
0 |
0 |
T129 |
7711 |
35 |
0 |
0 |
T130 |
61402 |
254 |
0 |
0 |
T131 |
15356 |
26 |
0 |
0 |
T132 |
70932 |
559 |
0 |
0 |
T133 |
72450 |
403 |
0 |
0 |
T134 |
10440 |
168 |
0 |
0 |
T136 |
5431 |
31 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3507 |
0 |
0 |
T81 |
4861 |
29 |
0 |
0 |
T104 |
37339 |
237 |
0 |
0 |
T128 |
7794 |
36 |
0 |
0 |
T129 |
7711 |
7 |
0 |
0 |
T130 |
61402 |
446 |
0 |
0 |
T131 |
15356 |
151 |
0 |
0 |
T132 |
70932 |
460 |
0 |
0 |
T133 |
72450 |
764 |
0 |
0 |
T134 |
10440 |
156 |
0 |
0 |
T135 |
7377 |
18 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
2972 |
0 |
0 |
T81 |
4861 |
14 |
0 |
0 |
T104 |
37339 |
237 |
0 |
0 |
T128 |
7794 |
14 |
0 |
0 |
T129 |
7711 |
13 |
0 |
0 |
T130 |
61402 |
270 |
0 |
0 |
T131 |
15356 |
89 |
0 |
0 |
T132 |
70932 |
392 |
0 |
0 |
T133 |
72450 |
516 |
0 |
0 |
T134 |
10440 |
96 |
0 |
0 |
T136 |
5431 |
38 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1499 |
0 |
0 |
T81 |
4861 |
6 |
0 |
0 |
T104 |
37339 |
182 |
0 |
0 |
T128 |
7794 |
19 |
0 |
0 |
T130 |
61402 |
66 |
0 |
0 |
T131 |
15356 |
28 |
0 |
0 |
T132 |
70932 |
107 |
0 |
0 |
T133 |
72450 |
116 |
0 |
0 |
T134 |
10440 |
12 |
0 |
0 |
T135 |
7377 |
5 |
0 |
0 |
T136 |
5431 |
5 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1553 |
0 |
0 |
T81 |
4861 |
7 |
0 |
0 |
T92 |
16584 |
7 |
0 |
0 |
T104 |
37339 |
262 |
0 |
0 |
T128 |
7794 |
43 |
0 |
0 |
T129 |
7711 |
64 |
0 |
0 |
T130 |
61402 |
55 |
0 |
0 |
T131 |
15356 |
27 |
0 |
0 |
T132 |
70932 |
108 |
0 |
0 |
T133 |
72450 |
120 |
0 |
0 |
T136 |
5431 |
2 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1646 |
0 |
0 |
T81 |
4861 |
11 |
0 |
0 |
T104 |
37339 |
262 |
0 |
0 |
T128 |
7794 |
46 |
0 |
0 |
T129 |
7711 |
12 |
0 |
0 |
T130 |
61402 |
68 |
0 |
0 |
T131 |
15356 |
45 |
0 |
0 |
T132 |
70932 |
135 |
0 |
0 |
T133 |
72450 |
106 |
0 |
0 |
T134 |
10440 |
12 |
0 |
0 |
T136 |
5431 |
7 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1478 |
0 |
0 |
T81 |
4861 |
4 |
0 |
0 |
T104 |
37339 |
236 |
0 |
0 |
T128 |
7794 |
16 |
0 |
0 |
T129 |
7711 |
19 |
0 |
0 |
T130 |
61402 |
53 |
0 |
0 |
T131 |
15356 |
38 |
0 |
0 |
T132 |
70932 |
106 |
0 |
0 |
T133 |
72450 |
105 |
0 |
0 |
T134 |
10440 |
22 |
0 |
0 |
T136 |
5431 |
8 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1862 |
0 |
0 |
T81 |
4861 |
6 |
0 |
0 |
T104 |
37339 |
203 |
0 |
0 |
T128 |
7794 |
10 |
0 |
0 |
T129 |
7711 |
47 |
0 |
0 |
T130 |
61402 |
105 |
0 |
0 |
T131 |
15356 |
18 |
0 |
0 |
T132 |
70932 |
166 |
0 |
0 |
T133 |
72450 |
246 |
0 |
0 |
T134 |
10440 |
44 |
0 |
0 |
T136 |
5431 |
3 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
3255 |
0 |
0 |
T55 |
4454 |
35 |
0 |
0 |
T113 |
121719 |
42 |
0 |
0 |
T116 |
0 |
25 |
0 |
0 |
T137 |
0 |
23 |
0 |
0 |
T138 |
0 |
38 |
0 |
0 |
T139 |
0 |
68 |
0 |
0 |
T140 |
0 |
40 |
0 |
0 |
T141 |
0 |
70 |
0 |
0 |
T142 |
0 |
40 |
0 |
0 |
T143 |
0 |
9 |
0 |
0 |
T144 |
1933 |
0 |
0 |
0 |
T145 |
18911 |
0 |
0 |
0 |
T146 |
371081 |
0 |
0 |
0 |
T147 |
739023 |
0 |
0 |
0 |
T148 |
2448 |
0 |
0 |
0 |
T149 |
1397 |
0 |
0 |
0 |
T150 |
870 |
0 |
0 |
0 |
T151 |
224481 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1513 |
0 |
0 |
T81 |
4861 |
16 |
0 |
0 |
T104 |
37339 |
240 |
0 |
0 |
T128 |
7794 |
51 |
0 |
0 |
T129 |
7711 |
40 |
0 |
0 |
T130 |
61402 |
54 |
0 |
0 |
T131 |
15356 |
17 |
0 |
0 |
T132 |
70932 |
88 |
0 |
0 |
T133 |
72450 |
97 |
0 |
0 |
T134 |
10440 |
12 |
0 |
0 |
T135 |
7377 |
10 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1516 |
0 |
0 |
T104 |
37339 |
266 |
0 |
0 |
T128 |
7794 |
2 |
0 |
0 |
T129 |
7711 |
19 |
0 |
0 |
T130 |
61402 |
51 |
0 |
0 |
T131 |
15356 |
31 |
0 |
0 |
T132 |
70932 |
124 |
0 |
0 |
T133 |
72450 |
91 |
0 |
0 |
T134 |
10440 |
23 |
0 |
0 |
T135 |
7377 |
28 |
0 |
0 |
T136 |
5431 |
4 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1498 |
0 |
0 |
T104 |
37339 |
247 |
0 |
0 |
T128 |
7794 |
45 |
0 |
0 |
T129 |
7711 |
12 |
0 |
0 |
T130 |
61402 |
39 |
0 |
0 |
T131 |
15356 |
28 |
0 |
0 |
T132 |
70932 |
76 |
0 |
0 |
T133 |
72450 |
85 |
0 |
0 |
T134 |
10440 |
5 |
0 |
0 |
T135 |
7377 |
46 |
0 |
0 |
T136 |
5431 |
8 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1387 |
0 |
0 |
T81 |
4861 |
5 |
0 |
0 |
T104 |
37339 |
254 |
0 |
0 |
T128 |
7794 |
29 |
0 |
0 |
T129 |
7711 |
4 |
0 |
0 |
T130 |
61402 |
58 |
0 |
0 |
T131 |
15356 |
20 |
0 |
0 |
T132 |
70932 |
55 |
0 |
0 |
T133 |
72450 |
71 |
0 |
0 |
T134 |
10440 |
6 |
0 |
0 |
T136 |
5431 |
6 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1339 |
0 |
0 |
T81 |
4861 |
7 |
0 |
0 |
T104 |
37339 |
231 |
0 |
0 |
T129 |
7711 |
15 |
0 |
0 |
T130 |
61402 |
65 |
0 |
0 |
T131 |
15356 |
17 |
0 |
0 |
T132 |
70932 |
82 |
0 |
0 |
T133 |
72450 |
62 |
0 |
0 |
T134 |
10440 |
9 |
0 |
0 |
T135 |
7377 |
39 |
0 |
0 |
T136 |
5431 |
2 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1432 |
0 |
0 |
T81 |
4861 |
5 |
0 |
0 |
T104 |
37339 |
248 |
0 |
0 |
T128 |
7794 |
13 |
0 |
0 |
T129 |
7711 |
13 |
0 |
0 |
T130 |
61402 |
40 |
0 |
0 |
T131 |
15356 |
16 |
0 |
0 |
T132 |
70932 |
77 |
0 |
0 |
T133 |
72450 |
77 |
0 |
0 |
T134 |
10440 |
15 |
0 |
0 |
T136 |
5431 |
9 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1820 |
0 |
0 |
T81 |
4861 |
14 |
0 |
0 |
T104 |
37339 |
215 |
0 |
0 |
T128 |
7794 |
59 |
0 |
0 |
T129 |
7711 |
26 |
0 |
0 |
T130 |
61402 |
114 |
0 |
0 |
T131 |
15356 |
38 |
0 |
0 |
T132 |
70932 |
195 |
0 |
0 |
T133 |
72450 |
207 |
0 |
0 |
T134 |
10440 |
14 |
0 |
0 |
T135 |
7377 |
2 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1320 |
0 |
0 |
T81 |
4861 |
6 |
0 |
0 |
T87 |
11778 |
3 |
0 |
0 |
T104 |
37339 |
214 |
0 |
0 |
T128 |
7794 |
32 |
0 |
0 |
T129 |
7711 |
48 |
0 |
0 |
T130 |
61402 |
41 |
0 |
0 |
T131 |
15356 |
21 |
0 |
0 |
T132 |
70932 |
93 |
0 |
0 |
T133 |
72450 |
68 |
0 |
0 |
T134 |
10440 |
10 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
2133 |
0 |
0 |
T81 |
4861 |
7 |
0 |
0 |
T87 |
11778 |
2 |
0 |
0 |
T104 |
37339 |
265 |
0 |
0 |
T128 |
7794 |
12 |
0 |
0 |
T129 |
7711 |
23 |
0 |
0 |
T130 |
61402 |
88 |
0 |
0 |
T131 |
15356 |
48 |
0 |
0 |
T132 |
70932 |
300 |
0 |
0 |
T133 |
72450 |
228 |
0 |
0 |
T136 |
5431 |
10 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1529 |
0 |
0 |
T81 |
4861 |
8 |
0 |
0 |
T104 |
37339 |
220 |
0 |
0 |
T128 |
7794 |
12 |
0 |
0 |
T129 |
7711 |
20 |
0 |
0 |
T130 |
61402 |
65 |
0 |
0 |
T131 |
15356 |
23 |
0 |
0 |
T132 |
70932 |
121 |
0 |
0 |
T133 |
72450 |
103 |
0 |
0 |
T134 |
10440 |
17 |
0 |
0 |
T136 |
5431 |
4 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1368 |
0 |
0 |
T81 |
4861 |
5 |
0 |
0 |
T104 |
37339 |
256 |
0 |
0 |
T128 |
7794 |
9 |
0 |
0 |
T130 |
61402 |
24 |
0 |
0 |
T131 |
15356 |
36 |
0 |
0 |
T132 |
70932 |
75 |
0 |
0 |
T133 |
72450 |
72 |
0 |
0 |
T134 |
10440 |
15 |
0 |
0 |
T135 |
7377 |
29 |
0 |
0 |
T136 |
5431 |
9 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1370 |
0 |
0 |
T81 |
4861 |
10 |
0 |
0 |
T104 |
37339 |
281 |
0 |
0 |
T128 |
7794 |
6 |
0 |
0 |
T129 |
7711 |
9 |
0 |
0 |
T130 |
61402 |
34 |
0 |
0 |
T131 |
15356 |
21 |
0 |
0 |
T132 |
70932 |
77 |
0 |
0 |
T133 |
72450 |
92 |
0 |
0 |
T134 |
10440 |
8 |
0 |
0 |
T136 |
5431 |
2 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1318 |
0 |
0 |
T81 |
4861 |
8 |
0 |
0 |
T87 |
11778 |
7 |
0 |
0 |
T92 |
16584 |
3 |
0 |
0 |
T104 |
37339 |
230 |
0 |
0 |
T128 |
7794 |
24 |
0 |
0 |
T129 |
7711 |
9 |
0 |
0 |
T130 |
61402 |
57 |
0 |
0 |
T131 |
15356 |
10 |
0 |
0 |
T132 |
70932 |
72 |
0 |
0 |
T133 |
72450 |
65 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1360 |
0 |
0 |
T81 |
4861 |
8 |
0 |
0 |
T104 |
37339 |
267 |
0 |
0 |
T128 |
7794 |
32 |
0 |
0 |
T129 |
7711 |
10 |
0 |
0 |
T130 |
61402 |
39 |
0 |
0 |
T131 |
15356 |
30 |
0 |
0 |
T132 |
70932 |
78 |
0 |
0 |
T133 |
72450 |
59 |
0 |
0 |
T134 |
10440 |
11 |
0 |
0 |
T136 |
5431 |
2 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1262 |
0 |
0 |
T104 |
37339 |
237 |
0 |
0 |
T128 |
7794 |
14 |
0 |
0 |
T129 |
7711 |
8 |
0 |
0 |
T130 |
61402 |
42 |
0 |
0 |
T131 |
15356 |
24 |
0 |
0 |
T132 |
70932 |
63 |
0 |
0 |
T133 |
72450 |
53 |
0 |
0 |
T134 |
10440 |
13 |
0 |
0 |
T135 |
7377 |
9 |
0 |
0 |
T136 |
5431 |
5 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
519390724 |
1319 |
0 |
0 |
T81 |
4861 |
4 |
0 |
0 |
T104 |
37339 |
234 |
0 |
0 |
T128 |
7794 |
10 |
0 |
0 |
T129 |
7711 |
32 |
0 |
0 |
T130 |
61402 |
68 |
0 |
0 |
T131 |
15356 |
29 |
0 |
0 |
T132 |
70932 |
67 |
0 |
0 |
T133 |
72450 |
82 |
0 |
0 |
T134 |
10440 |
16 |
0 |
0 |
T136 |
5431 |
4 |
0 |
0 |