| T811 |
/workspace/coverage/default/31.spi_device_csb_read.1062477888 |
|
|
Mar 26 02:04:40 PM PDT 24 |
Mar 26 02:04:43 PM PDT 24 |
66057310 ps |
| T812 |
/workspace/coverage/default/15.spi_device_mem_parity.3120175259 |
|
|
Mar 26 02:02:42 PM PDT 24 |
Mar 26 02:02:43 PM PDT 24 |
18448139 ps |
| T813 |
/workspace/coverage/default/43.spi_device_read_buffer_direct.3598830771 |
|
|
Mar 26 02:06:00 PM PDT 24 |
Mar 26 02:06:05 PM PDT 24 |
106470616 ps |
| T814 |
/workspace/coverage/default/15.spi_device_read_buffer_direct.3142131771 |
|
|
Mar 26 02:02:58 PM PDT 24 |
Mar 26 02:03:04 PM PDT 24 |
1857203981 ps |
| T815 |
/workspace/coverage/default/37.spi_device_alert_test.925632606 |
|
|
Mar 26 02:05:26 PM PDT 24 |
Mar 26 02:05:27 PM PDT 24 |
13830086 ps |
| T261 |
/workspace/coverage/default/6.spi_device_flash_and_tpm.2250031810 |
|
|
Mar 26 02:01:27 PM PDT 24 |
Mar 26 02:08:46 PM PDT 24 |
617477665842 ps |
| T816 |
/workspace/coverage/default/30.spi_device_pass_cmd_filtering.1815332661 |
|
|
Mar 26 02:04:40 PM PDT 24 |
Mar 26 02:04:53 PM PDT 24 |
15723174664 ps |
| T817 |
/workspace/coverage/default/18.spi_device_flash_all.2115792089 |
|
|
Mar 26 02:03:20 PM PDT 24 |
Mar 26 02:05:24 PM PDT 24 |
84111005576 ps |
| T818 |
/workspace/coverage/default/43.spi_device_cfg_cmd.2571473570 |
|
|
Mar 26 02:05:58 PM PDT 24 |
Mar 26 02:06:03 PM PDT 24 |
105488997 ps |
| T819 |
/workspace/coverage/default/19.spi_device_pass_cmd_filtering.3294849321 |
|
|
Mar 26 02:03:18 PM PDT 24 |
Mar 26 02:03:24 PM PDT 24 |
904528483 ps |
| T820 |
/workspace/coverage/default/22.spi_device_read_buffer_direct.2612847656 |
|
|
Mar 26 02:03:48 PM PDT 24 |
Mar 26 02:03:55 PM PDT 24 |
27509390661 ps |
| T821 |
/workspace/coverage/default/13.spi_device_ram_cfg.814795221 |
|
|
Mar 26 02:02:30 PM PDT 24 |
Mar 26 02:02:31 PM PDT 24 |
15935458 ps |
| T822 |
/workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1915340037 |
|
|
Mar 26 02:05:42 PM PDT 24 |
Mar 26 02:06:11 PM PDT 24 |
34010491260 ps |
| T823 |
/workspace/coverage/default/48.spi_device_flash_all.1612554888 |
|
|
Mar 26 02:06:35 PM PDT 24 |
Mar 26 02:07:26 PM PDT 24 |
21446783610 ps |
| T824 |
/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.711305672 |
|
|
Mar 26 02:04:33 PM PDT 24 |
Mar 26 02:04:41 PM PDT 24 |
1360690171 ps |
| T825 |
/workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1798359271 |
|
|
Mar 26 02:03:46 PM PDT 24 |
Mar 26 02:04:06 PM PDT 24 |
21724017142 ps |
| T826 |
/workspace/coverage/default/16.spi_device_tpm_rw.3099997532 |
|
|
Mar 26 02:02:57 PM PDT 24 |
Mar 26 02:03:01 PM PDT 24 |
1128193208 ps |
| T827 |
/workspace/coverage/default/14.spi_device_flash_all.2825039037 |
|
|
Mar 26 02:02:44 PM PDT 24 |
Mar 26 02:03:12 PM PDT 24 |
3729216386 ps |
| T828 |
/workspace/coverage/default/12.spi_device_stress_all.516950280 |
|
|
Mar 26 02:02:27 PM PDT 24 |
Mar 26 02:07:36 PM PDT 24 |
53527719584 ps |
| T829 |
/workspace/coverage/default/39.spi_device_pass_cmd_filtering.2664569879 |
|
|
Mar 26 02:05:37 PM PDT 24 |
Mar 26 02:05:43 PM PDT 24 |
562637748 ps |
| T830 |
/workspace/coverage/default/12.spi_device_alert_test.4271656853 |
|
|
Mar 26 02:02:20 PM PDT 24 |
Mar 26 02:02:21 PM PDT 24 |
13351748 ps |
| T245 |
/workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.565898764 |
|
|
Mar 26 02:01:56 PM PDT 24 |
Mar 26 02:03:29 PM PDT 24 |
15364805508 ps |
| T831 |
/workspace/coverage/default/26.spi_device_intercept.2028159584 |
|
|
Mar 26 02:04:12 PM PDT 24 |
Mar 26 02:04:18 PM PDT 24 |
211676018 ps |
| T832 |
/workspace/coverage/default/6.spi_device_cfg_cmd.2666953173 |
|
|
Mar 26 02:01:29 PM PDT 24 |
Mar 26 02:01:33 PM PDT 24 |
474373498 ps |
| T833 |
/workspace/coverage/default/31.spi_device_intercept.1837633680 |
|
|
Mar 26 02:04:49 PM PDT 24 |
Mar 26 02:04:57 PM PDT 24 |
361068452 ps |
| T834 |
/workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1907934031 |
|
|
Mar 26 02:06:43 PM PDT 24 |
Mar 26 02:08:19 PM PDT 24 |
61166387603 ps |
| T835 |
/workspace/coverage/default/23.spi_device_flash_and_tpm.861186656 |
|
|
Mar 26 02:04:00 PM PDT 24 |
Mar 26 02:04:54 PM PDT 24 |
27585631454 ps |
| T836 |
/workspace/coverage/default/4.spi_device_tpm_rw.4142417127 |
|
|
Mar 26 02:01:13 PM PDT 24 |
Mar 26 02:01:15 PM PDT 24 |
462050461 ps |
| T837 |
/workspace/coverage/default/48.spi_device_tpm_sts_read.4159085603 |
|
|
Mar 26 02:06:34 PM PDT 24 |
Mar 26 02:06:36 PM PDT 24 |
30064726 ps |
| T838 |
/workspace/coverage/default/48.spi_device_upload.2637649713 |
|
|
Mar 26 02:06:36 PM PDT 24 |
Mar 26 02:07:11 PM PDT 24 |
11415059436 ps |
| T839 |
/workspace/coverage/default/49.spi_device_flash_mode.2596069044 |
|
|
Mar 26 02:06:43 PM PDT 24 |
Mar 26 02:06:51 PM PDT 24 |
356081683 ps |
| T840 |
/workspace/coverage/default/2.spi_device_ram_cfg.2410080246 |
|
|
Mar 26 02:01:04 PM PDT 24 |
Mar 26 02:01:05 PM PDT 24 |
43721471 ps |
| T841 |
/workspace/coverage/default/14.spi_device_cfg_cmd.1082076158 |
|
|
Mar 26 02:02:42 PM PDT 24 |
Mar 26 02:02:46 PM PDT 24 |
2012483046 ps |
| T842 |
/workspace/coverage/default/42.spi_device_flash_all.4109093428 |
|
|
Mar 26 02:06:07 PM PDT 24 |
Mar 26 02:06:53 PM PDT 24 |
5532038363 ps |
| T843 |
/workspace/coverage/default/42.spi_device_tpm_all.201016351 |
|
|
Mar 26 02:05:59 PM PDT 24 |
Mar 26 02:06:49 PM PDT 24 |
173161924158 ps |
| T844 |
/workspace/coverage/default/12.spi_device_pass_cmd_filtering.4151793703 |
|
|
Mar 26 02:02:16 PM PDT 24 |
Mar 26 02:02:24 PM PDT 24 |
1046340502 ps |
| T845 |
/workspace/coverage/default/17.spi_device_tpm_sts_read.3249606545 |
|
|
Mar 26 02:03:08 PM PDT 24 |
Mar 26 02:03:12 PM PDT 24 |
87046493 ps |
| T846 |
/workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3005453488 |
|
|
Mar 26 02:03:31 PM PDT 24 |
Mar 26 02:04:45 PM PDT 24 |
47858189440 ps |
| T847 |
/workspace/coverage/default/40.spi_device_csb_read.2493792670 |
|
|
Mar 26 02:05:36 PM PDT 24 |
Mar 26 02:05:37 PM PDT 24 |
16161265 ps |
| T848 |
/workspace/coverage/default/9.spi_device_mem_parity.3809896844 |
|
|
Mar 26 02:01:53 PM PDT 24 |
Mar 26 02:01:55 PM PDT 24 |
225596400 ps |
| T849 |
/workspace/coverage/default/11.spi_device_csb_read.877405074 |
|
|
Mar 26 02:02:17 PM PDT 24 |
Mar 26 02:02:17 PM PDT 24 |
30174337 ps |
| T850 |
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1704661667 |
|
|
Mar 26 02:01:55 PM PDT 24 |
Mar 26 02:02:03 PM PDT 24 |
9112895138 ps |
| T851 |
/workspace/coverage/default/1.spi_device_intercept.3229337134 |
|
|
Mar 26 02:01:02 PM PDT 24 |
Mar 26 02:01:08 PM PDT 24 |
1812838355 ps |
| T852 |
/workspace/coverage/default/10.spi_device_stress_all.3342142282 |
|
|
Mar 26 02:02:16 PM PDT 24 |
Mar 26 02:03:17 PM PDT 24 |
15869512471 ps |
| T853 |
/workspace/coverage/default/6.spi_device_upload.3702963400 |
|
|
Mar 26 02:01:32 PM PDT 24 |
Mar 26 02:01:38 PM PDT 24 |
1399491699 ps |
| T854 |
/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2130729589 |
|
|
Mar 26 02:02:44 PM PDT 24 |
Mar 26 02:02:50 PM PDT 24 |
1068354531 ps |
| T855 |
/workspace/coverage/default/46.spi_device_flash_and_tpm.3067259159 |
|
|
Mar 26 02:06:20 PM PDT 24 |
Mar 26 02:12:27 PM PDT 24 |
50227223489 ps |
| T856 |
/workspace/coverage/default/45.spi_device_cfg_cmd.2747707869 |
|
|
Mar 26 02:06:10 PM PDT 24 |
Mar 26 02:06:12 PM PDT 24 |
97412769 ps |
| T857 |
/workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2014744435 |
|
|
Mar 26 02:01:27 PM PDT 24 |
Mar 26 02:01:31 PM PDT 24 |
2148262560 ps |
| T858 |
/workspace/coverage/default/18.spi_device_intercept.1780815497 |
|
|
Mar 26 02:03:08 PM PDT 24 |
Mar 26 02:03:15 PM PDT 24 |
887192302 ps |
| T859 |
/workspace/coverage/default/36.spi_device_flash_all.1359685350 |
|
|
Mar 26 02:05:26 PM PDT 24 |
Mar 26 02:07:04 PM PDT 24 |
40962525963 ps |
| T860 |
/workspace/coverage/default/32.spi_device_upload.112857280 |
|
|
Mar 26 02:04:50 PM PDT 24 |
Mar 26 02:05:09 PM PDT 24 |
15294607299 ps |
| T861 |
/workspace/coverage/default/40.spi_device_flash_and_tpm.939539577 |
|
|
Mar 26 02:05:46 PM PDT 24 |
Mar 26 02:07:19 PM PDT 24 |
125358939648 ps |
| T862 |
/workspace/coverage/default/9.spi_device_read_buffer_direct.3729004506 |
|
|
Mar 26 02:02:09 PM PDT 24 |
Mar 26 02:02:13 PM PDT 24 |
528907441 ps |
| T863 |
/workspace/coverage/default/38.spi_device_csb_read.781497047 |
|
|
Mar 26 02:05:26 PM PDT 24 |
Mar 26 02:05:27 PM PDT 24 |
23878249 ps |
| T864 |
/workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1207321326 |
|
|
Mar 26 02:04:18 PM PDT 24 |
Mar 26 02:06:56 PM PDT 24 |
33943567300 ps |
| T865 |
/workspace/coverage/default/20.spi_device_csb_read.428123925 |
|
|
Mar 26 02:03:33 PM PDT 24 |
Mar 26 02:03:34 PM PDT 24 |
26033279 ps |
| T866 |
/workspace/coverage/default/28.spi_device_tpm_all.1461619171 |
|
|
Mar 26 02:04:25 PM PDT 24 |
Mar 26 02:04:36 PM PDT 24 |
1413178679 ps |
| T867 |
/workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4285161909 |
|
|
Mar 26 02:06:12 PM PDT 24 |
Mar 26 02:06:21 PM PDT 24 |
2941431786 ps |
| T868 |
/workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1549856756 |
|
|
Mar 26 02:05:35 PM PDT 24 |
Mar 26 02:09:55 PM PDT 24 |
43017504165 ps |
| T869 |
/workspace/coverage/default/5.spi_device_csb_read.381357684 |
|
|
Mar 26 02:01:27 PM PDT 24 |
Mar 26 02:01:29 PM PDT 24 |
30930823 ps |
| T870 |
/workspace/coverage/default/31.spi_device_alert_test.835929428 |
|
|
Mar 26 02:04:46 PM PDT 24 |
Mar 26 02:04:47 PM PDT 24 |
31053349 ps |
| T871 |
/workspace/coverage/default/29.spi_device_flash_mode.453832255 |
|
|
Mar 26 02:04:40 PM PDT 24 |
Mar 26 02:04:55 PM PDT 24 |
709723550 ps |
| T872 |
/workspace/coverage/default/32.spi_device_tpm_rw.3090591666 |
|
|
Mar 26 02:04:48 PM PDT 24 |
Mar 26 02:04:53 PM PDT 24 |
18233210 ps |
| T873 |
/workspace/coverage/default/24.spi_device_tpm_rw.2612191177 |
|
|
Mar 26 02:04:07 PM PDT 24 |
Mar 26 02:04:10 PM PDT 24 |
856967471 ps |
| T75 |
/workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.539663296 |
|
|
Mar 26 02:03:45 PM PDT 24 |
Mar 26 02:05:49 PM PDT 24 |
17184180899 ps |
| T874 |
/workspace/coverage/default/43.spi_device_tpm_all.1116395573 |
|
|
Mar 26 02:05:59 PM PDT 24 |
Mar 26 02:06:24 PM PDT 24 |
16117317969 ps |
| T875 |
/workspace/coverage/default/36.spi_device_tpm_all.3291126683 |
|
|
Mar 26 02:05:11 PM PDT 24 |
Mar 26 02:05:32 PM PDT 24 |
4605556438 ps |
| T876 |
/workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3637167904 |
|
|
Mar 26 02:06:35 PM PDT 24 |
Mar 26 02:08:39 PM PDT 24 |
5668047296 ps |
| T877 |
/workspace/coverage/default/15.spi_device_flash_all.2079923725 |
|
|
Mar 26 02:02:55 PM PDT 24 |
Mar 26 02:03:13 PM PDT 24 |
1296866284 ps |
| T878 |
/workspace/coverage/default/32.spi_device_flash_mode.4165403598 |
|
|
Mar 26 02:04:47 PM PDT 24 |
Mar 26 02:05:24 PM PDT 24 |
5357153578 ps |
| T879 |
/workspace/coverage/default/28.spi_device_cfg_cmd.1596399204 |
|
|
Mar 26 02:04:24 PM PDT 24 |
Mar 26 02:04:31 PM PDT 24 |
806769888 ps |
| T880 |
/workspace/coverage/default/14.spi_device_tpm_read_hw_reg.825489228 |
|
|
Mar 26 02:02:43 PM PDT 24 |
Mar 26 02:02:54 PM PDT 24 |
3098796080 ps |
| T881 |
/workspace/coverage/default/15.spi_device_flash_mode.3885318637 |
|
|
Mar 26 02:02:57 PM PDT 24 |
Mar 26 02:03:18 PM PDT 24 |
17151981324 ps |
| T882 |
/workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3958846164 |
|
|
Mar 26 02:05:47 PM PDT 24 |
Mar 26 02:07:35 PM PDT 24 |
51360281871 ps |
| T883 |
/workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2378877207 |
|
|
Mar 26 02:03:20 PM PDT 24 |
Mar 26 02:03:25 PM PDT 24 |
328352186 ps |
| T884 |
/workspace/coverage/default/36.spi_device_pass_cmd_filtering.2745994023 |
|
|
Mar 26 02:05:26 PM PDT 24 |
Mar 26 02:05:50 PM PDT 24 |
7372080561 ps |
| T885 |
/workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2658165756 |
|
|
Mar 26 02:02:09 PM PDT 24 |
Mar 26 02:05:55 PM PDT 24 |
157661359673 ps |
| T886 |
/workspace/coverage/default/16.spi_device_csb_read.239360437 |
|
|
Mar 26 02:02:54 PM PDT 24 |
Mar 26 02:02:55 PM PDT 24 |
18108178 ps |
| T887 |
/workspace/coverage/default/24.spi_device_tpm_all.221063621 |
|
|
Mar 26 02:04:00 PM PDT 24 |
Mar 26 02:04:08 PM PDT 24 |
646651280 ps |
| T888 |
/workspace/coverage/default/0.spi_device_tpm_sts_read.1489458539 |
|
|
Mar 26 02:00:50 PM PDT 24 |
Mar 26 02:00:52 PM PDT 24 |
23315709 ps |
| T889 |
/workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1593188697 |
|
|
Mar 26 02:04:12 PM PDT 24 |
Mar 26 02:04:16 PM PDT 24 |
58692875 ps |
| T890 |
/workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1575695512 |
|
|
Mar 26 02:04:48 PM PDT 24 |
Mar 26 02:05:33 PM PDT 24 |
21535175465 ps |
| T891 |
/workspace/coverage/default/21.spi_device_pass_cmd_filtering.2472176897 |
|
|
Mar 26 02:03:34 PM PDT 24 |
Mar 26 02:03:52 PM PDT 24 |
21878479498 ps |
| T255 |
/workspace/coverage/default/21.spi_device_flash_and_tpm.3947014689 |
|
|
Mar 26 02:03:47 PM PDT 24 |
Mar 26 02:08:24 PM PDT 24 |
195913673689 ps |
| T892 |
/workspace/coverage/default/44.spi_device_mailbox.632199111 |
|
|
Mar 26 02:06:12 PM PDT 24 |
Mar 26 02:06:43 PM PDT 24 |
10593760626 ps |
| T893 |
/workspace/coverage/default/16.spi_device_read_buffer_direct.29178605 |
|
|
Mar 26 02:02:58 PM PDT 24 |
Mar 26 02:03:01 PM PDT 24 |
95758617 ps |
| T894 |
/workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3364755080 |
|
|
Mar 26 02:03:08 PM PDT 24 |
Mar 26 02:03:30 PM PDT 24 |
24691313722 ps |
| T254 |
/workspace/coverage/default/21.spi_device_stress_all.576786180 |
|
|
Mar 26 02:03:47 PM PDT 24 |
Mar 26 02:08:48 PM PDT 24 |
26955443561 ps |
| T895 |
/workspace/coverage/default/6.spi_device_csb_read.3691446841 |
|
|
Mar 26 02:01:27 PM PDT 24 |
Mar 26 02:01:29 PM PDT 24 |
19964262 ps |
| T896 |
/workspace/coverage/default/41.spi_device_tpm_sts_read.2857646791 |
|
|
Mar 26 02:05:47 PM PDT 24 |
Mar 26 02:05:48 PM PDT 24 |
523427082 ps |
| T897 |
/workspace/coverage/default/26.spi_device_tpm_sts_read.2258337256 |
|
|
Mar 26 02:04:12 PM PDT 24 |
Mar 26 02:04:14 PM PDT 24 |
100476340 ps |
| T898 |
/workspace/coverage/default/37.spi_device_cfg_cmd.2888648907 |
|
|
Mar 26 02:05:25 PM PDT 24 |
Mar 26 02:05:32 PM PDT 24 |
2435368213 ps |
| T899 |
/workspace/coverage/default/21.spi_device_flash_all.2549881262 |
|
|
Mar 26 02:03:47 PM PDT 24 |
Mar 26 02:06:28 PM PDT 24 |
110990515661 ps |
| T900 |
/workspace/coverage/default/46.spi_device_upload.3579106492 |
|
|
Mar 26 02:06:24 PM PDT 24 |
Mar 26 02:07:01 PM PDT 24 |
24791102397 ps |
| T901 |
/workspace/coverage/default/18.spi_device_flash_mode.2493516226 |
|
|
Mar 26 02:03:06 PM PDT 24 |
Mar 26 02:03:57 PM PDT 24 |
20225033725 ps |
| T902 |
/workspace/coverage/default/25.spi_device_upload.995278310 |
|
|
Mar 26 02:04:13 PM PDT 24 |
Mar 26 02:04:24 PM PDT 24 |
3635085383 ps |
| T903 |
/workspace/coverage/default/12.spi_device_flash_all.3927980097 |
|
|
Mar 26 02:02:19 PM PDT 24 |
Mar 26 02:07:22 PM PDT 24 |
122550818005 ps |
| T904 |
/workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3443712655 |
|
|
Mar 26 02:05:12 PM PDT 24 |
Mar 26 02:05:21 PM PDT 24 |
5618989807 ps |
| T905 |
/workspace/coverage/default/44.spi_device_tpm_rw.601556266 |
|
|
Mar 26 02:06:09 PM PDT 24 |
Mar 26 02:06:10 PM PDT 24 |
23178824 ps |
| T239 |
/workspace/coverage/default/24.spi_device_flash_and_tpm.1933017237 |
|
|
Mar 26 02:04:02 PM PDT 24 |
Mar 26 02:14:33 PM PDT 24 |
82817024464 ps |
| T906 |
/workspace/coverage/default/16.spi_device_mem_parity.892915197 |
|
|
Mar 26 02:02:58 PM PDT 24 |
Mar 26 02:02:59 PM PDT 24 |
30888356 ps |
| T907 |
/workspace/coverage/default/47.spi_device_flash_all.1315107084 |
|
|
Mar 26 02:06:33 PM PDT 24 |
Mar 26 02:06:39 PM PDT 24 |
785355615 ps |
| T908 |
/workspace/coverage/default/26.spi_device_csb_read.3718144122 |
|
|
Mar 26 02:04:14 PM PDT 24 |
Mar 26 02:04:16 PM PDT 24 |
39918879 ps |
| T909 |
/workspace/coverage/default/5.spi_device_flash_and_tpm.1498569572 |
|
|
Mar 26 02:01:29 PM PDT 24 |
Mar 26 02:03:04 PM PDT 24 |
14055987900 ps |
| T910 |
/workspace/coverage/default/49.spi_device_flash_and_tpm.2666704935 |
|
|
Mar 26 02:06:41 PM PDT 24 |
Mar 26 02:09:30 PM PDT 24 |
12845091897 ps |
| T911 |
/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1935761680 |
|
|
Mar 26 02:04:17 PM PDT 24 |
Mar 26 02:04:30 PM PDT 24 |
2224660188 ps |
| T912 |
/workspace/coverage/default/6.spi_device_alert_test.2313272576 |
|
|
Mar 26 02:01:34 PM PDT 24 |
Mar 26 02:01:35 PM PDT 24 |
21343742 ps |
| T913 |
/workspace/coverage/default/42.spi_device_stress_all.1845717732 |
|
|
Mar 26 02:06:05 PM PDT 24 |
Mar 26 02:07:00 PM PDT 24 |
10776410208 ps |
| T914 |
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2199313353 |
|
|
Mar 26 02:01:37 PM PDT 24 |
Mar 26 02:01:46 PM PDT 24 |
2529058807 ps |
| T915 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.2342169057 |
|
|
Mar 26 02:01:03 PM PDT 24 |
Mar 26 02:01:20 PM PDT 24 |
65482054295 ps |
| T916 |
/workspace/coverage/default/21.spi_device_upload.769135378 |
|
|
Mar 26 02:03:32 PM PDT 24 |
Mar 26 02:03:36 PM PDT 24 |
208189502 ps |
| T917 |
/workspace/coverage/default/41.spi_device_alert_test.1437703391 |
|
|
Mar 26 02:05:52 PM PDT 24 |
Mar 26 02:05:53 PM PDT 24 |
83372975 ps |
| T918 |
/workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1172278558 |
|
|
Mar 26 02:05:56 PM PDT 24 |
Mar 26 02:06:01 PM PDT 24 |
1307579635 ps |
| T919 |
/workspace/coverage/default/1.spi_device_tpm_sts_read.3227290677 |
|
|
Mar 26 02:01:02 PM PDT 24 |
Mar 26 02:01:04 PM PDT 24 |
431849518 ps |
| T920 |
/workspace/coverage/default/36.spi_device_csb_read.2283854909 |
|
|
Mar 26 02:05:13 PM PDT 24 |
Mar 26 02:05:13 PM PDT 24 |
24789044 ps |
| T921 |
/workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3409971580 |
|
|
Mar 26 02:05:27 PM PDT 24 |
Mar 26 02:07:12 PM PDT 24 |
56137143914 ps |
| T922 |
/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3060652702 |
|
|
Mar 26 02:02:26 PM PDT 24 |
Mar 26 02:02:34 PM PDT 24 |
1654502110 ps |
| T923 |
/workspace/coverage/default/14.spi_device_tpm_rw.81121509 |
|
|
Mar 26 02:02:42 PM PDT 24 |
Mar 26 02:02:48 PM PDT 24 |
447471852 ps |
| T924 |
/workspace/coverage/default/41.spi_device_stress_all.252402160 |
|
|
Mar 26 02:05:49 PM PDT 24 |
Mar 26 02:05:50 PM PDT 24 |
159467838 ps |
| T925 |
/workspace/coverage/default/11.spi_device_read_buffer_direct.2387937657 |
|
|
Mar 26 02:02:18 PM PDT 24 |
Mar 26 02:02:22 PM PDT 24 |
613680177 ps |
| T926 |
/workspace/coverage/default/15.spi_device_cfg_cmd.3023321998 |
|
|
Mar 26 02:02:56 PM PDT 24 |
Mar 26 02:03:03 PM PDT 24 |
1960356774 ps |
| T927 |
/workspace/coverage/default/44.spi_device_tpm_sts_read.4118626654 |
|
|
Mar 26 02:06:10 PM PDT 24 |
Mar 26 02:06:11 PM PDT 24 |
120233090 ps |
| T928 |
/workspace/coverage/default/24.spi_device_mailbox.3996695787 |
|
|
Mar 26 02:04:02 PM PDT 24 |
Mar 26 02:04:24 PM PDT 24 |
7994815690 ps |
| T929 |
/workspace/coverage/default/27.spi_device_flash_and_tpm.1561267989 |
|
|
Mar 26 02:04:25 PM PDT 24 |
Mar 26 02:05:09 PM PDT 24 |
4013449582 ps |
| T930 |
/workspace/coverage/default/20.spi_device_read_buffer_direct.332559715 |
|
|
Mar 26 02:03:33 PM PDT 24 |
Mar 26 02:03:37 PM PDT 24 |
279503673 ps |
| T931 |
/workspace/coverage/default/0.spi_device_csb_read.944212641 |
|
|
Mar 26 02:00:50 PM PDT 24 |
Mar 26 02:00:52 PM PDT 24 |
22057018 ps |
| T932 |
/workspace/coverage/default/15.spi_device_flash_and_tpm.977291043 |
|
|
Mar 26 02:02:55 PM PDT 24 |
Mar 26 02:04:11 PM PDT 24 |
6794163380 ps |
| T933 |
/workspace/coverage/default/15.spi_device_tpm_all.137831142 |
|
|
Mar 26 02:02:41 PM PDT 24 |
Mar 26 02:02:44 PM PDT 24 |
141876436 ps |
| T934 |
/workspace/coverage/default/11.spi_device_stress_all.3494345220 |
|
|
Mar 26 02:02:27 PM PDT 24 |
Mar 26 02:02:28 PM PDT 24 |
38814614 ps |
| T935 |
/workspace/coverage/default/7.spi_device_tpm_rw.102791874 |
|
|
Mar 26 02:01:37 PM PDT 24 |
Mar 26 02:01:38 PM PDT 24 |
52700511 ps |
| T936 |
/workspace/coverage/default/22.spi_device_tpm_all.4017355838 |
|
|
Mar 26 02:03:48 PM PDT 24 |
Mar 26 02:04:04 PM PDT 24 |
2888388622 ps |
| T937 |
/workspace/coverage/default/1.spi_device_tpm_rw.2892852913 |
|
|
Mar 26 02:01:08 PM PDT 24 |
Mar 26 02:01:11 PM PDT 24 |
185123795 ps |
| T938 |
/workspace/coverage/default/27.spi_device_tpm_rw.1186465735 |
|
|
Mar 26 02:04:17 PM PDT 24 |
Mar 26 02:04:18 PM PDT 24 |
29080162 ps |
| T939 |
/workspace/coverage/default/47.spi_device_cfg_cmd.867263281 |
|
|
Mar 26 02:06:21 PM PDT 24 |
Mar 26 02:06:24 PM PDT 24 |
56569711 ps |
| T259 |
/workspace/coverage/default/7.spi_device_stress_all.1372892431 |
|
|
Mar 26 02:01:54 PM PDT 24 |
Mar 26 02:03:45 PM PDT 24 |
7343746592 ps |
| T940 |
/workspace/coverage/default/22.spi_device_pass_cmd_filtering.1554092979 |
|
|
Mar 26 02:03:49 PM PDT 24 |
Mar 26 02:04:13 PM PDT 24 |
11454801843 ps |
| T941 |
/workspace/coverage/default/0.spi_device_flash_mode.500224093 |
|
|
Mar 26 02:00:52 PM PDT 24 |
Mar 26 02:01:06 PM PDT 24 |
1028627409 ps |
| T942 |
/workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1689154291 |
|
|
Mar 26 02:04:15 PM PDT 24 |
Mar 26 02:04:30 PM PDT 24 |
5374637881 ps |
| T943 |
/workspace/coverage/default/31.spi_device_flash_all.2771112623 |
|
|
Mar 26 02:04:46 PM PDT 24 |
Mar 26 02:07:08 PM PDT 24 |
95804851388 ps |
| T944 |
/workspace/coverage/default/42.spi_device_upload.188426592 |
|
|
Mar 26 02:05:54 PM PDT 24 |
Mar 26 02:06:11 PM PDT 24 |
4239890692 ps |
| T945 |
/workspace/coverage/default/48.spi_device_alert_test.2462485230 |
|
|
Mar 26 02:06:33 PM PDT 24 |
Mar 26 02:06:35 PM PDT 24 |
35649733 ps |
| T946 |
/workspace/coverage/default/4.spi_device_alert_test.1643876525 |
|
|
Mar 26 02:01:24 PM PDT 24 |
Mar 26 02:01:25 PM PDT 24 |
38093714 ps |
| T947 |
/workspace/coverage/default/10.spi_device_flash_mode.1126180482 |
|
|
Mar 26 02:02:08 PM PDT 24 |
Mar 26 02:02:27 PM PDT 24 |
5136184094 ps |
| T948 |
/workspace/coverage/default/42.spi_device_alert_test.4234463640 |
|
|
Mar 26 02:06:07 PM PDT 24 |
Mar 26 02:06:08 PM PDT 24 |
11552137 ps |
| T949 |
/workspace/coverage/default/35.spi_device_flash_all.3187555437 |
|
|
Mar 26 02:05:15 PM PDT 24 |
Mar 26 02:05:45 PM PDT 24 |
15991291169 ps |
| T950 |
/workspace/coverage/default/26.spi_device_alert_test.758331003 |
|
|
Mar 26 02:04:11 PM PDT 24 |
Mar 26 02:04:13 PM PDT 24 |
30235514 ps |
| T951 |
/workspace/coverage/default/47.spi_device_tpm_rw.1127445241 |
|
|
Mar 26 02:06:22 PM PDT 24 |
Mar 26 02:06:24 PM PDT 24 |
248632014 ps |
| T952 |
/workspace/coverage/default/11.spi_device_upload.2698897311 |
|
|
Mar 26 02:02:18 PM PDT 24 |
Mar 26 02:02:40 PM PDT 24 |
20927315079 ps |
| T953 |
/workspace/coverage/default/35.spi_device_mailbox.1953700364 |
|
|
Mar 26 02:05:16 PM PDT 24 |
Mar 26 02:05:21 PM PDT 24 |
12526387503 ps |
| T954 |
/workspace/coverage/default/3.spi_device_mem_parity.426165341 |
|
|
Mar 26 02:01:13 PM PDT 24 |
Mar 26 02:01:14 PM PDT 24 |
27410918 ps |
| T246 |
/workspace/coverage/default/46.spi_device_stress_all.2643953448 |
|
|
Mar 26 02:06:21 PM PDT 24 |
Mar 26 02:08:07 PM PDT 24 |
28158825327 ps |
| T955 |
/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1946601472 |
|
|
Mar 26 02:04:47 PM PDT 24 |
Mar 26 02:04:54 PM PDT 24 |
3949467691 ps |
| T956 |
/workspace/coverage/default/33.spi_device_stress_all.4231174308 |
|
|
Mar 26 02:04:59 PM PDT 24 |
Mar 26 02:10:02 PM PDT 24 |
168761431301 ps |
| T957 |
/workspace/coverage/default/23.spi_device_intercept.3024252856 |
|
|
Mar 26 02:03:48 PM PDT 24 |
Mar 26 02:03:51 PM PDT 24 |
186211079 ps |
| T958 |
/workspace/coverage/default/28.spi_device_alert_test.2207251647 |
|
|
Mar 26 02:04:24 PM PDT 24 |
Mar 26 02:04:25 PM PDT 24 |
25644041 ps |
| T959 |
/workspace/coverage/default/38.spi_device_flash_all.1254022148 |
|
|
Mar 26 02:05:41 PM PDT 24 |
Mar 26 02:06:23 PM PDT 24 |
7460849287 ps |
| T960 |
/workspace/coverage/default/26.spi_device_cfg_cmd.2275474767 |
|
|
Mar 26 02:04:12 PM PDT 24 |
Mar 26 02:04:17 PM PDT 24 |
371227991 ps |
| T961 |
/workspace/coverage/default/48.spi_device_pass_addr_payload_swap.911923096 |
|
|
Mar 26 02:06:36 PM PDT 24 |
Mar 26 02:06:41 PM PDT 24 |
358846890 ps |
| T962 |
/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2108719647 |
|
|
Mar 26 02:04:12 PM PDT 24 |
Mar 26 02:04:22 PM PDT 24 |
4517752295 ps |
| T963 |
/workspace/coverage/default/22.spi_device_flash_all.2615361063 |
|
|
Mar 26 02:03:48 PM PDT 24 |
Mar 26 02:04:08 PM PDT 24 |
6524634038 ps |
| T964 |
/workspace/coverage/default/24.spi_device_intercept.3679618401 |
|
|
Mar 26 02:04:02 PM PDT 24 |
Mar 26 02:04:06 PM PDT 24 |
320194334 ps |
| T965 |
/workspace/coverage/default/9.spi_device_cfg_cmd.2085550226 |
|
|
Mar 26 02:02:08 PM PDT 24 |
Mar 26 02:02:10 PM PDT 24 |
298014366 ps |
| T966 |
/workspace/coverage/default/13.spi_device_read_buffer_direct.1214956273 |
|
|
Mar 26 02:02:30 PM PDT 24 |
Mar 26 02:02:37 PM PDT 24 |
2644089481 ps |
| T967 |
/workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1155164014 |
|
|
Mar 26 02:06:00 PM PDT 24 |
Mar 26 02:06:10 PM PDT 24 |
4441387032 ps |
| T968 |
/workspace/coverage/default/18.spi_device_cfg_cmd.4046803103 |
|
|
Mar 26 02:03:10 PM PDT 24 |
Mar 26 02:03:21 PM PDT 24 |
2862827078 ps |
| T969 |
/workspace/coverage/default/11.spi_device_flash_mode.3937175339 |
|
|
Mar 26 02:02:18 PM PDT 24 |
Mar 26 02:02:47 PM PDT 24 |
14664923962 ps |
| T970 |
/workspace/coverage/default/48.spi_device_flash_mode.951272463 |
|
|
Mar 26 02:06:33 PM PDT 24 |
Mar 26 02:07:32 PM PDT 24 |
23379851157 ps |
| T971 |
/workspace/coverage/default/13.spi_device_pass_cmd_filtering.4220722350 |
|
|
Mar 26 02:02:31 PM PDT 24 |
Mar 26 02:02:39 PM PDT 24 |
5870308935 ps |
| T972 |
/workspace/coverage/default/44.spi_device_flash_mode.16393622 |
|
|
Mar 26 02:06:12 PM PDT 24 |
Mar 26 02:06:24 PM PDT 24 |
1366854525 ps |
| T973 |
/workspace/coverage/default/7.spi_device_flash_all.300154887 |
|
|
Mar 26 02:01:53 PM PDT 24 |
Mar 26 02:02:45 PM PDT 24 |
13961605516 ps |
| T974 |
/workspace/coverage/default/0.spi_device_intercept.1108675535 |
|
|
Mar 26 02:00:49 PM PDT 24 |
Mar 26 02:01:06 PM PDT 24 |
19839707439 ps |
| T975 |
/workspace/coverage/default/35.spi_device_upload.390361434 |
|
|
Mar 26 02:05:11 PM PDT 24 |
Mar 26 02:05:46 PM PDT 24 |
105656443265 ps |
| T976 |
/workspace/coverage/default/39.spi_device_flash_all.1712154989 |
|
|
Mar 26 02:05:40 PM PDT 24 |
Mar 26 02:06:57 PM PDT 24 |
27635691760 ps |
| T977 |
/workspace/coverage/default/47.spi_device_alert_test.1509397226 |
|
|
Mar 26 02:06:33 PM PDT 24 |
Mar 26 02:06:35 PM PDT 24 |
13369544 ps |
| T978 |
/workspace/coverage/default/17.spi_device_stress_all.2224974322 |
|
|
Mar 26 02:03:08 PM PDT 24 |
Mar 26 02:07:43 PM PDT 24 |
201430003832 ps |
| T979 |
/workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2986862165 |
|
|
Mar 26 02:05:55 PM PDT 24 |
Mar 26 02:06:00 PM PDT 24 |
1698948934 ps |
| T980 |
/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1051481515 |
|
|
Mar 26 02:04:40 PM PDT 24 |
Mar 26 02:05:04 PM PDT 24 |
6569093599 ps |
| T981 |
/workspace/coverage/default/1.spi_device_mailbox.969849917 |
|
|
Mar 26 02:01:02 PM PDT 24 |
Mar 26 02:01:14 PM PDT 24 |
2677137722 ps |
| T249 |
/workspace/coverage/default/17.spi_device_flash_all.2535110831 |
|
|
Mar 26 02:03:09 PM PDT 24 |
Mar 26 02:03:35 PM PDT 24 |
6449938963 ps |
| T982 |
/workspace/coverage/default/44.spi_device_tpm_all.666445250 |
|
|
Mar 26 02:06:12 PM PDT 24 |
Mar 26 02:06:45 PM PDT 24 |
2308803716 ps |
| T983 |
/workspace/coverage/default/16.spi_device_intercept.3862220531 |
|
|
Mar 26 02:02:57 PM PDT 24 |
Mar 26 02:03:05 PM PDT 24 |
1836896370 ps |
| T984 |
/workspace/coverage/default/11.spi_device_mailbox.1590860628 |
|
|
Mar 26 02:02:20 PM PDT 24 |
Mar 26 02:02:37 PM PDT 24 |
18496561201 ps |
| T985 |
/workspace/coverage/default/31.spi_device_pass_cmd_filtering.1699428542 |
|
|
Mar 26 02:04:48 PM PDT 24 |
Mar 26 02:05:04 PM PDT 24 |
4400751722 ps |
| T986 |
/workspace/coverage/default/6.spi_device_tpm_rw.2845463218 |
|
|
Mar 26 02:01:33 PM PDT 24 |
Mar 26 02:01:35 PM PDT 24 |
321822886 ps |
| T987 |
/workspace/coverage/default/15.spi_device_upload.3513657041 |
|
|
Mar 26 02:02:57 PM PDT 24 |
Mar 26 02:03:15 PM PDT 24 |
29259763177 ps |
| T988 |
/workspace/coverage/default/18.spi_device_ram_cfg.1376688565 |
|
|
Mar 26 02:03:07 PM PDT 24 |
Mar 26 02:03:12 PM PDT 24 |
39276545 ps |
| T989 |
/workspace/coverage/default/27.spi_device_stress_all.1374722413 |
|
|
Mar 26 02:04:24 PM PDT 24 |
Mar 26 02:09:48 PM PDT 24 |
50336796320 ps |
| T990 |
/workspace/coverage/default/18.spi_device_pass_cmd_filtering.629746967 |
|
|
Mar 26 02:03:08 PM PDT 24 |
Mar 26 02:03:27 PM PDT 24 |
4295849585 ps |
| T991 |
/workspace/coverage/default/33.spi_device_intercept.4249242803 |
|
|
Mar 26 02:05:01 PM PDT 24 |
Mar 26 02:05:06 PM PDT 24 |
253732117 ps |
| T992 |
/workspace/coverage/default/2.spi_device_mailbox.3068220053 |
|
|
Mar 26 02:01:01 PM PDT 24 |
Mar 26 02:01:14 PM PDT 24 |
1926287730 ps |
| T993 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.2229553041 |
|
|
Mar 26 01:32:17 PM PDT 24 |
Mar 26 01:32:18 PM PDT 24 |
31711230 ps |
| T994 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.2883543508 |
|
|
Mar 26 01:32:18 PM PDT 24 |
Mar 26 01:32:19 PM PDT 24 |
15397260 ps |
| T79 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.141889380 |
|
|
Mar 26 01:32:04 PM PDT 24 |
Mar 26 01:32:06 PM PDT 24 |
79335217 ps |
| T128 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3535932007 |
|
|
Mar 26 01:32:12 PM PDT 24 |
Mar 26 01:32:15 PM PDT 24 |
77970693 ps |
| T80 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1197530800 |
|
|
Mar 26 01:32:09 PM PDT 24 |
Mar 26 01:32:23 PM PDT 24 |
591212746 ps |
| T995 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.2278316509 |
|
|
Mar 26 01:32:21 PM PDT 24 |
Mar 26 01:32:22 PM PDT 24 |
14020229 ps |
| T996 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3481827598 |
|
|
Mar 26 01:32:06 PM PDT 24 |
Mar 26 01:32:08 PM PDT 24 |
68011164 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.646941054 |
|
|
Mar 26 01:31:45 PM PDT 24 |
Mar 26 01:31:48 PM PDT 24 |
428963829 ps |
| T998 |
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.1836074974 |
|
|
Mar 26 01:32:20 PM PDT 24 |
Mar 26 01:32:20 PM PDT 24 |
13161503 ps |
| T81 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1354752225 |
|
|
Mar 26 01:32:07 PM PDT 24 |
Mar 26 01:32:09 PM PDT 24 |
194493397 ps |
| T98 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2443802911 |
|
|
Mar 26 01:31:59 PM PDT 24 |
Mar 26 01:32:00 PM PDT 24 |
18518554 ps |
| T999 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3129331109 |
|
|
Mar 26 01:31:58 PM PDT 24 |
Mar 26 01:32:00 PM PDT 24 |
113841295 ps |
| T1000 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1897825557 |
|
|
Mar 26 01:32:23 PM PDT 24 |
Mar 26 01:32:24 PM PDT 24 |
46960329 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.459375648 |
|
|
Mar 26 01:31:58 PM PDT 24 |
Mar 26 01:31:59 PM PDT 24 |
25811881 ps |
| T1002 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.569712917 |
|
|
Mar 26 01:32:08 PM PDT 24 |
Mar 26 01:32:13 PM PDT 24 |
902235549 ps |
| T1003 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.3079902613 |
|
|
Mar 26 01:32:24 PM PDT 24 |
Mar 26 01:32:25 PM PDT 24 |
36483661 ps |
| T99 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4204930828 |
|
|
Mar 26 01:31:54 PM PDT 24 |
Mar 26 01:31:56 PM PDT 24 |
365633256 ps |
| T82 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4111338941 |
|
|
Mar 26 01:31:57 PM PDT 24 |
Mar 26 01:32:00 PM PDT 24 |
69509953 ps |
| T1004 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.1570839023 |
|
|
Mar 26 01:32:21 PM PDT 24 |
Mar 26 01:32:21 PM PDT 24 |
26763932 ps |
| T100 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1432766829 |
|
|
Mar 26 01:32:09 PM PDT 24 |
Mar 26 01:32:12 PM PDT 24 |
371895854 ps |
| T101 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1110392729 |
|
|
Mar 26 01:32:11 PM PDT 24 |
Mar 26 01:32:14 PM PDT 24 |
66579416 ps |
| T102 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2617057963 |
|
|
Mar 26 01:31:39 PM PDT 24 |
Mar 26 01:31:42 PM PDT 24 |
481907471 ps |
| T1005 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.817286344 |
|
|
Mar 26 01:32:20 PM PDT 24 |
Mar 26 01:32:22 PM PDT 24 |
41347796 ps |
| T1006 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2467493718 |
|
|
Mar 26 01:32:23 PM PDT 24 |
Mar 26 01:32:25 PM PDT 24 |
23016567 ps |
| T103 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3880734620 |
|
|
Mar 26 01:32:06 PM PDT 24 |
Mar 26 01:32:08 PM PDT 24 |
55819909 ps |
| T84 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.259224379 |
|
|
Mar 26 01:31:52 PM PDT 24 |
Mar 26 01:31:56 PM PDT 24 |
109623633 ps |
| T83 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3124478158 |
|
|
Mar 26 01:32:06 PM PDT 24 |
Mar 26 01:32:09 PM PDT 24 |
245308247 ps |
| T1007 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.2470461914 |
|
|
Mar 26 01:32:02 PM PDT 24 |
Mar 26 01:32:02 PM PDT 24 |
51807097 ps |
| T1008 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.12642114 |
|
|
Mar 26 01:32:18 PM PDT 24 |
Mar 26 01:32:19 PM PDT 24 |
14877983 ps |
| T104 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1972467579 |
|
|
Mar 26 01:31:42 PM PDT 24 |
Mar 26 01:31:50 PM PDT 24 |
1697297382 ps |
| T87 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4287062213 |
|
|
Mar 26 01:32:05 PM PDT 24 |
Mar 26 01:32:08 PM PDT 24 |
1472581993 ps |
| T1009 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.717902101 |
|
|
Mar 26 01:32:28 PM PDT 24 |
Mar 26 01:32:29 PM PDT 24 |
33421258 ps |
| T105 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3313895047 |
|
|
Mar 26 01:31:54 PM PDT 24 |
Mar 26 01:32:16 PM PDT 24 |
302233375 ps |
| T1010 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.2809630635 |
|
|
Mar 26 01:32:18 PM PDT 24 |
Mar 26 01:32:19 PM PDT 24 |
15329416 ps |
| T1011 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.149189477 |
|
|
Mar 26 01:31:45 PM PDT 24 |
Mar 26 01:31:47 PM PDT 24 |
19258665 ps |
| T1012 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.374306809 |
|
|
Mar 26 01:32:16 PM PDT 24 |
Mar 26 01:32:17 PM PDT 24 |
14799847 ps |
| T92 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3617102565 |
|
|
Mar 26 01:32:17 PM PDT 24 |
Mar 26 01:32:22 PM PDT 24 |
318959527 ps |
| T106 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3981065465 |
|
|
Mar 26 01:32:11 PM PDT 24 |
Mar 26 01:32:12 PM PDT 24 |
54824064 ps |
| T1013 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3812227178 |
|
|
Mar 26 01:32:23 PM PDT 24 |
Mar 26 01:32:24 PM PDT 24 |
40251721 ps |
| T85 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3033312788 |
|
|
Mar 26 01:31:54 PM PDT 24 |
Mar 26 01:32:15 PM PDT 24 |
2849439076 ps |
| T1014 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.674288614 |
|
|
Mar 26 01:32:26 PM PDT 24 |
Mar 26 01:32:26 PM PDT 24 |
14987152 ps |
| T1015 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3459112467 |
|
|
Mar 26 01:31:58 PM PDT 24 |
Mar 26 01:32:25 PM PDT 24 |
5035805543 ps |
| T94 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1835784484 |
|
|
Mar 26 01:31:57 PM PDT 24 |
Mar 26 01:32:00 PM PDT 24 |
341367291 ps |
| T129 |
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3043238571 |
|
|
Mar 26 01:32:11 PM PDT 24 |
Mar 26 01:32:13 PM PDT 24 |
350550943 ps |
| T96 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.597174581 |
|
|
Mar 26 01:32:09 PM PDT 24 |
Mar 26 01:32:12 PM PDT 24 |
41671256 ps |
| T86 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1536066459 |
|
|
Mar 26 01:31:58 PM PDT 24 |
Mar 26 01:32:17 PM PDT 24 |
300088223 ps |
| T130 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3579624197 |
|
|
Mar 26 01:32:10 PM PDT 24 |
Mar 26 01:32:25 PM PDT 24 |
633009218 ps |
| T1016 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.292428332 |
|
|
Mar 26 01:31:43 PM PDT 24 |
Mar 26 01:31:44 PM PDT 24 |
22253295 ps |
| T1017 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.2334652967 |
|
|
Mar 26 01:31:42 PM PDT 24 |
Mar 26 01:31:43 PM PDT 24 |
43410385 ps |
| T162 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3800199225 |
|
|
Mar 26 01:31:42 PM PDT 24 |
Mar 26 01:32:04 PM PDT 24 |
3148520604 ps |
| T1018 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.573253642 |
|
|
Mar 26 01:32:27 PM PDT 24 |
Mar 26 01:32:29 PM PDT 24 |
245114808 ps |
| T1019 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3383415212 |
|
|
Mar 26 01:32:10 PM PDT 24 |
Mar 26 01:32:12 PM PDT 24 |
27595411 ps |
| T1020 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3133341690 |
|
|
Mar 26 01:31:55 PM PDT 24 |
Mar 26 01:31:58 PM PDT 24 |
443171451 ps |
| T1021 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.182083918 |
|
|
Mar 26 01:31:58 PM PDT 24 |
Mar 26 01:32:10 PM PDT 24 |
770068621 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1823695028 |
|
|
Mar 26 01:31:41 PM PDT 24 |
Mar 26 01:31:43 PM PDT 24 |
21395850 ps |
| T88 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4060767881 |
|
|
Mar 26 01:31:57 PM PDT 24 |
Mar 26 01:32:03 PM PDT 24 |
657097453 ps |
| T1022 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.48451754 |
|
|
Mar 26 01:32:07 PM PDT 24 |
Mar 26 01:32:08 PM PDT 24 |
14290943 ps |
| T1023 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.4216212302 |
|
|
Mar 26 01:32:20 PM PDT 24 |
Mar 26 01:32:21 PM PDT 24 |
12023787 ps |
| T89 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2307590811 |
|
|
Mar 26 01:31:56 PM PDT 24 |
Mar 26 01:31:58 PM PDT 24 |
113563009 ps |