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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 98.36 94.16 98.61 89.36 97.09 95.82 98.22


Total test records in report: 1116
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T1024 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2745871415 Mar 26 01:31:59 PM PDT 24 Mar 26 01:32:00 PM PDT 24 15039543 ps
T93 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3928172653 Mar 26 01:31:54 PM PDT 24 Mar 26 01:31:56 PM PDT 24 110318691 ps
T1025 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1603825303 Mar 26 01:32:09 PM PDT 24 Mar 26 01:32:12 PM PDT 24 166664228 ps
T1026 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2912597523 Mar 26 01:31:56 PM PDT 24 Mar 26 01:31:57 PM PDT 24 25641587 ps
T1027 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1700239283 Mar 26 01:31:58 PM PDT 24 Mar 26 01:31:59 PM PDT 24 14697727 ps
T131 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3838526204 Mar 26 01:32:20 PM PDT 24 Mar 26 01:32:24 PM PDT 24 639944147 ps
T164 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3670909425 Mar 26 01:32:08 PM PDT 24 Mar 26 01:32:20 PM PDT 24 408702781 ps
T107 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2071952996 Mar 26 01:32:09 PM PDT 24 Mar 26 01:32:10 PM PDT 24 76546601 ps
T1028 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2213735576 Mar 26 01:32:17 PM PDT 24 Mar 26 01:32:18 PM PDT 24 22435200 ps
T1029 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3234126804 Mar 26 01:32:16 PM PDT 24 Mar 26 01:32:17 PM PDT 24 12580990 ps
T136 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.181975431 Mar 26 01:31:55 PM PDT 24 Mar 26 01:31:57 PM PDT 24 603620402 ps
T1030 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3475707349 Mar 26 01:32:17 PM PDT 24 Mar 26 01:32:18 PM PDT 24 19226803 ps
T1031 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3956129565 Mar 26 01:32:16 PM PDT 24 Mar 26 01:32:17 PM PDT 24 12780959 ps
T132 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3187697472 Mar 26 01:32:10 PM PDT 24 Mar 26 01:32:27 PM PDT 24 3224312350 ps
T1032 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1668712576 Mar 26 01:32:10 PM PDT 24 Mar 26 01:32:18 PM PDT 24 279779486 ps
T1033 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.311797148 Mar 26 01:32:07 PM PDT 24 Mar 26 01:32:08 PM PDT 24 46622666 ps
T1034 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1511989616 Mar 26 01:32:11 PM PDT 24 Mar 26 01:32:13 PM PDT 24 87480759 ps
T1035 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2189335442 Mar 26 01:31:58 PM PDT 24 Mar 26 01:32:15 PM PDT 24 7615862942 ps
T1036 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4074572843 Mar 26 01:32:10 PM PDT 24 Mar 26 01:32:14 PM PDT 24 134781155 ps
T1037 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.878558128 Mar 26 01:32:08 PM PDT 24 Mar 26 01:32:09 PM PDT 24 34354064 ps
T1038 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3869365035 Mar 26 01:32:06 PM PDT 24 Mar 26 01:32:07 PM PDT 24 31619029 ps
T1039 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1723470977 Mar 26 01:32:21 PM PDT 24 Mar 26 01:32:22 PM PDT 24 49653068 ps
T90 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2406063755 Mar 26 01:32:18 PM PDT 24 Mar 26 01:32:21 PM PDT 24 186128729 ps
T1040 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3646817515 Mar 26 01:32:09 PM PDT 24 Mar 26 01:32:12 PM PDT 24 297593817 ps
T133 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3418611 Mar 26 01:32:12 PM PDT 24 Mar 26 01:32:28 PM PDT 24 724533355 ps
T1041 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3606085497 Mar 26 01:32:17 PM PDT 24 Mar 26 01:32:18 PM PDT 24 54116368 ps
T71 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1173878448 Mar 26 01:31:56 PM PDT 24 Mar 26 01:31:58 PM PDT 24 160456541 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3488984035 Mar 26 01:31:43 PM PDT 24 Mar 26 01:31:45 PM PDT 24 245295051 ps
T1043 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2343094874 Mar 26 01:31:46 PM PDT 24 Mar 26 01:31:46 PM PDT 24 10361564 ps
T1044 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2691860317 Mar 26 01:32:07 PM PDT 24 Mar 26 01:32:10 PM PDT 24 157643418 ps
T134 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.664769932 Mar 26 01:32:23 PM PDT 24 Mar 26 01:32:25 PM PDT 24 108786265 ps
T91 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3377473641 Mar 26 01:32:10 PM PDT 24 Mar 26 01:32:13 PM PDT 24 96212657 ps
T163 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3084981605 Mar 26 01:31:57 PM PDT 24 Mar 26 01:32:09 PM PDT 24 212416118 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.397214802 Mar 26 01:31:42 PM PDT 24 Mar 26 01:31:45 PM PDT 24 158638088 ps
T1046 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1327091871 Mar 26 01:32:16 PM PDT 24 Mar 26 01:32:17 PM PDT 24 38028377 ps
T1047 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.366785450 Mar 26 01:31:56 PM PDT 24 Mar 26 01:31:57 PM PDT 24 149490029 ps
T72 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1749538351 Mar 26 01:32:02 PM PDT 24 Mar 26 01:32:03 PM PDT 24 223324681 ps
T135 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2038552529 Mar 26 01:32:07 PM PDT 24 Mar 26 01:32:09 PM PDT 24 73797715 ps
T108 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.157497404 Mar 26 01:31:54 PM PDT 24 Mar 26 01:31:56 PM PDT 24 502439714 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3973034021 Mar 26 01:31:53 PM PDT 24 Mar 26 01:31:56 PM PDT 24 450202836 ps
T95 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4173610225 Mar 26 01:31:43 PM PDT 24 Mar 26 01:31:48 PM PDT 24 910997416 ps
T1049 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.462180529 Mar 26 01:32:23 PM PDT 24 Mar 26 01:32:44 PM PDT 24 820522228 ps
T109 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1243070043 Mar 26 01:31:56 PM PDT 24 Mar 26 01:31:58 PM PDT 24 142221862 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4022312371 Mar 26 01:31:59 PM PDT 24 Mar 26 01:32:00 PM PDT 24 102269648 ps
T97 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1085301725 Mar 26 01:32:06 PM PDT 24 Mar 26 01:32:09 PM PDT 24 173718882 ps
T1051 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.764171403 Mar 26 01:31:58 PM PDT 24 Mar 26 01:32:00 PM PDT 24 206476259 ps
T1052 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3877811187 Mar 26 01:31:53 PM PDT 24 Mar 26 01:31:54 PM PDT 24 20193025 ps
T1053 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1943181980 Mar 26 01:32:07 PM PDT 24 Mar 26 01:32:11 PM PDT 24 473611050 ps
T1054 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.585216817 Mar 26 01:32:09 PM PDT 24 Mar 26 01:32:15 PM PDT 24 258381295 ps
T165 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.189731789 Mar 26 01:32:19 PM PDT 24 Mar 26 01:32:39 PM PDT 24 3280931022 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3738361671 Mar 26 01:31:45 PM PDT 24 Mar 26 01:32:09 PM PDT 24 1526174460 ps
T1056 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2888232548 Mar 26 01:31:44 PM PDT 24 Mar 26 01:31:45 PM PDT 24 293292174 ps
T1057 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1823618834 Mar 26 01:32:19 PM PDT 24 Mar 26 01:32:20 PM PDT 24 44417168 ps
T1058 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2341026202 Mar 26 01:32:07 PM PDT 24 Mar 26 01:32:12 PM PDT 24 61345635 ps
T1059 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1519103345 Mar 26 01:32:23 PM PDT 24 Mar 26 01:32:23 PM PDT 24 14304044 ps
T1060 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4077221554 Mar 26 01:31:55 PM PDT 24 Mar 26 01:31:56 PM PDT 24 100506882 ps
T1061 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2131521597 Mar 26 01:32:25 PM PDT 24 Mar 26 01:32:26 PM PDT 24 53779036 ps
T110 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3348046177 Mar 26 01:31:45 PM PDT 24 Mar 26 01:31:54 PM PDT 24 106255614 ps
T1062 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1984048719 Mar 26 01:31:54 PM PDT 24 Mar 26 01:31:56 PM PDT 24 111285534 ps
T1063 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2786260630 Mar 26 01:32:16 PM PDT 24 Mar 26 01:32:17 PM PDT 24 18324667 ps
T1064 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.805813096 Mar 26 01:31:59 PM PDT 24 Mar 26 01:32:01 PM PDT 24 194597880 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.254530587 Mar 26 01:31:42 PM PDT 24 Mar 26 01:31:46 PM PDT 24 117975377 ps
T1066 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3902051037 Mar 26 01:32:10 PM PDT 24 Mar 26 01:32:13 PM PDT 24 429226130 ps
T1067 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2373103080 Mar 26 01:31:51 PM PDT 24 Mar 26 01:31:53 PM PDT 24 186652926 ps
T166 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2054351383 Mar 26 01:31:52 PM PDT 24 Mar 26 01:32:11 PM PDT 24 625429448 ps
T1068 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2683788798 Mar 26 01:32:16 PM PDT 24 Mar 26 01:32:20 PM PDT 24 436244023 ps
T1069 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1815052019 Mar 26 01:31:42 PM PDT 24 Mar 26 01:31:43 PM PDT 24 17141586 ps
T1070 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2630984021 Mar 26 01:32:18 PM PDT 24 Mar 26 01:32:19 PM PDT 24 31879589 ps
T1071 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3515744053 Mar 26 01:31:46 PM PDT 24 Mar 26 01:31:53 PM PDT 24 603498956 ps
T1072 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4193925885 Mar 26 01:32:05 PM PDT 24 Mar 26 01:32:06 PM PDT 24 34352438 ps
T1073 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1963177147 Mar 26 01:32:02 PM PDT 24 Mar 26 01:32:26 PM PDT 24 4217360384 ps
T1074 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2426357774 Mar 26 01:32:08 PM PDT 24 Mar 26 01:32:11 PM PDT 24 461263563 ps
T1075 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1671446437 Mar 26 01:31:57 PM PDT 24 Mar 26 01:31:59 PM PDT 24 547106268 ps
T1076 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2944672556 Mar 26 01:31:43 PM PDT 24 Mar 26 01:31:45 PM PDT 24 59009360 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1636882182 Mar 26 01:32:18 PM PDT 24 Mar 26 01:32:21 PM PDT 24 332003161 ps
T1078 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1411567329 Mar 26 01:32:11 PM PDT 24 Mar 26 01:32:16 PM PDT 24 222975069 ps
T1079 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2604897896 Mar 26 01:31:54 PM PDT 24 Mar 26 01:32:16 PM PDT 24 1865462801 ps
T1080 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1045975034 Mar 26 01:32:22 PM PDT 24 Mar 26 01:32:23 PM PDT 24 23905475 ps
T1081 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2657318811 Mar 26 01:31:52 PM PDT 24 Mar 26 01:31:54 PM PDT 24 309788830 ps
T1082 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2122431840 Mar 26 01:32:08 PM PDT 24 Mar 26 01:32:14 PM PDT 24 809593611 ps
T1083 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1106137409 Mar 26 01:32:18 PM PDT 24 Mar 26 01:32:21 PM PDT 24 108747062 ps
T1084 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4247615578 Mar 26 01:31:43 PM PDT 24 Mar 26 01:31:44 PM PDT 24 73979843 ps
T1085 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1808396597 Mar 26 01:32:18 PM PDT 24 Mar 26 01:32:19 PM PDT 24 18795248 ps
T1086 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.998800878 Mar 26 01:32:09 PM PDT 24 Mar 26 01:32:10 PM PDT 24 25567891 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.940819157 Mar 26 01:31:44 PM PDT 24 Mar 26 01:31:45 PM PDT 24 39986747 ps
T1088 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.843479273 Mar 26 01:32:08 PM PDT 24 Mar 26 01:32:09 PM PDT 24 148581355 ps
T1089 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3721899151 Mar 26 01:31:58 PM PDT 24 Mar 26 01:31:59 PM PDT 24 135892664 ps
T1090 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.481220261 Mar 26 01:31:59 PM PDT 24 Mar 26 01:32:02 PM PDT 24 119439016 ps
T1091 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3736120550 Mar 26 01:31:47 PM PDT 24 Mar 26 01:32:01 PM PDT 24 2586590002 ps
T1092 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3663076 Mar 26 01:32:05 PM PDT 24 Mar 26 01:32:07 PM PDT 24 66348846 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2184907946 Mar 26 01:31:59 PM PDT 24 Mar 26 01:32:01 PM PDT 24 38528991 ps
T1094 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2200490575 Mar 26 01:31:50 PM PDT 24 Mar 26 01:31:53 PM PDT 24 45727350 ps
T1095 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1032528561 Mar 26 01:32:23 PM PDT 24 Mar 26 01:32:23 PM PDT 24 21538774 ps
T1096 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3932208537 Mar 26 01:32:06 PM PDT 24 Mar 26 01:32:09 PM PDT 24 28314650 ps
T1097 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.984401309 Mar 26 01:32:12 PM PDT 24 Mar 26 01:32:13 PM PDT 24 13386954 ps
T1098 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1844954743 Mar 26 01:31:55 PM PDT 24 Mar 26 01:31:58 PM PDT 24 1132146963 ps
T1099 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3739518270 Mar 26 01:31:55 PM PDT 24 Mar 26 01:32:07 PM PDT 24 828241637 ps
T160 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1660268701 Mar 26 01:32:20 PM PDT 24 Mar 26 01:32:24 PM PDT 24 105579065 ps
T1100 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3426189130 Mar 26 01:31:43 PM PDT 24 Mar 26 01:31:46 PM PDT 24 62509747 ps
T1101 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.881742968 Mar 26 01:32:21 PM PDT 24 Mar 26 01:32:25 PM PDT 24 68579785 ps
T1102 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3020300763 Mar 26 01:32:04 PM PDT 24 Mar 26 01:32:11 PM PDT 24 425869972 ps
T1103 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.126254688 Mar 26 01:32:18 PM PDT 24 Mar 26 01:32:19 PM PDT 24 162530595 ps
T1104 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2414464420 Mar 26 01:31:47 PM PDT 24 Mar 26 01:31:49 PM PDT 24 17560854 ps
T1105 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.159987000 Mar 26 01:32:06 PM PDT 24 Mar 26 01:32:07 PM PDT 24 55990168 ps
T1106 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.730587292 Mar 26 01:31:45 PM PDT 24 Mar 26 01:31:45 PM PDT 24 65208223 ps
T1107 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.195330047 Mar 26 01:32:08 PM PDT 24 Mar 26 01:32:11 PM PDT 24 240576463 ps
T1108 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.269299237 Mar 26 01:32:09 PM PDT 24 Mar 26 01:32:17 PM PDT 24 1480230613 ps
T1109 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.823623480 Mar 26 01:31:59 PM PDT 24 Mar 26 01:32:01 PM PDT 24 120190443 ps
T1110 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1436497900 Mar 26 01:32:23 PM PDT 24 Mar 26 01:32:24 PM PDT 24 36100670 ps
T1111 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3607386385 Mar 26 01:31:44 PM PDT 24 Mar 26 01:31:52 PM PDT 24 1665019282 ps
T1112 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.105746749 Mar 26 01:32:21 PM PDT 24 Mar 26 01:32:22 PM PDT 24 33811837 ps
T1113 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3936080987 Mar 26 01:32:21 PM PDT 24 Mar 26 01:32:28 PM PDT 24 422321027 ps
T1114 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2792229291 Mar 26 01:32:05 PM PDT 24 Mar 26 01:32:08 PM PDT 24 127739455 ps
T161 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1725044018 Mar 26 01:32:10 PM PDT 24 Mar 26 01:32:13 PM PDT 24 769887032 ps
T1115 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2457150508 Mar 26 01:32:18 PM PDT 24 Mar 26 01:32:19 PM PDT 24 17398524 ps
T1116 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3694260126 Mar 26 01:32:04 PM PDT 24 Mar 26 01:32:06 PM PDT 24 58592827 ps

Test location /workspace/coverage/default/26.spi_device_stress_all.1209214592
Short name T4
Test name
Test status
Simulation time 87527109302 ps
CPU time 423.86 seconds
Started Mar 26 02:04:12 PM PDT 24
Finished Mar 26 02:11:17 PM PDT 24
Peak memory 273336 kb
Host smart-e32ef59e-f2ef-40a4-af4b-2ef6b74079c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209214592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1209214592
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1715452906
Short name T13
Test name
Test status
Simulation time 107249798721 ps
CPU time 403.74 seconds
Started Mar 26 02:04:13 PM PDT 24
Finished Mar 26 02:10:57 PM PDT 24
Peak memory 265532 kb
Host smart-39e668f0-e837-4497-bcbd-7392b2432993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715452906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1715452906
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1252640494
Short name T36
Test name
Test status
Simulation time 53582911292 ps
CPU time 172.14 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:09:02 PM PDT 24
Peak memory 265396 kb
Host smart-b63ed5ec-a457-4bc2-b426-c83de3ce1dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252640494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1252640494
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1354752225
Short name T81
Test name
Test status
Simulation time 194493397 ps
CPU time 1.6 seconds
Started Mar 26 01:32:07 PM PDT 24
Finished Mar 26 01:32:09 PM PDT 24
Peak memory 215412 kb
Host smart-dd1ed53c-0ccf-4be2-9403-8e28f8178004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354752225 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1354752225
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2368140885
Short name T69
Test name
Test status
Simulation time 13675072596 ps
CPU time 158.06 seconds
Started Mar 26 02:01:29 PM PDT 24
Finished Mar 26 02:04:07 PM PDT 24
Peak memory 271124 kb
Host smart-b4b9c060-5de4-4c7d-8d5d-9694b46c1e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368140885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2368140885
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.457978753
Short name T56
Test name
Test status
Simulation time 48184737 ps
CPU time 0.79 seconds
Started Mar 26 02:02:43 PM PDT 24
Finished Mar 26 02:02:44 PM PDT 24
Peak memory 216100 kb
Host smart-82b2fcf0-eda0-4a18-a351-653503b27a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457978753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.457978753
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1653836021
Short name T30
Test name
Test status
Simulation time 49782679189 ps
CPU time 414.71 seconds
Started Mar 26 02:01:15 PM PDT 24
Finished Mar 26 02:08:10 PM PDT 24
Peak memory 271268 kb
Host smart-eb91c463-eb3f-459e-a9c6-002c8144d733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653836021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1653836021
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3579624197
Short name T130
Test name
Test status
Simulation time 633009218 ps
CPU time 14.62 seconds
Started Mar 26 01:32:10 PM PDT 24
Finished Mar 26 01:32:25 PM PDT 24
Peak memory 216284 kb
Host smart-e51a4954-8337-4cf7-883c-50dbe2d08f43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579624197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3579624197
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3086620601
Short name T28
Test name
Test status
Simulation time 9634611889 ps
CPU time 94.66 seconds
Started Mar 26 02:00:53 PM PDT 24
Finished Mar 26 02:02:28 PM PDT 24
Peak memory 267504 kb
Host smart-10029460-ca75-4a09-b9de-bb8996117788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086620601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3086620601
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1856656283
Short name T59
Test name
Test status
Simulation time 267567477 ps
CPU time 1.04 seconds
Started Mar 26 02:01:00 PM PDT 24
Finished Mar 26 02:01:01 PM PDT 24
Peak memory 235312 kb
Host smart-863fd84b-5607-4271-8b96-4ffa77a0ce3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856656283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1856656283
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2341888427
Short name T14
Test name
Test status
Simulation time 620562895 ps
CPU time 11.86 seconds
Started Mar 26 02:02:56 PM PDT 24
Finished Mar 26 02:03:08 PM PDT 24
Peak memory 234148 kb
Host smart-f30404a5-1575-4f92-a49a-361a9f352457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341888427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2341888427
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1208026407
Short name T115
Test name
Test status
Simulation time 348861254216 ps
CPU time 705.53 seconds
Started Mar 26 02:02:42 PM PDT 24
Finished Mar 26 02:14:28 PM PDT 24
Peak memory 271364 kb
Host smart-db5b4dea-9b30-413c-8b5a-9be941ee3e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208026407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1208026407
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3923954872
Short name T201
Test name
Test status
Simulation time 1450592453696 ps
CPU time 664.2 seconds
Started Mar 26 02:01:14 PM PDT 24
Finished Mar 26 02:12:19 PM PDT 24
Peak memory 266932 kb
Host smart-593903a1-e0d5-46c1-8c02-c479122398d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923954872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3923954872
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4060767881
Short name T88
Test name
Test status
Simulation time 657097453 ps
CPU time 5.2 seconds
Started Mar 26 01:31:57 PM PDT 24
Finished Mar 26 01:32:03 PM PDT 24
Peak memory 215456 kb
Host smart-beecf9cb-d5b3-4f6f-bbc7-b01afa8f118c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060767881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
060767881
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1823695028
Short name T70
Test name
Test status
Simulation time 21395850 ps
CPU time 1.32 seconds
Started Mar 26 01:31:41 PM PDT 24
Finished Mar 26 01:31:43 PM PDT 24
Peak memory 216372 kb
Host smart-419c1e28-5f94-400f-bbc1-38b05bbec417
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823695028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1823695028
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2444566635
Short name T33
Test name
Test status
Simulation time 469868822897 ps
CPU time 393.37 seconds
Started Mar 26 02:06:00 PM PDT 24
Finished Mar 26 02:12:34 PM PDT 24
Peak memory 255340 kb
Host smart-b9d6dba2-d697-48a7-85fd-faf8ab10a535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444566635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2444566635
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1325050273
Short name T29
Test name
Test status
Simulation time 220662323119 ps
CPU time 328.94 seconds
Started Mar 26 02:05:00 PM PDT 24
Finished Mar 26 02:10:29 PM PDT 24
Peak memory 256236 kb
Host smart-05fdc75e-3d66-4425-86a3-edf6d5cea78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325050273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1325050273
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3927139163
Short name T21
Test name
Test status
Simulation time 16436468 ps
CPU time 1.04 seconds
Started Mar 26 02:00:52 PM PDT 24
Finished Mar 26 02:00:54 PM PDT 24
Peak memory 216500 kb
Host smart-965a6138-4621-4faf-ac4d-728faeec500c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927139163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3927139163
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4110977358
Short name T143
Test name
Test status
Simulation time 106109187512 ps
CPU time 391.54 seconds
Started Mar 26 02:06:00 PM PDT 24
Finished Mar 26 02:12:33 PM PDT 24
Peak memory 267444 kb
Host smart-d107ae7f-0010-4ba9-ac33-5a2142575f91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110977358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4110977358
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2154490545
Short name T253
Test name
Test status
Simulation time 21602221141 ps
CPU time 96.45 seconds
Started Mar 26 02:03:33 PM PDT 24
Finished Mar 26 02:05:10 PM PDT 24
Peak memory 256040 kb
Host smart-a271ecf9-e50b-4db0-a1d6-78d2f5edf856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154490545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2154490545
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1702071662
Short name T1
Test name
Test status
Simulation time 39683383772 ps
CPU time 125.17 seconds
Started Mar 26 02:03:09 PM PDT 24
Finished Mar 26 02:05:16 PM PDT 24
Peak memory 265340 kb
Host smart-5b2a436a-e14e-4296-aef8-bc951d89e29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702071662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1702071662
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2363939412
Short name T247
Test name
Test status
Simulation time 231305684858 ps
CPU time 896.96 seconds
Started Mar 26 02:04:40 PM PDT 24
Finished Mar 26 02:19:39 PM PDT 24
Peak memory 305292 kb
Host smart-df6c0163-9910-4671-be4d-df1b6978f260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363939412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2363939412
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2373413400
Short name T26
Test name
Test status
Simulation time 7099768930 ps
CPU time 55.29 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:04:42 PM PDT 24
Peak memory 255296 kb
Host smart-ecc63f04-76b0-45bd-bd11-ceb0f112f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373413400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2373413400
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3370536313
Short name T305
Test name
Test status
Simulation time 22629488 ps
CPU time 0.73 seconds
Started Mar 26 02:01:03 PM PDT 24
Finished Mar 26 02:01:04 PM PDT 24
Peak memory 204464 kb
Host smart-e6a93f6d-8dbe-4409-9a9d-72ea7432669a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370536313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
370536313
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3033312788
Short name T85
Test name
Test status
Simulation time 2849439076 ps
CPU time 20.41 seconds
Started Mar 26 01:31:54 PM PDT 24
Finished Mar 26 01:32:15 PM PDT 24
Peak memory 216088 kb
Host smart-5aba203b-d9d9-4f98-b53a-5212e7afd248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033312788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3033312788
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1582289362
Short name T266
Test name
Test status
Simulation time 454937718 ps
CPU time 18.19 seconds
Started Mar 26 02:06:19 PM PDT 24
Finished Mar 26 02:06:38 PM PDT 24
Peak memory 232520 kb
Host smart-c4d0ca65-dda3-43a1-8072-f5b6ee940fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582289362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1582289362
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1480683045
Short name T189
Test name
Test status
Simulation time 6605282809 ps
CPU time 167.25 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:04:41 PM PDT 24
Peak memory 272308 kb
Host smart-4d688044-73fe-4d6e-9ebb-13c2b4a9f7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480683045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1480683045
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4173610225
Short name T95
Test name
Test status
Simulation time 910997416 ps
CPU time 4.52 seconds
Started Mar 26 01:31:43 PM PDT 24
Finished Mar 26 01:31:48 PM PDT 24
Peak memory 215800 kb
Host smart-fd61407a-ef84-472f-abce-6c26c9b4535e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173610225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
173610225
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3104450383
Short name T32
Test name
Test status
Simulation time 68865314544 ps
CPU time 155.41 seconds
Started Mar 26 02:01:01 PM PDT 24
Finished Mar 26 02:03:37 PM PDT 24
Peak memory 240868 kb
Host smart-35c32a93-1ce4-4ab6-9c31-9a44f64707da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104450383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3104450383
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2292788118
Short name T177
Test name
Test status
Simulation time 5245307705 ps
CPU time 18.24 seconds
Started Mar 26 02:03:19 PM PDT 24
Finished Mar 26 02:03:38 PM PDT 24
Peak memory 233200 kb
Host smart-df739359-92c0-4ee7-a8d3-2e1270d3637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292788118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2292788118
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3766930211
Short name T20
Test name
Test status
Simulation time 145738599475 ps
CPU time 936.54 seconds
Started Mar 26 02:01:07 PM PDT 24
Finished Mar 26 02:16:44 PM PDT 24
Peak memory 282128 kb
Host smart-ffc29fd0-3fd3-4a17-823e-d8da79d63b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766930211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3766930211
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3800199225
Short name T162
Test name
Test status
Simulation time 3148520604 ps
CPU time 21.14 seconds
Started Mar 26 01:31:42 PM PDT 24
Finished Mar 26 01:32:04 PM PDT 24
Peak memory 215496 kb
Host smart-57221ffb-ae64-4b76-a993-05245cef84cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800199225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3800199225
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1429710547
Short name T173
Test name
Test status
Simulation time 46339693736 ps
CPU time 113.2 seconds
Started Mar 26 02:04:12 PM PDT 24
Finished Mar 26 02:06:07 PM PDT 24
Peak memory 252520 kb
Host smart-9c7e464b-080a-4dbb-bcfa-4abe1a497b7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429710547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1429710547
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.345748294
Short name T11
Test name
Test status
Simulation time 54849054827 ps
CPU time 84.79 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:06:51 PM PDT 24
Peak memory 249120 kb
Host smart-1aafc24f-b326-4af7-aacc-bcf79a49c3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345748294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.345748294
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1549809524
Short name T243
Test name
Test status
Simulation time 49111750826 ps
CPU time 80.41 seconds
Started Mar 26 02:06:11 PM PDT 24
Finished Mar 26 02:07:32 PM PDT 24
Peak memory 249656 kb
Host smart-f217dfd5-1e12-4936-91a7-3e7d060c0207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549809524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1549809524
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.539663296
Short name T75
Test name
Test status
Simulation time 17184180899 ps
CPU time 124 seconds
Started Mar 26 02:03:45 PM PDT 24
Finished Mar 26 02:05:49 PM PDT 24
Peak memory 256100 kb
Host smart-3d548c7a-0331-4f6d-b6b2-9fad28fb107c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539663296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.539663296
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1725044018
Short name T161
Test name
Test status
Simulation time 769887032 ps
CPU time 3 seconds
Started Mar 26 01:32:10 PM PDT 24
Finished Mar 26 01:32:13 PM PDT 24
Peak memory 217544 kb
Host smart-77a31eec-cf9e-40a3-ac76-aa7d28d571f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725044018 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1725044018
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/10.spi_device_intercept.707613793
Short name T743
Test name
Test status
Simulation time 69100943 ps
CPU time 2.73 seconds
Started Mar 26 02:02:06 PM PDT 24
Finished Mar 26 02:02:09 PM PDT 24
Peak memory 233616 kb
Host smart-f030738b-69fa-447a-ac4d-d5378f129035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707613793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.707613793
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1503890027
Short name T284
Test name
Test status
Simulation time 2565644350 ps
CPU time 10.74 seconds
Started Mar 26 02:02:32 PM PDT 24
Finished Mar 26 02:02:45 PM PDT 24
Peak memory 216204 kb
Host smart-2adfec23-9878-4fd2-ad72-d879eb4b237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503890027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1503890027
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.886806870
Short name T238
Test name
Test status
Simulation time 8185066880 ps
CPU time 81.55 seconds
Started Mar 26 02:02:55 PM PDT 24
Finished Mar 26 02:04:17 PM PDT 24
Peak memory 266636 kb
Host smart-a89b4db7-a861-42e3-b7aa-2c64e9cdbaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886806870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.886806870
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1868928331
Short name T248
Test name
Test status
Simulation time 25180033344 ps
CPU time 85.98 seconds
Started Mar 26 02:03:19 PM PDT 24
Finished Mar 26 02:04:45 PM PDT 24
Peak memory 248896 kb
Host smart-907759bc-7716-4a39-819e-f23504cefc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868928331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1868928331
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3947014689
Short name T255
Test name
Test status
Simulation time 195913673689 ps
CPU time 277.16 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:08:24 PM PDT 24
Peak memory 240548 kb
Host smart-c89f307d-546b-4136-a558-40b47e29d69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947014689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3947014689
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.317268155
Short name T221
Test name
Test status
Simulation time 19913560942 ps
CPU time 32.68 seconds
Started Mar 26 02:04:01 PM PDT 24
Finished Mar 26 02:04:34 PM PDT 24
Peak memory 240808 kb
Host smart-228028b9-4853-46c0-b4a3-e56f64905174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317268155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.317268155
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1914948406
Short name T252
Test name
Test status
Simulation time 18458953962 ps
CPU time 42.68 seconds
Started Mar 26 02:05:27 PM PDT 24
Finished Mar 26 02:06:09 PM PDT 24
Peak memory 254672 kb
Host smart-08455779-9f4a-489f-87a9-0a51d7a1d4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914948406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1914948406
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1844139154
Short name T256
Test name
Test status
Simulation time 5997386350 ps
CPU time 36.63 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:47 PM PDT 24
Peak memory 248316 kb
Host smart-cc136b85-8450-4c54-8a46-0d4600e9e1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844139154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1844139154
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1411567329
Short name T1078
Test name
Test status
Simulation time 222975069 ps
CPU time 5.03 seconds
Started Mar 26 01:32:11 PM PDT 24
Finished Mar 26 01:32:16 PM PDT 24
Peak memory 215468 kb
Host smart-056679ba-b70a-4d15-9c96-fc3a8f33bbdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411567329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1411567329
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1972467579
Short name T104
Test name
Test status
Simulation time 1697297382 ps
CPU time 8.41 seconds
Started Mar 26 01:31:42 PM PDT 24
Finished Mar 26 01:31:50 PM PDT 24
Peak memory 207104 kb
Host smart-e34be147-abac-4db3-bd96-6637c4259ad9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972467579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1972467579
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3736120550
Short name T1091
Test name
Test status
Simulation time 2586590002 ps
CPU time 13.92 seconds
Started Mar 26 01:31:47 PM PDT 24
Finished Mar 26 01:32:01 PM PDT 24
Peak memory 207212 kb
Host smart-b567e8df-b127-4167-b21a-259c35aff67f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736120550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3736120550
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2414464420
Short name T1104
Test name
Test status
Simulation time 17560854 ps
CPU time 1.17 seconds
Started Mar 26 01:31:47 PM PDT 24
Finished Mar 26 01:31:49 PM PDT 24
Peak memory 206972 kb
Host smart-7b100651-208a-4bdf-8a4c-d7aaf36c3322
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414464420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2414464420
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2888232548
Short name T1056
Test name
Test status
Simulation time 293292174 ps
CPU time 1.67 seconds
Started Mar 26 01:31:44 PM PDT 24
Finished Mar 26 01:31:45 PM PDT 24
Peak memory 215484 kb
Host smart-08fe5a34-312c-4a05-b25b-2e0a3f78349c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888232548 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2888232548
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.292428332
Short name T1016
Test name
Test status
Simulation time 22253295 ps
CPU time 1.38 seconds
Started Mar 26 01:31:43 PM PDT 24
Finished Mar 26 01:31:44 PM PDT 24
Peak memory 207124 kb
Host smart-42d14801-cf7a-427a-b7a2-16473129dd22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292428332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.292428332
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.149189477
Short name T1011
Test name
Test status
Simulation time 19258665 ps
CPU time 0.7 seconds
Started Mar 26 01:31:45 PM PDT 24
Finished Mar 26 01:31:47 PM PDT 24
Peak memory 203748 kb
Host smart-23ab343f-21b7-4b3f-bb04-83c1e40a4b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149189477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.149189477
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1815052019
Short name T1069
Test name
Test status
Simulation time 17141586 ps
CPU time 1.22 seconds
Started Mar 26 01:31:42 PM PDT 24
Finished Mar 26 01:31:43 PM PDT 24
Peak memory 215316 kb
Host smart-ad8c2c9f-2ea2-4e56-b8e5-a9ae369cfe4d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815052019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1815052019
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2343094874
Short name T1043
Test name
Test status
Simulation time 10361564 ps
CPU time 0.67 seconds
Started Mar 26 01:31:46 PM PDT 24
Finished Mar 26 01:31:46 PM PDT 24
Peak memory 203860 kb
Host smart-fc7aa236-8b13-4e26-86fb-8086b1f6d99e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343094874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2343094874
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.397214802
Short name T1045
Test name
Test status
Simulation time 158638088 ps
CPU time 2.7 seconds
Started Mar 26 01:31:42 PM PDT 24
Finished Mar 26 01:31:45 PM PDT 24
Peak memory 215272 kb
Host smart-dbf78a16-ff09-450e-a599-ead2d0bebd83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397214802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.397214802
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.254530587
Short name T1065
Test name
Test status
Simulation time 117975377 ps
CPU time 3.97 seconds
Started Mar 26 01:31:42 PM PDT 24
Finished Mar 26 01:31:46 PM PDT 24
Peak memory 215468 kb
Host smart-17b83e91-c231-4581-8e8e-712d79611535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254530587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.254530587
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3348046177
Short name T110
Test name
Test status
Simulation time 106255614 ps
CPU time 7.71 seconds
Started Mar 26 01:31:45 PM PDT 24
Finished Mar 26 01:31:54 PM PDT 24
Peak memory 207200 kb
Host smart-d31337db-637a-4764-a2a9-b3b39ea3e7af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348046177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3348046177
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3738361671
Short name T1055
Test name
Test status
Simulation time 1526174460 ps
CPU time 22.86 seconds
Started Mar 26 01:31:45 PM PDT 24
Finished Mar 26 01:32:09 PM PDT 24
Peak memory 207236 kb
Host smart-af9ef155-5bcc-4f9c-a7a0-a8b26cadedcb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738361671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3738361671
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3488984035
Short name T1042
Test name
Test status
Simulation time 245295051 ps
CPU time 1.69 seconds
Started Mar 26 01:31:43 PM PDT 24
Finished Mar 26 01:31:45 PM PDT 24
Peak memory 215456 kb
Host smart-98f2b837-8223-4552-b718-fd8ddb0f0c8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488984035 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3488984035
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2617057963
Short name T102
Test name
Test status
Simulation time 481907471 ps
CPU time 2.61 seconds
Started Mar 26 01:31:39 PM PDT 24
Finished Mar 26 01:31:42 PM PDT 24
Peak memory 215376 kb
Host smart-4eefcc69-7ee9-4d58-b48d-7fb319c8c401
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617057963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
617057963
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.730587292
Short name T1106
Test name
Test status
Simulation time 65208223 ps
CPU time 0.69 seconds
Started Mar 26 01:31:45 PM PDT 24
Finished Mar 26 01:31:45 PM PDT 24
Peak memory 203444 kb
Host smart-ccf1a683-be19-4114-a8b1-a4a5514ef7b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730587292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.730587292
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3426189130
Short name T1100
Test name
Test status
Simulation time 62509747 ps
CPU time 2.13 seconds
Started Mar 26 01:31:43 PM PDT 24
Finished Mar 26 01:31:46 PM PDT 24
Peak memory 215332 kb
Host smart-ca87855c-40e6-44f6-8615-7d943740a24c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426189130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3426189130
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4247615578
Short name T1084
Test name
Test status
Simulation time 73979843 ps
CPU time 0.65 seconds
Started Mar 26 01:31:43 PM PDT 24
Finished Mar 26 01:31:44 PM PDT 24
Peak memory 203360 kb
Host smart-f6f93990-8d95-412a-a56e-422d8ffe44f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247615578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4247615578
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.646941054
Short name T997
Test name
Test status
Simulation time 428963829 ps
CPU time 3.27 seconds
Started Mar 26 01:31:45 PM PDT 24
Finished Mar 26 01:31:48 PM PDT 24
Peak memory 215428 kb
Host smart-a2320895-fa8e-4b57-b659-7482854bdfce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646941054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.646941054
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3607386385
Short name T1111
Test name
Test status
Simulation time 1665019282 ps
CPU time 8.21 seconds
Started Mar 26 01:31:44 PM PDT 24
Finished Mar 26 01:31:52 PM PDT 24
Peak memory 215332 kb
Host smart-215243cc-d180-4795-b74d-8c99124812c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607386385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3607386385
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2691860317
Short name T1044
Test name
Test status
Simulation time 157643418 ps
CPU time 2.95 seconds
Started Mar 26 01:32:07 PM PDT 24
Finished Mar 26 01:32:10 PM PDT 24
Peak memory 217052 kb
Host smart-cf65473e-9db3-4a21-ac8d-cb2b710eb8e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691860317 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2691860317
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1432766829
Short name T100
Test name
Test status
Simulation time 371895854 ps
CPU time 2.63 seconds
Started Mar 26 01:32:09 PM PDT 24
Finished Mar 26 01:32:12 PM PDT 24
Peak memory 215400 kb
Host smart-71732b9a-ebdc-4236-8b03-70d322bdd359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432766829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1432766829
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.159987000
Short name T1105
Test name
Test status
Simulation time 55990168 ps
CPU time 0.7 seconds
Started Mar 26 01:32:06 PM PDT 24
Finished Mar 26 01:32:07 PM PDT 24
Peak memory 203356 kb
Host smart-d5dde7e2-7565-40ba-94c9-ccec4bd0ad30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159987000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.159987000
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3383415212
Short name T1019
Test name
Test status
Simulation time 27595411 ps
CPU time 1.66 seconds
Started Mar 26 01:32:10 PM PDT 24
Finished Mar 26 01:32:12 PM PDT 24
Peak memory 215680 kb
Host smart-a6ba3a3c-55c2-4126-81d0-6c0d0e08f05d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383415212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3383415212
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2122431840
Short name T1082
Test name
Test status
Simulation time 809593611 ps
CPU time 5.51 seconds
Started Mar 26 01:32:08 PM PDT 24
Finished Mar 26 01:32:14 PM PDT 24
Peak memory 215404 kb
Host smart-877b499c-1ed4-4a32-aa00-6927bd87b267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122431840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2122431840
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1668712576
Short name T1032
Test name
Test status
Simulation time 279779486 ps
CPU time 7.5 seconds
Started Mar 26 01:32:10 PM PDT 24
Finished Mar 26 01:32:18 PM PDT 24
Peak memory 215404 kb
Host smart-4c8e8c8f-a7f3-446c-933d-a856ea8e710c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668712576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1668712576
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3902051037
Short name T1066
Test name
Test status
Simulation time 429226130 ps
CPU time 2.73 seconds
Started Mar 26 01:32:10 PM PDT 24
Finished Mar 26 01:32:13 PM PDT 24
Peak memory 216468 kb
Host smart-6cc56de5-e277-4b3d-ab8f-507a34ed9a42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902051037 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3902051037
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2071952996
Short name T107
Test name
Test status
Simulation time 76546601 ps
CPU time 1.27 seconds
Started Mar 26 01:32:09 PM PDT 24
Finished Mar 26 01:32:10 PM PDT 24
Peak memory 207108 kb
Host smart-ee7b4e6a-f44e-423f-918e-6e81e6108d28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071952996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2071952996
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3869365035
Short name T1038
Test name
Test status
Simulation time 31619029 ps
CPU time 0.74 seconds
Started Mar 26 01:32:06 PM PDT 24
Finished Mar 26 01:32:07 PM PDT 24
Peak memory 203708 kb
Host smart-a95150cc-2af4-43ea-9476-acbd797377ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869365035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3869365035
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2426357774
Short name T1074
Test name
Test status
Simulation time 461263563 ps
CPU time 3.03 seconds
Started Mar 26 01:32:08 PM PDT 24
Finished Mar 26 01:32:11 PM PDT 24
Peak memory 215444 kb
Host smart-a92310a5-c69c-46fc-9a91-206e6702f66d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426357774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2426357774
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1197530800
Short name T80
Test name
Test status
Simulation time 591212746 ps
CPU time 14.41 seconds
Started Mar 26 01:32:09 PM PDT 24
Finished Mar 26 01:32:23 PM PDT 24
Peak memory 215460 kb
Host smart-65f0d7ed-ce75-4b50-9096-e33a7e2dbc98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197530800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1197530800
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1511989616
Short name T1034
Test name
Test status
Simulation time 87480759 ps
CPU time 1.68 seconds
Started Mar 26 01:32:11 PM PDT 24
Finished Mar 26 01:32:13 PM PDT 24
Peak memory 215308 kb
Host smart-6ef10bcc-ec30-41e8-91ff-63160599287a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511989616 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1511989616
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.195330047
Short name T1107
Test name
Test status
Simulation time 240576463 ps
CPU time 2.84 seconds
Started Mar 26 01:32:08 PM PDT 24
Finished Mar 26 01:32:11 PM PDT 24
Peak memory 215416 kb
Host smart-67d3fbcd-0364-4d45-9390-348ecd8a98ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195330047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.195330047
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.48451754
Short name T1022
Test name
Test status
Simulation time 14290943 ps
CPU time 0.72 seconds
Started Mar 26 01:32:07 PM PDT 24
Finished Mar 26 01:32:08 PM PDT 24
Peak memory 203300 kb
Host smart-6a9e6559-9ffa-43fa-a2c4-caf84b70b37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48451754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.48451754
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3646817515
Short name T1040
Test name
Test status
Simulation time 297593817 ps
CPU time 2.91 seconds
Started Mar 26 01:32:09 PM PDT 24
Finished Mar 26 01:32:12 PM PDT 24
Peak memory 215380 kb
Host smart-b4bbbf4f-4762-4717-8998-beda867a6670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646817515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3646817515
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1085301725
Short name T97
Test name
Test status
Simulation time 173718882 ps
CPU time 3.28 seconds
Started Mar 26 01:32:06 PM PDT 24
Finished Mar 26 01:32:09 PM PDT 24
Peak memory 215704 kb
Host smart-37ff6b93-eebb-443e-94f4-6b7dec94059c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085301725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1085301725
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.585216817
Short name T1054
Test name
Test status
Simulation time 258381295 ps
CPU time 6.34 seconds
Started Mar 26 01:32:09 PM PDT 24
Finished Mar 26 01:32:15 PM PDT 24
Peak memory 222408 kb
Host smart-b7de0745-82e9-424c-9007-e5c1789ddbf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585216817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.585216817
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3981065465
Short name T106
Test name
Test status
Simulation time 54824064 ps
CPU time 1.23 seconds
Started Mar 26 01:32:11 PM PDT 24
Finished Mar 26 01:32:12 PM PDT 24
Peak memory 207020 kb
Host smart-aa27cb84-f3d3-4f5a-a379-56297c83f22a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981065465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3981065465
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.311797148
Short name T1033
Test name
Test status
Simulation time 46622666 ps
CPU time 0.74 seconds
Started Mar 26 01:32:07 PM PDT 24
Finished Mar 26 01:32:08 PM PDT 24
Peak memory 203452 kb
Host smart-f8151771-8686-4c88-92c1-0017dd10a9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311797148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.311797148
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.569712917
Short name T1002
Test name
Test status
Simulation time 902235549 ps
CPU time 3.94 seconds
Started Mar 26 01:32:08 PM PDT 24
Finished Mar 26 01:32:13 PM PDT 24
Peak memory 215496 kb
Host smart-3a6d41ea-e137-4d7c-a680-547fc0bf52c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569712917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.569712917
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.141889380
Short name T79
Test name
Test status
Simulation time 79335217 ps
CPU time 2.16 seconds
Started Mar 26 01:32:04 PM PDT 24
Finished Mar 26 01:32:06 PM PDT 24
Peak memory 216568 kb
Host smart-90dec6b2-11ca-4ca4-ac40-b71926ad5333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141889380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.141889380
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4074572843
Short name T1036
Test name
Test status
Simulation time 134781155 ps
CPU time 3.59 seconds
Started Mar 26 01:32:10 PM PDT 24
Finished Mar 26 01:32:14 PM PDT 24
Peak memory 217512 kb
Host smart-9923be4f-ca81-4f66-9bc1-7d0dfc2c9cbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074572843 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4074572843
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3880734620
Short name T103
Test name
Test status
Simulation time 55819909 ps
CPU time 1.94 seconds
Started Mar 26 01:32:06 PM PDT 24
Finished Mar 26 01:32:08 PM PDT 24
Peak memory 215376 kb
Host smart-ab52d565-1124-4088-95e6-92ce917f0370
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880734620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3880734620
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.843479273
Short name T1088
Test name
Test status
Simulation time 148581355 ps
CPU time 0.76 seconds
Started Mar 26 01:32:08 PM PDT 24
Finished Mar 26 01:32:09 PM PDT 24
Peak memory 203384 kb
Host smart-316211a2-8023-4d85-aca2-53b86baedbab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843479273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.843479273
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1943181980
Short name T1053
Test name
Test status
Simulation time 473611050 ps
CPU time 3.8 seconds
Started Mar 26 01:32:07 PM PDT 24
Finished Mar 26 01:32:11 PM PDT 24
Peak memory 215228 kb
Host smart-5e955cda-af48-4e53-beee-8708c317c18b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943181980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1943181980
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3124478158
Short name T83
Test name
Test status
Simulation time 245308247 ps
CPU time 2.73 seconds
Started Mar 26 01:32:06 PM PDT 24
Finished Mar 26 01:32:09 PM PDT 24
Peak memory 215512 kb
Host smart-08dd443b-85f7-4c7e-a988-5b5f1279f845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124478158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3124478158
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3670909425
Short name T164
Test name
Test status
Simulation time 408702781 ps
CPU time 11.91 seconds
Started Mar 26 01:32:08 PM PDT 24
Finished Mar 26 01:32:20 PM PDT 24
Peak memory 215324 kb
Host smart-ebfaf23a-0ca8-4997-921b-62f27531476d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670909425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3670909425
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3481827598
Short name T996
Test name
Test status
Simulation time 68011164 ps
CPU time 1.95 seconds
Started Mar 26 01:32:06 PM PDT 24
Finished Mar 26 01:32:08 PM PDT 24
Peak memory 215448 kb
Host smart-174b900f-6cce-4aae-8180-0b87edee944d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481827598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3481827598
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.878558128
Short name T1037
Test name
Test status
Simulation time 34354064 ps
CPU time 0.72 seconds
Started Mar 26 01:32:08 PM PDT 24
Finished Mar 26 01:32:09 PM PDT 24
Peak memory 203784 kb
Host smart-d64a8224-0ddd-477e-b5b1-52827b497a53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878558128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.878558128
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3535932007
Short name T128
Test name
Test status
Simulation time 77970693 ps
CPU time 1.95 seconds
Started Mar 26 01:32:12 PM PDT 24
Finished Mar 26 01:32:15 PM PDT 24
Peak memory 207136 kb
Host smart-e983a2e3-ed24-4d19-9a90-6460d8021ede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535932007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3535932007
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3377473641
Short name T91
Test name
Test status
Simulation time 96212657 ps
CPU time 2.83 seconds
Started Mar 26 01:32:10 PM PDT 24
Finished Mar 26 01:32:13 PM PDT 24
Peak memory 215432 kb
Host smart-fbbc39fb-bd33-4790-aec0-76e6d95c8d93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377473641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3377473641
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3187697472
Short name T132
Test name
Test status
Simulation time 3224312350 ps
CPU time 16.59 seconds
Started Mar 26 01:32:10 PM PDT 24
Finished Mar 26 01:32:27 PM PDT 24
Peak memory 223704 kb
Host smart-cf86c323-da12-4cab-9eb3-784252ac76fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187697472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3187697472
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.597174581
Short name T96
Test name
Test status
Simulation time 41671256 ps
CPU time 2.93 seconds
Started Mar 26 01:32:09 PM PDT 24
Finished Mar 26 01:32:12 PM PDT 24
Peak memory 217628 kb
Host smart-42d83170-594c-49d5-ab13-62c50cacbd8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597174581 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.597174581
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1110392729
Short name T101
Test name
Test status
Simulation time 66579416 ps
CPU time 2.09 seconds
Started Mar 26 01:32:11 PM PDT 24
Finished Mar 26 01:32:14 PM PDT 24
Peak memory 207332 kb
Host smart-bfa96c16-f1fc-4c2c-a07f-0c5afc9e3529
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110392729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1110392729
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.984401309
Short name T1097
Test name
Test status
Simulation time 13386954 ps
CPU time 0.73 seconds
Started Mar 26 01:32:12 PM PDT 24
Finished Mar 26 01:32:13 PM PDT 24
Peak memory 203360 kb
Host smart-9912a3e9-4029-4041-a7bb-57cba6fae3b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984401309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.984401309
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3043238571
Short name T129
Test name
Test status
Simulation time 350550943 ps
CPU time 2.04 seconds
Started Mar 26 01:32:11 PM PDT 24
Finished Mar 26 01:32:13 PM PDT 24
Peak memory 207128 kb
Host smart-9f04bbe3-9fdd-4732-9663-f4a6aa1cc0c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043238571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3043238571
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2341026202
Short name T1058
Test name
Test status
Simulation time 61345635 ps
CPU time 4.71 seconds
Started Mar 26 01:32:07 PM PDT 24
Finished Mar 26 01:32:12 PM PDT 24
Peak memory 216536 kb
Host smart-238a1eaa-08ee-488e-9c76-cef5e98073f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341026202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2341026202
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3418611
Short name T133
Test name
Test status
Simulation time 724533355 ps
CPU time 15.81 seconds
Started Mar 26 01:32:12 PM PDT 24
Finished Mar 26 01:32:28 PM PDT 24
Peak memory 215348 kb
Host smart-7ff24c0d-c5c4-49a4-b2b0-dc591d67321b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_t
l_intg_err.3418611
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1106137409
Short name T1083
Test name
Test status
Simulation time 108747062 ps
CPU time 3.82 seconds
Started Mar 26 01:32:18 PM PDT 24
Finished Mar 26 01:32:21 PM PDT 24
Peak memory 216528 kb
Host smart-5e838d86-c496-4498-8f44-77bbe59efc5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106137409 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1106137409
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2467493718
Short name T1006
Test name
Test status
Simulation time 23016567 ps
CPU time 1.4 seconds
Started Mar 26 01:32:23 PM PDT 24
Finished Mar 26 01:32:25 PM PDT 24
Peak memory 207104 kb
Host smart-85e8401b-0c0e-4ffd-92ff-e22a514e3a4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467493718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2467493718
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1808396597
Short name T1085
Test name
Test status
Simulation time 18795248 ps
CPU time 0.77 seconds
Started Mar 26 01:32:18 PM PDT 24
Finished Mar 26 01:32:19 PM PDT 24
Peak memory 203328 kb
Host smart-f5c57c05-3fe5-40c5-9d81-302262f2fc18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808396597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1808396597
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.573253642
Short name T1018
Test name
Test status
Simulation time 245114808 ps
CPU time 1.96 seconds
Started Mar 26 01:32:27 PM PDT 24
Finished Mar 26 01:32:29 PM PDT 24
Peak memory 215612 kb
Host smart-179e9d79-7b89-4f8e-bdee-a7d87966738b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573253642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.573253642
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3617102565
Short name T92
Test name
Test status
Simulation time 318959527 ps
CPU time 4.64 seconds
Started Mar 26 01:32:17 PM PDT 24
Finished Mar 26 01:32:22 PM PDT 24
Peak memory 215616 kb
Host smart-823d76f9-1ca2-4432-8df3-27d7ef2acfd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617102565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3617102565
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3936080987
Short name T1113
Test name
Test status
Simulation time 422321027 ps
CPU time 7.17 seconds
Started Mar 26 01:32:21 PM PDT 24
Finished Mar 26 01:32:28 PM PDT 24
Peak memory 215504 kb
Host smart-85d9a75c-46a6-4a16-ad77-6f4b3ae9927e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936080987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3936080987
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3838526204
Short name T131
Test name
Test status
Simulation time 639944147 ps
CPU time 3.72 seconds
Started Mar 26 01:32:20 PM PDT 24
Finished Mar 26 01:32:24 PM PDT 24
Peak memory 217844 kb
Host smart-6f231ca5-70a2-468d-a359-a9a710455367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838526204 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3838526204
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1636882182
Short name T1077
Test name
Test status
Simulation time 332003161 ps
CPU time 2.31 seconds
Started Mar 26 01:32:18 PM PDT 24
Finished Mar 26 01:32:21 PM PDT 24
Peak memory 215416 kb
Host smart-a44908c2-2fc6-4c16-8e4a-c4982f3f9a5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636882182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1636882182
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1436497900
Short name T1110
Test name
Test status
Simulation time 36100670 ps
CPU time 0.68 seconds
Started Mar 26 01:32:23 PM PDT 24
Finished Mar 26 01:32:24 PM PDT 24
Peak memory 203444 kb
Host smart-e7374ead-88a6-4825-855a-255c5a0cdff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436497900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1436497900
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.817286344
Short name T1005
Test name
Test status
Simulation time 41347796 ps
CPU time 2.58 seconds
Started Mar 26 01:32:20 PM PDT 24
Finished Mar 26 01:32:22 PM PDT 24
Peak memory 214592 kb
Host smart-93182318-578b-4c7b-96be-5de886905816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817286344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.817286344
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1660268701
Short name T160
Test name
Test status
Simulation time 105579065 ps
CPU time 4.51 seconds
Started Mar 26 01:32:20 PM PDT 24
Finished Mar 26 01:32:24 PM PDT 24
Peak memory 214652 kb
Host smart-a934ff60-c324-4336-924e-b434fd31f91c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660268701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1660268701
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.189731789
Short name T165
Test name
Test status
Simulation time 3280931022 ps
CPU time 19.7 seconds
Started Mar 26 01:32:19 PM PDT 24
Finished Mar 26 01:32:39 PM PDT 24
Peak memory 215736 kb
Host smart-8a33f389-334f-46e1-9ae3-2628a4b2baaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189731789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.189731789
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2683788798
Short name T1068
Test name
Test status
Simulation time 436244023 ps
CPU time 3.7 seconds
Started Mar 26 01:32:16 PM PDT 24
Finished Mar 26 01:32:20 PM PDT 24
Peak memory 216524 kb
Host smart-b8734893-d9a0-4ac3-8459-0259950c729e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683788798 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2683788798
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.664769932
Short name T134
Test name
Test status
Simulation time 108786265 ps
CPU time 2.43 seconds
Started Mar 26 01:32:23 PM PDT 24
Finished Mar 26 01:32:25 PM PDT 24
Peak memory 215408 kb
Host smart-07c736b3-4c73-4329-aa23-a98e91f533f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664769932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.664769932
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2457150508
Short name T1115
Test name
Test status
Simulation time 17398524 ps
CPU time 0.68 seconds
Started Mar 26 01:32:18 PM PDT 24
Finished Mar 26 01:32:19 PM PDT 24
Peak memory 203440 kb
Host smart-088fb575-c8b6-4208-9931-933ae0bfab29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457150508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2457150508
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.881742968
Short name T1101
Test name
Test status
Simulation time 68579785 ps
CPU time 4.46 seconds
Started Mar 26 01:32:21 PM PDT 24
Finished Mar 26 01:32:25 PM PDT 24
Peak memory 215372 kb
Host smart-04489dac-91ff-491b-b356-cced4f6c1109
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881742968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.881742968
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2406063755
Short name T90
Test name
Test status
Simulation time 186128729 ps
CPU time 2.95 seconds
Started Mar 26 01:32:18 PM PDT 24
Finished Mar 26 01:32:21 PM PDT 24
Peak memory 215376 kb
Host smart-f03ad4f9-e2cb-4950-b1b3-ffa7dc936670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406063755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2406063755
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.462180529
Short name T1049
Test name
Test status
Simulation time 820522228 ps
CPU time 21.7 seconds
Started Mar 26 01:32:23 PM PDT 24
Finished Mar 26 01:32:44 PM PDT 24
Peak memory 215376 kb
Host smart-5c20e48a-4df5-4995-94e3-b7dafee2486b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462180529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.462180529
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2189335442
Short name T1035
Test name
Test status
Simulation time 7615862942 ps
CPU time 17.36 seconds
Started Mar 26 01:31:58 PM PDT 24
Finished Mar 26 01:32:15 PM PDT 24
Peak memory 207236 kb
Host smart-b12b779f-d75c-4a05-bdc7-d81d361b95a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189335442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2189335442
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1963177147
Short name T1073
Test name
Test status
Simulation time 4217360384 ps
CPU time 24.67 seconds
Started Mar 26 01:32:02 PM PDT 24
Finished Mar 26 01:32:26 PM PDT 24
Peak memory 207264 kb
Host smart-ae2f84e7-7fd4-4405-97fa-5329933ab39e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963177147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1963177147
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1173878448
Short name T71
Test name
Test status
Simulation time 160456541 ps
CPU time 1.48 seconds
Started Mar 26 01:31:56 PM PDT 24
Finished Mar 26 01:31:58 PM PDT 24
Peak memory 216472 kb
Host smart-299d8db0-b46d-4a73-8e52-106a72a399c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173878448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1173878448
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1844954743
Short name T1098
Test name
Test status
Simulation time 1132146963 ps
CPU time 3.66 seconds
Started Mar 26 01:31:55 PM PDT 24
Finished Mar 26 01:31:58 PM PDT 24
Peak memory 216480 kb
Host smart-1c7670b3-9b90-444e-af6e-c31c3db05619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844954743 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1844954743
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.157497404
Short name T108
Test name
Test status
Simulation time 502439714 ps
CPU time 1.29 seconds
Started Mar 26 01:31:54 PM PDT 24
Finished Mar 26 01:31:56 PM PDT 24
Peak memory 215324 kb
Host smart-884660dd-e33f-42cb-899c-1baabf769a50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157497404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.157497404
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2334652967
Short name T1017
Test name
Test status
Simulation time 43410385 ps
CPU time 0.75 seconds
Started Mar 26 01:31:42 PM PDT 24
Finished Mar 26 01:31:43 PM PDT 24
Peak memory 203420 kb
Host smart-ade7a8c2-93c0-41e8-8122-f45dfebc9856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334652967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
334652967
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2200490575
Short name T1094
Test name
Test status
Simulation time 45727350 ps
CPU time 1.88 seconds
Started Mar 26 01:31:50 PM PDT 24
Finished Mar 26 01:31:53 PM PDT 24
Peak memory 215280 kb
Host smart-c35f3164-8451-4b83-afba-a38c44e757c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200490575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2200490575
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.940819157
Short name T1087
Test name
Test status
Simulation time 39986747 ps
CPU time 0.69 seconds
Started Mar 26 01:31:44 PM PDT 24
Finished Mar 26 01:31:45 PM PDT 24
Peak memory 203608 kb
Host smart-49ecd56d-611c-4199-bdfb-a41954323101
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940819157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.940819157
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1984048719
Short name T1062
Test name
Test status
Simulation time 111285534 ps
CPU time 1.88 seconds
Started Mar 26 01:31:54 PM PDT 24
Finished Mar 26 01:31:56 PM PDT 24
Peak memory 215348 kb
Host smart-0073a8a0-bc2b-4776-9403-b492dbf517ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984048719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1984048719
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2944672556
Short name T1076
Test name
Test status
Simulation time 59009360 ps
CPU time 1.91 seconds
Started Mar 26 01:31:43 PM PDT 24
Finished Mar 26 01:31:45 PM PDT 24
Peak memory 215600 kb
Host smart-87ad8dda-6c71-4127-ab84-2f958a6980d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944672556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
944672556
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3515744053
Short name T1071
Test name
Test status
Simulation time 603498956 ps
CPU time 7.01 seconds
Started Mar 26 01:31:46 PM PDT 24
Finished Mar 26 01:31:53 PM PDT 24
Peak memory 215612 kb
Host smart-d9d7acb7-e749-4677-98f2-d3a9c05a4445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515744053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3515744053
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.374306809
Short name T1012
Test name
Test status
Simulation time 14799847 ps
CPU time 0.75 seconds
Started Mar 26 01:32:16 PM PDT 24
Finished Mar 26 01:32:17 PM PDT 24
Peak memory 203388 kb
Host smart-5fb65dee-2c02-43a5-af7b-fd409286abd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374306809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.374306809
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3475707349
Short name T1030
Test name
Test status
Simulation time 19226803 ps
CPU time 0.71 seconds
Started Mar 26 01:32:17 PM PDT 24
Finished Mar 26 01:32:18 PM PDT 24
Peak memory 203400 kb
Host smart-c31c89a1-6b8c-4d69-bc52-8a9b467a71df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475707349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3475707349
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2786260630
Short name T1063
Test name
Test status
Simulation time 18324667 ps
CPU time 0.74 seconds
Started Mar 26 01:32:16 PM PDT 24
Finished Mar 26 01:32:17 PM PDT 24
Peak memory 203704 kb
Host smart-8fc52a72-0190-40d4-84e3-5768c2d96535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786260630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2786260630
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1032528561
Short name T1095
Test name
Test status
Simulation time 21538774 ps
CPU time 0.69 seconds
Started Mar 26 01:32:23 PM PDT 24
Finished Mar 26 01:32:23 PM PDT 24
Peak memory 203708 kb
Host smart-d84c5ffd-dccb-4778-8252-318fe105febf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032528561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1032528561
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3606085497
Short name T1041
Test name
Test status
Simulation time 54116368 ps
CPU time 0.73 seconds
Started Mar 26 01:32:17 PM PDT 24
Finished Mar 26 01:32:18 PM PDT 24
Peak memory 203676 kb
Host smart-7ac9d7c4-ef09-46fb-9392-a2153af902ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606085497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3606085497
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.105746749
Short name T1112
Test name
Test status
Simulation time 33811837 ps
CPU time 0.66 seconds
Started Mar 26 01:32:21 PM PDT 24
Finished Mar 26 01:32:22 PM PDT 24
Peak memory 203376 kb
Host smart-4be8c86c-991c-46fd-bbca-8ac2ebedc25f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105746749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.105746749
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1327091871
Short name T1046
Test name
Test status
Simulation time 38028377 ps
CPU time 0.69 seconds
Started Mar 26 01:32:16 PM PDT 24
Finished Mar 26 01:32:17 PM PDT 24
Peak memory 203388 kb
Host smart-67583c6a-4342-4743-95fa-393957d4f891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327091871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1327091871
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4216212302
Short name T1023
Test name
Test status
Simulation time 12023787 ps
CPU time 0.69 seconds
Started Mar 26 01:32:20 PM PDT 24
Finished Mar 26 01:32:21 PM PDT 24
Peak memory 203352 kb
Host smart-c0e18276-b30a-49e1-afe8-ac4ae3733abd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216212302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4216212302
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2809630635
Short name T1010
Test name
Test status
Simulation time 15329416 ps
CPU time 0.73 seconds
Started Mar 26 01:32:18 PM PDT 24
Finished Mar 26 01:32:19 PM PDT 24
Peak memory 203396 kb
Host smart-172c584e-6c97-41bf-a5c1-fbf585b3f35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809630635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2809630635
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1519103345
Short name T1059
Test name
Test status
Simulation time 14304044 ps
CPU time 0.71 seconds
Started Mar 26 01:32:23 PM PDT 24
Finished Mar 26 01:32:23 PM PDT 24
Peak memory 203392 kb
Host smart-1180052d-3aeb-4ad3-a505-71499038e8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519103345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1519103345
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2604897896
Short name T1079
Test name
Test status
Simulation time 1865462801 ps
CPU time 22.17 seconds
Started Mar 26 01:31:54 PM PDT 24
Finished Mar 26 01:32:16 PM PDT 24
Peak memory 215384 kb
Host smart-2f85fd4a-4635-444d-b2fa-99356e084340
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604897896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2604897896
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3459112467
Short name T1015
Test name
Test status
Simulation time 5035805543 ps
CPU time 26.17 seconds
Started Mar 26 01:31:58 PM PDT 24
Finished Mar 26 01:32:25 PM PDT 24
Peak memory 207224 kb
Host smart-16019cce-6d19-4f98-9bb1-f1b84b03f9e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459112467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3459112467
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1749538351
Short name T72
Test name
Test status
Simulation time 223324681 ps
CPU time 1.19 seconds
Started Mar 26 01:32:02 PM PDT 24
Finished Mar 26 01:32:03 PM PDT 24
Peak memory 216420 kb
Host smart-47ec96a6-1f07-402a-92d5-e5770f7fbb48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749538351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1749538351
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.181975431
Short name T136
Test name
Test status
Simulation time 603620402 ps
CPU time 1.8 seconds
Started Mar 26 01:31:55 PM PDT 24
Finished Mar 26 01:31:57 PM PDT 24
Peak memory 215392 kb
Host smart-7d7dc458-66dc-4056-a22f-2a276429ccb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181975431 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.181975431
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1671446437
Short name T1075
Test name
Test status
Simulation time 547106268 ps
CPU time 1.97 seconds
Started Mar 26 01:31:57 PM PDT 24
Finished Mar 26 01:31:59 PM PDT 24
Peak memory 215376 kb
Host smart-78e0c14a-a477-4554-930b-490659eeb688
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671446437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
671446437
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2470461914
Short name T1007
Test name
Test status
Simulation time 51807097 ps
CPU time 0.71 seconds
Started Mar 26 01:32:02 PM PDT 24
Finished Mar 26 01:32:02 PM PDT 24
Peak memory 203752 kb
Host smart-d761c53b-cefb-4fb2-b148-f3aa1fffe082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470461914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
470461914
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4204930828
Short name T99
Test name
Test status
Simulation time 365633256 ps
CPU time 1.3 seconds
Started Mar 26 01:31:54 PM PDT 24
Finished Mar 26 01:31:56 PM PDT 24
Peak memory 215348 kb
Host smart-a4ef62b5-fac6-4c13-901a-f34c2f90fbbd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204930828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4204930828
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2912597523
Short name T1026
Test name
Test status
Simulation time 25641587 ps
CPU time 0.71 seconds
Started Mar 26 01:31:56 PM PDT 24
Finished Mar 26 01:31:57 PM PDT 24
Peak memory 203356 kb
Host smart-654a2cb6-2681-440a-8bc4-aa8ed20d0710
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912597523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2912597523
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3973034021
Short name T1048
Test name
Test status
Simulation time 450202836 ps
CPU time 2.84 seconds
Started Mar 26 01:31:53 PM PDT 24
Finished Mar 26 01:31:56 PM PDT 24
Peak memory 215404 kb
Host smart-d3077367-787b-4627-9c07-51ca0531001c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973034021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3973034021
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3084981605
Short name T163
Test name
Test status
Simulation time 212416118 ps
CPU time 11.98 seconds
Started Mar 26 01:31:57 PM PDT 24
Finished Mar 26 01:32:09 PM PDT 24
Peak memory 215364 kb
Host smart-61b8f15b-f4b4-4e4a-967e-14cb12008bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084981605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3084981605
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2229553041
Short name T993
Test name
Test status
Simulation time 31711230 ps
CPU time 0.75 seconds
Started Mar 26 01:32:17 PM PDT 24
Finished Mar 26 01:32:18 PM PDT 24
Peak memory 203792 kb
Host smart-86339f65-2cd2-41e7-8532-8ef674b89890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229553041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2229553041
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2213735576
Short name T1028
Test name
Test status
Simulation time 22435200 ps
CPU time 0.78 seconds
Started Mar 26 01:32:17 PM PDT 24
Finished Mar 26 01:32:18 PM PDT 24
Peak memory 203472 kb
Host smart-68883d99-af72-4183-bcd1-e29d4a0ace20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213735576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2213735576
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2131521597
Short name T1061
Test name
Test status
Simulation time 53779036 ps
CPU time 0.68 seconds
Started Mar 26 01:32:25 PM PDT 24
Finished Mar 26 01:32:26 PM PDT 24
Peak memory 203756 kb
Host smart-ccaaedff-3176-4daf-9d61-d0fe7fb02d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131521597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2131521597
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1897825557
Short name T1000
Test name
Test status
Simulation time 46960329 ps
CPU time 0.76 seconds
Started Mar 26 01:32:23 PM PDT 24
Finished Mar 26 01:32:24 PM PDT 24
Peak memory 203760 kb
Host smart-c94f9165-bec9-4397-8bf8-f233811571db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897825557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1897825557
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1723470977
Short name T1039
Test name
Test status
Simulation time 49653068 ps
CPU time 0.77 seconds
Started Mar 26 01:32:21 PM PDT 24
Finished Mar 26 01:32:22 PM PDT 24
Peak memory 203748 kb
Host smart-40a2d611-6332-4d9d-8861-31515eb4f330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723470977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1723470977
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2883543508
Short name T994
Test name
Test status
Simulation time 15397260 ps
CPU time 0.75 seconds
Started Mar 26 01:32:18 PM PDT 24
Finished Mar 26 01:32:19 PM PDT 24
Peak memory 203760 kb
Host smart-4670bc73-5117-4f36-960a-fc2f2eca7944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883543508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2883543508
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.12642114
Short name T1008
Test name
Test status
Simulation time 14877983 ps
CPU time 0.74 seconds
Started Mar 26 01:32:18 PM PDT 24
Finished Mar 26 01:32:19 PM PDT 24
Peak memory 203352 kb
Host smart-cd22278f-a14d-41b0-9b40-e27e1d25e971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12642114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.12642114
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3956129565
Short name T1031
Test name
Test status
Simulation time 12780959 ps
CPU time 0.75 seconds
Started Mar 26 01:32:16 PM PDT 24
Finished Mar 26 01:32:17 PM PDT 24
Peak memory 203456 kb
Host smart-ab2c4c06-28c4-4084-9dcf-a7c2d684dcab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956129565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3956129565
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.717902101
Short name T1009
Test name
Test status
Simulation time 33421258 ps
CPU time 0.69 seconds
Started Mar 26 01:32:28 PM PDT 24
Finished Mar 26 01:32:29 PM PDT 24
Peak memory 203444 kb
Host smart-760ac2bc-43ff-4262-a80f-5ee3bae85a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717902101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.717902101
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3234126804
Short name T1029
Test name
Test status
Simulation time 12580990 ps
CPU time 0.7 seconds
Started Mar 26 01:32:16 PM PDT 24
Finished Mar 26 01:32:17 PM PDT 24
Peak memory 203444 kb
Host smart-e9619268-19ec-48d3-9ac1-e09ae2f8e338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234126804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3234126804
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3313895047
Short name T105
Test name
Test status
Simulation time 302233375 ps
CPU time 22.03 seconds
Started Mar 26 01:31:54 PM PDT 24
Finished Mar 26 01:32:16 PM PDT 24
Peak memory 215404 kb
Host smart-bd0fdd3f-a9fd-4cc2-80f5-12947c80fa6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313895047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3313895047
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3739518270
Short name T1099
Test name
Test status
Simulation time 828241637 ps
CPU time 12.39 seconds
Started Mar 26 01:31:55 PM PDT 24
Finished Mar 26 01:32:07 PM PDT 24
Peak memory 207152 kb
Host smart-1997e716-33bd-4afa-96e8-879ea4c7527c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739518270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3739518270
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4022312371
Short name T1050
Test name
Test status
Simulation time 102269648 ps
CPU time 1.13 seconds
Started Mar 26 01:31:59 PM PDT 24
Finished Mar 26 01:32:00 PM PDT 24
Peak memory 206968 kb
Host smart-98646228-274c-460a-8fb8-3d32cdf28565
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022312371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4022312371
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.259224379
Short name T84
Test name
Test status
Simulation time 109623633 ps
CPU time 3.58 seconds
Started Mar 26 01:31:52 PM PDT 24
Finished Mar 26 01:31:56 PM PDT 24
Peak memory 217012 kb
Host smart-88b0e413-2b7c-4810-af0f-46104bbd9228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259224379 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.259224379
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2184907946
Short name T1093
Test name
Test status
Simulation time 38528991 ps
CPU time 1.38 seconds
Started Mar 26 01:31:59 PM PDT 24
Finished Mar 26 01:32:01 PM PDT 24
Peak memory 215324 kb
Host smart-fc5160f3-98a6-4397-bd8b-6666ae69c622
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184907946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
184907946
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2745871415
Short name T1024
Test name
Test status
Simulation time 15039543 ps
CPU time 0.75 seconds
Started Mar 26 01:31:59 PM PDT 24
Finished Mar 26 01:32:00 PM PDT 24
Peak memory 203344 kb
Host smart-a2d675e8-2795-4369-a2d5-2cb72027f323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745871415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
745871415
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1243070043
Short name T109
Test name
Test status
Simulation time 142221862 ps
CPU time 1.53 seconds
Started Mar 26 01:31:56 PM PDT 24
Finished Mar 26 01:31:58 PM PDT 24
Peak memory 215288 kb
Host smart-328e21a0-ff81-4017-b1f8-ab16554fc4da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243070043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1243070043
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1700239283
Short name T1027
Test name
Test status
Simulation time 14697727 ps
CPU time 0.66 seconds
Started Mar 26 01:31:58 PM PDT 24
Finished Mar 26 01:31:59 PM PDT 24
Peak memory 203292 kb
Host smart-0ebd923a-e629-4f04-a0f3-27684d354604
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700239283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1700239283
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.823623480
Short name T1109
Test name
Test status
Simulation time 120190443 ps
CPU time 1.67 seconds
Started Mar 26 01:31:59 PM PDT 24
Finished Mar 26 01:32:01 PM PDT 24
Peak memory 206836 kb
Host smart-e09005b9-fd93-44d3-a618-85ad10d147e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823623480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.823623480
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2657318811
Short name T1081
Test name
Test status
Simulation time 309788830 ps
CPU time 1.73 seconds
Started Mar 26 01:31:52 PM PDT 24
Finished Mar 26 01:31:54 PM PDT 24
Peak memory 216524 kb
Host smart-4d2409f5-6f94-4075-8a3c-5cfe16cfe1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657318811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
657318811
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2054351383
Short name T166
Test name
Test status
Simulation time 625429448 ps
CPU time 19.14 seconds
Started Mar 26 01:31:52 PM PDT 24
Finished Mar 26 01:32:11 PM PDT 24
Peak memory 215348 kb
Host smart-c79636d3-9097-4266-8a4f-5b54907b4e48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054351383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2054351383
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3079902613
Short name T1003
Test name
Test status
Simulation time 36483661 ps
CPU time 0.75 seconds
Started Mar 26 01:32:24 PM PDT 24
Finished Mar 26 01:32:25 PM PDT 24
Peak memory 203768 kb
Host smart-1f9e0861-ef54-4dac-856b-93da08177a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079902613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3079902613
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1570839023
Short name T1004
Test name
Test status
Simulation time 26763932 ps
CPU time 0.7 seconds
Started Mar 26 01:32:21 PM PDT 24
Finished Mar 26 01:32:21 PM PDT 24
Peak memory 203380 kb
Host smart-ed007d41-e6c7-4d2c-8259-22a7d28795d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570839023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1570839023
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.674288614
Short name T1014
Test name
Test status
Simulation time 14987152 ps
CPU time 0.74 seconds
Started Mar 26 01:32:26 PM PDT 24
Finished Mar 26 01:32:26 PM PDT 24
Peak memory 203760 kb
Host smart-f481e12f-28e1-4163-b386-b0b46f878c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674288614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.674288614
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1045975034
Short name T1080
Test name
Test status
Simulation time 23905475 ps
CPU time 0.74 seconds
Started Mar 26 01:32:22 PM PDT 24
Finished Mar 26 01:32:23 PM PDT 24
Peak memory 203380 kb
Host smart-32c45aa6-2220-4ab0-85e1-e0a08feb793f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045975034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1045975034
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2278316509
Short name T995
Test name
Test status
Simulation time 14020229 ps
CPU time 0.7 seconds
Started Mar 26 01:32:21 PM PDT 24
Finished Mar 26 01:32:22 PM PDT 24
Peak memory 203456 kb
Host smart-dae6678f-ad1c-471d-bb73-c6079724e5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278316509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2278316509
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.126254688
Short name T1103
Test name
Test status
Simulation time 162530595 ps
CPU time 0.71 seconds
Started Mar 26 01:32:18 PM PDT 24
Finished Mar 26 01:32:19 PM PDT 24
Peak memory 203792 kb
Host smart-b8366020-0a25-49d4-bb16-3b2da02ddefb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126254688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.126254688
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1823618834
Short name T1057
Test name
Test status
Simulation time 44417168 ps
CPU time 0.75 seconds
Started Mar 26 01:32:19 PM PDT 24
Finished Mar 26 01:32:20 PM PDT 24
Peak memory 203700 kb
Host smart-75bb404a-0409-4129-867e-23797837ebe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823618834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1823618834
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3812227178
Short name T1013
Test name
Test status
Simulation time 40251721 ps
CPU time 0.74 seconds
Started Mar 26 01:32:23 PM PDT 24
Finished Mar 26 01:32:24 PM PDT 24
Peak memory 203432 kb
Host smart-39a26f1e-9f70-4553-8941-3633bcd75b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812227178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3812227178
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2630984021
Short name T1070
Test name
Test status
Simulation time 31879589 ps
CPU time 0.7 seconds
Started Mar 26 01:32:18 PM PDT 24
Finished Mar 26 01:32:19 PM PDT 24
Peak memory 203348 kb
Host smart-1d3e0b58-75c3-428b-ae25-3ee0efdc30ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630984021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2630984021
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1836074974
Short name T998
Test name
Test status
Simulation time 13161503 ps
CPU time 0.72 seconds
Started Mar 26 01:32:20 PM PDT 24
Finished Mar 26 01:32:20 PM PDT 24
Peak memory 203376 kb
Host smart-d54c998c-7812-41d6-ae00-2e1537739689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836074974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1836074974
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4111338941
Short name T82
Test name
Test status
Simulation time 69509953 ps
CPU time 2.4 seconds
Started Mar 26 01:31:57 PM PDT 24
Finished Mar 26 01:32:00 PM PDT 24
Peak memory 216536 kb
Host smart-7c1f4916-1508-45ce-b093-8b7d9e296bec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111338941 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4111338941
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3721899151
Short name T1089
Test name
Test status
Simulation time 135892664 ps
CPU time 1.14 seconds
Started Mar 26 01:31:58 PM PDT 24
Finished Mar 26 01:31:59 PM PDT 24
Peak memory 207108 kb
Host smart-9ab23368-aeb7-4f19-8cea-5fa85a23e42b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721899151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
721899151
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3877811187
Short name T1052
Test name
Test status
Simulation time 20193025 ps
CPU time 0.78 seconds
Started Mar 26 01:31:53 PM PDT 24
Finished Mar 26 01:31:54 PM PDT 24
Peak memory 203400 kb
Host smart-f0a72bf2-2e37-4933-89b1-b1ac218f55d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877811187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
877811187
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2373103080
Short name T1067
Test name
Test status
Simulation time 186652926 ps
CPU time 1.87 seconds
Started Mar 26 01:31:51 PM PDT 24
Finished Mar 26 01:31:53 PM PDT 24
Peak memory 215532 kb
Host smart-7a145b70-4637-4ec6-917d-217820ab4539
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373103080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2373103080
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2307590811
Short name T89
Test name
Test status
Simulation time 113563009 ps
CPU time 2.1 seconds
Started Mar 26 01:31:56 PM PDT 24
Finished Mar 26 01:31:58 PM PDT 24
Peak memory 216540 kb
Host smart-fd6e9e4d-e332-4191-b473-3be5931d3a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307590811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
307590811
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.764171403
Short name T1051
Test name
Test status
Simulation time 206476259 ps
CPU time 2.61 seconds
Started Mar 26 01:31:58 PM PDT 24
Finished Mar 26 01:32:00 PM PDT 24
Peak memory 217724 kb
Host smart-4b50a685-17bd-4d7c-86d1-fff4e414aff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764171403 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.764171403
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.805813096
Short name T1064
Test name
Test status
Simulation time 194597880 ps
CPU time 1.46 seconds
Started Mar 26 01:31:59 PM PDT 24
Finished Mar 26 01:32:01 PM PDT 24
Peak memory 207260 kb
Host smart-46cc9b00-161c-48ad-b608-c232466a8eb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805813096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.805813096
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.459375648
Short name T1001
Test name
Test status
Simulation time 25811881 ps
CPU time 0.73 seconds
Started Mar 26 01:31:58 PM PDT 24
Finished Mar 26 01:31:59 PM PDT 24
Peak memory 203388 kb
Host smart-2dd25a14-55a5-4545-a9c8-07f52fbc000a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459375648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.459375648
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3133341690
Short name T1020
Test name
Test status
Simulation time 443171451 ps
CPU time 3.04 seconds
Started Mar 26 01:31:55 PM PDT 24
Finished Mar 26 01:31:58 PM PDT 24
Peak memory 215444 kb
Host smart-c9618198-8744-49c2-bdcb-ae1fcb3220b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133341690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3133341690
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4077221554
Short name T1060
Test name
Test status
Simulation time 100506882 ps
CPU time 1.7 seconds
Started Mar 26 01:31:55 PM PDT 24
Finished Mar 26 01:31:56 PM PDT 24
Peak memory 215552 kb
Host smart-b24def45-810d-4ebf-8443-91b3d9488530
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077221554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
077221554
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.182083918
Short name T1021
Test name
Test status
Simulation time 770068621 ps
CPU time 12.27 seconds
Started Mar 26 01:31:58 PM PDT 24
Finished Mar 26 01:32:10 PM PDT 24
Peak memory 215340 kb
Host smart-6c4dac70-93d9-4265-af4f-37cbb1f3fe3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182083918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.182083918
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1835784484
Short name T94
Test name
Test status
Simulation time 341367291 ps
CPU time 2.73 seconds
Started Mar 26 01:31:57 PM PDT 24
Finished Mar 26 01:32:00 PM PDT 24
Peak memory 216492 kb
Host smart-de6c3c37-9465-44c4-8ba1-3ee4f10cacc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835784484 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1835784484
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2443802911
Short name T98
Test name
Test status
Simulation time 18518554 ps
CPU time 1.21 seconds
Started Mar 26 01:31:59 PM PDT 24
Finished Mar 26 01:32:00 PM PDT 24
Peak memory 207040 kb
Host smart-8ffa1d00-a2c5-4422-828e-d16386aa60fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443802911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
443802911
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.366785450
Short name T1047
Test name
Test status
Simulation time 149490029 ps
CPU time 0.71 seconds
Started Mar 26 01:31:56 PM PDT 24
Finished Mar 26 01:31:57 PM PDT 24
Peak memory 203368 kb
Host smart-2de165b3-f7f6-4df0-a30d-7ab197bdf36c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366785450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.366785450
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3129331109
Short name T999
Test name
Test status
Simulation time 113841295 ps
CPU time 1.88 seconds
Started Mar 26 01:31:58 PM PDT 24
Finished Mar 26 01:32:00 PM PDT 24
Peak memory 215388 kb
Host smart-c5505bda-9a00-4219-b8f1-f42e7e64dbdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129331109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3129331109
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3928172653
Short name T93
Test name
Test status
Simulation time 110318691 ps
CPU time 1.98 seconds
Started Mar 26 01:31:54 PM PDT 24
Finished Mar 26 01:31:56 PM PDT 24
Peak memory 215560 kb
Host smart-d60252be-d4ed-4c4c-b34e-532bcdfa6f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928172653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
928172653
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1536066459
Short name T86
Test name
Test status
Simulation time 300088223 ps
CPU time 19.82 seconds
Started Mar 26 01:31:58 PM PDT 24
Finished Mar 26 01:32:17 PM PDT 24
Peak memory 215312 kb
Host smart-1939baa2-8b81-4b1e-af41-21ecae80c68f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536066459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1536066459
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3694260126
Short name T1116
Test name
Test status
Simulation time 58592827 ps
CPU time 1.75 seconds
Started Mar 26 01:32:04 PM PDT 24
Finished Mar 26 01:32:06 PM PDT 24
Peak memory 215356 kb
Host smart-886dcf1a-21d9-4f55-9cc8-d43bbe29fb32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694260126 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3694260126
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2792229291
Short name T1114
Test name
Test status
Simulation time 127739455 ps
CPU time 2.42 seconds
Started Mar 26 01:32:05 PM PDT 24
Finished Mar 26 01:32:08 PM PDT 24
Peak memory 207088 kb
Host smart-b7b20c3a-a2a4-48ec-a6ff-462c686761da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792229291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
792229291
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.998800878
Short name T1086
Test name
Test status
Simulation time 25567891 ps
CPU time 0.71 seconds
Started Mar 26 01:32:09 PM PDT 24
Finished Mar 26 01:32:10 PM PDT 24
Peak memory 203456 kb
Host smart-cf644acf-003e-4783-ab0e-c79bffc1ef29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998800878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.998800878
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2038552529
Short name T135
Test name
Test status
Simulation time 73797715 ps
CPU time 1.89 seconds
Started Mar 26 01:32:07 PM PDT 24
Finished Mar 26 01:32:09 PM PDT 24
Peak memory 206904 kb
Host smart-fa838f4d-a67d-4a7d-9f76-557fff160dfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038552529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2038552529
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.481220261
Short name T1090
Test name
Test status
Simulation time 119439016 ps
CPU time 3.19 seconds
Started Mar 26 01:31:59 PM PDT 24
Finished Mar 26 01:32:02 PM PDT 24
Peak memory 215692 kb
Host smart-dfffb647-0e2f-4fc0-93a7-0f43371d7d60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481220261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.481220261
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3020300763
Short name T1102
Test name
Test status
Simulation time 425869972 ps
CPU time 6.43 seconds
Started Mar 26 01:32:04 PM PDT 24
Finished Mar 26 01:32:11 PM PDT 24
Peak memory 215440 kb
Host smart-e61aec9e-eaf2-4d71-8e88-add80f42befd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020300763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3020300763
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3932208537
Short name T1096
Test name
Test status
Simulation time 28314650 ps
CPU time 1.73 seconds
Started Mar 26 01:32:06 PM PDT 24
Finished Mar 26 01:32:09 PM PDT 24
Peak memory 215452 kb
Host smart-dcfcabb3-9f36-4be0-9943-77f5a5d685f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932208537 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3932208537
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3663076
Short name T1092
Test name
Test status
Simulation time 66348846 ps
CPU time 2.23 seconds
Started Mar 26 01:32:05 PM PDT 24
Finished Mar 26 01:32:07 PM PDT 24
Peak memory 207180 kb
Host smart-c46f6bef-b44b-4f48-b52c-3c84ffdd8ce5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3663076
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4193925885
Short name T1072
Test name
Test status
Simulation time 34352438 ps
CPU time 0.78 seconds
Started Mar 26 01:32:05 PM PDT 24
Finished Mar 26 01:32:06 PM PDT 24
Peak memory 203760 kb
Host smart-0e8369b8-9986-4de8-bf90-7dad38dc7fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193925885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
193925885
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1603825303
Short name T1025
Test name
Test status
Simulation time 166664228 ps
CPU time 3.09 seconds
Started Mar 26 01:32:09 PM PDT 24
Finished Mar 26 01:32:12 PM PDT 24
Peak memory 215596 kb
Host smart-91fbb675-4732-4ca9-a132-b23390308eff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603825303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1603825303
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4287062213
Short name T87
Test name
Test status
Simulation time 1472581993 ps
CPU time 3.09 seconds
Started Mar 26 01:32:05 PM PDT 24
Finished Mar 26 01:32:08 PM PDT 24
Peak memory 215480 kb
Host smart-580e9287-f9a7-4ca0-8683-1c6c35f4c99e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287062213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
287062213
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.269299237
Short name T1108
Test name
Test status
Simulation time 1480230613 ps
CPU time 7.11 seconds
Started Mar 26 01:32:09 PM PDT 24
Finished Mar 26 01:32:17 PM PDT 24
Peak memory 215436 kb
Host smart-4598a3c1-789a-4cb4-93fa-a6b9974b46e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269299237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.269299237
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.854874254
Short name T656
Test name
Test status
Simulation time 45639888 ps
CPU time 0.72 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:03 PM PDT 24
Peak memory 205144 kb
Host smart-b9bde923-df85-4d37-aef6-c97d287143ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854874254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.854874254
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2507271382
Short name T531
Test name
Test status
Simulation time 2961252556 ps
CPU time 11.14 seconds
Started Mar 26 02:00:51 PM PDT 24
Finished Mar 26 02:01:04 PM PDT 24
Peak memory 233560 kb
Host smart-eeb88774-95a9-4a61-a1bf-ab1c74346672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507271382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2507271382
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.944212641
Short name T931
Test name
Test status
Simulation time 22057018 ps
CPU time 0.75 seconds
Started Mar 26 02:00:50 PM PDT 24
Finished Mar 26 02:00:52 PM PDT 24
Peak memory 205512 kb
Host smart-8c6195db-39c9-4a9a-8ca4-8c8f71753f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944212641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.944212641
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1760910015
Short name T258
Test name
Test status
Simulation time 57290022450 ps
CPU time 204.07 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:04:26 PM PDT 24
Peak memory 249088 kb
Host smart-92f6bb4f-b88a-419a-981b-bd0f8445e1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760910015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1760910015
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1428787091
Short name T561
Test name
Test status
Simulation time 123311102646 ps
CPU time 142.9 seconds
Started Mar 26 02:01:06 PM PDT 24
Finished Mar 26 02:03:29 PM PDT 24
Peak memory 239684 kb
Host smart-c04a7991-0fc3-4c90-8825-730906fdfb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428787091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1428787091
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.500224093
Short name T941
Test name
Test status
Simulation time 1028627409 ps
CPU time 12.78 seconds
Started Mar 26 02:00:52 PM PDT 24
Finished Mar 26 02:01:06 PM PDT 24
Peak memory 223524 kb
Host smart-35efbcbc-f149-4317-ab8d-2ebd82b14c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500224093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.500224093
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1108675535
Short name T974
Test name
Test status
Simulation time 19839707439 ps
CPU time 14.78 seconds
Started Mar 26 02:00:49 PM PDT 24
Finished Mar 26 02:01:06 PM PDT 24
Peak memory 224416 kb
Host smart-cabe25bd-156b-460a-aec6-2038dde58866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108675535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1108675535
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3756618551
Short name T517
Test name
Test status
Simulation time 26549887290 ps
CPU time 41.18 seconds
Started Mar 26 02:00:51 PM PDT 24
Finished Mar 26 02:01:33 PM PDT 24
Peak memory 233556 kb
Host smart-f563ca40-8d7e-4e06-a000-9f900e38c3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756618551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3756618551
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2892175823
Short name T542
Test name
Test status
Simulation time 1623287029 ps
CPU time 7.26 seconds
Started Mar 26 02:00:51 PM PDT 24
Finished Mar 26 02:01:00 PM PDT 24
Peak memory 218412 kb
Host smart-6e7c2377-e535-434d-881f-1ea38ff55c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892175823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2892175823
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.148548594
Short name T799
Test name
Test status
Simulation time 103775503 ps
CPU time 2.58 seconds
Started Mar 26 02:00:50 PM PDT 24
Finished Mar 26 02:00:55 PM PDT 24
Peak memory 218396 kb
Host smart-9eeddb26-5486-447f-b82d-0751483d7490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148548594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.148548594
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1868551817
Short name T341
Test name
Test status
Simulation time 23246668 ps
CPU time 0.74 seconds
Started Mar 26 02:00:51 PM PDT 24
Finished Mar 26 02:00:54 PM PDT 24
Peak memory 216088 kb
Host smart-8073aae2-fd6d-4465-9c6f-20dbbf17c967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868551817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1868551817
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.274523071
Short name T755
Test name
Test status
Simulation time 74932427 ps
CPU time 3.41 seconds
Started Mar 26 02:00:52 PM PDT 24
Finished Mar 26 02:00:57 PM PDT 24
Peak memory 222740 kb
Host smart-9ddebab4-280d-4eb3-a3d5-2147a4bb81fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=274523071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.274523071
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4205400719
Short name T750
Test name
Test status
Simulation time 7645007224 ps
CPU time 39.33 seconds
Started Mar 26 02:00:51 PM PDT 24
Finished Mar 26 02:01:31 PM PDT 24
Peak memory 216268 kb
Host smart-380bc5c8-b03a-4fed-9463-70a2102c716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205400719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4205400719
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1257933574
Short name T691
Test name
Test status
Simulation time 41327816864 ps
CPU time 36.2 seconds
Started Mar 26 02:00:50 PM PDT 24
Finished Mar 26 02:01:28 PM PDT 24
Peak memory 216216 kb
Host smart-a5abcebc-8b2c-4672-a154-7c1e2dfb0e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257933574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1257933574
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.939694198
Short name T158
Test name
Test status
Simulation time 249312292 ps
CPU time 6.75 seconds
Started Mar 26 02:00:52 PM PDT 24
Finished Mar 26 02:01:00 PM PDT 24
Peak memory 216304 kb
Host smart-0e2a9b25-6116-42f7-b329-76b8dc2b763d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939694198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.939694198
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1489458539
Short name T888
Test name
Test status
Simulation time 23315709 ps
CPU time 0.79 seconds
Started Mar 26 02:00:50 PM PDT 24
Finished Mar 26 02:00:52 PM PDT 24
Peak memory 205696 kb
Host smart-9da2d305-36a2-47ea-9931-12a14fe4ca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489458539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1489458539
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3745306427
Short name T568
Test name
Test status
Simulation time 383646670 ps
CPU time 3.22 seconds
Started Mar 26 02:00:49 PM PDT 24
Finished Mar 26 02:00:54 PM PDT 24
Peak memory 232472 kb
Host smart-c99da73c-e9d4-4fd9-92a0-00e7e4300e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745306427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3745306427
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.547206177
Short name T348
Test name
Test status
Simulation time 51747628 ps
CPU time 2.52 seconds
Started Mar 26 02:01:00 PM PDT 24
Finished Mar 26 02:01:02 PM PDT 24
Peak memory 218016 kb
Host smart-d2618604-04b1-4dd7-9e3d-71c57b9b5820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547206177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.547206177
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.845654613
Short name T695
Test name
Test status
Simulation time 42699977 ps
CPU time 0.87 seconds
Started Mar 26 02:01:03 PM PDT 24
Finished Mar 26 02:01:05 PM PDT 24
Peak memory 206276 kb
Host smart-a66f168e-348c-4602-a888-381098874296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845654613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.845654613
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1231452878
Short name T617
Test name
Test status
Simulation time 698096021 ps
CPU time 5.96 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:08 PM PDT 24
Peak memory 218272 kb
Host smart-2aced56c-6d1c-4d5a-9dbd-169da9778240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231452878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1231452878
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1238613518
Short name T536
Test name
Test status
Simulation time 21545714346 ps
CPU time 66.87 seconds
Started Mar 26 02:01:07 PM PDT 24
Finished Mar 26 02:02:14 PM PDT 24
Peak memory 235888 kb
Host smart-8ae4433d-0cc5-4e49-b795-1a5739a24eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238613518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1238613518
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3121782624
Short name T187
Test name
Test status
Simulation time 21525719414 ps
CPU time 195.22 seconds
Started Mar 26 02:01:03 PM PDT 24
Finished Mar 26 02:04:19 PM PDT 24
Peak memory 256720 kb
Host smart-3d689683-7634-41ba-8a9d-7c681aaafb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121782624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3121782624
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3582577512
Short name T468
Test name
Test status
Simulation time 1886106239 ps
CPU time 14.12 seconds
Started Mar 26 02:01:01 PM PDT 24
Finished Mar 26 02:01:16 PM PDT 24
Peak memory 245396 kb
Host smart-13a8f4c9-6823-47a6-b31a-1bedf18ab79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582577512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3582577512
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3229337134
Short name T851
Test name
Test status
Simulation time 1812838355 ps
CPU time 5.12 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:08 PM PDT 24
Peak memory 233308 kb
Host smart-059258ff-e38e-4950-94e8-bdbc7d54b984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229337134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3229337134
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.969849917
Short name T981
Test name
Test status
Simulation time 2677137722 ps
CPU time 11.42 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:14 PM PDT 24
Peak memory 224428 kb
Host smart-2e3af800-081b-4aea-ace9-70f326417fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969849917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.969849917
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1163731604
Short name T583
Test name
Test status
Simulation time 158773175 ps
CPU time 1.01 seconds
Started Mar 26 02:01:00 PM PDT 24
Finished Mar 26 02:01:01 PM PDT 24
Peak memory 217632 kb
Host smart-2d0d6887-42e5-4275-9620-8daf6425ae05
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163731604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1163731604
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1133116295
Short name T482
Test name
Test status
Simulation time 20905965193 ps
CPU time 13.13 seconds
Started Mar 26 02:01:05 PM PDT 24
Finished Mar 26 02:01:18 PM PDT 24
Peak memory 224440 kb
Host smart-8a14b10f-907d-432a-a4a9-a7c04523100b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133116295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1133116295
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4071600607
Short name T365
Test name
Test status
Simulation time 187376488 ps
CPU time 2.45 seconds
Started Mar 26 02:01:05 PM PDT 24
Finished Mar 26 02:01:07 PM PDT 24
Peak memory 216656 kb
Host smart-bea664a9-8360-4e31-80b4-5eb20b4271a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071600607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4071600607
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.1339990309
Short name T803
Test name
Test status
Simulation time 17852491 ps
CPU time 0.75 seconds
Started Mar 26 02:01:01 PM PDT 24
Finished Mar 26 02:01:02 PM PDT 24
Peak memory 216108 kb
Host smart-9db5d84f-44ca-4d14-9889-00d57cc08511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339990309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.1339990309
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4048720987
Short name T394
Test name
Test status
Simulation time 425034051 ps
CPU time 3.77 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:06 PM PDT 24
Peak memory 220128 kb
Host smart-2a8f5337-a45f-4d86-b0e7-f921d8db57f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4048720987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4048720987
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.941269722
Short name T61
Test name
Test status
Simulation time 796891169 ps
CPU time 1.14 seconds
Started Mar 26 02:01:07 PM PDT 24
Finished Mar 26 02:01:08 PM PDT 24
Peak memory 235416 kb
Host smart-50ca0107-cccc-4522-b8b0-c5eaf69bf99f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941269722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.941269722
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2892240540
Short name T790
Test name
Test status
Simulation time 3063996052 ps
CPU time 15.49 seconds
Started Mar 26 02:01:01 PM PDT 24
Finished Mar 26 02:01:17 PM PDT 24
Peak memory 216184 kb
Host smart-d1c82e1c-cedb-4423-b5c5-0bc74fb28d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892240540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2892240540
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3746173088
Short name T426
Test name
Test status
Simulation time 26696536455 ps
CPU time 27.81 seconds
Started Mar 26 02:01:06 PM PDT 24
Finished Mar 26 02:01:34 PM PDT 24
Peak memory 216252 kb
Host smart-824de945-ed51-4a9b-bde4-5169f1accb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746173088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3746173088
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2892852913
Short name T937
Test name
Test status
Simulation time 185123795 ps
CPU time 2.95 seconds
Started Mar 26 02:01:08 PM PDT 24
Finished Mar 26 02:01:11 PM PDT 24
Peak memory 216428 kb
Host smart-a6639b4d-9a6b-4074-8e97-50e48a632419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892852913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2892852913
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3227290677
Short name T919
Test name
Test status
Simulation time 431849518 ps
CPU time 1.1 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:04 PM PDT 24
Peak memory 206540 kb
Host smart-b4c154d0-4756-4bec-b727-3f3e306961c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227290677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3227290677
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.824738960
Short name T231
Test name
Test status
Simulation time 4577722585 ps
CPU time 18.94 seconds
Started Mar 26 02:01:03 PM PDT 24
Finished Mar 26 02:01:22 PM PDT 24
Peak memory 232364 kb
Host smart-05fb9187-8f8e-46d3-8ca1-c8e99d3dc1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824738960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.824738960
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3923923515
Short name T614
Test name
Test status
Simulation time 44662159 ps
CPU time 0.78 seconds
Started Mar 26 02:02:17 PM PDT 24
Finished Mar 26 02:02:18 PM PDT 24
Peak memory 204564 kb
Host smart-2f6106e4-375a-47f0-9c53-ac4e2c021d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923923515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3923923515
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2862435612
Short name T716
Test name
Test status
Simulation time 268130938 ps
CPU time 5.02 seconds
Started Mar 26 02:02:09 PM PDT 24
Finished Mar 26 02:02:14 PM PDT 24
Peak memory 233592 kb
Host smart-cc457e30-3594-4209-83d2-1a91355eb002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862435612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2862435612
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3754407699
Short name T565
Test name
Test status
Simulation time 23626928 ps
CPU time 0.81 seconds
Started Mar 26 02:02:07 PM PDT 24
Finished Mar 26 02:02:08 PM PDT 24
Peak memory 206224 kb
Host smart-4c284fa3-0253-4c6c-8f3d-8740d09260d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754407699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3754407699
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.989895942
Short name T804
Test name
Test status
Simulation time 23712414555 ps
CPU time 142.21 seconds
Started Mar 26 02:02:05 PM PDT 24
Finished Mar 26 02:04:28 PM PDT 24
Peak memory 255012 kb
Host smart-0c81f8a4-20e0-43be-910a-5a7d3d853e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989895942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.989895942
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1686653262
Short name T612
Test name
Test status
Simulation time 12350254294 ps
CPU time 118.13 seconds
Started Mar 26 02:02:09 PM PDT 24
Finished Mar 26 02:04:07 PM PDT 24
Peak memory 252520 kb
Host smart-a487b944-e2ee-4582-b673-f7211666631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686653262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1686653262
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2658165756
Short name T885
Test name
Test status
Simulation time 157661359673 ps
CPU time 226 seconds
Started Mar 26 02:02:09 PM PDT 24
Finished Mar 26 02:05:55 PM PDT 24
Peak memory 251128 kb
Host smart-ab340d7c-451a-48e8-aa9a-7df6e3ace60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658165756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2658165756
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1126180482
Short name T947
Test name
Test status
Simulation time 5136184094 ps
CPU time 18.56 seconds
Started Mar 26 02:02:08 PM PDT 24
Finished Mar 26 02:02:27 PM PDT 24
Peak memory 224476 kb
Host smart-368a2b68-57c1-4f26-a396-ee429c7594ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126180482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1126180482
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1414536877
Short name T364
Test name
Test status
Simulation time 5354963504 ps
CPU time 7.3 seconds
Started Mar 26 02:02:08 PM PDT 24
Finished Mar 26 02:02:15 PM PDT 24
Peak memory 218676 kb
Host smart-f0e92bd3-d3e5-4854-90b2-c5e60b7a1591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414536877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1414536877
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2804645837
Short name T307
Test name
Test status
Simulation time 82401575 ps
CPU time 1.09 seconds
Started Mar 26 02:02:07 PM PDT 24
Finished Mar 26 02:02:08 PM PDT 24
Peak memory 217700 kb
Host smart-2cb5f51a-5846-4e85-b229-075b6edc1ac7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804645837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2804645837
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2497907411
Short name T486
Test name
Test status
Simulation time 1509524237 ps
CPU time 3.14 seconds
Started Mar 26 02:02:07 PM PDT 24
Finished Mar 26 02:02:11 PM PDT 24
Peak memory 233476 kb
Host smart-50c36c31-3824-4961-bd85-5287c97bdd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497907411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2497907411
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.358458196
Short name T721
Test name
Test status
Simulation time 21012165424 ps
CPU time 27.63 seconds
Started Mar 26 02:02:08 PM PDT 24
Finished Mar 26 02:02:35 PM PDT 24
Peak memory 218680 kb
Host smart-052d6854-6b57-438f-9cc2-e9cda32af8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358458196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.358458196
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2911383734
Short name T398
Test name
Test status
Simulation time 17272633 ps
CPU time 0.78 seconds
Started Mar 26 02:02:05 PM PDT 24
Finished Mar 26 02:02:06 PM PDT 24
Peak memory 215964 kb
Host smart-693c00fe-2462-4238-a5db-ad34e77a9796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911383734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2911383734
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3869838021
Short name T35
Test name
Test status
Simulation time 428868839 ps
CPU time 4.05 seconds
Started Mar 26 02:02:10 PM PDT 24
Finished Mar 26 02:02:14 PM PDT 24
Peak memory 219824 kb
Host smart-c2426eeb-c2f3-400c-8169-c4654b1fe357
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3869838021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3869838021
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3342142282
Short name T852
Test name
Test status
Simulation time 15869512471 ps
CPU time 60.58 seconds
Started Mar 26 02:02:16 PM PDT 24
Finished Mar 26 02:03:17 PM PDT 24
Peak memory 251856 kb
Host smart-5c73628b-3305-4a70-a999-df0f5615d585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342142282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3342142282
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3183406317
Short name T407
Test name
Test status
Simulation time 6740266164 ps
CPU time 37.02 seconds
Started Mar 26 02:02:07 PM PDT 24
Finished Mar 26 02:02:44 PM PDT 24
Peak memory 216256 kb
Host smart-507743b5-1ea1-4ed4-b677-8369bcf5f97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183406317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3183406317
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.242365798
Short name T363
Test name
Test status
Simulation time 76489063638 ps
CPU time 23.04 seconds
Started Mar 26 02:02:08 PM PDT 24
Finished Mar 26 02:02:31 PM PDT 24
Peak memory 216200 kb
Host smart-77a68ae1-a7e8-44a1-9265-40154592c46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242365798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.242365798
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.931567665
Short name T672
Test name
Test status
Simulation time 43401030 ps
CPU time 0.8 seconds
Started Mar 26 02:02:08 PM PDT 24
Finished Mar 26 02:02:09 PM PDT 24
Peak memory 205512 kb
Host smart-c1e69cde-cdc1-4018-a918-7f800fa791b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931567665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.931567665
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.787098720
Short name T483
Test name
Test status
Simulation time 84341802 ps
CPU time 1.02 seconds
Started Mar 26 02:02:10 PM PDT 24
Finished Mar 26 02:02:11 PM PDT 24
Peak memory 206472 kb
Host smart-ff8ad13c-2e00-483b-9e8b-b823f2b8c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787098720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.787098720
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1301725007
Short name T39
Test name
Test status
Simulation time 6434676693 ps
CPU time 16.38 seconds
Started Mar 26 02:02:01 PM PDT 24
Finished Mar 26 02:02:17 PM PDT 24
Peak memory 220084 kb
Host smart-1a80d544-9a8d-416e-9f93-f8f39e8121e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301725007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1301725007
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1210839916
Short name T768
Test name
Test status
Simulation time 31523537 ps
CPU time 0.69 seconds
Started Mar 26 02:02:19 PM PDT 24
Finished Mar 26 02:02:20 PM PDT 24
Peak memory 205320 kb
Host smart-e81de858-43dd-496e-8b1d-2c98c510922c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210839916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1210839916
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3525503687
Short name T377
Test name
Test status
Simulation time 319489757 ps
CPU time 2.71 seconds
Started Mar 26 02:02:21 PM PDT 24
Finished Mar 26 02:02:24 PM PDT 24
Peak memory 233176 kb
Host smart-fb63fc90-bcf8-4746-90dc-5a5d36874276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525503687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3525503687
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.877405074
Short name T849
Test name
Test status
Simulation time 30174337 ps
CPU time 0.8 seconds
Started Mar 26 02:02:17 PM PDT 24
Finished Mar 26 02:02:17 PM PDT 24
Peak memory 206200 kb
Host smart-39fe536e-3ead-4b6a-aabd-7308bbd40991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877405074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.877405074
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3946752394
Short name T543
Test name
Test status
Simulation time 156848945820 ps
CPU time 184.47 seconds
Started Mar 26 02:02:18 PM PDT 24
Finished Mar 26 02:05:22 PM PDT 24
Peak memory 252596 kb
Host smart-4cfe5a81-24a5-4ff8-9796-a2adfd06625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946752394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3946752394
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3064194883
Short name T525
Test name
Test status
Simulation time 9447245130 ps
CPU time 81.97 seconds
Started Mar 26 02:02:23 PM PDT 24
Finished Mar 26 02:03:45 PM PDT 24
Peak memory 238056 kb
Host smart-975e30fb-aaed-43dc-b43d-c5d5e006fcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064194883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3064194883
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.420695320
Short name T41
Test name
Test status
Simulation time 25400739965 ps
CPU time 211.69 seconds
Started Mar 26 02:02:20 PM PDT 24
Finished Mar 26 02:05:52 PM PDT 24
Peak memory 254060 kb
Host smart-21feead2-6b6c-4b03-b8eb-c5015e7668b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420695320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.420695320
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3937175339
Short name T969
Test name
Test status
Simulation time 14664923962 ps
CPU time 28.84 seconds
Started Mar 26 02:02:18 PM PDT 24
Finished Mar 26 02:02:47 PM PDT 24
Peak memory 234128 kb
Host smart-c3817c77-30f7-48ba-a74e-a4b8d73689e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937175339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3937175339
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1615286668
Short name T417
Test name
Test status
Simulation time 3139776785 ps
CPU time 12.6 seconds
Started Mar 26 02:02:19 PM PDT 24
Finished Mar 26 02:02:32 PM PDT 24
Peak memory 224364 kb
Host smart-c5021fa7-c7f5-426f-b970-5108893a6a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615286668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1615286668
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1590860628
Short name T984
Test name
Test status
Simulation time 18496561201 ps
CPU time 17.29 seconds
Started Mar 26 02:02:20 PM PDT 24
Finished Mar 26 02:02:37 PM PDT 24
Peak memory 227668 kb
Host smart-ee511361-ecd2-4e8d-b206-0e09eb613ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590860628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1590860628
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.4151431311
Short name T657
Test name
Test status
Simulation time 16392152 ps
CPU time 1.02 seconds
Started Mar 26 02:02:16 PM PDT 24
Finished Mar 26 02:02:17 PM PDT 24
Peak memory 216404 kb
Host smart-1c24805c-bb12-4540-bdfa-eda0cd51fb24
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151431311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.4151431311
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.562953134
Short name T680
Test name
Test status
Simulation time 806625226 ps
CPU time 4.06 seconds
Started Mar 26 02:02:19 PM PDT 24
Finished Mar 26 02:02:23 PM PDT 24
Peak memory 224384 kb
Host smart-5120c518-bf7f-442d-94e2-f0166140c7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562953134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.562953134
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1489014283
Short name T324
Test name
Test status
Simulation time 25878796520 ps
CPU time 16.54 seconds
Started Mar 26 02:02:20 PM PDT 24
Finished Mar 26 02:02:36 PM PDT 24
Peak memory 233600 kb
Host smart-f0a99a5c-7b56-4837-ba7d-3f68454acaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489014283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1489014283
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.863486074
Short name T767
Test name
Test status
Simulation time 18612925 ps
CPU time 0.73 seconds
Started Mar 26 02:02:23 PM PDT 24
Finished Mar 26 02:02:24 PM PDT 24
Peak memory 215932 kb
Host smart-ecf989b3-88db-4433-bb86-1143108ab0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863486074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.863486074
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2387937657
Short name T925
Test name
Test status
Simulation time 613680177 ps
CPU time 4.42 seconds
Started Mar 26 02:02:18 PM PDT 24
Finished Mar 26 02:02:22 PM PDT 24
Peak memory 219704 kb
Host smart-3faf8ae6-a3bf-4ce4-8661-0fb2ffd215e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2387937657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2387937657
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3494345220
Short name T934
Test name
Test status
Simulation time 38814614 ps
CPU time 0.93 seconds
Started Mar 26 02:02:27 PM PDT 24
Finished Mar 26 02:02:28 PM PDT 24
Peak memory 206080 kb
Host smart-0d63a1c6-6e9a-44b7-95de-3b28d76deb8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494345220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3494345220
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2834328711
Short name T389
Test name
Test status
Simulation time 5182180543 ps
CPU time 46.06 seconds
Started Mar 26 02:02:18 PM PDT 24
Finished Mar 26 02:03:05 PM PDT 24
Peak memory 216200 kb
Host smart-cc814795-27a0-48dc-8409-c46b7e1caf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834328711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2834328711
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2232844870
Short name T361
Test name
Test status
Simulation time 1585386224 ps
CPU time 8.88 seconds
Started Mar 26 02:02:26 PM PDT 24
Finished Mar 26 02:02:35 PM PDT 24
Peak memory 216012 kb
Host smart-ee686e60-7d97-4933-b2eb-210647511c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232844870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2232844870
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.497280972
Short name T634
Test name
Test status
Simulation time 91870792 ps
CPU time 0.94 seconds
Started Mar 26 02:02:19 PM PDT 24
Finished Mar 26 02:02:20 PM PDT 24
Peak memory 206560 kb
Host smart-85765a23-5ecd-42d2-98aa-49ae044db844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497280972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.497280972
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2410025527
Short name T476
Test name
Test status
Simulation time 62062849 ps
CPU time 0.87 seconds
Started Mar 26 02:02:17 PM PDT 24
Finished Mar 26 02:02:18 PM PDT 24
Peak memory 205532 kb
Host smart-b556432a-bace-4fe0-9c4b-d50c9124a399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410025527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2410025527
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2698897311
Short name T952
Test name
Test status
Simulation time 20927315079 ps
CPU time 21.98 seconds
Started Mar 26 02:02:18 PM PDT 24
Finished Mar 26 02:02:40 PM PDT 24
Peak memory 233608 kb
Host smart-2c47ee3f-ca4d-4d8b-9d57-ad402b0df326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698897311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2698897311
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4271656853
Short name T830
Test name
Test status
Simulation time 13351748 ps
CPU time 0.77 seconds
Started Mar 26 02:02:20 PM PDT 24
Finished Mar 26 02:02:21 PM PDT 24
Peak memory 205028 kb
Host smart-5e144613-703e-43fe-9ad2-4e3a0ea8b430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271656853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4271656853
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1334638774
Short name T593
Test name
Test status
Simulation time 82562565 ps
CPU time 2.09 seconds
Started Mar 26 02:02:26 PM PDT 24
Finished Mar 26 02:02:29 PM PDT 24
Peak memory 218124 kb
Host smart-c3024d58-990a-405d-84ba-641b8fc802f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334638774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1334638774
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.731752861
Short name T440
Test name
Test status
Simulation time 55488266 ps
CPU time 0.72 seconds
Started Mar 26 02:02:21 PM PDT 24
Finished Mar 26 02:02:22 PM PDT 24
Peak memory 205128 kb
Host smart-42d416bf-3179-4252-b8cc-b5f7f3fa0d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731752861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.731752861
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3927980097
Short name T903
Test name
Test status
Simulation time 122550818005 ps
CPU time 302.69 seconds
Started Mar 26 02:02:19 PM PDT 24
Finished Mar 26 02:07:22 PM PDT 24
Peak memory 250380 kb
Host smart-afc29a0a-f5d2-4cf5-9420-b04ad69248b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927980097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3927980097
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1148951225
Short name T720
Test name
Test status
Simulation time 52515829257 ps
CPU time 71.02 seconds
Started Mar 26 02:02:24 PM PDT 24
Finished Mar 26 02:03:36 PM PDT 24
Peak memory 252936 kb
Host smart-a95d5f55-c357-4fdc-85b0-6e673b6d257e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148951225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1148951225
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.336152772
Short name T314
Test name
Test status
Simulation time 31624468946 ps
CPU time 173.98 seconds
Started Mar 26 02:02:17 PM PDT 24
Finished Mar 26 02:05:11 PM PDT 24
Peak memory 249000 kb
Host smart-2853d975-3145-4943-9c0d-09c21f88177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336152772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.336152772
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1638853137
Short name T267
Test name
Test status
Simulation time 26497539871 ps
CPU time 36.68 seconds
Started Mar 26 02:02:24 PM PDT 24
Finished Mar 26 02:03:00 PM PDT 24
Peak memory 250852 kb
Host smart-4282a879-05bc-4516-a4bc-398e40688207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638853137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1638853137
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2546724166
Short name T344
Test name
Test status
Simulation time 862508959 ps
CPU time 4.68 seconds
Started Mar 26 02:02:19 PM PDT 24
Finished Mar 26 02:02:24 PM PDT 24
Peak memory 233464 kb
Host smart-8f4f3134-209b-419a-b86c-407d8c84845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546724166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2546724166
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2451546657
Short name T181
Test name
Test status
Simulation time 16580055446 ps
CPU time 48.22 seconds
Started Mar 26 02:02:18 PM PDT 24
Finished Mar 26 02:03:07 PM PDT 24
Peak memory 234308 kb
Host smart-dd9da113-82f7-4a2d-b142-2802b988fc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451546657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2451546657
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1858083355
Short name T677
Test name
Test status
Simulation time 55425715 ps
CPU time 1.06 seconds
Started Mar 26 02:02:20 PM PDT 24
Finished Mar 26 02:02:21 PM PDT 24
Peak memory 216404 kb
Host smart-0f7a1ffa-99a6-4bf1-a7d0-cfb0ec88201c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858083355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1858083355
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.506160043
Short name T429
Test name
Test status
Simulation time 296366460 ps
CPU time 4.69 seconds
Started Mar 26 02:02:27 PM PDT 24
Finished Mar 26 02:02:31 PM PDT 24
Peak memory 224160 kb
Host smart-c48fa4a4-28dd-4dc1-9d9d-eaa0216e9632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506160043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.506160043
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4151793703
Short name T844
Test name
Test status
Simulation time 1046340502 ps
CPU time 7.13 seconds
Started Mar 26 02:02:16 PM PDT 24
Finished Mar 26 02:02:24 PM PDT 24
Peak memory 233696 kb
Host smart-05914675-cccc-475b-9957-fde800e7fcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151793703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4151793703
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.1042565762
Short name T445
Test name
Test status
Simulation time 34210879 ps
CPU time 0.74 seconds
Started Mar 26 02:02:19 PM PDT 24
Finished Mar 26 02:02:20 PM PDT 24
Peak memory 215984 kb
Host smart-e6c96588-4a60-4829-9ab7-dc53ee1c5eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042565762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.1042565762
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.598619923
Short name T463
Test name
Test status
Simulation time 1159236786 ps
CPU time 4.8 seconds
Started Mar 26 02:02:16 PM PDT 24
Finished Mar 26 02:02:21 PM PDT 24
Peak memory 220572 kb
Host smart-4f58484c-74ff-49d8-9aa0-02d555e4fbe3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=598619923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.598619923
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.516950280
Short name T828
Test name
Test status
Simulation time 53527719584 ps
CPU time 308.11 seconds
Started Mar 26 02:02:27 PM PDT 24
Finished Mar 26 02:07:36 PM PDT 24
Peak memory 250780 kb
Host smart-2527d45f-3449-4171-a552-34d4aac030de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516950280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.516950280
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3768537998
Short name T334
Test name
Test status
Simulation time 5898919230 ps
CPU time 27.57 seconds
Started Mar 26 02:02:19 PM PDT 24
Finished Mar 26 02:02:47 PM PDT 24
Peak memory 216152 kb
Host smart-b4898d28-44aa-4eee-8027-a9389bdf9c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768537998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3768537998
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3060652702
Short name T922
Test name
Test status
Simulation time 1654502110 ps
CPU time 8.05 seconds
Started Mar 26 02:02:26 PM PDT 24
Finished Mar 26 02:02:34 PM PDT 24
Peak memory 215932 kb
Host smart-311dfd56-a208-4afd-96bf-0528c3a36a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060652702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3060652702
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1273930699
Short name T802
Test name
Test status
Simulation time 24839554 ps
CPU time 1.05 seconds
Started Mar 26 02:02:20 PM PDT 24
Finished Mar 26 02:02:21 PM PDT 24
Peak memory 206768 kb
Host smart-825f1ff4-a669-4864-852a-e70d4f80bce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273930699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1273930699
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2757860190
Short name T701
Test name
Test status
Simulation time 54539258 ps
CPU time 0.83 seconds
Started Mar 26 02:02:24 PM PDT 24
Finished Mar 26 02:02:25 PM PDT 24
Peak memory 205396 kb
Host smart-e37125c6-1faa-40c4-a020-300dab30c33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757860190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2757860190
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3680100934
Short name T801
Test name
Test status
Simulation time 15515050579 ps
CPU time 18.46 seconds
Started Mar 26 02:02:18 PM PDT 24
Finished Mar 26 02:02:36 PM PDT 24
Peak memory 237964 kb
Host smart-d0a99a5e-a85d-4946-9099-afd386b672cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680100934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3680100934
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3321366384
Short name T346
Test name
Test status
Simulation time 30936065 ps
CPU time 0.72 seconds
Started Mar 26 02:02:32 PM PDT 24
Finished Mar 26 02:02:35 PM PDT 24
Peak memory 205488 kb
Host smart-0293a204-b09c-44fc-be9a-61054e796c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321366384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3321366384
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3628409636
Short name T212
Test name
Test status
Simulation time 689576924 ps
CPU time 3.12 seconds
Started Mar 26 02:02:37 PM PDT 24
Finished Mar 26 02:02:40 PM PDT 24
Peak memory 218880 kb
Host smart-9f407d85-8e01-48b4-8c47-bdbf2002af15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628409636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3628409636
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1046580750
Short name T415
Test name
Test status
Simulation time 38548651 ps
CPU time 0.84 seconds
Started Mar 26 02:02:18 PM PDT 24
Finished Mar 26 02:02:19 PM PDT 24
Peak memory 206160 kb
Host smart-7e466e77-8316-408b-8e59-4926073e6ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046580750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1046580750
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1411516775
Short name T8
Test name
Test status
Simulation time 132752550537 ps
CPU time 461.42 seconds
Started Mar 26 02:02:30 PM PDT 24
Finished Mar 26 02:10:12 PM PDT 24
Peak memory 266248 kb
Host smart-09794564-ce97-4796-8743-15ec34a2c3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411516775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1411516775
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1959981939
Short name T772
Test name
Test status
Simulation time 1526507233 ps
CPU time 26.81 seconds
Started Mar 26 02:02:33 PM PDT 24
Finished Mar 26 02:03:01 PM PDT 24
Peak memory 249316 kb
Host smart-ad17f51b-61ea-4c58-a9d6-8012af5c85d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959981939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1959981939
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3349848617
Short name T647
Test name
Test status
Simulation time 2238382477 ps
CPU time 8.98 seconds
Started Mar 26 02:02:30 PM PDT 24
Finished Mar 26 02:02:40 PM PDT 24
Peak memory 238552 kb
Host smart-29ae2a24-8f73-4f80-a458-4ef84e7b052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349848617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3349848617
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.320074079
Short name T446
Test name
Test status
Simulation time 4245681283 ps
CPU time 7.53 seconds
Started Mar 26 02:02:33 PM PDT 24
Finished Mar 26 02:02:41 PM PDT 24
Peak memory 219264 kb
Host smart-d663fe07-cd5f-487f-a9fc-4b968fc99d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320074079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.320074079
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2260371325
Short name T213
Test name
Test status
Simulation time 2694469133 ps
CPU time 17.89 seconds
Started Mar 26 02:02:32 PM PDT 24
Finished Mar 26 02:02:52 PM PDT 24
Peak memory 236356 kb
Host smart-22994a50-5d55-47ac-9f2f-0c5be096bd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260371325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2260371325
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1033598128
Short name T809
Test name
Test status
Simulation time 91866142 ps
CPU time 1.03 seconds
Started Mar 26 02:02:37 PM PDT 24
Finished Mar 26 02:02:39 PM PDT 24
Peak memory 216324 kb
Host smart-bdd81e3a-5857-47ca-997f-085b1e3ae307
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033598128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1033598128
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2559868168
Short name T693
Test name
Test status
Simulation time 2998907364 ps
CPU time 4.32 seconds
Started Mar 26 02:02:31 PM PDT 24
Finished Mar 26 02:02:37 PM PDT 24
Peak memory 233496 kb
Host smart-fa0ce2ca-a633-449b-a56b-692733364802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559868168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2559868168
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4220722350
Short name T971
Test name
Test status
Simulation time 5870308935 ps
CPU time 6.85 seconds
Started Mar 26 02:02:31 PM PDT 24
Finished Mar 26 02:02:39 PM PDT 24
Peak memory 233132 kb
Host smart-0046116b-503e-4cfa-979b-bf93f33cea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220722350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4220722350
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.814795221
Short name T821
Test name
Test status
Simulation time 15935458 ps
CPU time 0.75 seconds
Started Mar 26 02:02:30 PM PDT 24
Finished Mar 26 02:02:31 PM PDT 24
Peak memory 216292 kb
Host smart-4e39fa05-b682-47c8-a087-a8156413d1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814795221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.814795221
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1214956273
Short name T966
Test name
Test status
Simulation time 2644089481 ps
CPU time 6.53 seconds
Started Mar 26 02:02:30 PM PDT 24
Finished Mar 26 02:02:37 PM PDT 24
Peak memory 222736 kb
Host smart-754e137c-8ece-4df6-995e-54c97ef59817
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1214956273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1214956273
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.238041349
Short name T151
Test name
Test status
Simulation time 102038189965 ps
CPU time 136.64 seconds
Started Mar 26 02:02:33 PM PDT 24
Finished Mar 26 02:04:51 PM PDT 24
Peak memory 240024 kb
Host smart-e3144582-fbf0-4e0e-8a9a-567c2b0dc1fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238041349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.238041349
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3958672154
Short name T591
Test name
Test status
Simulation time 8888546020 ps
CPU time 14.99 seconds
Started Mar 26 02:02:32 PM PDT 24
Finished Mar 26 02:02:49 PM PDT 24
Peak memory 216104 kb
Host smart-132334f1-3bba-423f-97ee-cbd82b31137a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958672154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3958672154
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2655698819
Short name T498
Test name
Test status
Simulation time 48604404 ps
CPU time 1.62 seconds
Started Mar 26 02:02:30 PM PDT 24
Finished Mar 26 02:02:32 PM PDT 24
Peak memory 216204 kb
Host smart-213d6c28-159f-49ad-8d70-3983a633e483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655698819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2655698819
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.522829890
Short name T276
Test name
Test status
Simulation time 84994262 ps
CPU time 1.01 seconds
Started Mar 26 02:02:30 PM PDT 24
Finished Mar 26 02:02:32 PM PDT 24
Peak memory 205964 kb
Host smart-26863b75-c5d6-4c89-a4de-5bada191036d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522829890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.522829890
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1133566283
Short name T63
Test name
Test status
Simulation time 20348983687 ps
CPU time 19.91 seconds
Started Mar 26 02:02:32 PM PDT 24
Finished Mar 26 02:02:54 PM PDT 24
Peak memory 228520 kb
Host smart-018ea55c-2b84-4f01-a518-d7468840fe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133566283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1133566283
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.712514861
Short name T569
Test name
Test status
Simulation time 122411779 ps
CPU time 0.73 seconds
Started Mar 26 02:02:41 PM PDT 24
Finished Mar 26 02:02:42 PM PDT 24
Peak memory 205108 kb
Host smart-1ead0f98-fc5c-46b7-afcd-315fe9ec2f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712514861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.712514861
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1082076158
Short name T841
Test name
Test status
Simulation time 2012483046 ps
CPU time 3.69 seconds
Started Mar 26 02:02:42 PM PDT 24
Finished Mar 26 02:02:46 PM PDT 24
Peak memory 218012 kb
Host smart-a3b2fbbe-99ad-49e9-b08c-2f5836662f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082076158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1082076158
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1931276518
Short name T126
Test name
Test status
Simulation time 57708172 ps
CPU time 0.75 seconds
Started Mar 26 02:02:31 PM PDT 24
Finished Mar 26 02:02:33 PM PDT 24
Peak memory 206540 kb
Host smart-9440c5d6-24f2-428c-aa04-e01abee29bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931276518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1931276518
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2825039037
Short name T827
Test name
Test status
Simulation time 3729216386 ps
CPU time 28.35 seconds
Started Mar 26 02:02:44 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 240908 kb
Host smart-89fd38f8-02c8-4122-94f3-7493835cc205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825039037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2825039037
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2719271414
Short name T795
Test name
Test status
Simulation time 10515609311 ps
CPU time 94.55 seconds
Started Mar 26 02:02:42 PM PDT 24
Finished Mar 26 02:04:17 PM PDT 24
Peak memory 254220 kb
Host smart-9196f288-2ef0-417e-a788-0c64ee6974b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719271414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2719271414
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3022463243
Short name T204
Test name
Test status
Simulation time 8567341722 ps
CPU time 44.01 seconds
Started Mar 26 02:02:41 PM PDT 24
Finished Mar 26 02:03:26 PM PDT 24
Peak memory 255184 kb
Host smart-b449c744-2da7-4651-bf40-75ff47777dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022463243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3022463243
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2175141403
Short name T295
Test name
Test status
Simulation time 28819620740 ps
CPU time 13.98 seconds
Started Mar 26 02:02:41 PM PDT 24
Finished Mar 26 02:02:55 PM PDT 24
Peak memory 224488 kb
Host smart-fff80a07-5d91-4b87-971c-7f71529e4c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175141403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2175141403
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3258725984
Short name T203
Test name
Test status
Simulation time 5534826796 ps
CPU time 19.22 seconds
Started Mar 26 02:02:41 PM PDT 24
Finished Mar 26 02:03:01 PM PDT 24
Peak memory 233732 kb
Host smart-3850f465-21a7-41e8-ba19-4e312bddbb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258725984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3258725984
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3247592627
Short name T23
Test name
Test status
Simulation time 111420975 ps
CPU time 1.12 seconds
Started Mar 26 02:02:31 PM PDT 24
Finished Mar 26 02:02:33 PM PDT 24
Peak memory 216352 kb
Host smart-005e4d52-6636-4d30-b165-4e3fdb53f990
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247592627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3247592627
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2130729589
Short name T854
Test name
Test status
Simulation time 1068354531 ps
CPU time 5.99 seconds
Started Mar 26 02:02:44 PM PDT 24
Finished Mar 26 02:02:50 PM PDT 24
Peak memory 233044 kb
Host smart-30b6c449-3d25-4cda-9ead-79e10634bffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130729589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2130729589
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.693989443
Short name T289
Test name
Test status
Simulation time 5272096269 ps
CPU time 10.2 seconds
Started Mar 26 02:02:42 PM PDT 24
Finished Mar 26 02:02:52 PM PDT 24
Peak memory 224360 kb
Host smart-15513c41-b04e-4fce-bbef-4c9ea7aa9ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693989443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.693989443
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4280725477
Short name T449
Test name
Test status
Simulation time 890761969 ps
CPU time 6.01 seconds
Started Mar 26 02:02:44 PM PDT 24
Finished Mar 26 02:02:50 PM PDT 24
Peak memory 222124 kb
Host smart-4145e4b1-a95f-43f0-b54e-4c02d2de19d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4280725477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4280725477
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3951351556
Short name T188
Test name
Test status
Simulation time 82408908325 ps
CPU time 665.05 seconds
Started Mar 26 02:02:45 PM PDT 24
Finished Mar 26 02:13:50 PM PDT 24
Peak memory 264676 kb
Host smart-bc29c69e-d71a-41d8-96e9-9fe96e679428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951351556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3951351556
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3127836240
Short name T625
Test name
Test status
Simulation time 2432943989 ps
CPU time 5.55 seconds
Started Mar 26 02:02:43 PM PDT 24
Finished Mar 26 02:02:49 PM PDT 24
Peak memory 216176 kb
Host smart-b401eeac-bb48-4750-8f6b-8cd57b31e3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127836240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3127836240
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.825489228
Short name T880
Test name
Test status
Simulation time 3098796080 ps
CPU time 10.84 seconds
Started Mar 26 02:02:43 PM PDT 24
Finished Mar 26 02:02:54 PM PDT 24
Peak memory 216112 kb
Host smart-9244d96c-6826-4777-be1d-ba126e1860a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825489228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.825489228
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.81121509
Short name T923
Test name
Test status
Simulation time 447471852 ps
CPU time 5.95 seconds
Started Mar 26 02:02:42 PM PDT 24
Finished Mar 26 02:02:48 PM PDT 24
Peak memory 216124 kb
Host smart-31c50d0a-c03d-412a-a189-2c94998d1025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81121509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.81121509
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3838595925
Short name T557
Test name
Test status
Simulation time 43426553 ps
CPU time 0.83 seconds
Started Mar 26 02:02:41 PM PDT 24
Finished Mar 26 02:02:42 PM PDT 24
Peak memory 205420 kb
Host smart-648855a5-1779-488d-83a9-6528a1f67e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838595925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3838595925
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3781126603
Short name T64
Test name
Test status
Simulation time 1694266667 ps
CPU time 7.22 seconds
Started Mar 26 02:02:43 PM PDT 24
Finished Mar 26 02:02:50 PM PDT 24
Peak memory 240644 kb
Host smart-d917cee7-4919-422d-b83e-79e2c598fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781126603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3781126603
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2715723432
Short name T787
Test name
Test status
Simulation time 20867510 ps
CPU time 0.75 seconds
Started Mar 26 02:02:58 PM PDT 24
Finished Mar 26 02:02:59 PM PDT 24
Peak memory 204524 kb
Host smart-a62baa45-1cd3-444b-99eb-abb0e5221043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715723432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2715723432
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3023321998
Short name T926
Test name
Test status
Simulation time 1960356774 ps
CPU time 7.38 seconds
Started Mar 26 02:02:56 PM PDT 24
Finished Mar 26 02:03:03 PM PDT 24
Peak memory 218592 kb
Host smart-d8b05f94-c03a-48d9-ae5f-30aece8522b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023321998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3023321998
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3420598377
Short name T670
Test name
Test status
Simulation time 28952228 ps
CPU time 0.76 seconds
Started Mar 26 02:02:42 PM PDT 24
Finished Mar 26 02:02:43 PM PDT 24
Peak memory 205376 kb
Host smart-efb89a10-156b-46d6-96d3-4dc87122712d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420598377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3420598377
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2079923725
Short name T877
Test name
Test status
Simulation time 1296866284 ps
CPU time 17.98 seconds
Started Mar 26 02:02:55 PM PDT 24
Finished Mar 26 02:03:13 PM PDT 24
Peak memory 240744 kb
Host smart-4e73613c-30cc-4c9b-9290-49b3970e42b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079923725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2079923725
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.977291043
Short name T932
Test name
Test status
Simulation time 6794163380 ps
CPU time 75.44 seconds
Started Mar 26 02:02:55 PM PDT 24
Finished Mar 26 02:04:11 PM PDT 24
Peak memory 249148 kb
Host smart-d06cf3a3-b1c4-4640-b638-45f09b75775f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977291043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.977291043
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2532135809
Short name T609
Test name
Test status
Simulation time 7932313823 ps
CPU time 106.06 seconds
Started Mar 26 02:02:57 PM PDT 24
Finished Mar 26 02:04:44 PM PDT 24
Peak memory 264476 kb
Host smart-367c1005-f342-4b0b-a092-1d420d967049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532135809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2532135809
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3885318637
Short name T881
Test name
Test status
Simulation time 17151981324 ps
CPU time 20.74 seconds
Started Mar 26 02:02:57 PM PDT 24
Finished Mar 26 02:03:18 PM PDT 24
Peak memory 236912 kb
Host smart-75a84572-d241-4678-84c3-06923e9b15e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885318637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3885318637
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2009992796
Short name T730
Test name
Test status
Simulation time 167675744 ps
CPU time 3.23 seconds
Started Mar 26 02:02:56 PM PDT 24
Finished Mar 26 02:03:00 PM PDT 24
Peak memory 217528 kb
Host smart-61f26fa8-c8aa-490e-9a1c-bbf73643c2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009992796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2009992796
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.891661243
Short name T229
Test name
Test status
Simulation time 443438854 ps
CPU time 4.17 seconds
Started Mar 26 02:02:56 PM PDT 24
Finished Mar 26 02:03:00 PM PDT 24
Peak memory 216888 kb
Host smart-d856b36a-82ff-4144-a6b3-9f260921715f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891661243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.891661243
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3120175259
Short name T812
Test name
Test status
Simulation time 18448139 ps
CPU time 1.06 seconds
Started Mar 26 02:02:42 PM PDT 24
Finished Mar 26 02:02:43 PM PDT 24
Peak memory 216664 kb
Host smart-3f38b432-9f3d-42c0-817b-b82cb93dc48a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120175259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3120175259
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1417458883
Short name T395
Test name
Test status
Simulation time 202776785 ps
CPU time 3.61 seconds
Started Mar 26 02:02:57 PM PDT 24
Finished Mar 26 02:03:00 PM PDT 24
Peak memory 217864 kb
Host smart-8b2218b1-028f-47c3-886e-98ebb0f5e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417458883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1417458883
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1389051256
Short name T749
Test name
Test status
Simulation time 7213625471 ps
CPU time 10.67 seconds
Started Mar 26 02:02:44 PM PDT 24
Finished Mar 26 02:02:55 PM PDT 24
Peak memory 223636 kb
Host smart-702e2c6c-7dc7-4d58-9964-28372671c401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389051256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1389051256
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.3863174625
Short name T747
Test name
Test status
Simulation time 16911953 ps
CPU time 0.75 seconds
Started Mar 26 02:02:41 PM PDT 24
Finished Mar 26 02:02:42 PM PDT 24
Peak memory 216116 kb
Host smart-443de3d1-de8e-4a51-9d98-4a9f1c75dfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863174625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.3863174625
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3142131771
Short name T814
Test name
Test status
Simulation time 1857203981 ps
CPU time 5.74 seconds
Started Mar 26 02:02:58 PM PDT 24
Finished Mar 26 02:03:04 PM PDT 24
Peak memory 222168 kb
Host smart-ee4ce6af-cd7c-46da-bf0a-0b9d0fa17c3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3142131771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3142131771
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3824486021
Short name T198
Test name
Test status
Simulation time 105020838024 ps
CPU time 299.26 seconds
Started Mar 26 02:02:58 PM PDT 24
Finished Mar 26 02:07:57 PM PDT 24
Peak memory 253060 kb
Host smart-014fd89e-e796-4d58-85d1-9d5a67e7d891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824486021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3824486021
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.137831142
Short name T933
Test name
Test status
Simulation time 141876436 ps
CPU time 2.8 seconds
Started Mar 26 02:02:41 PM PDT 24
Finished Mar 26 02:02:44 PM PDT 24
Peak memory 216168 kb
Host smart-c69661da-0870-4806-b71b-59f5e5444f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137831142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.137831142
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4063626142
Short name T763
Test name
Test status
Simulation time 8525833063 ps
CPU time 16.61 seconds
Started Mar 26 02:02:43 PM PDT 24
Finished Mar 26 02:03:00 PM PDT 24
Peak memory 216092 kb
Host smart-62790e75-1367-403a-a7f5-dd01dd532c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063626142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4063626142
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2300814153
Short name T603
Test name
Test status
Simulation time 262895476 ps
CPU time 2.53 seconds
Started Mar 26 02:02:40 PM PDT 24
Finished Mar 26 02:02:43 PM PDT 24
Peak memory 216252 kb
Host smart-e250fe94-b742-4141-91c5-af6ad3ddc054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300814153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2300814153
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2629920601
Short name T622
Test name
Test status
Simulation time 82188039 ps
CPU time 0.84 seconds
Started Mar 26 02:02:42 PM PDT 24
Finished Mar 26 02:02:43 PM PDT 24
Peak memory 205536 kb
Host smart-d37688cb-0575-45ca-b7bc-da6b7117dfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629920601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2629920601
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3513657041
Short name T987
Test name
Test status
Simulation time 29259763177 ps
CPU time 17.31 seconds
Started Mar 26 02:02:57 PM PDT 24
Finished Mar 26 02:03:15 PM PDT 24
Peak memory 218332 kb
Host smart-3d68e6fb-663b-4262-8e30-f2130f47055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513657041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3513657041
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3176076613
Short name T641
Test name
Test status
Simulation time 21415427 ps
CPU time 0.73 seconds
Started Mar 26 02:03:07 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 205072 kb
Host smart-4188d87a-0a15-4711-af09-5ea4f1083907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176076613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3176076613
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2729299730
Short name T472
Test name
Test status
Simulation time 125170383 ps
CPU time 2.85 seconds
Started Mar 26 02:02:56 PM PDT 24
Finished Mar 26 02:02:59 PM PDT 24
Peak memory 218408 kb
Host smart-7862d884-57fa-44ad-8b73-2102a834e4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729299730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2729299730
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.239360437
Short name T886
Test name
Test status
Simulation time 18108178 ps
CPU time 0.79 seconds
Started Mar 26 02:02:54 PM PDT 24
Finished Mar 26 02:02:55 PM PDT 24
Peak memory 206448 kb
Host smart-02140482-fecf-4805-b47f-4588644b06c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239360437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.239360437
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.156577954
Short name T157
Test name
Test status
Simulation time 5830699814 ps
CPU time 67.94 seconds
Started Mar 26 02:02:59 PM PDT 24
Finished Mar 26 02:04:07 PM PDT 24
Peak memory 235196 kb
Host smart-f5d37dcc-4aca-4e89-a9c1-d6c8ab0320e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156577954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.156577954
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1644486011
Short name T686
Test name
Test status
Simulation time 12688084074 ps
CPU time 78.38 seconds
Started Mar 26 02:02:55 PM PDT 24
Finished Mar 26 02:04:14 PM PDT 24
Peak memory 221548 kb
Host smart-400f484e-0305-4150-a9df-e84374c1b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644486011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1644486011
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3862220531
Short name T983
Test name
Test status
Simulation time 1836896370 ps
CPU time 7.52 seconds
Started Mar 26 02:02:57 PM PDT 24
Finished Mar 26 02:03:05 PM PDT 24
Peak memory 218504 kb
Host smart-c070f3a8-d8d9-4e60-9e67-7209c20ac2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862220531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3862220531
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1414714158
Short name T465
Test name
Test status
Simulation time 8271925704 ps
CPU time 26.01 seconds
Started Mar 26 02:02:58 PM PDT 24
Finished Mar 26 02:03:24 PM PDT 24
Peak memory 220524 kb
Host smart-aad34f2d-5141-450e-b7db-242d7dbfcbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414714158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1414714158
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.892915197
Short name T906
Test name
Test status
Simulation time 30888356 ps
CPU time 1.09 seconds
Started Mar 26 02:02:58 PM PDT 24
Finished Mar 26 02:02:59 PM PDT 24
Peak memory 216508 kb
Host smart-cd92f900-7bdb-4824-8c86-796954b748a9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892915197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.892915197
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3002330685
Short name T588
Test name
Test status
Simulation time 1764964445 ps
CPU time 6.93 seconds
Started Mar 26 02:02:58 PM PDT 24
Finished Mar 26 02:03:05 PM PDT 24
Peak memory 239320 kb
Host smart-c0c78a73-7e17-489c-b1eb-c140ea27c4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002330685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3002330685
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1922504394
Short name T781
Test name
Test status
Simulation time 2882530577 ps
CPU time 6.39 seconds
Started Mar 26 02:02:57 PM PDT 24
Finished Mar 26 02:03:03 PM PDT 24
Peak memory 216532 kb
Host smart-2ee220e4-ee6b-4c95-97bc-cff09e2e1bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922504394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1922504394
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.3190748136
Short name T500
Test name
Test status
Simulation time 42089534 ps
CPU time 0.72 seconds
Started Mar 26 02:02:57 PM PDT 24
Finished Mar 26 02:02:58 PM PDT 24
Peak memory 216072 kb
Host smart-25b7605a-f445-48cd-b9a5-36a9aa299101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190748136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.3190748136
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.29178605
Short name T893
Test name
Test status
Simulation time 95758617 ps
CPU time 3.3 seconds
Started Mar 26 02:02:58 PM PDT 24
Finished Mar 26 02:03:01 PM PDT 24
Peak memory 222720 kb
Host smart-bbf4889f-2561-4d74-baab-e587e9e3ee4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=29178605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direc
t.29178605
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2734195886
Short name T138
Test name
Test status
Simulation time 61012841280 ps
CPU time 170.7 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:06:02 PM PDT 24
Peak memory 273272 kb
Host smart-6723c241-ec08-4561-88bc-ef51de76fdcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734195886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2734195886
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3176491261
Short name T270
Test name
Test status
Simulation time 5117413384 ps
CPU time 13.62 seconds
Started Mar 26 02:02:55 PM PDT 24
Finished Mar 26 02:03:09 PM PDT 24
Peak memory 216184 kb
Host smart-42712610-943a-490d-ad18-775d258c1652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176491261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3176491261
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.745991204
Short name T745
Test name
Test status
Simulation time 2191251472 ps
CPU time 4.84 seconds
Started Mar 26 02:02:58 PM PDT 24
Finished Mar 26 02:03:03 PM PDT 24
Peak memory 216176 kb
Host smart-fa9e2075-2504-4820-ae45-c4ae0472ec1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745991204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.745991204
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3099997532
Short name T826
Test name
Test status
Simulation time 1128193208 ps
CPU time 4.06 seconds
Started Mar 26 02:02:57 PM PDT 24
Finished Mar 26 02:03:01 PM PDT 24
Peak memory 216240 kb
Host smart-c3b52d67-6fe9-4106-9201-0aab13a1951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099997532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3099997532
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.594596792
Short name T356
Test name
Test status
Simulation time 21228077 ps
CPU time 0.74 seconds
Started Mar 26 02:02:59 PM PDT 24
Finished Mar 26 02:03:00 PM PDT 24
Peak memory 205516 kb
Host smart-595ff6de-c859-4354-97aa-821a24332b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594596792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.594596792
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1571243437
Short name T45
Test name
Test status
Simulation time 571955681 ps
CPU time 6.4 seconds
Started Mar 26 02:02:57 PM PDT 24
Finished Mar 26 02:03:04 PM PDT 24
Peak memory 234560 kb
Host smart-db458e9f-a1cd-4ec9-b4cd-5dc4b9d37a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571243437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1571243437
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3661936587
Short name T613
Test name
Test status
Simulation time 11763185 ps
CPU time 0.75 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 205148 kb
Host smart-d34ba6b7-fbf1-42eb-aa3e-39dc115643fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661936587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3661936587
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2603216633
Short name T332
Test name
Test status
Simulation time 560948359 ps
CPU time 3.55 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:15 PM PDT 24
Peak memory 224360 kb
Host smart-c612039e-f447-49b1-ae0c-e10ec2909100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603216633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2603216633
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2094722003
Short name T279
Test name
Test status
Simulation time 16284017 ps
CPU time 0.78 seconds
Started Mar 26 02:03:06 PM PDT 24
Finished Mar 26 02:03:11 PM PDT 24
Peak memory 206480 kb
Host smart-4a50ec0a-488f-45dd-8608-2a1b69434201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094722003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2094722003
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2535110831
Short name T249
Test name
Test status
Simulation time 6449938963 ps
CPU time 24.33 seconds
Started Mar 26 02:03:09 PM PDT 24
Finished Mar 26 02:03:35 PM PDT 24
Peak memory 239004 kb
Host smart-8528d82e-f8e2-42e8-8c18-5e98e6a4b17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535110831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2535110831
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1655058783
Short name T27
Test name
Test status
Simulation time 9952260196 ps
CPU time 25.91 seconds
Started Mar 26 02:03:09 PM PDT 24
Finished Mar 26 02:03:37 PM PDT 24
Peak memory 236288 kb
Host smart-bf59d518-5162-4b29-8dee-80d19fa3aa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655058783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1655058783
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2999913995
Short name T457
Test name
Test status
Simulation time 13099941553 ps
CPU time 34.12 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:45 PM PDT 24
Peak memory 246804 kb
Host smart-23a1e9fb-049e-4e82-8824-d3266056fcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999913995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2999913995
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.282717754
Short name T196
Test name
Test status
Simulation time 1266875510 ps
CPU time 6.57 seconds
Started Mar 26 02:03:09 PM PDT 24
Finished Mar 26 02:03:19 PM PDT 24
Peak memory 224220 kb
Host smart-51418c3e-8090-43a5-8ae4-2c0123baf554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282717754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.282717754
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3394313657
Short name T777
Test name
Test status
Simulation time 7939773100 ps
CPU time 15.58 seconds
Started Mar 26 02:03:10 PM PDT 24
Finished Mar 26 02:03:27 PM PDT 24
Peak memory 229272 kb
Host smart-71fdaac5-67a8-41ac-9e0b-50df738aeb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394313657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3394313657
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3100800565
Short name T400
Test name
Test status
Simulation time 82888113 ps
CPU time 1.15 seconds
Started Mar 26 02:03:06 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 216664 kb
Host smart-e9867b7f-9045-48f8-a1d6-9d96368ee0c9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100800565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3100800565
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3364755080
Short name T894
Test name
Test status
Simulation time 24691313722 ps
CPU time 18.57 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:30 PM PDT 24
Peak memory 224404 kb
Host smart-32c90088-4262-477a-b88b-8b73b646addf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364755080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3364755080
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1702344243
Short name T424
Test name
Test status
Simulation time 58504991650 ps
CPU time 22.26 seconds
Started Mar 26 02:03:10 PM PDT 24
Finished Mar 26 02:03:34 PM PDT 24
Peak memory 220752 kb
Host smart-bf18bfaf-4ae5-4ee7-9d8f-a317f3c259df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702344243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1702344243
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.1966447762
Short name T57
Test name
Test status
Simulation time 33787245 ps
CPU time 0.73 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 215996 kb
Host smart-e93d66e3-8643-48be-809d-235fa052cce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966447762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.1966447762
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.458096372
Short name T461
Test name
Test status
Simulation time 208019812 ps
CPU time 4.26 seconds
Started Mar 26 02:03:09 PM PDT 24
Finished Mar 26 02:03:15 PM PDT 24
Peak memory 222596 kb
Host smart-d1b12f60-5d5b-4e40-8d31-7c030fa24c22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=458096372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.458096372
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2224974322
Short name T978
Test name
Test status
Simulation time 201430003832 ps
CPU time 272.07 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:07:43 PM PDT 24
Peak memory 265732 kb
Host smart-236a2c29-5151-4e0d-a882-040011da5186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224974322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2224974322
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2884644346
Short name T17
Test name
Test status
Simulation time 7010008172 ps
CPU time 36.31 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:47 PM PDT 24
Peak memory 216176 kb
Host smart-32e95686-26a5-4b43-aeb8-0f93f61c3b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884644346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2884644346
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.884843413
Short name T764
Test name
Test status
Simulation time 2900602978 ps
CPU time 10.36 seconds
Started Mar 26 02:03:10 PM PDT 24
Finished Mar 26 02:03:22 PM PDT 24
Peak memory 216116 kb
Host smart-9b5a6c97-dfe1-4ab3-b971-cbd3dad1fc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884843413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.884843413
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1270401365
Short name T578
Test name
Test status
Simulation time 45158746 ps
CPU time 1.51 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 216004 kb
Host smart-399a4977-eead-42e3-9c05-9c69d252534d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270401365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1270401365
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3249606545
Short name T845
Test name
Test status
Simulation time 87046493 ps
CPU time 1.05 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 206520 kb
Host smart-5a85cec3-0135-45de-ba81-a3f864757708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249606545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3249606545
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2474554554
Short name T5
Test name
Test status
Simulation time 913205243 ps
CPU time 5.24 seconds
Started Mar 26 02:03:09 PM PDT 24
Finished Mar 26 02:03:16 PM PDT 24
Peak memory 235364 kb
Host smart-dff71dac-c1b1-40c6-889f-9a140b8de4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474554554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2474554554
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3706164223
Short name T340
Test name
Test status
Simulation time 34422506 ps
CPU time 0.74 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:03:23 PM PDT 24
Peak memory 205176 kb
Host smart-81e66cb6-7e6b-4dc0-9a6b-c3fab0107afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706164223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3706164223
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4046803103
Short name T968
Test name
Test status
Simulation time 2862827078 ps
CPU time 8.34 seconds
Started Mar 26 02:03:10 PM PDT 24
Finished Mar 26 02:03:21 PM PDT 24
Peak memory 233736 kb
Host smart-eaabc8c7-695a-48b3-9cea-3610a7b0a727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046803103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4046803103
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1600097194
Short name T414
Test name
Test status
Simulation time 239889843 ps
CPU time 0.8 seconds
Started Mar 26 02:03:09 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 206156 kb
Host smart-a564f876-bad0-4a71-adb4-d3f60721adef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600097194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1600097194
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2115792089
Short name T817
Test name
Test status
Simulation time 84111005576 ps
CPU time 123.96 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:05:24 PM PDT 24
Peak memory 248996 kb
Host smart-b954d73b-a4d5-4931-9c75-95e6912aacef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115792089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2115792089
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2319762656
Short name T153
Test name
Test status
Simulation time 532705737906 ps
CPU time 379.31 seconds
Started Mar 26 02:03:18 PM PDT 24
Finished Mar 26 02:09:39 PM PDT 24
Peak memory 257316 kb
Host smart-820edc3d-f6e9-43a8-b50d-331b56927b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319762656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2319762656
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2106356710
Short name T31
Test name
Test status
Simulation time 51423505855 ps
CPU time 62.16 seconds
Started Mar 26 02:03:24 PM PDT 24
Finished Mar 26 02:04:26 PM PDT 24
Peak memory 237500 kb
Host smart-bf8aa1f3-d70a-4357-b0c2-b072a1dba802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106356710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2106356710
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2493516226
Short name T901
Test name
Test status
Simulation time 20225033725 ps
CPU time 46.46 seconds
Started Mar 26 02:03:06 PM PDT 24
Finished Mar 26 02:03:57 PM PDT 24
Peak memory 236140 kb
Host smart-83093a61-fe96-4084-9ada-8c48025fcde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493516226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2493516226
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1780815497
Short name T858
Test name
Test status
Simulation time 887192302 ps
CPU time 3.67 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:15 PM PDT 24
Peak memory 233620 kb
Host smart-f82be03b-a6ee-498c-99a0-4397ffa1dd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780815497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1780815497
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1363070162
Short name T503
Test name
Test status
Simulation time 726197948 ps
CPU time 6.18 seconds
Started Mar 26 02:03:09 PM PDT 24
Finished Mar 26 02:03:17 PM PDT 24
Peak memory 230920 kb
Host smart-c57504eb-a5f6-4c47-9277-614b7274b0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363070162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1363070162
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.4266566775
Short name T22
Test name
Test status
Simulation time 154998266 ps
CPU time 1.01 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 217724 kb
Host smart-5e803c52-e473-4129-b350-093e95239014
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266566775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.4266566775
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3581726553
Short name T263
Test name
Test status
Simulation time 716104726 ps
CPU time 5.3 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:16 PM PDT 24
Peak memory 228252 kb
Host smart-da14152a-bfa3-46c8-bdca-9f52bcf14300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581726553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3581726553
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.629746967
Short name T990
Test name
Test status
Simulation time 4295849585 ps
CPU time 16.09 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:27 PM PDT 24
Peak memory 245348 kb
Host smart-938e8122-c15f-40c6-9db3-a168e085dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629746967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.629746967
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.1376688565
Short name T988
Test name
Test status
Simulation time 39276545 ps
CPU time 0.74 seconds
Started Mar 26 02:03:07 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 216012 kb
Host smart-4260a605-b751-4873-85aa-c778b3debb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376688565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.1376688565
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1205212065
Short name T564
Test name
Test status
Simulation time 2178826831 ps
CPU time 4.51 seconds
Started Mar 26 02:03:19 PM PDT 24
Finished Mar 26 02:03:24 PM PDT 24
Peak memory 218652 kb
Host smart-0499cb74-d860-4fb8-a989-a546f3830fd6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1205212065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1205212065
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4058315593
Short name T319
Test name
Test status
Simulation time 66601039 ps
CPU time 1.2 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:03:24 PM PDT 24
Peak memory 206628 kb
Host smart-613b8343-2d79-4851-843f-7db261b52b54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058315593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4058315593
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.77233497
Short name T24
Test name
Test status
Simulation time 3562040536 ps
CPU time 19.66 seconds
Started Mar 26 02:03:09 PM PDT 24
Finished Mar 26 02:03:31 PM PDT 24
Peak memory 216528 kb
Host smart-7f891783-f30e-40f5-9ad0-3d5c4c67f0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77233497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.77233497
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2580106840
Short name T504
Test name
Test status
Simulation time 20114051788 ps
CPU time 20.21 seconds
Started Mar 26 02:03:10 PM PDT 24
Finished Mar 26 02:03:33 PM PDT 24
Peak memory 216072 kb
Host smart-516b42e2-8500-4fb9-ab7c-391fecef9647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580106840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2580106840
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2036926223
Short name T350
Test name
Test status
Simulation time 277994536 ps
CPU time 2.69 seconds
Started Mar 26 02:03:09 PM PDT 24
Finished Mar 26 02:03:14 PM PDT 24
Peak memory 216120 kb
Host smart-81c27bb4-da4f-4191-a8f0-b6c3c4c441d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036926223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2036926223
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3559928448
Short name T393
Test name
Test status
Simulation time 82270127 ps
CPU time 0.99 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:12 PM PDT 24
Peak memory 205568 kb
Host smart-034f168d-e971-4235-82f7-4b9a8ac7fb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559928448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3559928448
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1078349841
Short name T659
Test name
Test status
Simulation time 6027541928 ps
CPU time 17.13 seconds
Started Mar 26 02:03:08 PM PDT 24
Finished Mar 26 02:03:28 PM PDT 24
Peak memory 247164 kb
Host smart-43a875a1-ad85-4b41-a35c-1341bcaae2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078349841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1078349841
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2373839777
Short name T466
Test name
Test status
Simulation time 44085373 ps
CPU time 0.73 seconds
Started Mar 26 02:03:33 PM PDT 24
Finished Mar 26 02:03:34 PM PDT 24
Peak memory 205148 kb
Host smart-623efe75-2a65-4268-bcfb-c8b4baca6e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373839777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2373839777
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2341117090
Short name T589
Test name
Test status
Simulation time 40261190 ps
CPU time 2.47 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:03:25 PM PDT 24
Peak memory 216640 kb
Host smart-fb6d979c-cf23-4553-ae70-49fe91e46dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341117090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2341117090
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1935781742
Short name T335
Test name
Test status
Simulation time 35684285 ps
CPU time 0.79 seconds
Started Mar 26 02:03:19 PM PDT 24
Finished Mar 26 02:03:20 PM PDT 24
Peak memory 206156 kb
Host smart-5c634954-0551-4aff-b2e5-0f962c826ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935781742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1935781742
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.116546868
Short name T242
Test name
Test status
Simulation time 24614476355 ps
CPU time 96.96 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:04:57 PM PDT 24
Peak memory 253896 kb
Host smart-96e19ff8-d5d5-4b97-868a-55a885743833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116546868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.116546868
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.4073739136
Short name T200
Test name
Test status
Simulation time 132744784026 ps
CPU time 464.51 seconds
Started Mar 26 02:03:33 PM PDT 24
Finished Mar 26 02:11:18 PM PDT 24
Peak memory 265596 kb
Host smart-af1afe0e-708e-4758-821f-8039082d54d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073739136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.4073739136
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3684387938
Short name T668
Test name
Test status
Simulation time 12010738898 ps
CPU time 67.39 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:04:30 PM PDT 24
Peak memory 232600 kb
Host smart-2449c5ec-c293-4395-80ea-c7b0bb14b79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684387938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3684387938
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3390737233
Short name T660
Test name
Test status
Simulation time 11248537967 ps
CPU time 13.59 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:03:36 PM PDT 24
Peak memory 231012 kb
Host smart-206aad81-0c7f-4958-86e0-77f02903774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390737233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3390737233
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.888434374
Short name T669
Test name
Test status
Simulation time 90405575 ps
CPU time 1.08 seconds
Started Mar 26 02:03:21 PM PDT 24
Finished Mar 26 02:03:24 PM PDT 24
Peak memory 217740 kb
Host smart-7e048355-d5c9-465d-83b2-bc2d45ba700c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888434374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.888434374
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2378877207
Short name T883
Test name
Test status
Simulation time 328352186 ps
CPU time 2.96 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:03:25 PM PDT 24
Peak memory 233260 kb
Host smart-ffba859b-1fff-4b82-801a-371f43d14384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378877207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2378877207
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3294849321
Short name T819
Test name
Test status
Simulation time 904528483 ps
CPU time 4.54 seconds
Started Mar 26 02:03:18 PM PDT 24
Finished Mar 26 02:03:24 PM PDT 24
Peak memory 233636 kb
Host smart-8095eff1-f129-4b03-911b-145f15eac5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294849321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3294849321
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3933111438
Short name T495
Test name
Test status
Simulation time 24750936 ps
CPU time 0.74 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:03:23 PM PDT 24
Peak memory 215956 kb
Host smart-3e46cd07-4f4d-4729-8ec8-ebf852b84419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933111438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3933111438
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2417419373
Short name T474
Test name
Test status
Simulation time 660232367 ps
CPU time 5.25 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:03:25 PM PDT 24
Peak memory 222596 kb
Host smart-9d350d79-2eb5-4333-83b9-ebb02efa29a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2417419373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2417419373
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2520522056
Short name T170
Test name
Test status
Simulation time 15431939248 ps
CPU time 115.48 seconds
Started Mar 26 02:03:33 PM PDT 24
Finished Mar 26 02:05:29 PM PDT 24
Peak memory 251240 kb
Host smart-7df91780-bed8-405a-a617-d00b00afb73c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520522056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2520522056
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1146550086
Short name T460
Test name
Test status
Simulation time 7148350282 ps
CPU time 30.77 seconds
Started Mar 26 02:03:18 PM PDT 24
Finished Mar 26 02:03:50 PM PDT 24
Peak memory 216272 kb
Host smart-3647a17e-c50b-423e-9f09-0f882a938819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146550086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1146550086
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2033113361
Short name T388
Test name
Test status
Simulation time 13205709681 ps
CPU time 20.84 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:03:41 PM PDT 24
Peak memory 216200 kb
Host smart-81657d5e-82c0-4cae-9066-de2754e1cded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033113361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2033113361
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2633617334
Short name T632
Test name
Test status
Simulation time 1189057574 ps
CPU time 2.75 seconds
Started Mar 26 02:03:17 PM PDT 24
Finished Mar 26 02:03:20 PM PDT 24
Peak memory 216056 kb
Host smart-127d9f3a-143d-4875-b30e-787a77b98ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633617334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2633617334
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3365640781
Short name T349
Test name
Test status
Simulation time 329617041 ps
CPU time 0.96 seconds
Started Mar 26 02:03:21 PM PDT 24
Finished Mar 26 02:03:23 PM PDT 24
Peak memory 205544 kb
Host smart-5ce32e09-82e5-4a46-9d33-0a5d879ec08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365640781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3365640781
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.718860694
Short name T664
Test name
Test status
Simulation time 1742273496 ps
CPU time 5.12 seconds
Started Mar 26 02:03:20 PM PDT 24
Finished Mar 26 02:03:25 PM PDT 24
Peak memory 235272 kb
Host smart-9117c36b-e1ee-4f82-8283-1b15ff2b61da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718860694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.718860694
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2406501290
Short name T712
Test name
Test status
Simulation time 23288844 ps
CPU time 0.73 seconds
Started Mar 26 02:01:05 PM PDT 24
Finished Mar 26 02:01:06 PM PDT 24
Peak memory 204528 kb
Host smart-6473dbaa-582a-4918-b6f0-aac9267207bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406501290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
406501290
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3004685760
Short name T676
Test name
Test status
Simulation time 267871512 ps
CPU time 4 seconds
Started Mar 26 02:01:05 PM PDT 24
Finished Mar 26 02:01:09 PM PDT 24
Peak memory 218336 kb
Host smart-d72b7740-8ee8-4773-84ed-e58e9ddd43e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004685760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3004685760
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3627343634
Short name T470
Test name
Test status
Simulation time 42296897 ps
CPU time 0.76 seconds
Started Mar 26 02:01:04 PM PDT 24
Finished Mar 26 02:01:05 PM PDT 24
Peak memory 205152 kb
Host smart-cf26a5bb-11a7-40e6-8680-66667d1f1612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627343634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3627343634
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.271014417
Short name T171
Test name
Test status
Simulation time 17157003672 ps
CPU time 46.95 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:49 PM PDT 24
Peak memory 249016 kb
Host smart-49c5d2e3-2cfc-4853-833f-8c14314cbf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271014417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.271014417
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3001480107
Short name T412
Test name
Test status
Simulation time 71383322292 ps
CPU time 176.54 seconds
Started Mar 26 02:01:00 PM PDT 24
Finished Mar 26 02:03:56 PM PDT 24
Peak memory 262692 kb
Host smart-f8e75574-4508-48f2-b50f-356dc6824481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001480107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3001480107
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3819263594
Short name T111
Test name
Test status
Simulation time 4399287169 ps
CPU time 20.62 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:23 PM PDT 24
Peak memory 239384 kb
Host smart-5d71ae72-1e16-4aea-ab47-263c866a341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819263594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3819263594
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2480484624
Short name T119
Test name
Test status
Simulation time 1340370253 ps
CPU time 18.94 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:21 PM PDT 24
Peak memory 236096 kb
Host smart-9fc59a94-bbf5-4052-9ba7-bf16b9d614b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480484624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2480484624
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1443237175
Short name T432
Test name
Test status
Simulation time 899537005 ps
CPU time 3.76 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:06 PM PDT 24
Peak memory 233552 kb
Host smart-bd914c5f-2c01-449b-b3f7-c7fc78576674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443237175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1443237175
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3068220053
Short name T992
Test name
Test status
Simulation time 1926287730 ps
CPU time 12.74 seconds
Started Mar 26 02:01:01 PM PDT 24
Finished Mar 26 02:01:14 PM PDT 24
Peak memory 233756 kb
Host smart-2338b50f-9d49-4c1d-b7bd-b2fc4fe678de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068220053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3068220053
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.4173962531
Short name T489
Test name
Test status
Simulation time 30286046 ps
CPU time 1.06 seconds
Started Mar 26 02:01:04 PM PDT 24
Finished Mar 26 02:01:05 PM PDT 24
Peak memory 217656 kb
Host smart-7a7f1e45-ac05-4d99-9f7f-a19fe03f692e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173962531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.4173962531
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.289558593
Short name T683
Test name
Test status
Simulation time 1850087668 ps
CPU time 8.04 seconds
Started Mar 26 02:01:01 PM PDT 24
Finished Mar 26 02:01:10 PM PDT 24
Peak memory 218324 kb
Host smart-009080dd-d3b5-4bf3-a008-a79ec4d657b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289558593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
289558593
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2342169057
Short name T915
Test name
Test status
Simulation time 65482054295 ps
CPU time 16.8 seconds
Started Mar 26 02:01:03 PM PDT 24
Finished Mar 26 02:01:20 PM PDT 24
Peak memory 235624 kb
Host smart-a04ce099-aba4-4afa-8156-dffe2bfb0f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342169057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2342169057
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2410080246
Short name T840
Test name
Test status
Simulation time 43721471 ps
CPU time 0.74 seconds
Started Mar 26 02:01:04 PM PDT 24
Finished Mar 26 02:01:05 PM PDT 24
Peak memory 216088 kb
Host smart-7357361d-8db9-4cce-9a1c-b5e4b069b9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410080246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2410080246
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.218410687
Short name T798
Test name
Test status
Simulation time 66204698 ps
CPU time 3.23 seconds
Started Mar 26 02:01:04 PM PDT 24
Finished Mar 26 02:01:08 PM PDT 24
Peak memory 218752 kb
Host smart-e1947c6e-7254-4098-b162-15f4f82fd8e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=218410687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.218410687
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1133483330
Short name T62
Test name
Test status
Simulation time 38866912 ps
CPU time 1.04 seconds
Started Mar 26 02:01:01 PM PDT 24
Finished Mar 26 02:01:03 PM PDT 24
Peak memory 235312 kb
Host smart-f7631eb6-6100-47a1-94e9-bfcab6a36ecb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133483330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1133483330
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3844454361
Short name T516
Test name
Test status
Simulation time 245148001 ps
CPU time 1.16 seconds
Started Mar 26 02:01:04 PM PDT 24
Finished Mar 26 02:01:05 PM PDT 24
Peak memory 206712 kb
Host smart-a75d43d0-1ed8-475f-8959-588d0da9debe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844454361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3844454361
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1227168818
Short name T318
Test name
Test status
Simulation time 1990616502 ps
CPU time 20.38 seconds
Started Mar 26 02:01:08 PM PDT 24
Finished Mar 26 02:01:28 PM PDT 24
Peak memory 216184 kb
Host smart-17a6a6c0-1f0d-4b69-9a41-ea29c1fece72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227168818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1227168818
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1744215289
Short name T372
Test name
Test status
Simulation time 6636694380 ps
CPU time 17.08 seconds
Started Mar 26 02:01:01 PM PDT 24
Finished Mar 26 02:01:19 PM PDT 24
Peak memory 216200 kb
Host smart-d4a3b335-1216-4b4d-93c3-9f9ae7c4710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744215289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1744215289
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.682716301
Short name T556
Test name
Test status
Simulation time 44182515 ps
CPU time 1.35 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:04 PM PDT 24
Peak memory 216132 kb
Host smart-081c4b3e-5385-45ca-91f1-0229831d7822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682716301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.682716301
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3640768082
Short name T530
Test name
Test status
Simulation time 22589148 ps
CPU time 0.77 seconds
Started Mar 26 02:01:04 PM PDT 24
Finished Mar 26 02:01:05 PM PDT 24
Peak memory 205412 kb
Host smart-2281ae5d-f321-4148-a758-296b48d0d5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640768082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3640768082
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1227607289
Short name T723
Test name
Test status
Simulation time 1590721678 ps
CPU time 7.59 seconds
Started Mar 26 02:01:06 PM PDT 24
Finished Mar 26 02:01:13 PM PDT 24
Peak memory 232620 kb
Host smart-ddf5211e-cb04-442c-848e-bcb2526e663c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227607289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1227607289
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.969593853
Short name T623
Test name
Test status
Simulation time 35468802 ps
CPU time 0.76 seconds
Started Mar 26 02:03:35 PM PDT 24
Finished Mar 26 02:03:36 PM PDT 24
Peak memory 205476 kb
Host smart-031e9120-5e1b-4734-bd52-40129c39d734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969593853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.969593853
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1615810050
Short name T702
Test name
Test status
Simulation time 5492430914 ps
CPU time 16.87 seconds
Started Mar 26 02:03:34 PM PDT 24
Finished Mar 26 02:03:51 PM PDT 24
Peak memory 221908 kb
Host smart-0699e643-3eb0-4374-8a20-acb61edc2153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615810050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1615810050
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.428123925
Short name T865
Test name
Test status
Simulation time 26033279 ps
CPU time 0.78 seconds
Started Mar 26 02:03:33 PM PDT 24
Finished Mar 26 02:03:34 PM PDT 24
Peak memory 205548 kb
Host smart-b1af6e26-4e6a-4e45-83a3-ddae15b6cedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428123925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.428123925
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3005453488
Short name T846
Test name
Test status
Simulation time 47858189440 ps
CPU time 73.55 seconds
Started Mar 26 02:03:31 PM PDT 24
Finished Mar 26 02:04:45 PM PDT 24
Peak memory 235988 kb
Host smart-d0816a56-1fcb-4671-8253-c0978327c1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005453488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3005453488
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3205778340
Short name T199
Test name
Test status
Simulation time 6879282818 ps
CPU time 37.6 seconds
Started Mar 26 02:03:34 PM PDT 24
Finished Mar 26 02:04:12 PM PDT 24
Peak memory 224280 kb
Host smart-ec9b2373-69f9-4577-aa6c-bd777940ca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205778340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3205778340
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4198573961
Short name T507
Test name
Test status
Simulation time 4810809842 ps
CPU time 9.07 seconds
Started Mar 26 02:03:34 PM PDT 24
Finished Mar 26 02:03:43 PM PDT 24
Peak memory 234044 kb
Host smart-372e41f5-f8af-4c60-853d-2a461e157a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198573961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4198573961
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2564955563
Short name T211
Test name
Test status
Simulation time 158206497 ps
CPU time 2.62 seconds
Started Mar 26 02:03:32 PM PDT 24
Finished Mar 26 02:03:36 PM PDT 24
Peak memory 232584 kb
Host smart-9b95a05a-65b6-4264-bd9e-bf8e02b8c6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564955563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2564955563
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.972860689
Short name T222
Test name
Test status
Simulation time 8881718344 ps
CPU time 7.08 seconds
Started Mar 26 02:03:32 PM PDT 24
Finished Mar 26 02:03:40 PM PDT 24
Peak memory 232896 kb
Host smart-1cf2ece9-4b81-47f5-8bc8-2faa7b50f6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972860689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.972860689
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.357748770
Short name T169
Test name
Test status
Simulation time 5357084330 ps
CPU time 16.03 seconds
Started Mar 26 02:03:32 PM PDT 24
Finished Mar 26 02:03:49 PM PDT 24
Peak memory 224460 kb
Host smart-74e53711-64aa-4bb9-af67-510046869094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357748770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.357748770
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.332559715
Short name T930
Test name
Test status
Simulation time 279503673 ps
CPU time 3.73 seconds
Started Mar 26 02:03:33 PM PDT 24
Finished Mar 26 02:03:37 PM PDT 24
Peak memory 220312 kb
Host smart-1609861e-6d46-4b6b-8026-819732675d29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=332559715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.332559715
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2466129103
Short name T241
Test name
Test status
Simulation time 150689736139 ps
CPU time 204.6 seconds
Started Mar 26 02:03:34 PM PDT 24
Finished Mar 26 02:06:58 PM PDT 24
Peak memory 273580 kb
Host smart-775aa85b-8fac-49ef-b8d3-08656bf125f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466129103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2466129103
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1021052091
Short name T665
Test name
Test status
Simulation time 25956296354 ps
CPU time 69.51 seconds
Started Mar 26 02:03:33 PM PDT 24
Finished Mar 26 02:04:43 PM PDT 24
Peak memory 216120 kb
Host smart-8e0069b5-5620-4d5b-871f-240425a363ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021052091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1021052091
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.395250209
Short name T654
Test name
Test status
Simulation time 16614245778 ps
CPU time 17.62 seconds
Started Mar 26 02:03:33 PM PDT 24
Finished Mar 26 02:03:51 PM PDT 24
Peak memory 216248 kb
Host smart-392aae8d-3799-49a7-858b-4f08c95e3e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395250209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.395250209
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2501163311
Short name T301
Test name
Test status
Simulation time 318436458 ps
CPU time 3.13 seconds
Started Mar 26 02:03:34 PM PDT 24
Finished Mar 26 02:03:37 PM PDT 24
Peak memory 216192 kb
Host smart-01fcd777-13b7-4454-a874-924e9572fef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501163311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2501163311
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3608057811
Short name T77
Test name
Test status
Simulation time 80178944 ps
CPU time 1 seconds
Started Mar 26 02:03:32 PM PDT 24
Finished Mar 26 02:03:34 PM PDT 24
Peak memory 205464 kb
Host smart-dd5f8906-4b90-440b-a8af-f3e90ebd7e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608057811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3608057811
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1777728566
Short name T604
Test name
Test status
Simulation time 192414652 ps
CPU time 3.2 seconds
Started Mar 26 02:03:32 PM PDT 24
Finished Mar 26 02:03:35 PM PDT 24
Peak memory 232548 kb
Host smart-1f5ecdbb-b04f-40b2-b2f9-1e536d780280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777728566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1777728566
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3457841836
Short name T436
Test name
Test status
Simulation time 65921784 ps
CPU time 0.75 seconds
Started Mar 26 02:03:46 PM PDT 24
Finished Mar 26 02:03:46 PM PDT 24
Peak memory 205364 kb
Host smart-72c4717b-ac95-488d-b8d8-6d1522cd30f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457841836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3457841836
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1753379178
Short name T658
Test name
Test status
Simulation time 1016939122 ps
CPU time 6.88 seconds
Started Mar 26 02:03:50 PM PDT 24
Finished Mar 26 02:03:57 PM PDT 24
Peak memory 233068 kb
Host smart-33c5e7e0-bb1b-4cb8-852a-e930d13fdc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753379178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1753379178
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.546881213
Short name T423
Test name
Test status
Simulation time 58099291 ps
CPU time 0.79 seconds
Started Mar 26 02:03:31 PM PDT 24
Finished Mar 26 02:03:32 PM PDT 24
Peak memory 206248 kb
Host smart-8f601a87-6c73-457d-975c-847b20004cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546881213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.546881213
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2549881262
Short name T899
Test name
Test status
Simulation time 110990515661 ps
CPU time 160.2 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:06:28 PM PDT 24
Peak memory 250004 kb
Host smart-764eb77f-3392-4f72-b9bb-45bd5eb10d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549881262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2549881262
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.172492405
Short name T769
Test name
Test status
Simulation time 37325394506 ps
CPU time 42.51 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:04:30 PM PDT 24
Peak memory 250084 kb
Host smart-ec35a7a7-e787-4aa6-b87f-51fbcba2b20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172492405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.172492405
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.716099680
Short name T638
Test name
Test status
Simulation time 2115051814 ps
CPU time 6.15 seconds
Started Mar 26 02:03:33 PM PDT 24
Finished Mar 26 02:03:39 PM PDT 24
Peak memory 233660 kb
Host smart-26282770-636a-4daf-980f-7e7a1ffd3314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716099680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.716099680
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1018637607
Short name T524
Test name
Test status
Simulation time 4914330739 ps
CPU time 8.86 seconds
Started Mar 26 02:03:34 PM PDT 24
Finished Mar 26 02:03:43 PM PDT 24
Peak memory 240812 kb
Host smart-ea5ef776-f6ca-4ed4-9960-5833039e5e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018637607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1018637607
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.505593822
Short name T688
Test name
Test status
Simulation time 2099835075 ps
CPU time 9.2 seconds
Started Mar 26 02:03:34 PM PDT 24
Finished Mar 26 02:03:43 PM PDT 24
Peak memory 237408 kb
Host smart-a293aa1b-8946-4be7-8e72-309267c224c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505593822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.505593822
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2472176897
Short name T891
Test name
Test status
Simulation time 21878479498 ps
CPU time 17.96 seconds
Started Mar 26 02:03:34 PM PDT 24
Finished Mar 26 02:03:52 PM PDT 24
Peak memory 218536 kb
Host smart-fc8534df-dca2-4f09-bcd5-17156c86a002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472176897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2472176897
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3324720465
Short name T124
Test name
Test status
Simulation time 1165565636 ps
CPU time 4.88 seconds
Started Mar 26 02:03:46 PM PDT 24
Finished Mar 26 02:03:51 PM PDT 24
Peak memory 218800 kb
Host smart-55926c63-23c0-4712-81a2-2621f9571c85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3324720465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3324720465
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.576786180
Short name T254
Test name
Test status
Simulation time 26955443561 ps
CPU time 300.5 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:08:48 PM PDT 24
Peak memory 298152 kb
Host smart-3b80a996-e419-4397-bec7-a4e20f33026d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576786180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.576786180
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1747425218
Short name T696
Test name
Test status
Simulation time 8487124936 ps
CPU time 12.72 seconds
Started Mar 26 02:03:33 PM PDT 24
Finished Mar 26 02:03:46 PM PDT 24
Peak memory 216228 kb
Host smart-c2d43859-7f1c-4e1c-ba2f-e91bbe45ccf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747425218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1747425218
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2748054971
Short name T459
Test name
Test status
Simulation time 2384622488 ps
CPU time 5.32 seconds
Started Mar 26 02:03:32 PM PDT 24
Finished Mar 26 02:03:39 PM PDT 24
Peak memory 216168 kb
Host smart-c747d357-17e0-42a9-9a9a-8a9f6509cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748054971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2748054971
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1790022300
Short name T582
Test name
Test status
Simulation time 430966230 ps
CPU time 4.38 seconds
Started Mar 26 02:03:31 PM PDT 24
Finished Mar 26 02:03:36 PM PDT 24
Peak memory 216028 kb
Host smart-5109bc08-441b-457f-81cb-6493b7b20531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790022300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1790022300
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3456475804
Short name T742
Test name
Test status
Simulation time 32761745 ps
CPU time 0.91 seconds
Started Mar 26 02:03:35 PM PDT 24
Finished Mar 26 02:03:36 PM PDT 24
Peak memory 205800 kb
Host smart-ba9e09f8-2fe0-4b4d-b146-8dda84c2d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456475804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3456475804
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.769135378
Short name T916
Test name
Test status
Simulation time 208189502 ps
CPU time 4.53 seconds
Started Mar 26 02:03:32 PM PDT 24
Finished Mar 26 02:03:36 PM PDT 24
Peak memory 233948 kb
Host smart-3052356a-5e27-49e6-bc34-5f4b71a57a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769135378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.769135378
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.541371091
Short name T304
Test name
Test status
Simulation time 13554524 ps
CPU time 0.75 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:03:49 PM PDT 24
Peak memory 205152 kb
Host smart-241e3b82-6367-4909-98bf-50c6e195b2a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541371091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.541371091
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.4145143760
Short name T65
Test name
Test status
Simulation time 605970136 ps
CPU time 4.63 seconds
Started Mar 26 02:03:46 PM PDT 24
Finished Mar 26 02:03:50 PM PDT 24
Peak memory 232716 kb
Host smart-de459ddb-1154-4217-8603-41e3cb255a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145143760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4145143760
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.618485107
Short name T296
Test name
Test status
Simulation time 30615605 ps
CPU time 0.74 seconds
Started Mar 26 02:03:50 PM PDT 24
Finished Mar 26 02:03:51 PM PDT 24
Peak memory 205136 kb
Host smart-63feb8d2-e620-4ae7-b9b7-72a5880eb018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618485107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.618485107
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2615361063
Short name T963
Test name
Test status
Simulation time 6524634038 ps
CPU time 19.55 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:04:08 PM PDT 24
Peak memory 240856 kb
Host smart-e35f6ce1-9328-4c5d-8b24-8f0790e576ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615361063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2615361063
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1301781788
Short name T731
Test name
Test status
Simulation time 10652514010 ps
CPU time 87.26 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:05:14 PM PDT 24
Peak memory 251672 kb
Host smart-de50579b-71d1-494f-9333-b04006759547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301781788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1301781788
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1412162492
Short name T808
Test name
Test status
Simulation time 11293522817 ps
CPU time 19.96 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:04:08 PM PDT 24
Peak memory 238384 kb
Host smart-cb6290e2-5282-4273-935b-ef9e1c098820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412162492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1412162492
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1619920957
Short name T509
Test name
Test status
Simulation time 426279827 ps
CPU time 2.84 seconds
Started Mar 26 02:03:49 PM PDT 24
Finished Mar 26 02:03:51 PM PDT 24
Peak memory 217396 kb
Host smart-3877139f-facc-4d7b-961f-0802cf666002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619920957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1619920957
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2058294605
Short name T770
Test name
Test status
Simulation time 841802030 ps
CPU time 2.55 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:03:51 PM PDT 24
Peak memory 218332 kb
Host smart-e9a7e6d9-4ea9-495c-9d6d-bccf7955649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058294605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2058294605
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1913138924
Short name T244
Test name
Test status
Simulation time 3608200154 ps
CPU time 10.28 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:03:58 PM PDT 24
Peak memory 224384 kb
Host smart-326512be-8182-491c-b441-009f26100c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913138924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1913138924
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1554092979
Short name T940
Test name
Test status
Simulation time 11454801843 ps
CPU time 24.23 seconds
Started Mar 26 02:03:49 PM PDT 24
Finished Mar 26 02:04:13 PM PDT 24
Peak memory 232668 kb
Host smart-15bb429d-2ec7-4c52-a253-d02656992aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554092979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1554092979
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2612847656
Short name T820
Test name
Test status
Simulation time 27509390661 ps
CPU time 6.91 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:03:55 PM PDT 24
Peak memory 222788 kb
Host smart-d38a5c74-a231-4ec0-b3ca-32a04334be52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2612847656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2612847656
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1472453527
Short name T116
Test name
Test status
Simulation time 6920980937 ps
CPU time 69.81 seconds
Started Mar 26 02:03:46 PM PDT 24
Finished Mar 26 02:04:55 PM PDT 24
Peak memory 253880 kb
Host smart-5f010162-7013-4685-82e0-3a494c5681b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472453527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1472453527
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4017355838
Short name T936
Test name
Test status
Simulation time 2888388622 ps
CPU time 15.43 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:04:04 PM PDT 24
Peak memory 216284 kb
Host smart-f2084912-d8f0-4439-be89-d8eb13d18d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017355838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4017355838
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1470072279
Short name T452
Test name
Test status
Simulation time 1478369111 ps
CPU time 2.34 seconds
Started Mar 26 02:03:45 PM PDT 24
Finished Mar 26 02:03:47 PM PDT 24
Peak memory 207776 kb
Host smart-74bd8037-6c89-41a8-9c70-72a095436340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470072279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1470072279
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2884982312
Short name T159
Test name
Test status
Simulation time 18287731 ps
CPU time 1.01 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:03:49 PM PDT 24
Peak memory 206744 kb
Host smart-49db7b1c-e664-4b20-974e-217453413047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884982312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2884982312
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1146745433
Short name T420
Test name
Test status
Simulation time 292849269 ps
CPU time 1 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:03:49 PM PDT 24
Peak memory 205880 kb
Host smart-0ce60b0f-b40e-4442-affe-cf41f7976074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146745433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1146745433
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3975577532
Short name T38
Test name
Test status
Simulation time 558839329 ps
CPU time 6.63 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:03:54 PM PDT 24
Peak memory 233444 kb
Host smart-60076bc2-0fd5-415c-ae59-77babda68686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975577532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3975577532
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.687725015
Short name T435
Test name
Test status
Simulation time 110876416 ps
CPU time 0.78 seconds
Started Mar 26 02:04:03 PM PDT 24
Finished Mar 26 02:04:03 PM PDT 24
Peak memory 205488 kb
Host smart-048d1d1c-5480-4681-befb-e84801ba3e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687725015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.687725015
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3270859247
Short name T473
Test name
Test status
Simulation time 7341654396 ps
CPU time 5.63 seconds
Started Mar 26 02:04:01 PM PDT 24
Finished Mar 26 02:04:07 PM PDT 24
Peak memory 224504 kb
Host smart-8ef0028c-4711-40d0-971b-6bc0a2aa607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270859247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3270859247
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4233562069
Short name T285
Test name
Test status
Simulation time 23164304 ps
CPU time 0.85 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:03:48 PM PDT 24
Peak memory 206260 kb
Host smart-b5ea914e-298e-4128-81b1-cb3c20d0aaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233562069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4233562069
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.861186656
Short name T835
Test name
Test status
Simulation time 27585631454 ps
CPU time 53.65 seconds
Started Mar 26 02:04:00 PM PDT 24
Finished Mar 26 02:04:54 PM PDT 24
Peak memory 239512 kb
Host smart-f76dd5f7-b12b-459f-ab88-96290ca0bcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861186656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.861186656
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.921298252
Short name T156
Test name
Test status
Simulation time 16450719778 ps
CPU time 108.78 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:05:50 PM PDT 24
Peak memory 253404 kb
Host smart-ee8f596f-74d4-4fb2-ba96-f208182272bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921298252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.921298252
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.351260806
Short name T737
Test name
Test status
Simulation time 28355627624 ps
CPU time 44.92 seconds
Started Mar 26 02:04:06 PM PDT 24
Finished Mar 26 02:04:51 PM PDT 24
Peak memory 248948 kb
Host smart-db60f90d-b01f-4ac7-82ee-e2a8f94f2018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351260806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.351260806
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3024252856
Short name T957
Test name
Test status
Simulation time 186211079 ps
CPU time 3.41 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:03:51 PM PDT 24
Peak memory 232640 kb
Host smart-7ada2cf7-7564-4bec-bfdd-69974bd5ebc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024252856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3024252856
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.894019465
Short name T298
Test name
Test status
Simulation time 3075730121 ps
CPU time 13.01 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:04:00 PM PDT 24
Peak memory 256060 kb
Host smart-b3de9eaf-424b-4e5e-8310-c702be31a18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894019465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.894019465
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1661910715
Short name T586
Test name
Test status
Simulation time 3811365985 ps
CPU time 16 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:04:03 PM PDT 24
Peak memory 233052 kb
Host smart-d3c5c6d0-c828-4235-950c-aa6fb007edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661910715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1661910715
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2302704342
Short name T751
Test name
Test status
Simulation time 16897973621 ps
CPU time 19.63 seconds
Started Mar 26 02:03:46 PM PDT 24
Finished Mar 26 02:04:06 PM PDT 24
Peak memory 234360 kb
Host smart-83c4d3f4-e6a2-4834-aeaa-3569e0b453bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302704342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2302704342
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.67904345
Short name T315
Test name
Test status
Simulation time 2510864608 ps
CPU time 6.42 seconds
Started Mar 26 02:04:04 PM PDT 24
Finished Mar 26 02:04:11 PM PDT 24
Peak memory 222300 kb
Host smart-88bf5eb0-db8d-41b2-958e-f0883c12e685
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=67904345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direc
t.67904345
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.9747439
Short name T358
Test name
Test status
Simulation time 168345038 ps
CPU time 0.98 seconds
Started Mar 26 02:03:59 PM PDT 24
Finished Mar 26 02:04:01 PM PDT 24
Peak memory 206780 kb
Host smart-a2ff8b7e-dab5-4502-80f0-173a463cf08d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9747439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_
all.9747439
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1910586043
Short name T714
Test name
Test status
Simulation time 14989288213 ps
CPU time 25.98 seconds
Started Mar 26 02:03:50 PM PDT 24
Finished Mar 26 02:04:16 PM PDT 24
Peak memory 216124 kb
Host smart-ce0a2c5b-1fd0-4036-9f84-2e3d47ce2a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910586043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1910586043
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1798359271
Short name T825
Test name
Test status
Simulation time 21724017142 ps
CPU time 19.8 seconds
Started Mar 26 02:03:46 PM PDT 24
Finished Mar 26 02:04:06 PM PDT 24
Peak memory 216104 kb
Host smart-050a0a08-2aca-4ff7-89cc-79efe30e4726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798359271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1798359271
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3449085621
Short name T148
Test name
Test status
Simulation time 24506471 ps
CPU time 1.5 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:03:49 PM PDT 24
Peak memory 216016 kb
Host smart-29de6da9-fe04-4805-b732-7fcede1fd783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449085621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3449085621
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3379221973
Short name T571
Test name
Test status
Simulation time 272170973 ps
CPU time 0.96 seconds
Started Mar 26 02:03:47 PM PDT 24
Finished Mar 26 02:03:48 PM PDT 24
Peak memory 206492 kb
Host smart-077172f9-2119-45ce-aac0-884afbb15349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379221973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3379221973
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4042409867
Short name T418
Test name
Test status
Simulation time 1070714906 ps
CPU time 5.94 seconds
Started Mar 26 02:03:48 PM PDT 24
Finished Mar 26 02:03:54 PM PDT 24
Peak memory 218916 kb
Host smart-6280555d-850b-4c9a-9592-8819cdb6121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042409867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4042409867
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2402140020
Short name T328
Test name
Test status
Simulation time 32420879 ps
CPU time 0.75 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:04:03 PM PDT 24
Peak memory 205160 kb
Host smart-12695d21-2c4e-4aeb-a4a7-b9ef9d09001b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402140020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2402140020
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3508874136
Short name T748
Test name
Test status
Simulation time 98216380 ps
CPU time 2.32 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:04:05 PM PDT 24
Peak memory 218284 kb
Host smart-f87308cd-8fea-4459-a289-176ac71067f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508874136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3508874136
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2627047757
Short name T477
Test name
Test status
Simulation time 17150484 ps
CPU time 0.81 seconds
Started Mar 26 02:04:03 PM PDT 24
Finished Mar 26 02:04:04 PM PDT 24
Peak memory 205184 kb
Host smart-86d3582a-7795-4b2c-9f7c-bf51c75d4e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627047757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2627047757
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.296980192
Short name T147
Test name
Test status
Simulation time 30792983586 ps
CPU time 74.26 seconds
Started Mar 26 02:04:00 PM PDT 24
Finished Mar 26 02:05:14 PM PDT 24
Peak memory 251040 kb
Host smart-823d77f1-72c3-4396-a184-8b441c0d327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296980192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.296980192
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1933017237
Short name T239
Test name
Test status
Simulation time 82817024464 ps
CPU time 630.21 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:14:33 PM PDT 24
Peak memory 267244 kb
Host smart-9c297312-0ae7-45d9-86ad-2c6ae51371dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933017237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1933017237
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2014026777
Short name T154
Test name
Test status
Simulation time 8425014000 ps
CPU time 27.08 seconds
Started Mar 26 02:04:01 PM PDT 24
Finished Mar 26 02:04:28 PM PDT 24
Peak memory 232960 kb
Host smart-ac6777d6-4184-477c-b10d-b540ad2a08a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014026777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2014026777
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3417596494
Short name T546
Test name
Test status
Simulation time 10706580296 ps
CPU time 55.16 seconds
Started Mar 26 02:04:01 PM PDT 24
Finished Mar 26 02:04:56 PM PDT 24
Peak memory 249016 kb
Host smart-c0bdbed3-8f12-41d5-af08-cb1b3b150681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417596494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3417596494
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3679618401
Short name T964
Test name
Test status
Simulation time 320194334 ps
CPU time 4.28 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:04:06 PM PDT 24
Peak memory 234080 kb
Host smart-38d24767-8139-474d-ab76-033e6e7a3d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679618401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3679618401
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3996695787
Short name T928
Test name
Test status
Simulation time 7994815690 ps
CPU time 21.44 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:04:24 PM PDT 24
Peak memory 235420 kb
Host smart-ab7d5737-92f5-4a65-af9b-a1f6edcd000e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996695787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3996695787
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.57148119
Short name T371
Test name
Test status
Simulation time 40480227606 ps
CPU time 14.74 seconds
Started Mar 26 02:04:01 PM PDT 24
Finished Mar 26 02:04:16 PM PDT 24
Peak memory 224432 kb
Host smart-f3a32d36-8d08-4c47-9a69-9c85c650a841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57148119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.57148119
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2779796417
Short name T209
Test name
Test status
Simulation time 10959947784 ps
CPU time 33.11 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:04:35 PM PDT 24
Peak memory 232576 kb
Host smart-3581c0fd-0c68-4a2f-a3c4-02997143bec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779796417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2779796417
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2800068874
Short name T650
Test name
Test status
Simulation time 337948612 ps
CPU time 3.59 seconds
Started Mar 26 02:04:01 PM PDT 24
Finished Mar 26 02:04:05 PM PDT 24
Peak memory 222552 kb
Host smart-d9474a8e-7bc3-4d4b-8ab1-fb73352cd1bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2800068874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2800068874
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3930573048
Short name T520
Test name
Test status
Simulation time 221649831 ps
CPU time 0.94 seconds
Started Mar 26 02:04:01 PM PDT 24
Finished Mar 26 02:04:02 PM PDT 24
Peak memory 206256 kb
Host smart-476b4d37-ca8f-4cc7-accc-8fbb8516f272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930573048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3930573048
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.221063621
Short name T887
Test name
Test status
Simulation time 646651280 ps
CPU time 7.77 seconds
Started Mar 26 02:04:00 PM PDT 24
Finished Mar 26 02:04:08 PM PDT 24
Peak memory 216012 kb
Host smart-fc61dd22-a3a7-4356-9601-56ed7aaf724b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221063621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.221063621
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1946498866
Short name T705
Test name
Test status
Simulation time 9589302320 ps
CPU time 26.49 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:04:28 PM PDT 24
Peak memory 216236 kb
Host smart-51dc34f7-822b-4f5c-b5f3-8f437032dc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946498866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1946498866
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2612191177
Short name T873
Test name
Test status
Simulation time 856967471 ps
CPU time 2.86 seconds
Started Mar 26 02:04:07 PM PDT 24
Finished Mar 26 02:04:10 PM PDT 24
Peak memory 216252 kb
Host smart-653ebcbd-1c55-4525-8331-2c78284c0924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612191177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2612191177
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1028411638
Short name T297
Test name
Test status
Simulation time 98444102 ps
CPU time 1 seconds
Started Mar 26 02:04:03 PM PDT 24
Finished Mar 26 02:04:04 PM PDT 24
Peak memory 205564 kb
Host smart-c721904f-9aca-4541-b5bf-1503161f39d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028411638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1028411638
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1120334498
Short name T210
Test name
Test status
Simulation time 53473503181 ps
CPU time 38.51 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:04:40 PM PDT 24
Peak memory 224328 kb
Host smart-d16016d1-683d-4991-bd6d-c42e5078c3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120334498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1120334498
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.761225977
Short name T810
Test name
Test status
Simulation time 37156956 ps
CPU time 0.73 seconds
Started Mar 26 02:04:13 PM PDT 24
Finished Mar 26 02:04:14 PM PDT 24
Peak memory 205172 kb
Host smart-bf6764e1-3ba1-4dd4-ba20-a959d004ea88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761225977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.761225977
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.673808917
Short name T487
Test name
Test status
Simulation time 4098422144 ps
CPU time 5.7 seconds
Started Mar 26 02:04:14 PM PDT 24
Finished Mar 26 02:04:20 PM PDT 24
Peak memory 224388 kb
Host smart-f50795de-0168-4d56-8ffb-5b31a8097b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673808917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.673808917
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1762096691
Short name T3
Test name
Test status
Simulation time 36464400 ps
CPU time 0.79 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:04:03 PM PDT 24
Peak memory 206544 kb
Host smart-8e44a4c5-8841-411a-b237-42cbdb01cb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762096691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1762096691
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2534396109
Short name T441
Test name
Test status
Simulation time 1683585667 ps
CPU time 11.77 seconds
Started Mar 26 02:04:15 PM PDT 24
Finished Mar 26 02:04:27 PM PDT 24
Peak memory 219236 kb
Host smart-22a21050-210d-4ae5-b2c1-85d9f4bd8e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534396109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2534396109
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3553814407
Short name T355
Test name
Test status
Simulation time 7743146206 ps
CPU time 101.24 seconds
Started Mar 26 02:04:11 PM PDT 24
Finished Mar 26 02:05:54 PM PDT 24
Peak memory 249012 kb
Host smart-82895d8a-5c9f-4998-98ba-79e39475ff85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553814407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3553814407
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1207321326
Short name T864
Test name
Test status
Simulation time 33943567300 ps
CPU time 157.62 seconds
Started Mar 26 02:04:18 PM PDT 24
Finished Mar 26 02:06:56 PM PDT 24
Peak memory 255492 kb
Host smart-26585af6-d517-4721-aa6b-11ebc4f3aa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207321326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1207321326
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2461675514
Short name T510
Test name
Test status
Simulation time 5702597429 ps
CPU time 35.53 seconds
Started Mar 26 02:04:11 PM PDT 24
Finished Mar 26 02:04:48 PM PDT 24
Peak memory 240620 kb
Host smart-aa8e003f-9caa-480b-905c-bf2a79f63cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461675514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2461675514
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2158589361
Short name T594
Test name
Test status
Simulation time 2614425171 ps
CPU time 9.46 seconds
Started Mar 26 02:04:12 PM PDT 24
Finished Mar 26 02:04:22 PM PDT 24
Peak memory 233508 kb
Host smart-03bd20d9-3fac-4485-bc8d-789bdb7c213e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158589361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2158589361
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1187579414
Short name T125
Test name
Test status
Simulation time 49981880182 ps
CPU time 44.51 seconds
Started Mar 26 02:04:15 PM PDT 24
Finished Mar 26 02:05:00 PM PDT 24
Peak memory 248828 kb
Host smart-e7221521-5e58-4fa1-bcf0-7b89997a5caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187579414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1187579414
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2678343565
Short name T220
Test name
Test status
Simulation time 20691122221 ps
CPU time 35.72 seconds
Started Mar 26 02:04:05 PM PDT 24
Finished Mar 26 02:04:41 PM PDT 24
Peak memory 237848 kb
Host smart-4489a49f-0726-484e-8821-2a760d1bad67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678343565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2678343565
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2043474622
Short name T48
Test name
Test status
Simulation time 11394446532 ps
CPU time 31.06 seconds
Started Mar 26 02:04:03 PM PDT 24
Finished Mar 26 02:04:34 PM PDT 24
Peak memory 240664 kb
Host smart-b47e1784-d7a1-44da-9932-a0c14302ef67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043474622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2043474622
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.453160864
Short name T600
Test name
Test status
Simulation time 624596835 ps
CPU time 4.22 seconds
Started Mar 26 02:04:12 PM PDT 24
Finished Mar 26 02:04:18 PM PDT 24
Peak memory 218880 kb
Host smart-dbae00e5-2d46-400c-917a-c849dbd02251
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=453160864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.453160864
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.977786096
Short name T761
Test name
Test status
Simulation time 4121304289 ps
CPU time 24.04 seconds
Started Mar 26 02:04:00 PM PDT 24
Finished Mar 26 02:04:24 PM PDT 24
Peak memory 216428 kb
Host smart-15a26d20-775b-4b4e-a603-2d85f57863ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977786096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.977786096
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1866036514
Short name T353
Test name
Test status
Simulation time 8425954094 ps
CPU time 11.11 seconds
Started Mar 26 02:04:00 PM PDT 24
Finished Mar 26 02:04:11 PM PDT 24
Peak memory 216104 kb
Host smart-acbe48d1-7bc4-4bc3-be82-fa32868da7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866036514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1866036514
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3443578274
Short name T547
Test name
Test status
Simulation time 435767256 ps
CPU time 2.79 seconds
Started Mar 26 02:04:02 PM PDT 24
Finished Mar 26 02:04:05 PM PDT 24
Peak memory 216004 kb
Host smart-6233ea15-f414-45d1-b0fb-849a11cca754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443578274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3443578274
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1450627021
Short name T481
Test name
Test status
Simulation time 463564266 ps
CPU time 1.15 seconds
Started Mar 26 02:04:03 PM PDT 24
Finished Mar 26 02:04:05 PM PDT 24
Peak memory 206564 kb
Host smart-516653ba-812f-42a8-84d0-ee1c5ecc9a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450627021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1450627021
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.995278310
Short name T902
Test name
Test status
Simulation time 3635085383 ps
CPU time 9.91 seconds
Started Mar 26 02:04:13 PM PDT 24
Finished Mar 26 02:04:24 PM PDT 24
Peak memory 226760 kb
Host smart-2b85e7fd-76d2-4d5d-b63f-5718fd43fdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995278310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.995278310
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.758331003
Short name T950
Test name
Test status
Simulation time 30235514 ps
CPU time 0.74 seconds
Started Mar 26 02:04:11 PM PDT 24
Finished Mar 26 02:04:13 PM PDT 24
Peak memory 205112 kb
Host smart-4a60aac3-1d69-47c8-940e-1caa76bafa0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758331003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.758331003
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2275474767
Short name T960
Test name
Test status
Simulation time 371227991 ps
CPU time 3.73 seconds
Started Mar 26 02:04:12 PM PDT 24
Finished Mar 26 02:04:17 PM PDT 24
Peak memory 234544 kb
Host smart-b4237050-d2c3-446e-8e4e-bc716412c645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275474767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2275474767
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3718144122
Short name T908
Test name
Test status
Simulation time 39918879 ps
CPU time 0.74 seconds
Started Mar 26 02:04:14 PM PDT 24
Finished Mar 26 02:04:16 PM PDT 24
Peak memory 205140 kb
Host smart-500dee0a-5360-4ab0-b8a5-cab3187c5363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718144122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3718144122
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2748404285
Short name T646
Test name
Test status
Simulation time 8190719316 ps
CPU time 35.82 seconds
Started Mar 26 02:04:18 PM PDT 24
Finished Mar 26 02:04:54 PM PDT 24
Peak memory 240756 kb
Host smart-89579e80-daac-42bc-9e20-5183bec99f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748404285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2748404285
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.317305077
Short name T240
Test name
Test status
Simulation time 124343907870 ps
CPU time 301.68 seconds
Started Mar 26 02:04:13 PM PDT 24
Finished Mar 26 02:09:16 PM PDT 24
Peak memory 281704 kb
Host smart-f18e3feb-d2d1-4996-a5be-69436667741c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317305077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.317305077
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.502322252
Short name T532
Test name
Test status
Simulation time 2809835333 ps
CPU time 13.28 seconds
Started Mar 26 02:04:11 PM PDT 24
Finished Mar 26 02:04:24 PM PDT 24
Peak memory 240152 kb
Host smart-9f161272-464e-48e7-af76-0207f004ece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502322252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.502322252
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2028159584
Short name T831
Test name
Test status
Simulation time 211676018 ps
CPU time 4.62 seconds
Started Mar 26 02:04:12 PM PDT 24
Finished Mar 26 02:04:18 PM PDT 24
Peak memory 219364 kb
Host smart-88f09de6-8c05-4d94-87da-05b1aa41eeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028159584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2028159584
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3959820960
Short name T183
Test name
Test status
Simulation time 22764667082 ps
CPU time 37.36 seconds
Started Mar 26 02:04:11 PM PDT 24
Finished Mar 26 02:04:48 PM PDT 24
Peak memory 236228 kb
Host smart-29d27015-3b71-4693-9701-edd8a5c1c0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959820960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3959820960
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2108719647
Short name T962
Test name
Test status
Simulation time 4517752295 ps
CPU time 9.41 seconds
Started Mar 26 02:04:12 PM PDT 24
Finished Mar 26 02:04:22 PM PDT 24
Peak memory 237488 kb
Host smart-0a482c6c-ee33-4ece-8685-686f55744163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108719647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2108719647
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3221777415
Short name T598
Test name
Test status
Simulation time 2005689203 ps
CPU time 14.09 seconds
Started Mar 26 02:04:12 PM PDT 24
Finished Mar 26 02:04:27 PM PDT 24
Peak memory 234644 kb
Host smart-3db823ee-e698-4a71-9c1b-6616da60f6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221777415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3221777415
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3029211432
Short name T122
Test name
Test status
Simulation time 495267257 ps
CPU time 4.78 seconds
Started Mar 26 02:04:15 PM PDT 24
Finished Mar 26 02:04:20 PM PDT 24
Peak memory 222592 kb
Host smart-5279f3b1-cae0-42f8-85d5-937e8fcacc8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3029211432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3029211432
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2904821107
Short name T782
Test name
Test status
Simulation time 2820037751 ps
CPU time 28.98 seconds
Started Mar 26 02:04:17 PM PDT 24
Finished Mar 26 02:04:47 PM PDT 24
Peak memory 216072 kb
Host smart-666c7fbd-c09d-416c-af54-8810a02328fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904821107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2904821107
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1935761680
Short name T911
Test name
Test status
Simulation time 2224660188 ps
CPU time 12.89 seconds
Started Mar 26 02:04:17 PM PDT 24
Finished Mar 26 02:04:30 PM PDT 24
Peak memory 216224 kb
Host smart-ae482684-7c14-4ff1-b145-498468350e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935761680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1935761680
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2660279727
Short name T458
Test name
Test status
Simulation time 156001184 ps
CPU time 1.74 seconds
Started Mar 26 02:04:13 PM PDT 24
Finished Mar 26 02:04:15 PM PDT 24
Peak memory 216160 kb
Host smart-f921e6de-375f-4201-89d2-50aebdb2050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660279727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2660279727
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2258337256
Short name T897
Test name
Test status
Simulation time 100476340 ps
CPU time 1.05 seconds
Started Mar 26 02:04:12 PM PDT 24
Finished Mar 26 02:04:14 PM PDT 24
Peak memory 206460 kb
Host smart-1cf0fedf-8591-418e-a36e-231741481b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258337256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2258337256
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2509926871
Short name T549
Test name
Test status
Simulation time 8655062378 ps
CPU time 29.13 seconds
Started Mar 26 02:04:14 PM PDT 24
Finished Mar 26 02:04:44 PM PDT 24
Peak memory 237388 kb
Host smart-362f5c9b-9767-4bc6-b3f2-f125641c4123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509926871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2509926871
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1269018766
Short name T46
Test name
Test status
Simulation time 12216301 ps
CPU time 0.71 seconds
Started Mar 26 02:04:27 PM PDT 24
Finished Mar 26 02:04:28 PM PDT 24
Peak memory 204996 kb
Host smart-3f2908f9-0531-49f3-ae56-8f39019cc7dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269018766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1269018766
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3618200042
Short name T282
Test name
Test status
Simulation time 2838081900 ps
CPU time 3.09 seconds
Started Mar 26 02:04:18 PM PDT 24
Finished Mar 26 02:04:21 PM PDT 24
Peak memory 218492 kb
Host smart-171f3706-e339-4dcb-bcfe-1ec25cc3dd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618200042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3618200042
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2341224373
Short name T10
Test name
Test status
Simulation time 26759260 ps
CPU time 0.74 seconds
Started Mar 26 02:04:13 PM PDT 24
Finished Mar 26 02:04:14 PM PDT 24
Peak memory 205460 kb
Host smart-a7630489-d990-4f6b-968f-68430add81cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341224373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2341224373
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.180732885
Short name T642
Test name
Test status
Simulation time 32343470691 ps
CPU time 36.05 seconds
Started Mar 26 02:04:25 PM PDT 24
Finished Mar 26 02:05:01 PM PDT 24
Peak memory 240740 kb
Host smart-8abaa683-c65b-479b-ab49-13cf607dbdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180732885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.180732885
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1561267989
Short name T929
Test name
Test status
Simulation time 4013449582 ps
CPU time 43.22 seconds
Started Mar 26 02:04:25 PM PDT 24
Finished Mar 26 02:05:09 PM PDT 24
Peak memory 235744 kb
Host smart-89d8052c-6e2e-4279-ac87-db9b3a8b0470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561267989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1561267989
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.826519154
Short name T579
Test name
Test status
Simulation time 12032804498 ps
CPU time 84.8 seconds
Started Mar 26 02:04:32 PM PDT 24
Finished Mar 26 02:05:57 PM PDT 24
Peak memory 248892 kb
Host smart-ffeb2037-9fc7-4cfa-9e5b-3b5959417bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826519154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.826519154
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.134528555
Short name T496
Test name
Test status
Simulation time 18391997451 ps
CPU time 30.47 seconds
Started Mar 26 02:04:13 PM PDT 24
Finished Mar 26 02:04:44 PM PDT 24
Peak memory 242516 kb
Host smart-4f2e97d3-e47b-4469-923a-51156c2f7a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134528555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.134528555
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4033215036
Short name T522
Test name
Test status
Simulation time 372837386 ps
CPU time 3.53 seconds
Started Mar 26 02:04:14 PM PDT 24
Finished Mar 26 02:04:18 PM PDT 24
Peak memory 235000 kb
Host smart-8cd7d72e-e090-4d46-962f-3f444ab21273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033215036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4033215036
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4137267431
Short name T759
Test name
Test status
Simulation time 4737735813 ps
CPU time 12.56 seconds
Started Mar 26 02:04:14 PM PDT 24
Finished Mar 26 02:04:28 PM PDT 24
Peak memory 233788 kb
Host smart-01cda7ff-5bc5-4fc5-a2cf-b446c2ed622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137267431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4137267431
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1593188697
Short name T889
Test name
Test status
Simulation time 58692875 ps
CPU time 2.86 seconds
Started Mar 26 02:04:12 PM PDT 24
Finished Mar 26 02:04:16 PM PDT 24
Peak memory 232540 kb
Host smart-f5dc5540-46be-4c99-9957-ab1caa5e8cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593188697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1593188697
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2961982775
Short name T639
Test name
Test status
Simulation time 18223935620 ps
CPU time 18.36 seconds
Started Mar 26 02:04:13 PM PDT 24
Finished Mar 26 02:04:32 PM PDT 24
Peak memory 233924 kb
Host smart-406a7c0f-18cf-4e9a-a777-cf10bb4e5031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961982775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2961982775
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4277814712
Short name T123
Test name
Test status
Simulation time 10118437220 ps
CPU time 6.11 seconds
Started Mar 26 02:04:32 PM PDT 24
Finished Mar 26 02:04:38 PM PDT 24
Peak memory 221964 kb
Host smart-ec340d8a-d289-46be-a4f7-adf8ddfe0656
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4277814712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4277814712
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1374722413
Short name T989
Test name
Test status
Simulation time 50336796320 ps
CPU time 323.58 seconds
Started Mar 26 02:04:24 PM PDT 24
Finished Mar 26 02:09:48 PM PDT 24
Peak memory 254572 kb
Host smart-93c35145-7efc-460d-8ab1-6fb02c062879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374722413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1374722413
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.11769642
Short name T272
Test name
Test status
Simulation time 12593676518 ps
CPU time 65.87 seconds
Started Mar 26 02:04:14 PM PDT 24
Finished Mar 26 02:05:21 PM PDT 24
Peak memory 216064 kb
Host smart-fe6e28da-4657-493b-83bf-969929dd4339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11769642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.11769642
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1689154291
Short name T942
Test name
Test status
Simulation time 5374637881 ps
CPU time 15.09 seconds
Started Mar 26 02:04:15 PM PDT 24
Finished Mar 26 02:04:30 PM PDT 24
Peak memory 216268 kb
Host smart-555d18dc-3093-4258-b51c-db2879f974cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689154291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1689154291
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1186465735
Short name T938
Test name
Test status
Simulation time 29080162 ps
CPU time 1.07 seconds
Started Mar 26 02:04:17 PM PDT 24
Finished Mar 26 02:04:18 PM PDT 24
Peak memory 207296 kb
Host smart-a7e4489c-d50e-4ba3-8797-924c63466d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186465735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1186465735
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3523928468
Short name T548
Test name
Test status
Simulation time 171903551 ps
CPU time 0.98 seconds
Started Mar 26 02:04:13 PM PDT 24
Finished Mar 26 02:04:15 PM PDT 24
Peak memory 206552 kb
Host smart-00c3809e-f43c-467b-9bc3-ceaaeae577fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523928468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3523928468
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2120760009
Short name T444
Test name
Test status
Simulation time 25469522942 ps
CPU time 11.05 seconds
Started Mar 26 02:04:18 PM PDT 24
Finished Mar 26 02:04:29 PM PDT 24
Peak memory 235148 kb
Host smart-41dd6794-25de-4aab-963c-c189c6114163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120760009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2120760009
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2207251647
Short name T958
Test name
Test status
Simulation time 25644041 ps
CPU time 0.74 seconds
Started Mar 26 02:04:24 PM PDT 24
Finished Mar 26 02:04:25 PM PDT 24
Peak memory 205424 kb
Host smart-33a700a7-0d1f-4062-bea1-512faed7e5ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207251647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2207251647
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1596399204
Short name T879
Test name
Test status
Simulation time 806769888 ps
CPU time 6.44 seconds
Started Mar 26 02:04:24 PM PDT 24
Finished Mar 26 02:04:31 PM PDT 24
Peak memory 233520 kb
Host smart-be06543a-aec6-4434-bcb2-5071a9d95d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596399204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1596399204
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3128728245
Short name T644
Test name
Test status
Simulation time 26236380 ps
CPU time 0.78 seconds
Started Mar 26 02:04:27 PM PDT 24
Finished Mar 26 02:04:28 PM PDT 24
Peak memory 206236 kb
Host smart-90f57f63-163b-44b1-a263-fb51202ab62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128728245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3128728245
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1470726213
Short name T706
Test name
Test status
Simulation time 182948976953 ps
CPU time 137.42 seconds
Started Mar 26 02:04:24 PM PDT 24
Finished Mar 26 02:06:42 PM PDT 24
Peak memory 240812 kb
Host smart-1a09fde2-2057-45ca-b2e1-5dfaad623d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470726213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1470726213
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3792276798
Short name T719
Test name
Test status
Simulation time 110851064817 ps
CPU time 107.75 seconds
Started Mar 26 02:04:33 PM PDT 24
Finished Mar 26 02:06:21 PM PDT 24
Peak memory 248864 kb
Host smart-3c5d5a27-b908-4410-986b-3f4a12b49861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792276798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3792276798
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.176168262
Short name T618
Test name
Test status
Simulation time 5497292205 ps
CPU time 86.34 seconds
Started Mar 26 02:04:27 PM PDT 24
Finished Mar 26 02:05:53 PM PDT 24
Peak memory 265288 kb
Host smart-2f958e37-102b-41ce-84c9-88671b239ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176168262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.176168262
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.426849131
Short name T419
Test name
Test status
Simulation time 653493423 ps
CPU time 7.96 seconds
Started Mar 26 02:04:25 PM PDT 24
Finished Mar 26 02:04:33 PM PDT 24
Peak memory 234540 kb
Host smart-38f9b996-845b-49e7-bffa-21ce5fe9e960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426849131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.426849131
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4193773491
Short name T431
Test name
Test status
Simulation time 3121376968 ps
CPU time 10.99 seconds
Started Mar 26 02:04:24 PM PDT 24
Finished Mar 26 02:04:36 PM PDT 24
Peak memory 224404 kb
Host smart-fe66eb6f-e874-4433-bacf-7b7b1efa4e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193773491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4193773491
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.772252583
Short name T190
Test name
Test status
Simulation time 1505457763 ps
CPU time 5.44 seconds
Started Mar 26 02:04:33 PM PDT 24
Finished Mar 26 02:04:39 PM PDT 24
Peak memory 233500 kb
Host smart-6803c54e-02ea-46bb-8a7c-02a432f748e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772252583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.772252583
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1937678481
Short name T223
Test name
Test status
Simulation time 3618017094 ps
CPU time 7.33 seconds
Started Mar 26 02:04:26 PM PDT 24
Finished Mar 26 02:04:33 PM PDT 24
Peak memory 233608 kb
Host smart-adc2a2bb-383e-47f1-a151-e4dc454f64c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937678481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1937678481
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.537341414
Short name T336
Test name
Test status
Simulation time 418915405 ps
CPU time 2.83 seconds
Started Mar 26 02:04:29 PM PDT 24
Finished Mar 26 02:04:32 PM PDT 24
Peak memory 216628 kb
Host smart-e1c14487-0388-4b0f-90e7-ea511e07531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537341414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.537341414
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3414964486
Short name T455
Test name
Test status
Simulation time 776096066 ps
CPU time 3.78 seconds
Started Mar 26 02:04:26 PM PDT 24
Finished Mar 26 02:04:30 PM PDT 24
Peak memory 218556 kb
Host smart-ac42308c-8556-494f-9407-76d9ba40692c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3414964486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3414964486
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1798399986
Short name T758
Test name
Test status
Simulation time 1896401325 ps
CPU time 44.34 seconds
Started Mar 26 02:04:26 PM PDT 24
Finished Mar 26 02:05:10 PM PDT 24
Peak memory 240480 kb
Host smart-8e1e8a80-cd64-490d-bd9d-34e0ee2e11f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798399986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1798399986
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1461619171
Short name T866
Test name
Test status
Simulation time 1413178679 ps
CPU time 9.97 seconds
Started Mar 26 02:04:25 PM PDT 24
Finished Mar 26 02:04:36 PM PDT 24
Peak memory 216024 kb
Host smart-cb933a5a-cddf-4ea8-a894-e29ab5df670c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461619171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1461619171
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3923417459
Short name T76
Test name
Test status
Simulation time 5924341635 ps
CPU time 4.28 seconds
Started Mar 26 02:04:33 PM PDT 24
Finished Mar 26 02:04:37 PM PDT 24
Peak memory 215988 kb
Host smart-37e77a03-9837-4acf-a974-71327e6fbe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923417459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3923417459
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2110171933
Short name T607
Test name
Test status
Simulation time 180223794 ps
CPU time 1.46 seconds
Started Mar 26 02:04:26 PM PDT 24
Finished Mar 26 02:04:28 PM PDT 24
Peak memory 216116 kb
Host smart-7ab7eb26-8c63-47e9-9795-7139a0b5924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110171933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2110171933
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.73922394
Short name T576
Test name
Test status
Simulation time 25686091 ps
CPU time 0.7 seconds
Started Mar 26 02:04:26 PM PDT 24
Finished Mar 26 02:04:27 PM PDT 24
Peak memory 205352 kb
Host smart-4e3d3210-2ca5-40b9-8e64-dfcc36438f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73922394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.73922394
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3540083313
Short name T291
Test name
Test status
Simulation time 3674611997 ps
CPU time 15.56 seconds
Started Mar 26 02:04:25 PM PDT 24
Finished Mar 26 02:04:41 PM PDT 24
Peak memory 235928 kb
Host smart-bdb0f976-4e81-4523-8504-cd6da479c21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540083313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3540083313
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.236630740
Short name T554
Test name
Test status
Simulation time 16864325 ps
CPU time 0.76 seconds
Started Mar 26 02:04:38 PM PDT 24
Finished Mar 26 02:04:39 PM PDT 24
Peak memory 205104 kb
Host smart-c7fd0a22-636b-4091-8226-0cbb5b9232ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236630740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.236630740
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2240608593
Short name T551
Test name
Test status
Simulation time 1346268138 ps
CPU time 6.24 seconds
Started Mar 26 02:04:38 PM PDT 24
Finished Mar 26 02:04:45 PM PDT 24
Peak memory 233116 kb
Host smart-a1171328-d091-49ef-b287-2b4bb1b70ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240608593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2240608593
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3229758545
Short name T479
Test name
Test status
Simulation time 17855744 ps
CPU time 0.79 seconds
Started Mar 26 02:04:27 PM PDT 24
Finished Mar 26 02:04:28 PM PDT 24
Peak memory 205180 kb
Host smart-5f3ed8e5-e5bd-4ea4-a72b-6a2a63f70f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229758545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3229758545
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2676680896
Short name T405
Test name
Test status
Simulation time 30468080132 ps
CPU time 84.99 seconds
Started Mar 26 02:04:37 PM PDT 24
Finished Mar 26 02:06:02 PM PDT 24
Peak memory 248964 kb
Host smart-0ac02205-ca22-4e8e-b016-ca7d916bd6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676680896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2676680896
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2992915164
Short name T179
Test name
Test status
Simulation time 22244703752 ps
CPU time 209.34 seconds
Started Mar 26 02:04:38 PM PDT 24
Finished Mar 26 02:08:08 PM PDT 24
Peak memory 253524 kb
Host smart-ceb7d1e6-de76-4a48-8e19-b7bc7714a8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992915164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2992915164
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3260812892
Short name T774
Test name
Test status
Simulation time 131367925483 ps
CPU time 253.67 seconds
Started Mar 26 02:04:40 PM PDT 24
Finished Mar 26 02:08:56 PM PDT 24
Peak memory 249040 kb
Host smart-62c5ab25-3fe2-4e37-8699-2f26561bb07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260812892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3260812892
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.453832255
Short name T871
Test name
Test status
Simulation time 709723550 ps
CPU time 12.24 seconds
Started Mar 26 02:04:40 PM PDT 24
Finished Mar 26 02:04:55 PM PDT 24
Peak memory 234860 kb
Host smart-967f6b9c-0301-473c-a9d6-9683e62113bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453832255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.453832255
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2240511219
Short name T456
Test name
Test status
Simulation time 1695882667 ps
CPU time 6.52 seconds
Started Mar 26 02:04:40 PM PDT 24
Finished Mar 26 02:04:49 PM PDT 24
Peak memory 237224 kb
Host smart-e195b877-e1bb-415b-8803-e206cd0bd424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240511219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2240511219
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.267507588
Short name T7
Test name
Test status
Simulation time 861992035 ps
CPU time 7.56 seconds
Started Mar 26 02:04:40 PM PDT 24
Finished Mar 26 02:04:50 PM PDT 24
Peak memory 235152 kb
Host smart-0be42f64-cf6d-4582-99fe-e100723cfa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267507588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.267507588
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.711305672
Short name T824
Test name
Test status
Simulation time 1360690171 ps
CPU time 8 seconds
Started Mar 26 02:04:33 PM PDT 24
Finished Mar 26 02:04:41 PM PDT 24
Peak memory 224188 kb
Host smart-67fb01db-a88d-4911-9a97-c4f762584ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711305672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.711305672
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2455019236
Short name T369
Test name
Test status
Simulation time 155171477 ps
CPU time 2.61 seconds
Started Mar 26 02:04:26 PM PDT 24
Finished Mar 26 02:04:29 PM PDT 24
Peak memory 217568 kb
Host smart-e783efc5-af3f-43f1-9de4-492c12e5683d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455019236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2455019236
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.116762619
Short name T513
Test name
Test status
Simulation time 1496046079 ps
CPU time 5.04 seconds
Started Mar 26 02:04:39 PM PDT 24
Finished Mar 26 02:04:47 PM PDT 24
Peak memory 219128 kb
Host smart-8d7eba20-86ef-46ba-b8f1-6bb8b5e787bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=116762619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.116762619
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1089388255
Short name T499
Test name
Test status
Simulation time 2030994011 ps
CPU time 22.21 seconds
Started Mar 26 02:04:26 PM PDT 24
Finished Mar 26 02:04:49 PM PDT 24
Peak memory 219380 kb
Host smart-6e2ab2d8-c2fd-4ff5-a711-1b285412cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089388255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1089388255
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.172697141
Short name T629
Test name
Test status
Simulation time 9164826777 ps
CPU time 11.73 seconds
Started Mar 26 02:04:26 PM PDT 24
Finished Mar 26 02:04:38 PM PDT 24
Peak memory 216476 kb
Host smart-67d89ff2-8065-430b-a48f-de8222664ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172697141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.172697141
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2797597537
Short name T773
Test name
Test status
Simulation time 286032391 ps
CPU time 3.42 seconds
Started Mar 26 02:04:27 PM PDT 24
Finished Mar 26 02:04:31 PM PDT 24
Peak memory 216044 kb
Host smart-bb160f21-4962-45ce-8ca5-98bc888ea1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797597537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2797597537
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2357294852
Short name T739
Test name
Test status
Simulation time 244741425 ps
CPU time 0.88 seconds
Started Mar 26 02:04:25 PM PDT 24
Finished Mar 26 02:04:27 PM PDT 24
Peak memory 205416 kb
Host smart-f3744e98-2b32-4496-a33d-1795967a7401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357294852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2357294852
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2209183755
Short name T558
Test name
Test status
Simulation time 1345803675 ps
CPU time 3.78 seconds
Started Mar 26 02:04:38 PM PDT 24
Finished Mar 26 02:04:42 PM PDT 24
Peak memory 232576 kb
Host smart-83951fcd-4a15-4685-8377-ad970254e022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209183755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2209183755
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3768596742
Short name T624
Test name
Test status
Simulation time 14676226 ps
CPU time 0.73 seconds
Started Mar 26 02:01:16 PM PDT 24
Finished Mar 26 02:01:17 PM PDT 24
Peak memory 205072 kb
Host smart-e39cd1a1-a3fc-463f-aba1-5e6a2cd74632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768596742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
768596742
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1104643428
Short name T410
Test name
Test status
Simulation time 7870575328 ps
CPU time 5.4 seconds
Started Mar 26 02:01:14 PM PDT 24
Finished Mar 26 02:01:19 PM PDT 24
Peak memory 233304 kb
Host smart-84bb9087-52d7-44ee-8acd-dd44327f042d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104643428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1104643428
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1210044621
Short name T144
Test name
Test status
Simulation time 19356100 ps
CPU time 0.78 seconds
Started Mar 26 02:01:15 PM PDT 24
Finished Mar 26 02:01:16 PM PDT 24
Peak memory 205004 kb
Host smart-8167a262-83cd-48f0-bf08-af395e4e0471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210044621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1210044621
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1795339070
Short name T236
Test name
Test status
Simulation time 1836963040 ps
CPU time 15.8 seconds
Started Mar 26 02:01:14 PM PDT 24
Finished Mar 26 02:01:29 PM PDT 24
Peak memory 240356 kb
Host smart-bc6de668-99e9-4ef3-aa57-ee7893feb453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795339070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1795339070
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2530440310
Short name T425
Test name
Test status
Simulation time 5441529035 ps
CPU time 92.61 seconds
Started Mar 26 02:01:11 PM PDT 24
Finished Mar 26 02:02:45 PM PDT 24
Peak memory 264412 kb
Host smart-99cdd071-2304-43c8-b1b2-10025a31e496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530440310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2530440310
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1509639893
Short name T413
Test name
Test status
Simulation time 589693147 ps
CPU time 17.13 seconds
Started Mar 26 02:01:12 PM PDT 24
Finished Mar 26 02:01:30 PM PDT 24
Peak memory 232584 kb
Host smart-07105d90-456e-406f-aeb0-7a3f3d708596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509639893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1509639893
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3051289732
Short name T182
Test name
Test status
Simulation time 927157908 ps
CPU time 3.49 seconds
Started Mar 26 02:01:15 PM PDT 24
Finished Mar 26 02:01:18 PM PDT 24
Peak memory 224288 kb
Host smart-e011dae3-bf2d-4e62-85cf-8dd4ead865b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051289732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3051289732
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.120306639
Short name T224
Test name
Test status
Simulation time 1206285478 ps
CPU time 6.94 seconds
Started Mar 26 02:01:13 PM PDT 24
Finished Mar 26 02:01:20 PM PDT 24
Peak memory 224368 kb
Host smart-db04f601-7ddc-47fd-b62f-edacf78f5a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120306639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.120306639
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.426165341
Short name T954
Test name
Test status
Simulation time 27410918 ps
CPU time 1.04 seconds
Started Mar 26 02:01:13 PM PDT 24
Finished Mar 26 02:01:14 PM PDT 24
Peak memory 216292 kb
Host smart-07961e5b-5265-4869-a3fb-ff6b349262be
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426165341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.426165341
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3879100191
Short name T800
Test name
Test status
Simulation time 785770878 ps
CPU time 3.71 seconds
Started Mar 26 02:01:04 PM PDT 24
Finished Mar 26 02:01:08 PM PDT 24
Peak memory 233132 kb
Host smart-9c097c17-bf31-4ccd-89d9-3071206889f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879100191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3879100191
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.465984256
Short name T785
Test name
Test status
Simulation time 755209425 ps
CPU time 6.71 seconds
Started Mar 26 02:01:13 PM PDT 24
Finished Mar 26 02:01:20 PM PDT 24
Peak memory 232844 kb
Host smart-a0ad0a87-7598-428b-bf9a-352696762714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465984256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.465984256
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.3688533975
Short name T150
Test name
Test status
Simulation time 36316672 ps
CPU time 0.8 seconds
Started Mar 26 02:01:15 PM PDT 24
Finished Mar 26 02:01:16 PM PDT 24
Peak memory 215852 kb
Host smart-beb0822d-2b47-410b-99f1-5995bda41a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688533975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.3688533975
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3494002004
Short name T396
Test name
Test status
Simulation time 7079984368 ps
CPU time 6.53 seconds
Started Mar 26 02:01:14 PM PDT 24
Finished Mar 26 02:01:21 PM PDT 24
Peak memory 222680 kb
Host smart-0c957a41-d061-411f-a640-c8b9d4eb5660
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3494002004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3494002004
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2828271706
Short name T60
Test name
Test status
Simulation time 57563001 ps
CPU time 1.21 seconds
Started Mar 26 02:01:13 PM PDT 24
Finished Mar 26 02:01:15 PM PDT 24
Peak memory 235312 kb
Host smart-62c0e772-284a-46e8-a983-55034c557261
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828271706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2828271706
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.818614646
Short name T736
Test name
Test status
Simulation time 9950496037 ps
CPU time 25.51 seconds
Started Mar 26 02:01:14 PM PDT 24
Finished Mar 26 02:01:40 PM PDT 24
Peak memory 216148 kb
Host smart-a830d5d0-b695-4470-8fc7-fb0fe2aa48c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818614646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.818614646
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3235601480
Short name T535
Test name
Test status
Simulation time 8474895315 ps
CPU time 13.6 seconds
Started Mar 26 02:01:02 PM PDT 24
Finished Mar 26 02:01:16 PM PDT 24
Peak memory 216188 kb
Host smart-cc2f42c4-3dfb-4e02-b6f5-c2b30b37ef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235601480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3235601480
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.54438894
Short name T342
Test name
Test status
Simulation time 191496006 ps
CPU time 1.72 seconds
Started Mar 26 02:01:05 PM PDT 24
Finished Mar 26 02:01:07 PM PDT 24
Peak memory 216436 kb
Host smart-ed30781b-47f9-4612-a19a-bb36200b074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54438894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.54438894
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2983807390
Short name T710
Test name
Test status
Simulation time 146484702 ps
CPU time 1.11 seconds
Started Mar 26 02:01:04 PM PDT 24
Finished Mar 26 02:01:06 PM PDT 24
Peak memory 205968 kb
Host smart-8075d1f7-8f2e-47d5-99ec-014efc31683e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983807390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2983807390
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.854353825
Short name T512
Test name
Test status
Simulation time 1398366877 ps
CPU time 11.63 seconds
Started Mar 26 02:01:13 PM PDT 24
Finished Mar 26 02:01:25 PM PDT 24
Peak memory 250000 kb
Host smart-b682cab0-12a0-44ea-983c-b61ce5780f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854353825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.854353825
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.954901857
Short name T303
Test name
Test status
Simulation time 32958174 ps
CPU time 0.7 seconds
Started Mar 26 02:04:39 PM PDT 24
Finished Mar 26 02:04:40 PM PDT 24
Peak memory 204524 kb
Host smart-0fbe7b97-56f2-4133-8a5a-6f4a2bddc38a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954901857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.954901857
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2264680601
Short name T700
Test name
Test status
Simulation time 453309441 ps
CPU time 3.32 seconds
Started Mar 26 02:04:37 PM PDT 24
Finished Mar 26 02:04:42 PM PDT 24
Peak memory 233608 kb
Host smart-e6268876-98a6-44b7-ad8a-1aab9bc13d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264680601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2264680601
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2773009702
Short name T275
Test name
Test status
Simulation time 16114503 ps
CPU time 0.74 seconds
Started Mar 26 02:04:37 PM PDT 24
Finished Mar 26 02:04:39 PM PDT 24
Peak memory 205472 kb
Host smart-015bd579-0519-401e-8596-46dec234fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773009702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2773009702
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.210102021
Short name T366
Test name
Test status
Simulation time 6471466628 ps
CPU time 61.16 seconds
Started Mar 26 02:04:45 PM PDT 24
Finished Mar 26 02:05:46 PM PDT 24
Peak memory 249924 kb
Host smart-c6853b18-c67d-4dfe-97ad-975bc24987d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210102021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.210102021
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.416279305
Short name T175
Test name
Test status
Simulation time 5123212045 ps
CPU time 63.58 seconds
Started Mar 26 02:04:39 PM PDT 24
Finished Mar 26 02:05:43 PM PDT 24
Peak memory 238764 kb
Host smart-9dc4b938-5454-4749-9693-d729e315088a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416279305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.416279305
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.742862446
Short name T40
Test name
Test status
Simulation time 225744672123 ps
CPU time 478.89 seconds
Started Mar 26 02:04:41 PM PDT 24
Finished Mar 26 02:12:41 PM PDT 24
Peak memory 262336 kb
Host smart-00256843-aa16-4fa7-a417-ece3ee87cf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742862446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.742862446
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1718968344
Short name T805
Test name
Test status
Simulation time 3357910978 ps
CPU time 7.76 seconds
Started Mar 26 02:04:38 PM PDT 24
Finished Mar 26 02:04:46 PM PDT 24
Peak memory 240752 kb
Host smart-a07164d6-9252-47c6-9b70-2668cab2cd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718968344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1718968344
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.501218985
Short name T403
Test name
Test status
Simulation time 557602004 ps
CPU time 5.4 seconds
Started Mar 26 02:04:37 PM PDT 24
Finished Mar 26 02:04:42 PM PDT 24
Peak memory 235380 kb
Host smart-f441a5cb-f6b7-4cb0-929b-fd00b3ca9791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501218985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.501218985
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3896941580
Short name T66
Test name
Test status
Simulation time 10127302691 ps
CPU time 27.09 seconds
Started Mar 26 02:04:45 PM PDT 24
Finished Mar 26 02:05:12 PM PDT 24
Peak memory 240572 kb
Host smart-3ce63218-9761-4fa9-b518-55850d251ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896941580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3896941580
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1051481515
Short name T980
Test name
Test status
Simulation time 6569093599 ps
CPU time 22.08 seconds
Started Mar 26 02:04:40 PM PDT 24
Finished Mar 26 02:05:04 PM PDT 24
Peak memory 224432 kb
Host smart-eaa83e6e-9d8d-4d5c-9d06-b66a52ebd7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051481515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1051481515
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1815332661
Short name T816
Test name
Test status
Simulation time 15723174664 ps
CPU time 10.68 seconds
Started Mar 26 02:04:40 PM PDT 24
Finished Mar 26 02:04:53 PM PDT 24
Peak memory 219780 kb
Host smart-106e9e9e-8486-47d9-a88c-4f8a043b333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815332661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1815332661
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.646811546
Short name T471
Test name
Test status
Simulation time 2958943924 ps
CPU time 4.47 seconds
Started Mar 26 02:04:38 PM PDT 24
Finished Mar 26 02:04:43 PM PDT 24
Peak memory 218720 kb
Host smart-b23d224d-47c9-4ccb-a808-16b60f4beef0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=646811546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.646811546
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4028298785
Short name T55
Test name
Test status
Simulation time 92818841 ps
CPU time 0.96 seconds
Started Mar 26 02:04:41 PM PDT 24
Finished Mar 26 02:04:43 PM PDT 24
Peak memory 206448 kb
Host smart-499a1272-e8f1-4d61-9dfc-9f791e41b838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028298785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4028298785
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2477647938
Short name T707
Test name
Test status
Simulation time 427883079 ps
CPU time 3.95 seconds
Started Mar 26 02:04:36 PM PDT 24
Finished Mar 26 02:04:40 PM PDT 24
Peak memory 216108 kb
Host smart-0d389f7a-5995-4865-a512-bc58c2a71ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477647938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2477647938
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1252963904
Short name T15
Test name
Test status
Simulation time 864865112 ps
CPU time 5.93 seconds
Started Mar 26 02:04:40 PM PDT 24
Finished Mar 26 02:04:48 PM PDT 24
Peak memory 215992 kb
Host smart-a5e5aef0-57a0-4e16-a36c-2079b5b26c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252963904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1252963904
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1717011967
Short name T540
Test name
Test status
Simulation time 26469406 ps
CPU time 0.79 seconds
Started Mar 26 02:04:39 PM PDT 24
Finished Mar 26 02:04:40 PM PDT 24
Peak memory 205452 kb
Host smart-fc3d65c2-ae59-4a5f-a317-a0f652760494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717011967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1717011967
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2520032127
Short name T778
Test name
Test status
Simulation time 189514705 ps
CPU time 0.97 seconds
Started Mar 26 02:04:39 PM PDT 24
Finished Mar 26 02:04:40 PM PDT 24
Peak memory 206464 kb
Host smart-a90160fd-1b4a-4613-8440-f33ffba78c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520032127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2520032127
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3758489276
Short name T178
Test name
Test status
Simulation time 4657327934 ps
CPU time 7.75 seconds
Started Mar 26 02:04:41 PM PDT 24
Finished Mar 26 02:04:50 PM PDT 24
Peak memory 235868 kb
Host smart-774339f6-a632-464e-ae8c-5242690e52d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758489276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3758489276
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.835929428
Short name T870
Test name
Test status
Simulation time 31053349 ps
CPU time 0.75 seconds
Started Mar 26 02:04:46 PM PDT 24
Finished Mar 26 02:04:47 PM PDT 24
Peak memory 204484 kb
Host smart-068a5aa0-fb55-490f-a5da-10bffb37f70b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835929428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.835929428
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4211350932
Short name T317
Test name
Test status
Simulation time 2143006227 ps
CPU time 8.61 seconds
Started Mar 26 02:04:46 PM PDT 24
Finished Mar 26 02:04:55 PM PDT 24
Peak memory 219648 kb
Host smart-3ab78f70-ca93-43a4-b190-6b8f7b3bbabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211350932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4211350932
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1062477888
Short name T811
Test name
Test status
Simulation time 66057310 ps
CPU time 0.84 seconds
Started Mar 26 02:04:40 PM PDT 24
Finished Mar 26 02:04:43 PM PDT 24
Peak memory 206456 kb
Host smart-b3bf0eb3-1210-4c0a-a06f-ec667cd25db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062477888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1062477888
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2771112623
Short name T943
Test name
Test status
Simulation time 95804851388 ps
CPU time 141.7 seconds
Started Mar 26 02:04:46 PM PDT 24
Finished Mar 26 02:07:08 PM PDT 24
Peak memory 249032 kb
Host smart-93a9a060-fdcc-4ac4-99d8-baca0be0866a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771112623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2771112623
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3599322792
Short name T112
Test name
Test status
Simulation time 181856060105 ps
CPU time 333.9 seconds
Started Mar 26 02:04:47 PM PDT 24
Finished Mar 26 02:10:22 PM PDT 24
Peak memory 249020 kb
Host smart-a5741be2-e5d0-4197-931e-10a8bf237919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599322792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3599322792
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1575695512
Short name T890
Test name
Test status
Simulation time 21535175465 ps
CPU time 45.04 seconds
Started Mar 26 02:04:48 PM PDT 24
Finished Mar 26 02:05:33 PM PDT 24
Peak memory 232768 kb
Host smart-5afb6251-913c-4f44-81bd-995e66637bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575695512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1575695512
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3508490038
Short name T121
Test name
Test status
Simulation time 11389179321 ps
CPU time 21.99 seconds
Started Mar 26 02:04:49 PM PDT 24
Finished Mar 26 02:05:12 PM PDT 24
Peak memory 235260 kb
Host smart-dd934e1e-4bf5-4dce-a146-ad02586f1919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508490038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3508490038
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1837633680
Short name T833
Test name
Test status
Simulation time 361068452 ps
CPU time 4.87 seconds
Started Mar 26 02:04:49 PM PDT 24
Finished Mar 26 02:04:57 PM PDT 24
Peak memory 233592 kb
Host smart-8e8b7ee8-d93d-4ecc-8df9-924976cd98d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837633680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1837633680
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1386239497
Short name T552
Test name
Test status
Simulation time 185651004 ps
CPU time 2.67 seconds
Started Mar 26 02:04:48 PM PDT 24
Finished Mar 26 02:04:53 PM PDT 24
Peak memory 233476 kb
Host smart-5aeba5c4-2dbd-4543-84d7-b009173cc996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386239497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1386239497
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3571461195
Short name T451
Test name
Test status
Simulation time 2836319173 ps
CPU time 7.03 seconds
Started Mar 26 02:04:48 PM PDT 24
Finished Mar 26 02:04:55 PM PDT 24
Peak memory 235760 kb
Host smart-69cd1f6e-1d4d-43bb-ad6d-52767e2b86ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571461195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3571461195
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1699428542
Short name T985
Test name
Test status
Simulation time 4400751722 ps
CPU time 15.12 seconds
Started Mar 26 02:04:48 PM PDT 24
Finished Mar 26 02:05:04 PM PDT 24
Peak memory 218332 kb
Host smart-da7d7598-033a-47aa-ab91-d436e8ed06e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699428542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1699428542
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2948130572
Short name T592
Test name
Test status
Simulation time 520592992 ps
CPU time 3.06 seconds
Started Mar 26 02:04:48 PM PDT 24
Finished Mar 26 02:04:55 PM PDT 24
Peak memory 218512 kb
Host smart-feddd18e-49e0-4732-b971-6d18b457ad10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2948130572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2948130572
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3601007883
Short name T566
Test name
Test status
Simulation time 183953275 ps
CPU time 0.94 seconds
Started Mar 26 02:04:50 PM PDT 24
Finished Mar 26 02:04:56 PM PDT 24
Peak memory 206596 kb
Host smart-d6faca1c-65bb-40d4-9ccc-1b2c01a5d5e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601007883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3601007883
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3199729266
Short name T544
Test name
Test status
Simulation time 29618199692 ps
CPU time 42.12 seconds
Started Mar 26 02:04:40 PM PDT 24
Finished Mar 26 02:05:24 PM PDT 24
Peak memory 216048 kb
Host smart-d8974a18-4776-43ed-acef-1866be565cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199729266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3199729266
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3308563829
Short name T725
Test name
Test status
Simulation time 7845504650 ps
CPU time 20.01 seconds
Started Mar 26 02:04:46 PM PDT 24
Finished Mar 26 02:05:06 PM PDT 24
Peak memory 215952 kb
Host smart-48bc0dcc-b050-45f5-aca0-b7ad5f3fc050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308563829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3308563829
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3510561217
Short name T534
Test name
Test status
Simulation time 799304173 ps
CPU time 3.22 seconds
Started Mar 26 02:04:49 PM PDT 24
Finished Mar 26 02:04:56 PM PDT 24
Peak memory 216048 kb
Host smart-85b48c03-15fa-48f4-83ae-2f0f8fe871f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510561217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3510561217
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1598554119
Short name T443
Test name
Test status
Simulation time 163821217 ps
CPU time 0.82 seconds
Started Mar 26 02:04:46 PM PDT 24
Finished Mar 26 02:04:47 PM PDT 24
Peak memory 205456 kb
Host smart-4bc98ac9-15e2-4a8b-8355-697271f0299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598554119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1598554119
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3327382902
Short name T615
Test name
Test status
Simulation time 1353880914 ps
CPU time 10.01 seconds
Started Mar 26 02:04:49 PM PDT 24
Finished Mar 26 02:05:02 PM PDT 24
Peak memory 227624 kb
Host smart-008c6c7b-6aa7-4fdf-8b54-a51a7f8aea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327382902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3327382902
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2373595144
Short name T149
Test name
Test status
Simulation time 14722779 ps
CPU time 0.74 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:05:00 PM PDT 24
Peak memory 205152 kb
Host smart-44a5b3b4-55b5-4e48-ba7b-9cc6bdd68d35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373595144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2373595144
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.323599944
Short name T684
Test name
Test status
Simulation time 132700825 ps
CPU time 2.43 seconds
Started Mar 26 02:04:51 PM PDT 24
Finished Mar 26 02:04:57 PM PDT 24
Peak memory 218452 kb
Host smart-8a30411c-efc7-4273-94b3-0aebaf0ebb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323599944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.323599944
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3565544534
Short name T367
Test name
Test status
Simulation time 52377036 ps
CPU time 0.76 seconds
Started Mar 26 02:04:53 PM PDT 24
Finished Mar 26 02:04:56 PM PDT 24
Peak memory 205456 kb
Host smart-35811e8c-1692-4cd8-869f-159f8d951965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565544534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3565544534
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2381669079
Short name T528
Test name
Test status
Simulation time 16808604146 ps
CPU time 114.19 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:06:54 PM PDT 24
Peak memory 256264 kb
Host smart-5cb8d562-5df0-45d2-ac16-462bf382b9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381669079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2381669079
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1613954827
Short name T42
Test name
Test status
Simulation time 25733237702 ps
CPU time 229.72 seconds
Started Mar 26 02:05:00 PM PDT 24
Finished Mar 26 02:08:50 PM PDT 24
Peak memory 265416 kb
Host smart-9c5301ea-de77-4da9-8e04-9d443461a705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613954827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1613954827
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3831345094
Short name T114
Test name
Test status
Simulation time 61278614314 ps
CPU time 195.97 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:08:16 PM PDT 24
Peak memory 267308 kb
Host smart-4876386c-7c6e-4a93-a86d-4a553e34037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831345094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3831345094
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4165403598
Short name T878
Test name
Test status
Simulation time 5357153578 ps
CPU time 36.42 seconds
Started Mar 26 02:04:47 PM PDT 24
Finished Mar 26 02:05:24 PM PDT 24
Peak memory 240880 kb
Host smart-a036c22b-d821-40ac-8b99-02971e249898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165403598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4165403598
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.982763607
Short name T68
Test name
Test status
Simulation time 2501015231 ps
CPU time 6.18 seconds
Started Mar 26 02:04:48 PM PDT 24
Finished Mar 26 02:04:56 PM PDT 24
Peak memory 219408 kb
Host smart-81fc6cbd-e4a2-42d0-885c-cbf6cef2976c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982763607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.982763607
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3404045557
Short name T649
Test name
Test status
Simulation time 360469756 ps
CPU time 2.82 seconds
Started Mar 26 02:04:52 PM PDT 24
Finished Mar 26 02:04:57 PM PDT 24
Peak memory 224320 kb
Host smart-cdc5335b-5131-4d23-bcfa-d93082818300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404045557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3404045557
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1946601472
Short name T955
Test name
Test status
Simulation time 3949467691 ps
CPU time 6.47 seconds
Started Mar 26 02:04:47 PM PDT 24
Finished Mar 26 02:04:54 PM PDT 24
Peak memory 218980 kb
Host smart-c08b5279-66b5-4ba1-a0c0-b5e428d89579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946601472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1946601472
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1903371593
Short name T511
Test name
Test status
Simulation time 879626979 ps
CPU time 6.68 seconds
Started Mar 26 02:04:47 PM PDT 24
Finished Mar 26 02:04:54 PM PDT 24
Peak memory 216744 kb
Host smart-07b29e8b-2434-4e49-9a33-9afd65f8d07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903371593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1903371593
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.972683824
Short name T711
Test name
Test status
Simulation time 501710985 ps
CPU time 4.55 seconds
Started Mar 26 02:04:48 PM PDT 24
Finished Mar 26 02:04:55 PM PDT 24
Peak memory 222636 kb
Host smart-f967f4df-beb3-4dcf-bbc6-de00a7bdaa5f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=972683824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.972683824
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1303735987
Short name T733
Test name
Test status
Simulation time 228279485071 ps
CPU time 106.47 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:06:45 PM PDT 24
Peak memory 235232 kb
Host smart-8fd12bac-b63f-47c1-b5c7-7f2d80c5d221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303735987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1303735987
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3093948466
Short name T439
Test name
Test status
Simulation time 58962339161 ps
CPU time 74.28 seconds
Started Mar 26 02:04:48 PM PDT 24
Finished Mar 26 02:06:04 PM PDT 24
Peak memory 216212 kb
Host smart-c65d4d8e-2e60-469f-b09a-cfa5111b6ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093948466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3093948466
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3822048576
Short name T274
Test name
Test status
Simulation time 4375581654 ps
CPU time 6.54 seconds
Started Mar 26 02:04:49 PM PDT 24
Finished Mar 26 02:04:59 PM PDT 24
Peak memory 216200 kb
Host smart-b6007d05-8251-4938-ab2d-fb7b5904e450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822048576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3822048576
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3090591666
Short name T872
Test name
Test status
Simulation time 18233210 ps
CPU time 1.06 seconds
Started Mar 26 02:04:48 PM PDT 24
Finished Mar 26 02:04:53 PM PDT 24
Peak memory 206904 kb
Host smart-a0b7222a-8404-453e-9c1b-0df1d2ae83c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090591666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3090591666
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2656658247
Short name T391
Test name
Test status
Simulation time 90168399 ps
CPU time 0.83 seconds
Started Mar 26 02:04:48 PM PDT 24
Finished Mar 26 02:04:53 PM PDT 24
Peak memory 205544 kb
Host smart-805f2406-845e-4d66-8385-4f45f2caac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656658247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2656658247
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.112857280
Short name T860
Test name
Test status
Simulation time 15294607299 ps
CPU time 16.36 seconds
Started Mar 26 02:04:50 PM PDT 24
Finished Mar 26 02:05:09 PM PDT 24
Peak memory 249744 kb
Host smart-5a949862-6ef3-4e5e-b908-fb344aee577a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112857280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.112857280
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.945481460
Short name T51
Test name
Test status
Simulation time 24788451 ps
CPU time 0.73 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:05:01 PM PDT 24
Peak memory 205056 kb
Host smart-953c3da7-b910-491d-b35b-283e70c3e13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945481460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.945481460
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1053173354
Short name T227
Test name
Test status
Simulation time 116281378 ps
CPU time 2.52 seconds
Started Mar 26 02:05:00 PM PDT 24
Finished Mar 26 02:05:03 PM PDT 24
Peak memory 224388 kb
Host smart-4c13200d-9229-4aad-baeb-ad955e69e9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053173354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1053173354
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3235807908
Short name T345
Test name
Test status
Simulation time 64218789 ps
CPU time 0.81 seconds
Started Mar 26 02:05:00 PM PDT 24
Finished Mar 26 02:05:01 PM PDT 24
Peak memory 206144 kb
Host smart-4ed6b986-786d-421d-98c4-2dc9026e2010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235807908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3235807908
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3826741776
Short name T756
Test name
Test status
Simulation time 33242369137 ps
CPU time 46.24 seconds
Started Mar 26 02:05:00 PM PDT 24
Finished Mar 26 02:05:47 PM PDT 24
Peak memory 240844 kb
Host smart-df14dbdf-4a7f-4829-be6d-7866ef2859ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826741776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3826741776
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2627091046
Short name T788
Test name
Test status
Simulation time 16379630013 ps
CPU time 158.95 seconds
Started Mar 26 02:05:01 PM PDT 24
Finished Mar 26 02:07:41 PM PDT 24
Peak memory 249156 kb
Host smart-2079149a-9560-4a85-bc44-d4a17d9fe888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627091046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2627091046
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3064504281
Short name T792
Test name
Test status
Simulation time 929001153 ps
CPU time 18.11 seconds
Started Mar 26 02:05:01 PM PDT 24
Finished Mar 26 02:05:20 PM PDT 24
Peak memory 240808 kb
Host smart-f9d84478-0be5-444d-8b34-912939e936e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064504281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3064504281
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4249242803
Short name T991
Test name
Test status
Simulation time 253732117 ps
CPU time 4.74 seconds
Started Mar 26 02:05:01 PM PDT 24
Finished Mar 26 02:05:06 PM PDT 24
Peak memory 233576 kb
Host smart-c07b5897-25a8-40ba-85e0-2a340eb9e775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249242803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4249242803
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3861883454
Short name T145
Test name
Test status
Simulation time 995400075 ps
CPU time 3.48 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:05:03 PM PDT 24
Peak memory 218220 kb
Host smart-a7056535-c3d8-4b44-bff2-fbd28eb2ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861883454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3861883454
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3403285032
Short name T257
Test name
Test status
Simulation time 195122176 ps
CPU time 3.87 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:05:04 PM PDT 24
Peak memory 221808 kb
Host smart-056a05c0-ccba-401e-9ca8-ac091b54ea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403285032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3403285032
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3044709665
Short name T343
Test name
Test status
Simulation time 1954016738 ps
CPU time 3.09 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:05:03 PM PDT 24
Peak memory 232536 kb
Host smart-4b6be2e6-ab2c-4c80-a2b7-dddae83a3bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044709665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3044709665
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2013236687
Short name T775
Test name
Test status
Simulation time 190343760 ps
CPU time 4.15 seconds
Started Mar 26 02:04:58 PM PDT 24
Finished Mar 26 02:05:03 PM PDT 24
Peak memory 222628 kb
Host smart-358ca87e-67dd-4783-8755-6ba2a6c6c882
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2013236687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2013236687
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.4231174308
Short name T956
Test name
Test status
Simulation time 168761431301 ps
CPU time 302.3 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:10:02 PM PDT 24
Peak memory 256948 kb
Host smart-43237ffc-b9b8-485d-81d1-eea1272d1103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231174308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.4231174308
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1340563425
Short name T308
Test name
Test status
Simulation time 790194977 ps
CPU time 5.68 seconds
Started Mar 26 02:05:00 PM PDT 24
Finished Mar 26 02:05:06 PM PDT 24
Peak memory 216192 kb
Host smart-ab4b3c6f-1e50-4916-9201-0b9b80207b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340563425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1340563425
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.483708455
Short name T726
Test name
Test status
Simulation time 1712793865 ps
CPU time 3.42 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:05:02 PM PDT 24
Peak memory 215904 kb
Host smart-f0bc37d6-0628-43ff-a29f-4962b3144303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483708455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.483708455
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3456905341
Short name T442
Test name
Test status
Simulation time 494792832 ps
CPU time 1.48 seconds
Started Mar 26 02:05:00 PM PDT 24
Finished Mar 26 02:05:02 PM PDT 24
Peak memory 216132 kb
Host smart-fc7f5a33-5f79-4ed0-b82d-b46b15f9d86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456905341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3456905341
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3164658505
Short name T793
Test name
Test status
Simulation time 73157230 ps
CPU time 0.84 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:05:01 PM PDT 24
Peak memory 205436 kb
Host smart-b0e8ec1a-72d0-417c-bb4f-8637ffadc649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164658505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3164658505
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1935132054
Short name T427
Test name
Test status
Simulation time 4816237406 ps
CPU time 15.21 seconds
Started Mar 26 02:05:01 PM PDT 24
Finished Mar 26 02:05:17 PM PDT 24
Peak memory 233676 kb
Host smart-6de76c93-91ce-4588-b810-2cb1c1f75bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935132054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1935132054
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.833637886
Short name T411
Test name
Test status
Simulation time 37435066 ps
CPU time 0.73 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:05:13 PM PDT 24
Peak memory 204484 kb
Host smart-23bec625-3272-4263-a611-cb69b4705e2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833637886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.833637886
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2005112696
Short name T786
Test name
Test status
Simulation time 445260122 ps
CPU time 4.34 seconds
Started Mar 26 02:05:15 PM PDT 24
Finished Mar 26 02:05:21 PM PDT 24
Peak memory 224132 kb
Host smart-0c072293-43f0-4a22-ba55-057ffe565a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005112696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2005112696
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1850062824
Short name T404
Test name
Test status
Simulation time 43754276 ps
CPU time 0.81 seconds
Started Mar 26 02:05:02 PM PDT 24
Finished Mar 26 02:05:03 PM PDT 24
Peak memory 206036 kb
Host smart-9e3f3f0a-882b-4559-9f30-dd86f832b59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850062824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1850062824
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.750147379
Short name T715
Test name
Test status
Simulation time 7328057799 ps
CPU time 42.37 seconds
Started Mar 26 02:05:15 PM PDT 24
Finished Mar 26 02:05:59 PM PDT 24
Peak memory 240764 kb
Host smart-0223d18c-a219-4a40-a622-fca7da759b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750147379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.750147379
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2279578386
Short name T605
Test name
Test status
Simulation time 46677276299 ps
CPU time 276.76 seconds
Started Mar 26 02:05:11 PM PDT 24
Finished Mar 26 02:09:48 PM PDT 24
Peak memory 265704 kb
Host smart-f73a5849-3196-45a4-970e-b4eb73bc1df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279578386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2279578386
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1498438672
Short name T290
Test name
Test status
Simulation time 56855555656 ps
CPU time 82.99 seconds
Started Mar 26 02:05:13 PM PDT 24
Finished Mar 26 02:06:36 PM PDT 24
Peak memory 249112 kb
Host smart-f6c8126f-71e3-4919-832c-56dc89458a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498438672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1498438672
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.41092473
Short name T746
Test name
Test status
Simulation time 3335530152 ps
CPU time 20.94 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:05:33 PM PDT 24
Peak memory 244616 kb
Host smart-1fa2cb0b-65a8-40be-ab6b-4d52af2c94af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41092473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.41092473
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.947935122
Short name T734
Test name
Test status
Simulation time 6716373500 ps
CPU time 16.83 seconds
Started Mar 26 02:05:13 PM PDT 24
Finished Mar 26 02:05:30 PM PDT 24
Peak memory 219988 kb
Host smart-9cc044d5-35ce-4e4b-928d-916415d38fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947935122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.947935122
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2822771342
Short name T44
Test name
Test status
Simulation time 6565250894 ps
CPU time 31.62 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:05:44 PM PDT 24
Peak memory 238568 kb
Host smart-9d0229a7-83ca-45db-b954-9e0183c5f82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822771342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2822771342
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1514787404
Short name T771
Test name
Test status
Simulation time 15578632083 ps
CPU time 14.35 seconds
Started Mar 26 02:05:11 PM PDT 24
Finished Mar 26 02:05:25 PM PDT 24
Peak memory 217644 kb
Host smart-2a48bd41-0dbd-4a25-9fed-da9c28e64d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514787404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1514787404
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.6970609
Short name T384
Test name
Test status
Simulation time 1646054244 ps
CPU time 6.94 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:05:07 PM PDT 24
Peak memory 222676 kb
Host smart-8fbd503b-3a41-40bb-8fba-b481b0447ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6970609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.6970609
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2550740618
Short name T681
Test name
Test status
Simulation time 469476664 ps
CPU time 4.26 seconds
Started Mar 26 02:05:11 PM PDT 24
Finished Mar 26 02:05:16 PM PDT 24
Peak memory 222660 kb
Host smart-ad6b21ec-6a03-4e3e-8ed2-e9eaca37766e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2550740618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2550740618
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1274410730
Short name T139
Test name
Test status
Simulation time 259094213 ps
CPU time 1.14 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:05:14 PM PDT 24
Peak memory 206672 kb
Host smart-97302b6a-8944-4ef2-a7fd-8e25c4d85f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274410730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1274410730
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2730141356
Short name T488
Test name
Test status
Simulation time 1951323440 ps
CPU time 30.72 seconds
Started Mar 26 02:05:00 PM PDT 24
Finished Mar 26 02:05:31 PM PDT 24
Peak memory 216144 kb
Host smart-5e94ff59-2a0b-4b71-8e6d-564787f600b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730141356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2730141356
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1097623465
Short name T601
Test name
Test status
Simulation time 6705690280 ps
CPU time 10.24 seconds
Started Mar 26 02:04:58 PM PDT 24
Finished Mar 26 02:05:08 PM PDT 24
Peak memory 216192 kb
Host smart-48b32002-319f-48f6-9cb1-b72276e5297e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097623465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1097623465
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.654089374
Short name T537
Test name
Test status
Simulation time 218024707 ps
CPU time 6.8 seconds
Started Mar 26 02:04:59 PM PDT 24
Finished Mar 26 02:05:06 PM PDT 24
Peak memory 216092 kb
Host smart-a745d2ef-348c-4c0f-ae06-b4625e7dc7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654089374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.654089374
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3371999409
Short name T433
Test name
Test status
Simulation time 320016829 ps
CPU time 0.98 seconds
Started Mar 26 02:04:58 PM PDT 24
Finished Mar 26 02:05:00 PM PDT 24
Peak memory 205532 kb
Host smart-a6e72f96-d2a3-447d-905a-6f5b8d9ab89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371999409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3371999409
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.374414467
Short name T631
Test name
Test status
Simulation time 10246691299 ps
CPU time 11.46 seconds
Started Mar 26 02:05:13 PM PDT 24
Finished Mar 26 02:05:24 PM PDT 24
Peak memory 219808 kb
Host smart-6bd4cb67-2c7d-40b8-aa43-afa7a8dd29a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374414467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.374414467
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1169095847
Short name T699
Test name
Test status
Simulation time 13271986 ps
CPU time 0.74 seconds
Started Mar 26 02:05:15 PM PDT 24
Finished Mar 26 02:05:18 PM PDT 24
Peak memory 204584 kb
Host smart-ddd9bcc3-7b80-44b9-9b9b-e0c32c74ec24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169095847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1169095847
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2516258147
Short name T505
Test name
Test status
Simulation time 5682499047 ps
CPU time 5.92 seconds
Started Mar 26 02:05:13 PM PDT 24
Finished Mar 26 02:05:19 PM PDT 24
Peak memory 234196 kb
Host smart-8062f9e4-85fd-4cb8-a08c-e9abb3267820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516258147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2516258147
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2564173053
Short name T278
Test name
Test status
Simulation time 31618299 ps
CPU time 0.73 seconds
Started Mar 26 02:05:10 PM PDT 24
Finished Mar 26 02:05:11 PM PDT 24
Peak memory 205564 kb
Host smart-fb01cc97-8e06-4870-8dd4-bd4a9affc2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564173053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2564173053
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3187555437
Short name T949
Test name
Test status
Simulation time 15991291169 ps
CPU time 29.75 seconds
Started Mar 26 02:05:15 PM PDT 24
Finished Mar 26 02:05:45 PM PDT 24
Peak memory 235308 kb
Host smart-8410d08a-d59d-473e-8f71-1ffa8115e427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187555437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3187555437
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3875677920
Short name T573
Test name
Test status
Simulation time 6717507251 ps
CPU time 44.34 seconds
Started Mar 26 02:05:14 PM PDT 24
Finished Mar 26 02:05:58 PM PDT 24
Peak memory 222760 kb
Host smart-9204eb4f-87f5-4f45-b653-e62e714af9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875677920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3875677920
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.395986313
Short name T352
Test name
Test status
Simulation time 10298052639 ps
CPU time 72.94 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:06:25 PM PDT 24
Peak memory 248864 kb
Host smart-4c0ee156-f314-4deb-8e81-a6c83ab6cb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395986313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.395986313
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2639916543
Short name T401
Test name
Test status
Simulation time 5603351465 ps
CPU time 15.87 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:05:28 PM PDT 24
Peak memory 239320 kb
Host smart-0dc6c3b6-e974-45f1-93d3-f6805fe0ba8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639916543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2639916543
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.725564675
Short name T606
Test name
Test status
Simulation time 367430002 ps
CPU time 3.25 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:05:16 PM PDT 24
Peak memory 218036 kb
Host smart-c078e46e-5ac5-4f22-b3d8-5e6631fddf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725564675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.725564675
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1953700364
Short name T953
Test name
Test status
Simulation time 12526387503 ps
CPU time 4.16 seconds
Started Mar 26 02:05:16 PM PDT 24
Finished Mar 26 02:05:21 PM PDT 24
Peak memory 218468 kb
Host smart-f0df856a-1214-4f78-9b4a-985ffd78ad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953700364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1953700364
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1317844558
Short name T675
Test name
Test status
Simulation time 5947215952 ps
CPU time 20.93 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:05:33 PM PDT 24
Peak memory 235420 kb
Host smart-6e5777d5-d8bd-4a18-b9f7-25c42689426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317844558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1317844558
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1316274026
Short name T195
Test name
Test status
Simulation time 7087703096 ps
CPU time 21.58 seconds
Started Mar 26 02:05:11 PM PDT 24
Finished Mar 26 02:05:33 PM PDT 24
Peak memory 229308 kb
Host smart-7595bc8a-57d7-4942-b65e-20bc97ef4ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316274026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1316274026
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1200436131
Short name T376
Test name
Test status
Simulation time 3432726061 ps
CPU time 4.37 seconds
Started Mar 26 02:05:14 PM PDT 24
Finished Mar 26 02:05:19 PM PDT 24
Peak memory 218404 kb
Host smart-4e4edebe-c90c-44c8-9372-0e1b9d35eb7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1200436131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1200436131
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2432344016
Short name T142
Test name
Test status
Simulation time 31964819437 ps
CPU time 107.5 seconds
Started Mar 26 02:05:13 PM PDT 24
Finished Mar 26 02:07:00 PM PDT 24
Peak memory 265700 kb
Host smart-ab0b7349-7330-4303-a9bc-864bfb35841d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432344016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2432344016
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.144697070
Short name T728
Test name
Test status
Simulation time 30958346128 ps
CPU time 47.16 seconds
Started Mar 26 02:05:14 PM PDT 24
Finished Mar 26 02:06:01 PM PDT 24
Peak memory 216184 kb
Host smart-13528fef-d999-4ac5-98b1-3e81638a850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144697070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.144697070
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3443712655
Short name T904
Test name
Test status
Simulation time 5618989807 ps
CPU time 8.28 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:05:21 PM PDT 24
Peak memory 216172 kb
Host smart-b7277101-de65-4293-98d4-cb6829513ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443712655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3443712655
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.754072463
Short name T428
Test name
Test status
Simulation time 62558603 ps
CPU time 1.67 seconds
Started Mar 26 02:05:14 PM PDT 24
Finished Mar 26 02:05:16 PM PDT 24
Peak memory 216048 kb
Host smart-e9dfe572-c6a1-4410-8ad6-e71a00a5b524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754072463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.754072463
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1996757851
Short name T380
Test name
Test status
Simulation time 1511570388 ps
CPU time 1.02 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:05:13 PM PDT 24
Peak memory 205764 kb
Host smart-682df421-1cdc-4f9b-8e89-757f5aed45be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996757851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1996757851
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.390361434
Short name T975
Test name
Test status
Simulation time 105656443265 ps
CPU time 34.35 seconds
Started Mar 26 02:05:11 PM PDT 24
Finished Mar 26 02:05:46 PM PDT 24
Peak memory 232828 kb
Host smart-b039330d-2fca-41cc-9990-56170a0f2d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390361434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.390361434
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1342505405
Short name T694
Test name
Test status
Simulation time 12273465 ps
CPU time 0.72 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:27 PM PDT 24
Peak memory 205068 kb
Host smart-f774c07e-5315-45e7-8fad-2341fd376fc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342505405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1342505405
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1825477061
Short name T779
Test name
Test status
Simulation time 110773937 ps
CPU time 2.57 seconds
Started Mar 26 02:05:24 PM PDT 24
Finished Mar 26 02:05:27 PM PDT 24
Peak memory 233112 kb
Host smart-43a2448b-77da-44ef-ba0a-b6eb2009f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825477061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1825477061
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2283854909
Short name T920
Test name
Test status
Simulation time 24789044 ps
CPU time 0.77 seconds
Started Mar 26 02:05:13 PM PDT 24
Finished Mar 26 02:05:13 PM PDT 24
Peak memory 205100 kb
Host smart-21b85d7d-ec96-4325-b51e-cf3286bb7c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283854909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2283854909
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1359685350
Short name T859
Test name
Test status
Simulation time 40962525963 ps
CPU time 98.37 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:07:04 PM PDT 24
Peak memory 249108 kb
Host smart-88361769-5115-4c8a-86a7-5f48d2fc8800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359685350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1359685350
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3269183319
Short name T260
Test name
Test status
Simulation time 24571514602 ps
CPU time 148.33 seconds
Started Mar 26 02:05:25 PM PDT 24
Finished Mar 26 02:07:53 PM PDT 24
Peak memory 255816 kb
Host smart-c62dbcf9-e168-45f6-b9e5-6d3dec09060e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269183319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3269183319
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3343054712
Short name T462
Test name
Test status
Simulation time 1706732089 ps
CPU time 37.41 seconds
Started Mar 26 02:05:25 PM PDT 24
Finished Mar 26 02:06:03 PM PDT 24
Peak memory 257088 kb
Host smart-232d3e0d-d50b-45a4-a6ea-536bbdd47d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343054712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3343054712
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3012648546
Short name T630
Test name
Test status
Simulation time 2923269561 ps
CPU time 18.3 seconds
Started Mar 26 02:05:23 PM PDT 24
Finished Mar 26 02:05:42 PM PDT 24
Peak memory 221548 kb
Host smart-6da928e9-b69f-40c5-b2f5-9b6edd5cb710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012648546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3012648546
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3473872036
Short name T687
Test name
Test status
Simulation time 937161660 ps
CPU time 5.86 seconds
Started Mar 26 02:05:24 PM PDT 24
Finished Mar 26 02:05:30 PM PDT 24
Peak memory 233968 kb
Host smart-766bd5e2-42c7-4faa-85f1-dd36fa5a9e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473872036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3473872036
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.712726178
Short name T230
Test name
Test status
Simulation time 1534044806 ps
CPU time 11.61 seconds
Started Mar 26 02:05:24 PM PDT 24
Finished Mar 26 02:05:36 PM PDT 24
Peak memory 226668 kb
Host smart-3c69a99d-b650-41d7-b824-4a5b698ffa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712726178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.712726178
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2627511691
Short name T454
Test name
Test status
Simulation time 8286465033 ps
CPU time 23.55 seconds
Started Mar 26 02:05:23 PM PDT 24
Finished Mar 26 02:05:47 PM PDT 24
Peak memory 233572 kb
Host smart-c1b62138-3ff5-4186-b46d-b133631acb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627511691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2627511691
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2745994023
Short name T884
Test name
Test status
Simulation time 7372080561 ps
CPU time 23.79 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:50 PM PDT 24
Peak memory 237348 kb
Host smart-36057488-a0c5-463e-b26c-5310dd16d963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745994023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2745994023
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.367066071
Short name T322
Test name
Test status
Simulation time 108437809 ps
CPU time 3.81 seconds
Started Mar 26 02:05:25 PM PDT 24
Finished Mar 26 02:05:29 PM PDT 24
Peak memory 221992 kb
Host smart-81379191-aa8f-491f-9c77-956edfb1669d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=367066071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.367066071
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.4270073229
Short name T176
Test name
Test status
Simulation time 147955533123 ps
CPU time 273.86 seconds
Started Mar 26 02:05:25 PM PDT 24
Finished Mar 26 02:09:59 PM PDT 24
Peak memory 251788 kb
Host smart-55affdce-6a1c-43a5-ab8a-6202ec599eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270073229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.4270073229
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3291126683
Short name T875
Test name
Test status
Simulation time 4605556438 ps
CPU time 20.7 seconds
Started Mar 26 02:05:11 PM PDT 24
Finished Mar 26 02:05:32 PM PDT 24
Peak memory 216076 kb
Host smart-2ee73154-7892-4b3e-9d41-9c0f4c8004d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291126683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3291126683
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1095262849
Short name T666
Test name
Test status
Simulation time 9912009583 ps
CPU time 9.78 seconds
Started Mar 26 02:05:14 PM PDT 24
Finished Mar 26 02:05:23 PM PDT 24
Peak memory 216156 kb
Host smart-29c32e43-e55b-4ba9-a1a0-f8d8c50af29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095262849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1095262849
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3892141366
Short name T469
Test name
Test status
Simulation time 196391442 ps
CPU time 6.26 seconds
Started Mar 26 02:05:17 PM PDT 24
Finished Mar 26 02:05:23 PM PDT 24
Peak memory 217336 kb
Host smart-add22419-bb5b-4b97-95dd-ad795e97838d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892141366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3892141366
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1242454412
Short name T636
Test name
Test status
Simulation time 98682865 ps
CPU time 0.82 seconds
Started Mar 26 02:05:12 PM PDT 24
Finished Mar 26 02:05:13 PM PDT 24
Peak memory 205456 kb
Host smart-ca123257-a7b1-4273-ac88-97084311fe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242454412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1242454412
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.925693529
Short name T708
Test name
Test status
Simulation time 8512280113 ps
CPU time 9.22 seconds
Started Mar 26 02:05:24 PM PDT 24
Finished Mar 26 02:05:34 PM PDT 24
Peak memory 216292 kb
Host smart-ab2c9908-fa9d-4501-ad71-2e280b11ae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925693529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.925693529
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.925632606
Short name T815
Test name
Test status
Simulation time 13830086 ps
CPU time 0.74 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:27 PM PDT 24
Peak memory 205136 kb
Host smart-31dc23ea-c7a0-41e4-9936-e117ae3eb37f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925632606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.925632606
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2888648907
Short name T898
Test name
Test status
Simulation time 2435368213 ps
CPU time 7.2 seconds
Started Mar 26 02:05:25 PM PDT 24
Finished Mar 26 02:05:32 PM PDT 24
Peak memory 233548 kb
Host smart-6e58a2ad-0f32-4e2e-937d-a8eac2ba13fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888648907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2888648907
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.621231282
Short name T704
Test name
Test status
Simulation time 49776669 ps
CPU time 0.78 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:27 PM PDT 24
Peak memory 206036 kb
Host smart-db4190a6-12e1-4fcd-a973-dd40e6dc3e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621231282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.621231282
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3409971580
Short name T921
Test name
Test status
Simulation time 56137143914 ps
CPU time 104.12 seconds
Started Mar 26 02:05:27 PM PDT 24
Finished Mar 26 02:07:12 PM PDT 24
Peak memory 233688 kb
Host smart-26a8095b-b7dc-4835-9788-7b204dc2ec50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409971580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3409971580
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1060800293
Short name T581
Test name
Test status
Simulation time 9253075194 ps
CPU time 10.79 seconds
Started Mar 26 02:05:27 PM PDT 24
Finished Mar 26 02:05:38 PM PDT 24
Peak memory 239972 kb
Host smart-8eab005a-19ff-4ce7-b365-1e908915f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060800293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1060800293
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.593653065
Short name T797
Test name
Test status
Simulation time 8662321014 ps
CPU time 9.86 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:37 PM PDT 24
Peak memory 233432 kb
Host smart-8944763b-76c7-4801-84aa-902265b1ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593653065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.593653065
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.578173875
Short name T379
Test name
Test status
Simulation time 4371119307 ps
CPU time 8.87 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:35 PM PDT 24
Peak memory 224432 kb
Host smart-ac72437a-6020-48bd-bdfa-afdeed80ac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578173875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.578173875
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3939672556
Short name T738
Test name
Test status
Simulation time 15714567468 ps
CPU time 15.98 seconds
Started Mar 26 02:05:25 PM PDT 24
Finished Mar 26 02:05:41 PM PDT 24
Peak memory 236784 kb
Host smart-25356124-ea10-406e-9c98-ce54465b9d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939672556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3939672556
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1079329787
Short name T541
Test name
Test status
Simulation time 1441183870 ps
CPU time 6.34 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:32 PM PDT 24
Peak memory 216896 kb
Host smart-1fd1e024-e32e-4b1d-b555-dc4ef5efbd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079329787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1079329787
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.818686080
Short name T515
Test name
Test status
Simulation time 131090406 ps
CPU time 3.31 seconds
Started Mar 26 02:05:28 PM PDT 24
Finished Mar 26 02:05:31 PM PDT 24
Peak memory 219624 kb
Host smart-c2a44bd3-1828-49fd-8e00-59cd9488db98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=818686080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.818686080
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2140767978
Short name T409
Test name
Test status
Simulation time 56345509157 ps
CPU time 166.88 seconds
Started Mar 26 02:05:27 PM PDT 24
Finished Mar 26 02:08:14 PM PDT 24
Peak memory 257328 kb
Host smart-9be42177-adf8-4bfb-ae2c-f45a46fb799f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140767978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2140767978
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.163472927
Short name T527
Test name
Test status
Simulation time 4977425309 ps
CPU time 30.19 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:57 PM PDT 24
Peak memory 216080 kb
Host smart-2c38153a-1cc0-4abc-9251-5481a529c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163472927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.163472927
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.914017600
Short name T724
Test name
Test status
Simulation time 7391675165 ps
CPU time 12.66 seconds
Started Mar 26 02:05:25 PM PDT 24
Finished Mar 26 02:05:37 PM PDT 24
Peak memory 216096 kb
Host smart-0de0474d-1d48-4faa-833d-2b9ffd1342c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914017600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.914017600
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3255300111
Short name T286
Test name
Test status
Simulation time 705671193 ps
CPU time 1.37 seconds
Started Mar 26 02:05:25 PM PDT 24
Finished Mar 26 02:05:26 PM PDT 24
Peak memory 207924 kb
Host smart-8c62b381-6d30-40e9-960e-13c9c8f3f415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255300111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3255300111
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3531881082
Short name T776
Test name
Test status
Simulation time 155024610 ps
CPU time 0.93 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:27 PM PDT 24
Peak memory 206376 kb
Host smart-73e13a20-ff68-42b7-a4b1-cdb84b3aeb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531881082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3531881082
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3385013818
Short name T697
Test name
Test status
Simulation time 731461213 ps
CPU time 7.96 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:34 PM PDT 24
Peak memory 233596 kb
Host smart-b8e86d27-8d16-4ba4-a813-8052be7a8781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385013818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3385013818
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.918806161
Short name T661
Test name
Test status
Simulation time 10976414 ps
CPU time 0.72 seconds
Started Mar 26 02:05:38 PM PDT 24
Finished Mar 26 02:05:39 PM PDT 24
Peak memory 205180 kb
Host smart-8fc1021c-532a-400f-9f30-ff7a1142af51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918806161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.918806161
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4245307600
Short name T685
Test name
Test status
Simulation time 3235129688 ps
CPU time 3.82 seconds
Started Mar 26 02:05:36 PM PDT 24
Finished Mar 26 02:05:40 PM PDT 24
Peak memory 233168 kb
Host smart-ad699331-8da8-44b3-b0d9-e76ecf947b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245307600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4245307600
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.781497047
Short name T863
Test name
Test status
Simulation time 23878249 ps
CPU time 0.81 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:27 PM PDT 24
Peak memory 206176 kb
Host smart-9866628b-bb76-4759-86d3-bdcb954654f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781497047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.781497047
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1254022148
Short name T959
Test name
Test status
Simulation time 7460849287 ps
CPU time 41.39 seconds
Started Mar 26 02:05:41 PM PDT 24
Finished Mar 26 02:06:23 PM PDT 24
Peak memory 249004 kb
Host smart-51cd478c-86bf-48db-b900-38a8d2d58949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254022148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1254022148
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3904457110
Short name T523
Test name
Test status
Simulation time 37018234073 ps
CPU time 110.65 seconds
Started Mar 26 02:05:36 PM PDT 24
Finished Mar 26 02:07:27 PM PDT 24
Peak memory 249108 kb
Host smart-61ef03d8-5961-4695-8521-8db2eb2362ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904457110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3904457110
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.131621144
Short name T271
Test name
Test status
Simulation time 15075638812 ps
CPU time 137.45 seconds
Started Mar 26 02:05:42 PM PDT 24
Finished Mar 26 02:08:00 PM PDT 24
Peak memory 254324 kb
Host smart-ffaff595-c89e-4b36-8251-9681b0e856ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131621144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.131621144
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3954962173
Short name T268
Test name
Test status
Simulation time 7910544830 ps
CPU time 30.29 seconds
Started Mar 26 02:05:40 PM PDT 24
Finished Mar 26 02:06:11 PM PDT 24
Peak memory 240836 kb
Host smart-46234559-85f8-44df-98a4-1f108d9f2f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954962173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3954962173
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.62106943
Short name T682
Test name
Test status
Simulation time 3777502775 ps
CPU time 14.04 seconds
Started Mar 26 02:05:29 PM PDT 24
Finished Mar 26 02:05:43 PM PDT 24
Peak memory 238440 kb
Host smart-f2340aa6-bdc7-4a99-98c4-a3328624f5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62106943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.62106943
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.809647443
Short name T185
Test name
Test status
Simulation time 26432867883 ps
CPU time 23.63 seconds
Started Mar 26 02:05:29 PM PDT 24
Finished Mar 26 02:05:53 PM PDT 24
Peak memory 236652 kb
Host smart-451b0b1b-5bee-481b-b6f9-4d842dd2afe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809647443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.809647443
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3916510315
Short name T590
Test name
Test status
Simulation time 15102665444 ps
CPU time 35.48 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:06:02 PM PDT 24
Peak memory 236888 kb
Host smart-3f420ae3-ae5f-47df-8685-eabde7923a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916510315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3916510315
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3782504690
Short name T796
Test name
Test status
Simulation time 43405366 ps
CPU time 2.3 seconds
Started Mar 26 02:05:27 PM PDT 24
Finished Mar 26 02:05:29 PM PDT 24
Peak memory 218356 kb
Host smart-103b6f9d-b17f-4693-89d5-1d3329f70f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782504690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3782504690
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1749425824
Short name T117
Test name
Test status
Simulation time 427392274 ps
CPU time 3.66 seconds
Started Mar 26 02:05:37 PM PDT 24
Finished Mar 26 02:05:40 PM PDT 24
Peak memory 222148 kb
Host smart-8ebc5a3c-9b40-48f9-82ae-11675dfb58d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1749425824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1749425824
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3657440295
Short name T478
Test name
Test status
Simulation time 26794579690 ps
CPU time 207.74 seconds
Started Mar 26 02:05:41 PM PDT 24
Finished Mar 26 02:09:09 PM PDT 24
Peak memory 260532 kb
Host smart-2f896dda-c733-4112-9ecd-ff609e89972a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657440295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3657440295
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.131453734
Short name T627
Test name
Test status
Simulation time 10873396350 ps
CPU time 65.86 seconds
Started Mar 26 02:05:28 PM PDT 24
Finished Mar 26 02:06:34 PM PDT 24
Peak memory 216196 kb
Host smart-221ecb45-7df2-4dfd-aa65-fa25da101a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131453734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.131453734
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.797631723
Short name T651
Test name
Test status
Simulation time 1890884921 ps
CPU time 9.9 seconds
Started Mar 26 02:05:26 PM PDT 24
Finished Mar 26 02:05:36 PM PDT 24
Peak memory 216112 kb
Host smart-2224c030-79d2-43aa-b93d-699c4ab98233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797631723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.797631723
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3373483294
Short name T421
Test name
Test status
Simulation time 567829446 ps
CPU time 2.62 seconds
Started Mar 26 02:05:27 PM PDT 24
Finished Mar 26 02:05:30 PM PDT 24
Peak memory 216052 kb
Host smart-b2009035-1e53-4976-ad07-7c645175ad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373483294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3373483294
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.573716703
Short name T640
Test name
Test status
Simulation time 82541422 ps
CPU time 1.06 seconds
Started Mar 26 02:05:27 PM PDT 24
Finished Mar 26 02:05:28 PM PDT 24
Peak memory 206492 kb
Host smart-9d20245e-e6aa-4e2a-8e5a-3b3bd376f502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573716703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.573716703
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1413468554
Short name T180
Test name
Test status
Simulation time 55071958463 ps
CPU time 42.29 seconds
Started Mar 26 02:05:27 PM PDT 24
Finished Mar 26 02:06:09 PM PDT 24
Peak memory 248976 kb
Host smart-deca8bdb-10f9-4f13-bba4-1f6ff0ce7327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413468554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1413468554
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1090845979
Short name T628
Test name
Test status
Simulation time 40918056 ps
CPU time 0.72 seconds
Started Mar 26 02:05:36 PM PDT 24
Finished Mar 26 02:05:36 PM PDT 24
Peak memory 205060 kb
Host smart-65ff7fd3-ec6e-4d63-a6b7-80947aaf2a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090845979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1090845979
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2468512327
Short name T386
Test name
Test status
Simulation time 329738158 ps
CPU time 4.1 seconds
Started Mar 26 02:05:37 PM PDT 24
Finished Mar 26 02:05:42 PM PDT 24
Peak memory 224308 kb
Host smart-760513d0-7dd5-4a7f-b32f-3bf992adc310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468512327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2468512327
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3379176087
Short name T422
Test name
Test status
Simulation time 19802549 ps
CPU time 0.79 seconds
Started Mar 26 02:05:42 PM PDT 24
Finished Mar 26 02:05:43 PM PDT 24
Peak memory 205236 kb
Host smart-379e8306-2ef0-4ac4-ad74-4c65e00bf016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379176087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3379176087
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1712154989
Short name T976
Test name
Test status
Simulation time 27635691760 ps
CPU time 76.06 seconds
Started Mar 26 02:05:40 PM PDT 24
Finished Mar 26 02:06:57 PM PDT 24
Peak memory 251768 kb
Host smart-0650f971-3002-42e8-aa0e-365c14fd3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712154989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1712154989
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2411318220
Short name T306
Test name
Test status
Simulation time 12775854798 ps
CPU time 89.86 seconds
Started Mar 26 02:05:36 PM PDT 24
Finished Mar 26 02:07:06 PM PDT 24
Peak memory 262388 kb
Host smart-bb4adc16-e315-446a-bd61-0d542933fda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411318220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2411318220
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1549856756
Short name T868
Test name
Test status
Simulation time 43017504165 ps
CPU time 259.62 seconds
Started Mar 26 02:05:35 PM PDT 24
Finished Mar 26 02:09:55 PM PDT 24
Peak memory 256388 kb
Host smart-9b2ff451-c9f1-4517-95c6-bd5a35184dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549856756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1549856756
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.113580452
Short name T338
Test name
Test status
Simulation time 465265571 ps
CPU time 11.2 seconds
Started Mar 26 02:05:41 PM PDT 24
Finished Mar 26 02:05:52 PM PDT 24
Peak memory 240720 kb
Host smart-4376b1f2-1d06-4fc6-8435-c1b910721259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113580452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.113580452
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1888337381
Short name T619
Test name
Test status
Simulation time 877713641 ps
CPU time 4.77 seconds
Started Mar 26 02:05:42 PM PDT 24
Finished Mar 26 02:05:47 PM PDT 24
Peak memory 237860 kb
Host smart-5e72bfca-118f-4155-96b5-14bb451848bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888337381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1888337381
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3512693764
Short name T368
Test name
Test status
Simulation time 22408374387 ps
CPU time 38.97 seconds
Started Mar 26 02:05:36 PM PDT 24
Finished Mar 26 02:06:15 PM PDT 24
Peak memory 237336 kb
Host smart-1b4174b1-7cec-42cd-902c-e9fc45f4727f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512693764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3512693764
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1915340037
Short name T822
Test name
Test status
Simulation time 34010491260 ps
CPU time 28.69 seconds
Started Mar 26 02:05:42 PM PDT 24
Finished Mar 26 02:06:11 PM PDT 24
Peak memory 234524 kb
Host smart-6cef4e3d-41a3-4ff6-b1c6-557b3a56bfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915340037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1915340037
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2664569879
Short name T829
Test name
Test status
Simulation time 562637748 ps
CPU time 5.4 seconds
Started Mar 26 02:05:37 PM PDT 24
Finished Mar 26 02:05:43 PM PDT 24
Peak memory 224376 kb
Host smart-fcbcbdaa-7a80-4ea8-a9e5-43e8e558327e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664569879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2664569879
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3725528124
Short name T596
Test name
Test status
Simulation time 491873172 ps
CPU time 4.46 seconds
Started Mar 26 02:05:34 PM PDT 24
Finished Mar 26 02:05:39 PM PDT 24
Peak memory 219920 kb
Host smart-c7a93437-f89f-42af-a2a3-9f53514c4445
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3725528124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3725528124
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1847206282
Short name T250
Test name
Test status
Simulation time 5049731992 ps
CPU time 93.99 seconds
Started Mar 26 02:05:37 PM PDT 24
Finished Mar 26 02:07:12 PM PDT 24
Peak memory 267280 kb
Host smart-dbc593db-4465-4f1e-b6ce-3ef3a55adf22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847206282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1847206282
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2666073067
Short name T567
Test name
Test status
Simulation time 23202470843 ps
CPU time 28.47 seconds
Started Mar 26 02:05:40 PM PDT 24
Finished Mar 26 02:06:09 PM PDT 24
Peak memory 216040 kb
Host smart-fcd6a473-4c79-45cf-be8d-5487aa3a2ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666073067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2666073067
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1131294527
Short name T497
Test name
Test status
Simulation time 10758771702 ps
CPU time 29.77 seconds
Started Mar 26 02:05:36 PM PDT 24
Finished Mar 26 02:06:06 PM PDT 24
Peak memory 216156 kb
Host smart-bc928c06-f860-4889-9582-e2d28cd382e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131294527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1131294527
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1802321987
Short name T539
Test name
Test status
Simulation time 130415055 ps
CPU time 1.08 seconds
Started Mar 26 02:05:36 PM PDT 24
Finished Mar 26 02:05:37 PM PDT 24
Peak memory 206748 kb
Host smart-10db26fa-a096-426f-bd99-fa2a952630a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802321987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1802321987
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1303080918
Short name T16
Test name
Test status
Simulation time 69025941 ps
CPU time 0.93 seconds
Started Mar 26 02:05:35 PM PDT 24
Finished Mar 26 02:05:36 PM PDT 24
Peak memory 205544 kb
Host smart-1ec39b6c-4068-4ace-a972-5db04464700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303080918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1303080918
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1286464948
Short name T490
Test name
Test status
Simulation time 2176576585 ps
CPU time 7.84 seconds
Started Mar 26 02:05:37 PM PDT 24
Finished Mar 26 02:05:44 PM PDT 24
Peak memory 229032 kb
Host smart-f6111bb8-eedd-43e3-9f2b-4e545e7ae5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286464948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1286464948
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1643876525
Short name T946
Test name
Test status
Simulation time 38093714 ps
CPU time 0.73 seconds
Started Mar 26 02:01:24 PM PDT 24
Finished Mar 26 02:01:25 PM PDT 24
Peak memory 205136 kb
Host smart-b11e87f8-9ea2-4a61-b0be-f853b0333ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643876525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
643876525
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2833633259
Short name T485
Test name
Test status
Simulation time 182202430 ps
CPU time 3.94 seconds
Started Mar 26 02:01:25 PM PDT 24
Finished Mar 26 02:01:29 PM PDT 24
Peak memory 233100 kb
Host smart-7553250b-3fc6-4e1b-9e4c-75e9aa9b1a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833633259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2833633259
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2182904535
Short name T610
Test name
Test status
Simulation time 50843956 ps
CPU time 0.79 seconds
Started Mar 26 02:01:14 PM PDT 24
Finished Mar 26 02:01:15 PM PDT 24
Peak memory 205516 kb
Host smart-a9e03f98-e8d0-4309-85ef-7f9f6914fb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182904535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2182904535
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3683028386
Short name T740
Test name
Test status
Simulation time 21460339675 ps
CPU time 95.22 seconds
Started Mar 26 02:01:34 PM PDT 24
Finished Mar 26 02:03:10 PM PDT 24
Peak memory 251552 kb
Host smart-05f0b8a4-5cba-42f3-867a-dc875529a5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683028386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3683028386
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2295936909
Short name T514
Test name
Test status
Simulation time 22840480930 ps
CPU time 71.98 seconds
Started Mar 26 02:01:25 PM PDT 24
Finished Mar 26 02:02:37 PM PDT 24
Peak memory 253496 kb
Host smart-901b818b-a196-4c1d-b458-737cfc9595c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295936909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2295936909
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1688195655
Short name T172
Test name
Test status
Simulation time 114714997400 ps
CPU time 235.76 seconds
Started Mar 26 02:01:27 PM PDT 24
Finished Mar 26 02:05:24 PM PDT 24
Peak memory 263916 kb
Host smart-8ab68459-435c-404f-9e56-012ec0de9d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688195655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1688195655
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.410347734
Short name T118
Test name
Test status
Simulation time 803620996 ps
CPU time 6.31 seconds
Started Mar 26 02:01:31 PM PDT 24
Finished Mar 26 02:01:37 PM PDT 24
Peak memory 232408 kb
Host smart-72fd369e-6cec-4ba3-8d1a-a2825ce7fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410347734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.410347734
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3317334190
Short name T633
Test name
Test status
Simulation time 730963998 ps
CPU time 3.09 seconds
Started Mar 26 02:01:34 PM PDT 24
Finished Mar 26 02:01:38 PM PDT 24
Peak memory 224352 kb
Host smart-b5df5de3-6505-4bbb-8687-fe26e678e62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317334190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3317334190
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4005541987
Short name T645
Test name
Test status
Simulation time 332678699 ps
CPU time 3.99 seconds
Started Mar 26 02:01:29 PM PDT 24
Finished Mar 26 02:01:33 PM PDT 24
Peak memory 218884 kb
Host smart-bd56bec1-8f5f-48ee-baf9-63c04eb60ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005541987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4005541987
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2152887536
Short name T320
Test name
Test status
Simulation time 29452019 ps
CPU time 1.1 seconds
Started Mar 26 02:01:13 PM PDT 24
Finished Mar 26 02:01:15 PM PDT 24
Peak memory 216508 kb
Host smart-1cdedfda-6967-485c-a4b5-e30501bdf56a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152887536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2152887536
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.895486457
Short name T595
Test name
Test status
Simulation time 21229377294 ps
CPU time 48.82 seconds
Started Mar 26 02:01:13 PM PDT 24
Finished Mar 26 02:02:02 PM PDT 24
Peak memory 246596 kb
Host smart-5392d40f-5dfe-4102-9790-233d1f67a85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895486457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
895486457
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1564537376
Short name T12
Test name
Test status
Simulation time 15782467242 ps
CPU time 16.48 seconds
Started Mar 26 02:01:13 PM PDT 24
Finished Mar 26 02:01:30 PM PDT 24
Peak memory 236064 kb
Host smart-b3b303d3-47ff-42ad-b1a9-fbb972c25298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564537376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1564537376
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2970813952
Short name T621
Test name
Test status
Simulation time 36720136 ps
CPU time 0.77 seconds
Started Mar 26 02:01:12 PM PDT 24
Finished Mar 26 02:01:14 PM PDT 24
Peak memory 216108 kb
Host smart-5ce76d69-1003-4c5a-adf7-721b52040d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970813952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2970813952
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1037233891
Short name T292
Test name
Test status
Simulation time 614509876 ps
CPU time 3.57 seconds
Started Mar 26 02:01:26 PM PDT 24
Finished Mar 26 02:01:30 PM PDT 24
Peak memory 218784 kb
Host smart-c312af48-6971-466a-91e8-770cd52f30a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1037233891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1037233891
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2113426218
Short name T54
Test name
Test status
Simulation time 66099560 ps
CPU time 0.97 seconds
Started Mar 26 02:01:25 PM PDT 24
Finished Mar 26 02:01:26 PM PDT 24
Peak memory 234476 kb
Host smart-abeee2c6-62c9-4b4b-90c8-48360ae0fc50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113426218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2113426218
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.196554937
Short name T518
Test name
Test status
Simulation time 1204354074 ps
CPU time 13.88 seconds
Started Mar 26 02:01:15 PM PDT 24
Finished Mar 26 02:01:29 PM PDT 24
Peak memory 216196 kb
Host smart-f5ea34d4-998e-4208-99e8-85d1411b307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196554937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.196554937
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3662353908
Short name T529
Test name
Test status
Simulation time 711113802 ps
CPU time 5.4 seconds
Started Mar 26 02:01:17 PM PDT 24
Finished Mar 26 02:01:22 PM PDT 24
Peak memory 216216 kb
Host smart-456e590f-9456-46c1-ae92-9e6d633cc121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662353908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3662353908
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4142417127
Short name T836
Test name
Test status
Simulation time 462050461 ps
CPU time 2.17 seconds
Started Mar 26 02:01:13 PM PDT 24
Finished Mar 26 02:01:15 PM PDT 24
Peak memory 216052 kb
Host smart-59729ac2-3178-47a9-8100-b7821ec2acae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142417127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4142417127
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4249948643
Short name T311
Test name
Test status
Simulation time 63467100 ps
CPU time 0.75 seconds
Started Mar 26 02:01:13 PM PDT 24
Finished Mar 26 02:01:14 PM PDT 24
Peak memory 205472 kb
Host smart-67eec4b6-c095-479f-b102-623020aed717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249948643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4249948643
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2589900175
Short name T783
Test name
Test status
Simulation time 13513737360 ps
CPU time 39.33 seconds
Started Mar 26 02:01:27 PM PDT 24
Finished Mar 26 02:02:07 PM PDT 24
Peak memory 229552 kb
Host smart-3124188a-72e6-4972-b866-9dd1335c08e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589900175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2589900175
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2139642587
Short name T323
Test name
Test status
Simulation time 14021159 ps
CPU time 0.78 seconds
Started Mar 26 02:05:56 PM PDT 24
Finished Mar 26 02:05:57 PM PDT 24
Peak memory 204432 kb
Host smart-14cbe318-121e-40b0-b3b6-d234f0abb49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139642587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2139642587
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2202512871
Short name T585
Test name
Test status
Simulation time 55540955 ps
CPU time 2.21 seconds
Started Mar 26 02:05:35 PM PDT 24
Finished Mar 26 02:05:38 PM PDT 24
Peak memory 218304 kb
Host smart-d383db55-6208-4c50-8389-05a80b144eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202512871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2202512871
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2493792670
Short name T847
Test name
Test status
Simulation time 16161265 ps
CPU time 0.79 seconds
Started Mar 26 02:05:36 PM PDT 24
Finished Mar 26 02:05:37 PM PDT 24
Peak memory 205116 kb
Host smart-8febce0f-7ba9-424b-b502-cffc0941020d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493792670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2493792670
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.302473731
Short name T316
Test name
Test status
Simulation time 159565912893 ps
CPU time 209.29 seconds
Started Mar 26 02:05:47 PM PDT 24
Finished Mar 26 02:09:17 PM PDT 24
Peak memory 252100 kb
Host smart-5c77918f-d119-4281-b281-6107ae40d086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302473731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.302473731
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.939539577
Short name T861
Test name
Test status
Simulation time 125358939648 ps
CPU time 92.92 seconds
Started Mar 26 02:05:46 PM PDT 24
Finished Mar 26 02:07:19 PM PDT 24
Peak memory 235684 kb
Host smart-3edb65b4-9509-412a-b882-86b2270c7a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939539577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.939539577
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2783516335
Short name T18
Test name
Test status
Simulation time 65586041596 ps
CPU time 70.57 seconds
Started Mar 26 02:05:48 PM PDT 24
Finished Mar 26 02:06:58 PM PDT 24
Peak memory 240088 kb
Host smart-8b5779ed-efdc-491d-9eb1-6c039713178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783516335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2783516335
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2534419159
Short name T453
Test name
Test status
Simulation time 1136408317 ps
CPU time 10.88 seconds
Started Mar 26 02:05:52 PM PDT 24
Finished Mar 26 02:06:03 PM PDT 24
Peak memory 234940 kb
Host smart-341b9a80-6b94-4014-9cf5-455df16e79f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534419159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2534419159
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4013732886
Short name T580
Test name
Test status
Simulation time 5370007876 ps
CPU time 9.21 seconds
Started Mar 26 02:05:37 PM PDT 24
Finished Mar 26 02:05:47 PM PDT 24
Peak memory 220124 kb
Host smart-f0799e56-3dff-4a36-b520-00333a1d04b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013732886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4013732886
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.796357891
Short name T78
Test name
Test status
Simulation time 19477421376 ps
CPU time 52.98 seconds
Started Mar 26 02:05:37 PM PDT 24
Finished Mar 26 02:06:30 PM PDT 24
Peak memory 240664 kb
Host smart-1fa21880-6f9a-46d7-bdcc-810e686553b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796357891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.796357891
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2920528386
Short name T492
Test name
Test status
Simulation time 27014054044 ps
CPU time 22.82 seconds
Started Mar 26 02:05:40 PM PDT 24
Finished Mar 26 02:06:04 PM PDT 24
Peak memory 233620 kb
Host smart-fe160e17-b81e-4dcb-95df-9a1a767d9827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920528386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2920528386
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.561063953
Short name T447
Test name
Test status
Simulation time 39488929314 ps
CPU time 28.32 seconds
Started Mar 26 02:05:41 PM PDT 24
Finished Mar 26 02:06:09 PM PDT 24
Peak memory 241708 kb
Host smart-2d0b531d-4853-4521-bf05-70478221d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561063953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.561063953
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1014399596
Short name T329
Test name
Test status
Simulation time 2684439713 ps
CPU time 4.56 seconds
Started Mar 26 02:05:47 PM PDT 24
Finished Mar 26 02:05:52 PM PDT 24
Peak memory 218904 kb
Host smart-8cdf252b-b7dc-4033-b0c7-efaed1671061
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1014399596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1014399596
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1822551008
Short name T113
Test name
Test status
Simulation time 48687803346 ps
CPU time 169.57 seconds
Started Mar 26 02:05:55 PM PDT 24
Finished Mar 26 02:08:45 PM PDT 24
Peak memory 268412 kb
Host smart-7d79b985-dad2-4c1e-b988-a11b79036751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822551008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1822551008
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2192776917
Short name T789
Test name
Test status
Simulation time 28876436353 ps
CPU time 36.85 seconds
Started Mar 26 02:05:35 PM PDT 24
Finished Mar 26 02:06:12 PM PDT 24
Peak memory 216072 kb
Host smart-07aa12cd-cebc-45b6-8a80-c1fde7c9d4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192776917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2192776917
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3666144747
Short name T337
Test name
Test status
Simulation time 44057483216 ps
CPU time 10.86 seconds
Started Mar 26 02:05:35 PM PDT 24
Finished Mar 26 02:05:46 PM PDT 24
Peak memory 216248 kb
Host smart-0e904679-6b54-4ffb-ba63-f0f5ca49e0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666144747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3666144747
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2874910854
Short name T753
Test name
Test status
Simulation time 109827240 ps
CPU time 1.27 seconds
Started Mar 26 02:05:40 PM PDT 24
Finished Mar 26 02:05:42 PM PDT 24
Peak memory 215992 kb
Host smart-ae3d80d8-b259-401c-a2cf-b68e6393e216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874910854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2874910854
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3965200954
Short name T741
Test name
Test status
Simulation time 202334373 ps
CPU time 0.81 seconds
Started Mar 26 02:05:42 PM PDT 24
Finished Mar 26 02:05:43 PM PDT 24
Peak memory 205420 kb
Host smart-9b5e597f-532e-46c7-931b-38296080cc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965200954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3965200954
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3107380857
Short name T635
Test name
Test status
Simulation time 10817590501 ps
CPU time 11.52 seconds
Started Mar 26 02:05:35 PM PDT 24
Finished Mar 26 02:05:47 PM PDT 24
Peak memory 235156 kb
Host smart-f02bd39e-8154-44b1-b73c-2f52594a6e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107380857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3107380857
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1437703391
Short name T917
Test name
Test status
Simulation time 83372975 ps
CPU time 0.71 seconds
Started Mar 26 02:05:52 PM PDT 24
Finished Mar 26 02:05:53 PM PDT 24
Peak memory 205148 kb
Host smart-66c00ea3-998b-4999-9e5b-c172f1b41aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437703391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1437703391
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.989794304
Short name T219
Test name
Test status
Simulation time 71310672 ps
CPU time 2.82 seconds
Started Mar 26 02:05:53 PM PDT 24
Finished Mar 26 02:05:56 PM PDT 24
Peak memory 234108 kb
Host smart-428fb6ee-829f-4cbe-b13f-3f80fb04cba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989794304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.989794304
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3792653996
Short name T678
Test name
Test status
Simulation time 37828187 ps
CPU time 0.77 seconds
Started Mar 26 02:05:48 PM PDT 24
Finished Mar 26 02:05:49 PM PDT 24
Peak memory 206212 kb
Host smart-c4d96f1f-8487-4444-8ff6-d7c7ae2fd60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792653996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3792653996
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3554387970
Short name T186
Test name
Test status
Simulation time 23517382784 ps
CPU time 135.63 seconds
Started Mar 26 02:05:49 PM PDT 24
Finished Mar 26 02:08:05 PM PDT 24
Peak memory 242368 kb
Host smart-701f7f4d-da34-4ac3-8460-73d3cae92ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554387970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3554387970
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2256598864
Short name T202
Test name
Test status
Simulation time 10756179673 ps
CPU time 49.3 seconds
Started Mar 26 02:05:46 PM PDT 24
Finished Mar 26 02:06:36 PM PDT 24
Peak memory 254916 kb
Host smart-1105d12b-d644-481e-807d-ab93304c9be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256598864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2256598864
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3958846164
Short name T882
Test name
Test status
Simulation time 51360281871 ps
CPU time 108.66 seconds
Started Mar 26 02:05:47 PM PDT 24
Finished Mar 26 02:07:35 PM PDT 24
Peak memory 250100 kb
Host smart-c6ed60cc-53d1-471a-989e-c0c6fefeff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958846164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3958846164
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.4117393477
Short name T378
Test name
Test status
Simulation time 2383795324 ps
CPU time 8.21 seconds
Started Mar 26 02:05:54 PM PDT 24
Finished Mar 26 02:06:02 PM PDT 24
Peak memory 232748 kb
Host smart-6b25bf31-c264-414c-ae3b-bb9737bfb686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117393477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4117393477
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4284444038
Short name T127
Test name
Test status
Simulation time 597230412 ps
CPU time 5.07 seconds
Started Mar 26 02:05:47 PM PDT 24
Finished Mar 26 02:05:52 PM PDT 24
Peak memory 220816 kb
Host smart-46054903-9d1c-45cc-8b2b-a4f23ffd1e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284444038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4284444038
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4294267157
Short name T43
Test name
Test status
Simulation time 169166744341 ps
CPU time 46.38 seconds
Started Mar 26 02:05:55 PM PDT 24
Finished Mar 26 02:06:41 PM PDT 24
Peak memory 227956 kb
Host smart-ad87e4fd-e207-42a6-973b-e7e247939a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294267157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4294267157
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1172278558
Short name T918
Test name
Test status
Simulation time 1307579635 ps
CPU time 5.29 seconds
Started Mar 26 02:05:56 PM PDT 24
Finished Mar 26 02:06:01 PM PDT 24
Peak memory 233484 kb
Host smart-6bdf2a0b-dbb4-4b95-906d-baa390068a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172278558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1172278558
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3565906872
Short name T521
Test name
Test status
Simulation time 1751340044 ps
CPU time 6.24 seconds
Started Mar 26 02:05:48 PM PDT 24
Finished Mar 26 02:05:54 PM PDT 24
Peak memory 217804 kb
Host smart-cbf58c1e-78b8-404f-a600-afa388df0cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565906872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3565906872
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2610161048
Short name T408
Test name
Test status
Simulation time 380343521 ps
CPU time 3.77 seconds
Started Mar 26 02:05:54 PM PDT 24
Finished Mar 26 02:05:57 PM PDT 24
Peak memory 222172 kb
Host smart-6de7db94-60df-46c4-85da-091ea6e561b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2610161048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2610161048
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.252402160
Short name T924
Test name
Test status
Simulation time 159467838 ps
CPU time 1.03 seconds
Started Mar 26 02:05:49 PM PDT 24
Finished Mar 26 02:05:50 PM PDT 24
Peak memory 206528 kb
Host smart-4a3e1958-c427-454e-acd2-2a92e1376933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252402160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.252402160
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1788282552
Short name T616
Test name
Test status
Simulation time 1982035276 ps
CPU time 16.72 seconds
Started Mar 26 02:05:54 PM PDT 24
Finished Mar 26 02:06:11 PM PDT 24
Peak memory 216260 kb
Host smart-79acbe5a-13ae-4e75-8bc7-ac3fbad5b5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788282552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1788282552
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2986862165
Short name T979
Test name
Test status
Simulation time 1698948934 ps
CPU time 4.59 seconds
Started Mar 26 02:05:55 PM PDT 24
Finished Mar 26 02:06:00 PM PDT 24
Peak memory 215920 kb
Host smart-c3d9a0b7-7868-410b-a757-abf959a98477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986862165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2986862165
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1592553472
Short name T493
Test name
Test status
Simulation time 330058264 ps
CPU time 1.01 seconds
Started Mar 26 02:05:53 PM PDT 24
Finished Mar 26 02:05:55 PM PDT 24
Peak memory 207508 kb
Host smart-798c05bf-c7eb-4fc1-be7a-f280e34775ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592553472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1592553472
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2857646791
Short name T896
Test name
Test status
Simulation time 523427082 ps
CPU time 1.15 seconds
Started Mar 26 02:05:47 PM PDT 24
Finished Mar 26 02:05:48 PM PDT 24
Peak memory 206540 kb
Host smart-5c13a242-99cb-40ed-91d1-75b69be554ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857646791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2857646791
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.190917548
Short name T228
Test name
Test status
Simulation time 40608946 ps
CPU time 2.77 seconds
Started Mar 26 02:05:56 PM PDT 24
Finished Mar 26 02:05:59 PM PDT 24
Peak memory 232528 kb
Host smart-33bcb13e-2dfc-4965-a2d8-3977e6fcb585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190917548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.190917548
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4234463640
Short name T948
Test name
Test status
Simulation time 11552137 ps
CPU time 0.79 seconds
Started Mar 26 02:06:07 PM PDT 24
Finished Mar 26 02:06:08 PM PDT 24
Peak memory 205164 kb
Host smart-c612e75a-8e01-4b7b-9f72-95e9f23584b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234463640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4234463640
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1739961702
Short name T9
Test name
Test status
Simulation time 236127709 ps
CPU time 2.7 seconds
Started Mar 26 02:05:59 PM PDT 24
Finished Mar 26 02:06:03 PM PDT 24
Peak memory 217656 kb
Host smart-7c43720c-b041-434a-beb1-8609625376d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739961702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1739961702
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2120553858
Short name T402
Test name
Test status
Simulation time 45552784 ps
CPU time 0.78 seconds
Started Mar 26 02:05:48 PM PDT 24
Finished Mar 26 02:05:49 PM PDT 24
Peak memory 206028 kb
Host smart-ff69c671-f060-45f6-8b46-f60520c699a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120553858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2120553858
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4109093428
Short name T842
Test name
Test status
Simulation time 5532038363 ps
CPU time 46.09 seconds
Started Mar 26 02:06:07 PM PDT 24
Finished Mar 26 02:06:53 PM PDT 24
Peak memory 254548 kb
Host smart-707d3bfe-85e8-4c1a-b044-910f0adadf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109093428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4109093428
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2542842356
Short name T74
Test name
Test status
Simulation time 9417031453 ps
CPU time 126.15 seconds
Started Mar 26 02:06:05 PM PDT 24
Finished Mar 26 02:08:12 PM PDT 24
Peak memory 257960 kb
Host smart-ed79ed12-7abd-4dae-8a05-f771293b2bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542842356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2542842356
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3617216812
Short name T494
Test name
Test status
Simulation time 3791969444 ps
CPU time 14.05 seconds
Started Mar 26 02:05:58 PM PDT 24
Finished Mar 26 02:06:14 PM PDT 24
Peak memory 240788 kb
Host smart-67c80065-916c-403b-9212-9bd9d3c7d4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617216812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3617216812
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3689682574
Short name T754
Test name
Test status
Simulation time 19675860667 ps
CPU time 11.44 seconds
Started Mar 26 02:05:55 PM PDT 24
Finished Mar 26 02:06:07 PM PDT 24
Peak memory 219500 kb
Host smart-a224fb42-216a-4d16-9bfa-0234606540d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689682574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3689682574
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3235753828
Short name T232
Test name
Test status
Simulation time 25712728614 ps
CPU time 15.79 seconds
Started Mar 26 02:05:49 PM PDT 24
Finished Mar 26 02:06:05 PM PDT 24
Peak memory 240660 kb
Host smart-0f300928-3a3b-488a-87a7-3a85355c35af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235753828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3235753828
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3010568297
Short name T406
Test name
Test status
Simulation time 8182656169 ps
CPU time 28.38 seconds
Started Mar 26 02:05:54 PM PDT 24
Finished Mar 26 02:06:22 PM PDT 24
Peak memory 245376 kb
Host smart-9c439140-53c7-444b-ae08-5263e52c8a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010568297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3010568297
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1198019402
Short name T191
Test name
Test status
Simulation time 742937820 ps
CPU time 6.39 seconds
Started Mar 26 02:05:47 PM PDT 24
Finished Mar 26 02:05:54 PM PDT 24
Peak memory 226572 kb
Host smart-785db4c4-4e19-4970-9451-a49087a36f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198019402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1198019402
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2357730119
Short name T599
Test name
Test status
Simulation time 926952516 ps
CPU time 6.14 seconds
Started Mar 26 02:05:58 PM PDT 24
Finished Mar 26 02:06:04 PM PDT 24
Peak memory 222692 kb
Host smart-86bc3bb5-f146-47bf-86d0-aa595291e10e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2357730119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2357730119
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1845717732
Short name T913
Test name
Test status
Simulation time 10776410208 ps
CPU time 54.91 seconds
Started Mar 26 02:06:05 PM PDT 24
Finished Mar 26 02:07:00 PM PDT 24
Peak memory 249872 kb
Host smart-404ebbf7-c088-4d4a-9e10-661130ab12ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845717732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1845717732
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.201016351
Short name T843
Test name
Test status
Simulation time 173161924158 ps
CPU time 48.11 seconds
Started Mar 26 02:05:59 PM PDT 24
Finished Mar 26 02:06:49 PM PDT 24
Peak memory 216268 kb
Host smart-0973efd1-f37c-4aed-a95e-6c4ff920987a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201016351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.201016351
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3188100776
Short name T351
Test name
Test status
Simulation time 23779998941 ps
CPU time 18.16 seconds
Started Mar 26 02:05:49 PM PDT 24
Finished Mar 26 02:06:08 PM PDT 24
Peak memory 216208 kb
Host smart-d48a3639-7c36-422f-8aab-701fa94ba036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188100776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3188100776
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.475550026
Short name T313
Test name
Test status
Simulation time 121694932 ps
CPU time 1.97 seconds
Started Mar 26 02:06:01 PM PDT 24
Finished Mar 26 02:06:03 PM PDT 24
Peak memory 216156 kb
Host smart-141f529d-0b7b-4721-8f9b-678124762c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475550026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.475550026
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1410794164
Short name T331
Test name
Test status
Simulation time 66841220 ps
CPU time 0.91 seconds
Started Mar 26 02:05:54 PM PDT 24
Finished Mar 26 02:05:55 PM PDT 24
Peak memory 205552 kb
Host smart-b6d43f09-7bea-4127-9a21-61de3835a96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410794164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1410794164
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.188426592
Short name T944
Test name
Test status
Simulation time 4239890692 ps
CPU time 17.43 seconds
Started Mar 26 02:05:54 PM PDT 24
Finished Mar 26 02:06:11 PM PDT 24
Peak memory 219344 kb
Host smart-4843c306-e445-40ca-bf53-f35a2fe24c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188426592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.188426592
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2748388571
Short name T438
Test name
Test status
Simulation time 17703390 ps
CPU time 0.7 seconds
Started Mar 26 02:06:00 PM PDT 24
Finished Mar 26 02:06:02 PM PDT 24
Peak memory 204924 kb
Host smart-45df5013-22ed-4e49-87a0-62d901c1c3b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748388571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2748388571
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2571473570
Short name T818
Test name
Test status
Simulation time 105488997 ps
CPU time 2.49 seconds
Started Mar 26 02:05:58 PM PDT 24
Finished Mar 26 02:06:03 PM PDT 24
Peak memory 218380 kb
Host smart-9a42ff36-4dc2-4922-a1e9-dfe2449ed25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571473570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2571473570
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2785429214
Short name T339
Test name
Test status
Simulation time 16387035 ps
CPU time 0.79 seconds
Started Mar 26 02:06:07 PM PDT 24
Finished Mar 26 02:06:08 PM PDT 24
Peak memory 206516 kb
Host smart-a1abdbef-c635-4619-b160-4c9e358c8019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785429214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2785429214
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3953480641
Short name T806
Test name
Test status
Simulation time 65036402185 ps
CPU time 256.25 seconds
Started Mar 26 02:05:59 PM PDT 24
Finished Mar 26 02:10:17 PM PDT 24
Peak memory 265776 kb
Host smart-da010ca7-94a3-4302-8680-ed63a045aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953480641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3953480641
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4003576033
Short name T251
Test name
Test status
Simulation time 138427827675 ps
CPU time 192.15 seconds
Started Mar 26 02:06:05 PM PDT 24
Finished Mar 26 02:09:18 PM PDT 24
Peak memory 268840 kb
Host smart-7efdf151-10e8-44f4-a4e1-ee6c2cff3518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003576033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4003576033
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1082962211
Short name T648
Test name
Test status
Simulation time 114492659827 ps
CPU time 231.03 seconds
Started Mar 26 02:06:07 PM PDT 24
Finished Mar 26 02:09:58 PM PDT 24
Peak memory 256920 kb
Host smart-606fe8e2-3289-48ed-a80f-5e03491fd247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082962211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1082962211
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3681440040
Short name T387
Test name
Test status
Simulation time 2693609482 ps
CPU time 10.47 seconds
Started Mar 26 02:05:58 PM PDT 24
Finished Mar 26 02:06:11 PM PDT 24
Peak memory 237520 kb
Host smart-f99793b3-25e7-495b-a689-f11603cf9fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681440040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3681440040
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.815283263
Short name T208
Test name
Test status
Simulation time 32713636046 ps
CPU time 31.02 seconds
Started Mar 26 02:06:02 PM PDT 24
Finished Mar 26 02:06:33 PM PDT 24
Peak memory 245236 kb
Host smart-33417341-0dab-4c00-b37e-d1c61456d769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815283263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.815283263
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3368975111
Short name T207
Test name
Test status
Simulation time 18940450732 ps
CPU time 27.86 seconds
Started Mar 26 02:06:00 PM PDT 24
Finished Mar 26 02:06:29 PM PDT 24
Peak memory 233704 kb
Host smart-a7cd1663-5517-4b00-ae26-13892c17fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368975111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3368975111
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1033877954
Short name T354
Test name
Test status
Simulation time 16280769524 ps
CPU time 11.93 seconds
Started Mar 26 02:06:04 PM PDT 24
Finished Mar 26 02:06:17 PM PDT 24
Peak memory 219492 kb
Host smart-1d5d739b-f37a-435c-87c2-ea214e49ec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033877954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1033877954
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3598830771
Short name T813
Test name
Test status
Simulation time 106470616 ps
CPU time 3.64 seconds
Started Mar 26 02:06:00 PM PDT 24
Finished Mar 26 02:06:05 PM PDT 24
Peak memory 221464 kb
Host smart-0b4f3504-90f8-43ff-82c9-4cc4f54d41e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3598830771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3598830771
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1116395573
Short name T874
Test name
Test status
Simulation time 16117317969 ps
CPU time 22.93 seconds
Started Mar 26 02:05:59 PM PDT 24
Finished Mar 26 02:06:24 PM PDT 24
Peak memory 216188 kb
Host smart-84501051-74fd-47d8-b435-0ae632b8e858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116395573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1116395573
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1155164014
Short name T967
Test name
Test status
Simulation time 4441387032 ps
CPU time 9.43 seconds
Started Mar 26 02:06:00 PM PDT 24
Finished Mar 26 02:06:10 PM PDT 24
Peak memory 216248 kb
Host smart-a8e63454-cc84-47b6-ae53-8538c21140fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155164014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1155164014
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2806337669
Short name T662
Test name
Test status
Simulation time 2327952020 ps
CPU time 2.07 seconds
Started Mar 26 02:06:06 PM PDT 24
Finished Mar 26 02:06:09 PM PDT 24
Peak memory 216200 kb
Host smart-404d1696-e6cb-4f1c-a663-d860877cc54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806337669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2806337669
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2853833601
Short name T519
Test name
Test status
Simulation time 80513112 ps
CPU time 0.98 seconds
Started Mar 26 02:05:58 PM PDT 24
Finished Mar 26 02:06:01 PM PDT 24
Peak memory 206480 kb
Host smart-518cbdc9-2211-4865-bc6d-6c6c543408a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853833601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2853833601
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1717443229
Short name T762
Test name
Test status
Simulation time 1771963649 ps
CPU time 13.31 seconds
Started Mar 26 02:05:59 PM PDT 24
Finished Mar 26 02:06:14 PM PDT 24
Peak memory 239760 kb
Host smart-0e933905-56aa-4377-8fe8-caf8c6262797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717443229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1717443229
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1906638739
Short name T765
Test name
Test status
Simulation time 13522583 ps
CPU time 0.73 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:11 PM PDT 24
Peak memory 205016 kb
Host smart-0b6817b4-4c1b-4317-92b4-679fd547b2ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906638739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1906638739
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2833418001
Short name T233
Test name
Test status
Simulation time 349960878 ps
CPU time 3.07 seconds
Started Mar 26 02:06:11 PM PDT 24
Finished Mar 26 02:06:14 PM PDT 24
Peak memory 233652 kb
Host smart-a26b2d05-3a03-4f4e-bc44-46c9e643f05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833418001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2833418001
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3105116105
Short name T294
Test name
Test status
Simulation time 21513001 ps
CPU time 0.79 seconds
Started Mar 26 02:06:04 PM PDT 24
Finished Mar 26 02:06:06 PM PDT 24
Peak memory 206220 kb
Host smart-6f95521c-78dc-4ff7-b880-ceb05c8add4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105116105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3105116105
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.41619332
Short name T37
Test name
Test status
Simulation time 28274591310 ps
CPU time 38.28 seconds
Started Mar 26 02:06:11 PM PDT 24
Finished Mar 26 02:06:49 PM PDT 24
Peak memory 247048 kb
Host smart-73fd1906-0c5d-47a1-8203-a9c9d9eabbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41619332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.41619332
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4089822324
Short name T262
Test name
Test status
Simulation time 314417228633 ps
CPU time 617.49 seconds
Started Mar 26 02:06:11 PM PDT 24
Finished Mar 26 02:16:29 PM PDT 24
Peak memory 253316 kb
Host smart-57bc537e-5258-4f35-b2ed-5839312aff24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089822324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4089822324
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3162863412
Short name T19
Test name
Test status
Simulation time 11670841844 ps
CPU time 153.12 seconds
Started Mar 26 02:06:09 PM PDT 24
Finished Mar 26 02:08:42 PM PDT 24
Peak memory 253464 kb
Host smart-0401beae-0e45-4eb1-983f-c1d62687a504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162863412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3162863412
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.16393622
Short name T972
Test name
Test status
Simulation time 1366854525 ps
CPU time 12.35 seconds
Started Mar 26 02:06:12 PM PDT 24
Finished Mar 26 02:06:24 PM PDT 24
Peak memory 232480 kb
Host smart-41ce2654-8730-48d1-abcd-ba51dcb0485e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16393622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.16393622
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3821018193
Short name T184
Test name
Test status
Simulation time 3035066914 ps
CPU time 4.88 seconds
Started Mar 26 02:06:12 PM PDT 24
Finished Mar 26 02:06:17 PM PDT 24
Peak memory 218456 kb
Host smart-4da669df-2a94-4a6b-8c1f-c95718517c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821018193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3821018193
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.632199111
Short name T892
Test name
Test status
Simulation time 10593760626 ps
CPU time 30.94 seconds
Started Mar 26 02:06:12 PM PDT 24
Finished Mar 26 02:06:43 PM PDT 24
Peak memory 232608 kb
Host smart-7e1b7916-77f9-4975-ba95-effa595a0c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632199111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.632199111
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3596987562
Short name T300
Test name
Test status
Simulation time 162930829 ps
CPU time 2.47 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:12 PM PDT 24
Peak memory 216496 kb
Host smart-957442dd-95f0-4bb8-a32f-a44ac3b0a50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596987562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3596987562
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2847888644
Short name T197
Test name
Test status
Simulation time 46813132200 ps
CPU time 15.59 seconds
Started Mar 26 02:06:08 PM PDT 24
Finished Mar 26 02:06:24 PM PDT 24
Peak memory 228568 kb
Host smart-73b75bec-815c-4013-934b-c4e141b62671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847888644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2847888644
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3585988418
Short name T392
Test name
Test status
Simulation time 1043913118 ps
CPU time 5.71 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:16 PM PDT 24
Peak memory 222128 kb
Host smart-f7d0059d-6f19-4a92-a321-73595012e29d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3585988418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3585988418
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3154766133
Short name T713
Test name
Test status
Simulation time 193167217 ps
CPU time 1.12 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:11 PM PDT 24
Peak memory 206820 kb
Host smart-9b53b583-3d80-4a30-9883-c6aa323631e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154766133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3154766133
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.666445250
Short name T982
Test name
Test status
Simulation time 2308803716 ps
CPU time 31.96 seconds
Started Mar 26 02:06:12 PM PDT 24
Finished Mar 26 02:06:45 PM PDT 24
Peak memory 216452 kb
Host smart-6ed37fde-f46f-438a-8d46-1a31203cde7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666445250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.666445250
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4285161909
Short name T867
Test name
Test status
Simulation time 2941431786 ps
CPU time 8.91 seconds
Started Mar 26 02:06:12 PM PDT 24
Finished Mar 26 02:06:21 PM PDT 24
Peak memory 216096 kb
Host smart-8482826b-9d68-4272-833a-b6c6c30020b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285161909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4285161909
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.601556266
Short name T905
Test name
Test status
Simulation time 23178824 ps
CPU time 0.83 seconds
Started Mar 26 02:06:09 PM PDT 24
Finished Mar 26 02:06:10 PM PDT 24
Peak memory 205544 kb
Host smart-a5976ff6-fb4e-4894-bd7b-dff48b756aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601556266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.601556266
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4118626654
Short name T927
Test name
Test status
Simulation time 120233090 ps
CPU time 1.1 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:11 PM PDT 24
Peak memory 206500 kb
Host smart-fa4bc62a-a914-4cae-b61e-3038e6ed998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118626654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4118626654
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.379752378
Short name T214
Test name
Test status
Simulation time 56210090570 ps
CPU time 13.7 seconds
Started Mar 26 02:06:11 PM PDT 24
Finished Mar 26 02:06:25 PM PDT 24
Peak memory 239484 kb
Host smart-4f50bb39-a32f-48e2-9708-3ec3a0b3cfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379752378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.379752378
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.480665517
Short name T333
Test name
Test status
Simulation time 15040969 ps
CPU time 0.75 seconds
Started Mar 26 02:06:09 PM PDT 24
Finished Mar 26 02:06:10 PM PDT 24
Peak memory 205124 kb
Host smart-494546bf-5c4a-4c67-a233-b712864ef092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480665517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.480665517
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2747707869
Short name T856
Test name
Test status
Simulation time 97412769 ps
CPU time 2.18 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:12 PM PDT 24
Peak memory 218448 kb
Host smart-575c0be8-c10c-4043-b209-55cbb9a196be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747707869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2747707869
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4237369336
Short name T277
Test name
Test status
Simulation time 29326730 ps
CPU time 0.8 seconds
Started Mar 26 02:06:11 PM PDT 24
Finished Mar 26 02:06:11 PM PDT 24
Peak memory 206400 kb
Host smart-bddc386c-f574-4313-98c1-47ae2ee78a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237369336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4237369336
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4184737059
Short name T194
Test name
Test status
Simulation time 28186246428 ps
CPU time 306.93 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:11:17 PM PDT 24
Peak memory 273720 kb
Host smart-0450cfb2-8ee8-4f25-88f1-a8bef365b4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184737059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4184737059
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.18640902
Short name T560
Test name
Test status
Simulation time 10638943918 ps
CPU time 22.06 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:33 PM PDT 24
Peak memory 235248 kb
Host smart-1f190aa3-c2ed-41a0-b999-de3a80932521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18640902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.18640902
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2930630934
Short name T370
Test name
Test status
Simulation time 392217335 ps
CPU time 4.76 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:15 PM PDT 24
Peak memory 218688 kb
Host smart-1ca980a5-1d4e-4ca3-9570-c526068e539b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930630934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2930630934
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3251384876
Short name T611
Test name
Test status
Simulation time 934425078 ps
CPU time 5.43 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:16 PM PDT 24
Peak memory 233048 kb
Host smart-fcff3f8e-17f4-437d-b2a7-9e529ea661ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251384876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3251384876
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3138813349
Short name T752
Test name
Test status
Simulation time 16235766534 ps
CPU time 47.52 seconds
Started Mar 26 02:06:12 PM PDT 24
Finished Mar 26 02:06:59 PM PDT 24
Peak memory 229836 kb
Host smart-db183455-3b32-4f27-b5a5-f7d6e52848f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138813349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3138813349
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2854585847
Short name T652
Test name
Test status
Simulation time 12044298017 ps
CPU time 18.75 seconds
Started Mar 26 02:06:12 PM PDT 24
Finished Mar 26 02:06:31 PM PDT 24
Peak memory 233532 kb
Host smart-195f7e78-9b99-4a69-8dd0-12f980689d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854585847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2854585847
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.925297217
Short name T550
Test name
Test status
Simulation time 617216320 ps
CPU time 3.54 seconds
Started Mar 26 02:06:11 PM PDT 24
Finished Mar 26 02:06:15 PM PDT 24
Peak memory 220136 kb
Host smart-2ec9f567-72d3-4f1e-a23c-7e626cb42ed1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=925297217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.925297217
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3785338792
Short name T562
Test name
Test status
Simulation time 1310138354 ps
CPU time 9.88 seconds
Started Mar 26 02:06:11 PM PDT 24
Finished Mar 26 02:06:21 PM PDT 24
Peak memory 215940 kb
Host smart-c78e93b6-fe46-4152-9b95-c7627bbaf005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785338792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3785338792
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.4125854173
Short name T73
Test name
Test status
Simulation time 2794278890 ps
CPU time 6.8 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:17 PM PDT 24
Peak memory 216268 kb
Host smart-36c286cd-e867-4da7-a658-80dfb07f38a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125854173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.4125854173
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2914851093
Short name T283
Test name
Test status
Simulation time 171753608 ps
CPU time 4.65 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:14 PM PDT 24
Peak memory 216172 kb
Host smart-422690c0-ed82-4ecc-9dda-96924c273b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914851093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2914851093
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.581359491
Short name T679
Test name
Test status
Simulation time 163017780 ps
CPU time 0.92 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:11 PM PDT 24
Peak memory 205504 kb
Host smart-279a27b7-7d9a-4dde-b339-8d617b7d2ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581359491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.581359491
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2186440144
Short name T299
Test name
Test status
Simulation time 368627260 ps
CPU time 5.38 seconds
Started Mar 26 02:06:10 PM PDT 24
Finished Mar 26 02:06:16 PM PDT 24
Peak memory 218304 kb
Host smart-f1a5d425-48c0-4c9b-9a59-d2b595d748e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186440144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2186440144
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3406596935
Short name T310
Test name
Test status
Simulation time 13329252 ps
CPU time 0.74 seconds
Started Mar 26 02:06:20 PM PDT 24
Finished Mar 26 02:06:21 PM PDT 24
Peak memory 205144 kb
Host smart-09bb556d-b979-4be8-9d78-ca359bb47de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406596935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3406596935
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4199899814
Short name T794
Test name
Test status
Simulation time 1117647388 ps
CPU time 5.57 seconds
Started Mar 26 02:06:24 PM PDT 24
Finished Mar 26 02:06:30 PM PDT 24
Peak memory 224392 kb
Host smart-25720a12-78e9-4f82-b2b3-9e9bf4fca95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199899814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4199899814
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2265247303
Short name T381
Test name
Test status
Simulation time 91133428 ps
CPU time 0.8 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:06:22 PM PDT 24
Peak memory 206272 kb
Host smart-fba27cb0-b588-49db-a6c1-eb1075f139ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265247303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2265247303
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1383900895
Short name T155
Test name
Test status
Simulation time 1133605414 ps
CPU time 23.74 seconds
Started Mar 26 02:06:20 PM PDT 24
Finished Mar 26 02:06:44 PM PDT 24
Peak memory 237704 kb
Host smart-c474788b-ecca-45e0-aca3-a23ba48094cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383900895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1383900895
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3067259159
Short name T855
Test name
Test status
Simulation time 50227223489 ps
CPU time 366.6 seconds
Started Mar 26 02:06:20 PM PDT 24
Finished Mar 26 02:12:27 PM PDT 24
Peak memory 262912 kb
Host smart-54e98786-dfb0-4363-8753-0ba30d86227a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067259159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3067259159
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3044629768
Short name T216
Test name
Test status
Simulation time 248519828648 ps
CPU time 157.04 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:08:58 PM PDT 24
Peak memory 248820 kb
Host smart-cf86dae7-f0ed-42d3-a5ae-6b2ab4811d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044629768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3044629768
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.64587970
Short name T434
Test name
Test status
Simulation time 235508176 ps
CPU time 9.97 seconds
Started Mar 26 02:06:19 PM PDT 24
Finished Mar 26 02:06:29 PM PDT 24
Peak memory 234064 kb
Host smart-a5df4d8a-83dd-423a-9844-8315bf36dd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64587970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.64587970
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3065944396
Short name T218
Test name
Test status
Simulation time 352957778 ps
CPU time 2.72 seconds
Started Mar 26 02:06:22 PM PDT 24
Finished Mar 26 02:06:25 PM PDT 24
Peak memory 224444 kb
Host smart-e3883d58-2c69-4d2a-8b8e-2c906bb9b8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065944396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3065944396
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.358361672
Short name T390
Test name
Test status
Simulation time 2183077506 ps
CPU time 9.38 seconds
Started Mar 26 02:06:20 PM PDT 24
Finished Mar 26 02:06:30 PM PDT 24
Peak memory 239400 kb
Host smart-c3f1f1e7-a460-4ad3-9047-a9dc22990357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358361672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.358361672
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1853097347
Short name T174
Test name
Test status
Simulation time 2799812449 ps
CPU time 11.38 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:06:33 PM PDT 24
Peak memory 237376 kb
Host smart-199bca28-ee69-4068-93d5-c18e487ed2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853097347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1853097347
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1242104713
Short name T735
Test name
Test status
Simulation time 7918619658 ps
CPU time 8.89 seconds
Started Mar 26 02:06:22 PM PDT 24
Finished Mar 26 02:06:31 PM PDT 24
Peak memory 239136 kb
Host smart-b72887ec-5eb0-43ee-928d-07c1af7a989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242104713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1242104713
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.859858549
Short name T385
Test name
Test status
Simulation time 443127785 ps
CPU time 4.01 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:06:25 PM PDT 24
Peak memory 222320 kb
Host smart-e3a0111a-4354-4537-a99a-e057ec16e0fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=859858549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.859858549
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2643953448
Short name T246
Test name
Test status
Simulation time 28158825327 ps
CPU time 106.38 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:08:07 PM PDT 24
Peak memory 249172 kb
Host smart-3b31bc21-1475-4e35-9119-bf5b24da2baf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643953448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2643953448
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3432158690
Short name T6
Test name
Test status
Simulation time 8148298006 ps
CPU time 41.65 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:07:03 PM PDT 24
Peak memory 216156 kb
Host smart-79c4e061-38c7-4c87-b260-9ff3982708e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432158690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3432158690
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2676977631
Short name T382
Test name
Test status
Simulation time 1097763694 ps
CPU time 7.94 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:06:29 PM PDT 24
Peak memory 216056 kb
Host smart-a0145a9a-46d5-4d62-ae3b-a759b4b7e1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676977631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2676977631
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1029697478
Short name T321
Test name
Test status
Simulation time 267246807 ps
CPU time 1.29 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:06:22 PM PDT 24
Peak memory 216212 kb
Host smart-ab4856ac-479c-4147-8a74-ea305be5a3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029697478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1029697478
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2326041488
Short name T330
Test name
Test status
Simulation time 65186255 ps
CPU time 0.71 seconds
Started Mar 26 02:06:22 PM PDT 24
Finished Mar 26 02:06:23 PM PDT 24
Peak memory 205436 kb
Host smart-23e40dd9-3bbe-450f-9efa-32325d27f054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326041488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2326041488
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3579106492
Short name T900
Test name
Test status
Simulation time 24791102397 ps
CPU time 37.22 seconds
Started Mar 26 02:06:24 PM PDT 24
Finished Mar 26 02:07:01 PM PDT 24
Peak memory 239704 kb
Host smart-e216088f-4b6c-48f8-afea-f36013777822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579106492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3579106492
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1509397226
Short name T977
Test name
Test status
Simulation time 13369544 ps
CPU time 0.75 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:06:35 PM PDT 24
Peak memory 204568 kb
Host smart-e2b40c0e-4c25-42f0-972d-b11ae15986c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509397226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1509397226
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.867263281
Short name T939
Test name
Test status
Simulation time 56569711 ps
CPU time 2.88 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:06:24 PM PDT 24
Peak memory 233492 kb
Host smart-89a0b334-e3fd-456a-a912-a4607bd8a7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867263281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.867263281
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3252672791
Short name T67
Test name
Test status
Simulation time 60515011 ps
CPU time 0.75 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:06:22 PM PDT 24
Peak memory 206120 kb
Host smart-ccf45c13-c370-42bc-b89e-5aa44981c5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252672791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3252672791
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1315107084
Short name T907
Test name
Test status
Simulation time 785355615 ps
CPU time 4.68 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:06:39 PM PDT 24
Peak memory 219312 kb
Host smart-8e869a18-c3eb-4172-bc1c-d78de3025329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315107084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1315107084
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2940034886
Short name T608
Test name
Test status
Simulation time 107188877903 ps
CPU time 389.18 seconds
Started Mar 26 02:06:34 PM PDT 24
Finished Mar 26 02:13:05 PM PDT 24
Peak memory 254096 kb
Host smart-89784338-6e9d-45a1-9bdd-6b22b243f2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940034886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2940034886
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.280620146
Short name T235
Test name
Test status
Simulation time 2535023685 ps
CPU time 48.2 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:07:22 PM PDT 24
Peak memory 251740 kb
Host smart-162742a1-d773-40d7-85e1-72733a5131c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280620146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.280620146
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2407366127
Short name T374
Test name
Test status
Simulation time 1960683166 ps
CPU time 8.85 seconds
Started Mar 26 02:06:20 PM PDT 24
Finished Mar 26 02:06:29 PM PDT 24
Peak memory 234312 kb
Host smart-b9932786-3a8f-4e66-90b9-78a517c58239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407366127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2407366127
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1425977897
Short name T206
Test name
Test status
Simulation time 11718370930 ps
CPU time 37.99 seconds
Started Mar 26 02:06:21 PM PDT 24
Finished Mar 26 02:06:59 PM PDT 24
Peak memory 240840 kb
Host smart-56546d8b-c21f-40b3-9989-e188c86bbe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425977897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1425977897
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.306944078
Short name T49
Test name
Test status
Simulation time 181119608 ps
CPU time 2.34 seconds
Started Mar 26 02:06:24 PM PDT 24
Finished Mar 26 02:06:27 PM PDT 24
Peak memory 218424 kb
Host smart-df8e94cf-9cc6-46e5-a212-0915dae11502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306944078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.306944078
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2673176082
Short name T193
Test name
Test status
Simulation time 19560833102 ps
CPU time 31.56 seconds
Started Mar 26 02:06:24 PM PDT 24
Finished Mar 26 02:06:56 PM PDT 24
Peak memory 238524 kb
Host smart-aca67455-6085-4619-9023-f08629075810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673176082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2673176082
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1519399895
Short name T587
Test name
Test status
Simulation time 294750617 ps
CPU time 3.05 seconds
Started Mar 26 02:06:22 PM PDT 24
Finished Mar 26 02:06:25 PM PDT 24
Peak memory 219640 kb
Host smart-af001a58-ee26-4f3b-8a88-fe17be138049
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1519399895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1519399895
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1103997105
Short name T137
Test name
Test status
Simulation time 8399519656 ps
CPU time 60.6 seconds
Started Mar 26 02:06:32 PM PDT 24
Finished Mar 26 02:07:34 PM PDT 24
Peak memory 241004 kb
Host smart-ab5332a0-94eb-4f50-8d30-0d39da2339d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103997105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1103997105
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1876955121
Short name T325
Test name
Test status
Simulation time 974347477 ps
CPU time 6.03 seconds
Started Mar 26 02:06:22 PM PDT 24
Finished Mar 26 02:06:28 PM PDT 24
Peak memory 216096 kb
Host smart-f02fa82e-0d4e-4fec-8a57-e8ae057c55e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876955121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1876955121
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3595633819
Short name T281
Test name
Test status
Simulation time 1202408144 ps
CPU time 7.87 seconds
Started Mar 26 02:06:24 PM PDT 24
Finished Mar 26 02:06:32 PM PDT 24
Peak memory 216168 kb
Host smart-5dba390a-703b-49cb-92e0-05bd0c3a7759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595633819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3595633819
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1127445241
Short name T951
Test name
Test status
Simulation time 248632014 ps
CPU time 2.37 seconds
Started Mar 26 02:06:22 PM PDT 24
Finished Mar 26 02:06:24 PM PDT 24
Peak memory 216188 kb
Host smart-d66e57c4-0bcd-49ae-8e53-060aaf79450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127445241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1127445241
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.965925531
Short name T574
Test name
Test status
Simulation time 93763943 ps
CPU time 0.88 seconds
Started Mar 26 02:06:22 PM PDT 24
Finished Mar 26 02:06:23 PM PDT 24
Peak memory 205532 kb
Host smart-46773f96-7f53-4510-bbb3-f3f7a399db93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965925531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.965925531
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1890670462
Short name T729
Test name
Test status
Simulation time 8635332219 ps
CPU time 30.01 seconds
Started Mar 26 02:06:23 PM PDT 24
Finished Mar 26 02:06:53 PM PDT 24
Peak memory 237924 kb
Host smart-fb2ef2df-fc04-4ea8-808f-1bf730a33ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890670462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1890670462
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2462485230
Short name T945
Test name
Test status
Simulation time 35649733 ps
CPU time 0.72 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:06:35 PM PDT 24
Peak memory 204592 kb
Host smart-4c5e9599-61d4-4b65-bea5-a88382ed6cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462485230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2462485230
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2907894008
Short name T312
Test name
Test status
Simulation time 5420343356 ps
CPU time 8.77 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:06:43 PM PDT 24
Peak memory 219616 kb
Host smart-79748189-5d53-4cd7-ab8a-a4e472956f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907894008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2907894008
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3243563988
Short name T709
Test name
Test status
Simulation time 105440560 ps
CPU time 0.8 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:06:35 PM PDT 24
Peak memory 206552 kb
Host smart-0ff980d6-abe0-43af-97f0-57ed16d67943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243563988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3243563988
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1612554888
Short name T823
Test name
Test status
Simulation time 21446783610 ps
CPU time 50.26 seconds
Started Mar 26 02:06:35 PM PDT 24
Finished Mar 26 02:07:26 PM PDT 24
Peak memory 240732 kb
Host smart-1c5cb4f9-b9df-4357-90f3-e794418a36a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612554888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1612554888
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2578876524
Short name T226
Test name
Test status
Simulation time 1272163887 ps
CPU time 27.05 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:07:01 PM PDT 24
Peak memory 239164 kb
Host smart-5f2e521e-b989-4ece-a1f4-f5019ffa4266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578876524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2578876524
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3637167904
Short name T876
Test name
Test status
Simulation time 5668047296 ps
CPU time 123.53 seconds
Started Mar 26 02:06:35 PM PDT 24
Finished Mar 26 02:08:39 PM PDT 24
Peak memory 255168 kb
Host smart-eaac8ac6-f981-4bfb-a90c-4c336d10cacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637167904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3637167904
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.951272463
Short name T970
Test name
Test status
Simulation time 23379851157 ps
CPU time 58.14 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:07:32 PM PDT 24
Peak memory 255428 kb
Host smart-2cc15452-6a7e-4639-978a-15fe16277b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951272463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.951272463
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2230431114
Short name T205
Test name
Test status
Simulation time 670592460 ps
CPU time 3.56 seconds
Started Mar 26 02:06:34 PM PDT 24
Finished Mar 26 02:06:39 PM PDT 24
Peak memory 217848 kb
Host smart-7967e7e5-66a9-44db-abbf-60f5aad03121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230431114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2230431114
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3142770022
Short name T502
Test name
Test status
Simulation time 13702246221 ps
CPU time 7.22 seconds
Started Mar 26 02:06:35 PM PDT 24
Finished Mar 26 02:06:43 PM PDT 24
Peak memory 232528 kb
Host smart-22646094-abd3-4426-91c3-4fad69d9a4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142770022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3142770022
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.911923096
Short name T961
Test name
Test status
Simulation time 358846890 ps
CPU time 3.3 seconds
Started Mar 26 02:06:36 PM PDT 24
Finished Mar 26 02:06:41 PM PDT 24
Peak memory 218228 kb
Host smart-c499bf96-5c91-4e63-b765-352909db1c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911923096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.911923096
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3458318370
Short name T448
Test name
Test status
Simulation time 353655254 ps
CPU time 3.9 seconds
Started Mar 26 02:06:37 PM PDT 24
Finished Mar 26 02:06:42 PM PDT 24
Peak memory 224128 kb
Host smart-dac58f2e-60e3-41d4-a8ae-f4ef2ee312ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458318370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3458318370
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2306885956
Short name T347
Test name
Test status
Simulation time 2087980171 ps
CPU time 6.75 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:06:41 PM PDT 24
Peak memory 222264 kb
Host smart-3378cb3a-2e38-4b4c-a2d0-2999cd927f3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2306885956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2306885956
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2899834562
Short name T141
Test name
Test status
Simulation time 21682735106 ps
CPU time 49.13 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:07:23 PM PDT 24
Peak memory 249436 kb
Host smart-b73de595-92a3-47e2-ab27-64b54b67f563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899834562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2899834562
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3579698567
Short name T2
Test name
Test status
Simulation time 2068424052 ps
CPU time 21.71 seconds
Started Mar 26 02:06:34 PM PDT 24
Finished Mar 26 02:06:58 PM PDT 24
Peak memory 216140 kb
Host smart-242fe8bc-5043-4adb-9534-c00cd149ca89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579698567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3579698567
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1388570208
Short name T273
Test name
Test status
Simulation time 13534561217 ps
CPU time 21.77 seconds
Started Mar 26 02:06:32 PM PDT 24
Finished Mar 26 02:06:54 PM PDT 24
Peak memory 216180 kb
Host smart-81f0911e-3dec-464c-9ef2-0ed55fee098a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388570208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1388570208
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3890772170
Short name T506
Test name
Test status
Simulation time 137441645 ps
CPU time 2.16 seconds
Started Mar 26 02:06:34 PM PDT 24
Finished Mar 26 02:06:38 PM PDT 24
Peak memory 216128 kb
Host smart-f923d05c-f1d9-4f82-98b4-8f6977c2c2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890772170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3890772170
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4159085603
Short name T837
Test name
Test status
Simulation time 30064726 ps
CPU time 0.84 seconds
Started Mar 26 02:06:34 PM PDT 24
Finished Mar 26 02:06:36 PM PDT 24
Peak memory 205460 kb
Host smart-d56b18ce-73d0-4033-9d7d-75c02bb1c185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159085603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4159085603
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2637649713
Short name T838
Test name
Test status
Simulation time 11415059436 ps
CPU time 33.86 seconds
Started Mar 26 02:06:36 PM PDT 24
Finished Mar 26 02:07:11 PM PDT 24
Peak memory 239716 kb
Host smart-1b673da3-08e9-4382-aaa4-0dbaeff9f16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637649713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2637649713
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1525215742
Short name T52
Test name
Test status
Simulation time 58304764 ps
CPU time 0.75 seconds
Started Mar 26 02:06:44 PM PDT 24
Finished Mar 26 02:06:45 PM PDT 24
Peak memory 205504 kb
Host smart-c8f58493-af22-4434-9443-7804d24917c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525215742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1525215742
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1358732925
Short name T526
Test name
Test status
Simulation time 6563570979 ps
CPU time 7.69 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:06:50 PM PDT 24
Peak memory 234060 kb
Host smart-96fbbea2-21b2-4798-9fde-c9b2a4762ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358732925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1358732925
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2724392877
Short name T399
Test name
Test status
Simulation time 29232030 ps
CPU time 0.76 seconds
Started Mar 26 02:06:32 PM PDT 24
Finished Mar 26 02:06:35 PM PDT 24
Peak memory 205412 kb
Host smart-c6917318-086c-4c08-982d-668411037e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724392877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2724392877
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2566401479
Short name T327
Test name
Test status
Simulation time 3317126212 ps
CPU time 28.18 seconds
Started Mar 26 02:06:42 PM PDT 24
Finished Mar 26 02:07:12 PM PDT 24
Peak memory 233728 kb
Host smart-0d023dd7-8d98-4ea4-83d8-c00ae8ff0f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566401479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2566401479
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2666704935
Short name T910
Test name
Test status
Simulation time 12845091897 ps
CPU time 169.48 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:09:30 PM PDT 24
Peak memory 256056 kb
Host smart-4fac38e9-fc26-4717-9aa8-ae4a172d9c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666704935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2666704935
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1907934031
Short name T834
Test name
Test status
Simulation time 61166387603 ps
CPU time 95.36 seconds
Started Mar 26 02:06:43 PM PDT 24
Finished Mar 26 02:08:19 PM PDT 24
Peak memory 232780 kb
Host smart-5c3cd071-afd6-4acf-a233-a2395e8566fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907934031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1907934031
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2596069044
Short name T839
Test name
Test status
Simulation time 356081683 ps
CPU time 7.38 seconds
Started Mar 26 02:06:43 PM PDT 24
Finished Mar 26 02:06:51 PM PDT 24
Peak memory 233692 kb
Host smart-9ddf5a48-229d-443e-a2ca-a4d941a34d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596069044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2596069044
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1775488903
Short name T689
Test name
Test status
Simulation time 1568380935 ps
CPU time 8.02 seconds
Started Mar 26 02:06:38 PM PDT 24
Finished Mar 26 02:06:46 PM PDT 24
Peak memory 232968 kb
Host smart-5e159566-7ea6-46d5-9bf3-dbfa486da920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775488903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1775488903
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.444201047
Short name T225
Test name
Test status
Simulation time 1049691941 ps
CPU time 9.56 seconds
Started Mar 26 02:06:34 PM PDT 24
Finished Mar 26 02:06:45 PM PDT 24
Peak memory 226088 kb
Host smart-ff04eed1-c231-4456-a7f9-af7e549a77f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444201047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.444201047
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1945234409
Short name T780
Test name
Test status
Simulation time 16827101933 ps
CPU time 8.59 seconds
Started Mar 26 02:06:36 PM PDT 24
Finished Mar 26 02:06:46 PM PDT 24
Peak memory 233620 kb
Host smart-1182d566-e19e-4b71-9b07-22ebabc1e0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945234409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1945234409
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1658500597
Short name T215
Test name
Test status
Simulation time 4654158767 ps
CPU time 8.3 seconds
Started Mar 26 02:06:35 PM PDT 24
Finished Mar 26 02:06:44 PM PDT 24
Peak memory 233656 kb
Host smart-50e20cf1-aa24-4cc7-b62b-6452ef20d974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658500597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1658500597
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3187721703
Short name T34
Test name
Test status
Simulation time 2214725628 ps
CPU time 6.46 seconds
Started Mar 26 02:06:42 PM PDT 24
Finished Mar 26 02:06:48 PM PDT 24
Peak memory 222716 kb
Host smart-701669bb-2eba-431d-b52f-a62db25d7ba6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3187721703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3187721703
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3236231567
Short name T744
Test name
Test status
Simulation time 91875258 ps
CPU time 1.08 seconds
Started Mar 26 02:06:43 PM PDT 24
Finished Mar 26 02:06:45 PM PDT 24
Peak memory 206684 kb
Host smart-34de77d8-b9ea-439a-b71c-4cbaf0975008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236231567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3236231567
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3249749588
Short name T360
Test name
Test status
Simulation time 12845480960 ps
CPU time 37.05 seconds
Started Mar 26 02:06:32 PM PDT 24
Finished Mar 26 02:07:09 PM PDT 24
Peak memory 216256 kb
Host smart-26b8ab3d-477b-4729-a321-cf1281d40ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249749588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3249749588
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.581206143
Short name T663
Test name
Test status
Simulation time 4504488084 ps
CPU time 12.2 seconds
Started Mar 26 02:06:35 PM PDT 24
Finished Mar 26 02:06:48 PM PDT 24
Peak memory 216228 kb
Host smart-60a1aa09-64ac-4d31-b2ef-8e2cc8c4d96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581206143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.581206143
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3430073292
Short name T653
Test name
Test status
Simulation time 80890985 ps
CPU time 2.28 seconds
Started Mar 26 02:06:31 PM PDT 24
Finished Mar 26 02:06:35 PM PDT 24
Peak memory 216088 kb
Host smart-c24fde75-a079-49f2-9faf-9915b8e84a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430073292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3430073292
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2558316867
Short name T674
Test name
Test status
Simulation time 266880061 ps
CPU time 1.01 seconds
Started Mar 26 02:06:33 PM PDT 24
Finished Mar 26 02:06:35 PM PDT 24
Peak memory 206568 kb
Host smart-f35c133f-d3d7-4a64-ad6a-d38a1e030778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558316867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2558316867
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2339002614
Short name T217
Test name
Test status
Simulation time 433554898 ps
CPU time 8.21 seconds
Started Mar 26 02:06:34 PM PDT 24
Finished Mar 26 02:06:44 PM PDT 24
Peak memory 240664 kb
Host smart-580aa574-ec11-4ecd-a4d9-6dabe74f3334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339002614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2339002614
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1534360560
Short name T53
Test name
Test status
Simulation time 32257617 ps
CPU time 0.76 seconds
Started Mar 26 02:01:33 PM PDT 24
Finished Mar 26 02:01:34 PM PDT 24
Peak memory 205152 kb
Host smart-f2e2ad47-8f9f-435c-bbdc-071a8726f4f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534360560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
534360560
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4143144265
Short name T383
Test name
Test status
Simulation time 764650543 ps
CPU time 4.11 seconds
Started Mar 26 02:01:29 PM PDT 24
Finished Mar 26 02:01:33 PM PDT 24
Peak memory 218436 kb
Host smart-5cd1bf74-195d-4cf0-b023-38df6b92cd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143144265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4143144265
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.381357684
Short name T869
Test name
Test status
Simulation time 30930823 ps
CPU time 0.79 seconds
Started Mar 26 02:01:27 PM PDT 24
Finished Mar 26 02:01:29 PM PDT 24
Peak memory 206376 kb
Host smart-a024a966-ef33-4859-8a1a-c9db80e2ddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381357684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.381357684
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1009405051
Short name T620
Test name
Test status
Simulation time 1878491422 ps
CPU time 29.14 seconds
Started Mar 26 02:01:25 PM PDT 24
Finished Mar 26 02:01:56 PM PDT 24
Peak memory 240740 kb
Host smart-5ff4ece3-df8b-4db8-b5f1-48ba26619f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009405051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1009405051
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1498569572
Short name T909
Test name
Test status
Simulation time 14055987900 ps
CPU time 94.56 seconds
Started Mar 26 02:01:29 PM PDT 24
Finished Mar 26 02:03:04 PM PDT 24
Peak memory 262904 kb
Host smart-d2356640-97b4-4694-9b9f-e1e5f3023f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498569572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1498569572
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3879538110
Short name T264
Test name
Test status
Simulation time 15303782684 ps
CPU time 157.01 seconds
Started Mar 26 02:01:26 PM PDT 24
Finished Mar 26 02:04:03 PM PDT 24
Peak memory 273636 kb
Host smart-98211eaa-605b-49fe-a5a9-4484b3d0cca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879538110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3879538110
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3794070237
Short name T357
Test name
Test status
Simulation time 8983403961 ps
CPU time 38.2 seconds
Started Mar 26 02:01:24 PM PDT 24
Finished Mar 26 02:02:03 PM PDT 24
Peak memory 248276 kb
Host smart-05c5c9d9-4f6d-4bac-8140-8e264daf21ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794070237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3794070237
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.62722966
Short name T673
Test name
Test status
Simulation time 1282961982 ps
CPU time 3.94 seconds
Started Mar 26 02:01:30 PM PDT 24
Finished Mar 26 02:01:35 PM PDT 24
Peak memory 233536 kb
Host smart-9155641d-7aa7-4614-9556-6b2996909430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62722966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.62722966
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.40003706
Short name T727
Test name
Test status
Simulation time 647673163 ps
CPU time 4.74 seconds
Started Mar 26 02:01:26 PM PDT 24
Finished Mar 26 02:01:31 PM PDT 24
Peak memory 224368 kb
Host smart-6391acd1-4281-4e36-ba1c-7d5758e89100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40003706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.40003706
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2619125011
Short name T602
Test name
Test status
Simulation time 25661482 ps
CPU time 1.18 seconds
Started Mar 26 02:01:30 PM PDT 24
Finished Mar 26 02:01:32 PM PDT 24
Peak memory 216432 kb
Host smart-91552fce-4965-4d3a-ba5a-7fdd630b17d4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619125011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2619125011
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3579097183
Short name T553
Test name
Test status
Simulation time 1866002985 ps
CPU time 6.1 seconds
Started Mar 26 02:01:27 PM PDT 24
Finished Mar 26 02:01:34 PM PDT 24
Peak memory 224248 kb
Host smart-a471edc4-9c85-4f90-b4ab-aa2ce15c8345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579097183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3579097183
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3163526733
Short name T807
Test name
Test status
Simulation time 23778577685 ps
CPU time 19.72 seconds
Started Mar 26 02:01:30 PM PDT 24
Finished Mar 26 02:01:51 PM PDT 24
Peak memory 234276 kb
Host smart-6f488195-8a11-48a6-997c-f0b26e8db9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163526733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3163526733
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.385911461
Short name T484
Test name
Test status
Simulation time 17071158 ps
CPU time 0.76 seconds
Started Mar 26 02:01:26 PM PDT 24
Finished Mar 26 02:01:27 PM PDT 24
Peak memory 216036 kb
Host smart-ef47c27f-c6dd-4e76-b939-b39a34512529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385911461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.385911461
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2475739471
Short name T501
Test name
Test status
Simulation time 946907339 ps
CPU time 3.85 seconds
Started Mar 26 02:01:34 PM PDT 24
Finished Mar 26 02:01:38 PM PDT 24
Peak memory 219792 kb
Host smart-a3182d1a-db75-48a6-a6e0-2c4de2275f0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2475739471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2475739471
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.618621400
Short name T140
Test name
Test status
Simulation time 656713436202 ps
CPU time 611.14 seconds
Started Mar 26 02:01:26 PM PDT 24
Finished Mar 26 02:11:38 PM PDT 24
Peak memory 269172 kb
Host smart-b3a15b19-fc39-49dd-b5ac-8bec95eeb52f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618621400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.618621400
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1955343402
Short name T430
Test name
Test status
Simulation time 1436680300 ps
CPU time 11.42 seconds
Started Mar 26 02:01:30 PM PDT 24
Finished Mar 26 02:01:42 PM PDT 24
Peak memory 217848 kb
Host smart-43b9e844-fb03-4bd3-8f55-e1d676d91395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955343402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1955343402
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1941855409
Short name T732
Test name
Test status
Simulation time 12122874128 ps
CPU time 10.64 seconds
Started Mar 26 02:01:31 PM PDT 24
Finished Mar 26 02:01:43 PM PDT 24
Peak memory 216076 kb
Host smart-707307ea-b121-4b9f-8561-86d767ea3718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941855409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1941855409
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2166187078
Short name T508
Test name
Test status
Simulation time 140916106 ps
CPU time 1.4 seconds
Started Mar 26 02:01:27 PM PDT 24
Finished Mar 26 02:01:29 PM PDT 24
Peak memory 216024 kb
Host smart-a109d4c8-eed0-4027-9ad3-a7ef08cf1bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166187078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2166187078
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2260329589
Short name T703
Test name
Test status
Simulation time 550490640 ps
CPU time 1.16 seconds
Started Mar 26 02:01:27 PM PDT 24
Finished Mar 26 02:01:29 PM PDT 24
Peak memory 206568 kb
Host smart-0ff97c55-ae09-44ba-a713-7bd3d4da1a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260329589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2260329589
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3546959345
Short name T791
Test name
Test status
Simulation time 1146729937 ps
CPU time 8.92 seconds
Started Mar 26 02:01:25 PM PDT 24
Finished Mar 26 02:01:34 PM PDT 24
Peak memory 228688 kb
Host smart-a2d5a2dc-0530-4d97-a46f-8373bb89be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546959345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3546959345
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2313272576
Short name T912
Test name
Test status
Simulation time 21343742 ps
CPU time 0.7 seconds
Started Mar 26 02:01:34 PM PDT 24
Finished Mar 26 02:01:35 PM PDT 24
Peak memory 205128 kb
Host smart-32ad08ca-554b-4bab-9e35-cf63156e7d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313272576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
313272576
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2666953173
Short name T832
Test name
Test status
Simulation time 474373498 ps
CPU time 2.43 seconds
Started Mar 26 02:01:29 PM PDT 24
Finished Mar 26 02:01:33 PM PDT 24
Peak memory 218392 kb
Host smart-fb0c2765-a0f5-4858-bdcb-debfcadaf9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666953173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2666953173
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3691446841
Short name T895
Test name
Test status
Simulation time 19964262 ps
CPU time 0.77 seconds
Started Mar 26 02:01:27 PM PDT 24
Finished Mar 26 02:01:29 PM PDT 24
Peak memory 205032 kb
Host smart-23b21448-b017-4728-a4a7-f37755d5f10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691446841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3691446841
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.730021253
Short name T152
Test name
Test status
Simulation time 101747592413 ps
CPU time 38.09 seconds
Started Mar 26 02:01:25 PM PDT 24
Finished Mar 26 02:02:04 PM PDT 24
Peak memory 236752 kb
Host smart-39fec70d-f1f4-437e-9ab3-4dae03d34da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730021253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.730021253
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2250031810
Short name T261
Test name
Test status
Simulation time 617477665842 ps
CPU time 438.2 seconds
Started Mar 26 02:01:27 PM PDT 24
Finished Mar 26 02:08:46 PM PDT 24
Peak memory 257356 kb
Host smart-a3eaa68d-844b-4aa0-866a-419d153ee522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250031810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2250031810
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3788055636
Short name T643
Test name
Test status
Simulation time 6103226701 ps
CPU time 37.81 seconds
Started Mar 26 02:01:29 PM PDT 24
Finished Mar 26 02:02:07 PM PDT 24
Peak memory 230380 kb
Host smart-ac45c1a7-f473-4c92-82fe-c2f0bf9d8742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788055636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3788055636
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2572061151
Short name T375
Test name
Test status
Simulation time 291351641 ps
CPU time 3.89 seconds
Started Mar 26 02:01:26 PM PDT 24
Finished Mar 26 02:01:30 PM PDT 24
Peak memory 233640 kb
Host smart-5f92645c-d8fe-447c-8291-a282f9e0fb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572061151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2572061151
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.177049904
Short name T766
Test name
Test status
Simulation time 62941760436 ps
CPU time 41.67 seconds
Started Mar 26 02:01:25 PM PDT 24
Finished Mar 26 02:02:08 PM PDT 24
Peak memory 228516 kb
Host smart-19470cdf-adf4-49c2-ad39-61a016ba02fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177049904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.177049904
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2471115475
Short name T464
Test name
Test status
Simulation time 104874354 ps
CPU time 1.11 seconds
Started Mar 26 02:01:25 PM PDT 24
Finished Mar 26 02:01:27 PM PDT 24
Peak memory 217592 kb
Host smart-caecfd18-1440-48be-bbe9-bbca109e88fb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471115475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2471115475
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4143629746
Short name T491
Test name
Test status
Simulation time 5797989887 ps
CPU time 5.87 seconds
Started Mar 26 02:01:28 PM PDT 24
Finished Mar 26 02:01:35 PM PDT 24
Peak memory 216528 kb
Host smart-e86f4e3d-f803-41a7-9710-ef8f6d21da66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143629746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4143629746
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4113606437
Short name T572
Test name
Test status
Simulation time 5134621793 ps
CPU time 7.3 seconds
Started Mar 26 02:01:28 PM PDT 24
Finished Mar 26 02:01:37 PM PDT 24
Peak memory 222616 kb
Host smart-cdb8e34c-b9f0-428a-a813-0047e91da200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113606437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4113606437
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.134077552
Short name T58
Test name
Test status
Simulation time 18471866 ps
CPU time 0.77 seconds
Started Mar 26 02:01:33 PM PDT 24
Finished Mar 26 02:01:35 PM PDT 24
Peak memory 216088 kb
Host smart-73039106-33b8-4c7f-9d4f-bc8fe3cf797d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134077552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.134077552
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1823830058
Short name T784
Test name
Test status
Simulation time 467881848 ps
CPU time 4.68 seconds
Started Mar 26 02:01:26 PM PDT 24
Finished Mar 26 02:01:31 PM PDT 24
Peak memory 218696 kb
Host smart-58f2015c-bdb9-4c9c-a2cb-57df388909e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1823830058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1823830058
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1739442550
Short name T359
Test name
Test status
Simulation time 42426378853 ps
CPU time 224.64 seconds
Started Mar 26 02:01:26 PM PDT 24
Finished Mar 26 02:05:11 PM PDT 24
Peak memory 254908 kb
Host smart-3399dc39-9940-4a64-83af-e42e5eac8a47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739442550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1739442550
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.490507357
Short name T47
Test name
Test status
Simulation time 3752119882 ps
CPU time 7.17 seconds
Started Mar 26 02:01:25 PM PDT 24
Finished Mar 26 02:01:32 PM PDT 24
Peak memory 216172 kb
Host smart-f794f9d5-8f53-4674-9b54-84268b262df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490507357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.490507357
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2014744435
Short name T857
Test name
Test status
Simulation time 2148262560 ps
CPU time 3.16 seconds
Started Mar 26 02:01:27 PM PDT 24
Finished Mar 26 02:01:31 PM PDT 24
Peak memory 216232 kb
Host smart-fd0abb9d-a863-46cd-9fb3-f175201a42d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014744435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2014744435
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2845463218
Short name T986
Test name
Test status
Simulation time 321822886 ps
CPU time 1.78 seconds
Started Mar 26 02:01:33 PM PDT 24
Finished Mar 26 02:01:35 PM PDT 24
Peak memory 216296 kb
Host smart-2cba08f2-b2f8-4957-ba7f-b56f6e871948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845463218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2845463218
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1009022847
Short name T287
Test name
Test status
Simulation time 51424006 ps
CPU time 0.97 seconds
Started Mar 26 02:01:27 PM PDT 24
Finished Mar 26 02:01:29 PM PDT 24
Peak memory 206532 kb
Host smart-529b39d2-0d5a-4181-ad01-10699cb79160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009022847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1009022847
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3702963400
Short name T853
Test name
Test status
Simulation time 1399491699 ps
CPU time 5.44 seconds
Started Mar 26 02:01:32 PM PDT 24
Finished Mar 26 02:01:38 PM PDT 24
Peak memory 233376 kb
Host smart-0b0d79c1-9bfd-400f-a253-999b023986bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702963400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3702963400
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1357548494
Short name T637
Test name
Test status
Simulation time 20184140 ps
CPU time 0.72 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:01:54 PM PDT 24
Peak memory 205192 kb
Host smart-40ad3b66-9e40-4d33-aa25-a475f5cb6ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357548494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
357548494
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1510155615
Short name T718
Test name
Test status
Simulation time 329964473 ps
CPU time 5.01 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:01:59 PM PDT 24
Peak memory 219328 kb
Host smart-cee4a1d2-5b25-4f07-bf51-2d3504fd0271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510155615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1510155615
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.559589761
Short name T302
Test name
Test status
Simulation time 34531314 ps
CPU time 0.77 seconds
Started Mar 26 02:01:39 PM PDT 24
Finished Mar 26 02:01:40 PM PDT 24
Peak memory 206160 kb
Host smart-2dba6c30-a7d3-44f9-839c-7256cd5cb8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559589761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.559589761
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.300154887
Short name T973
Test name
Test status
Simulation time 13961605516 ps
CPU time 51.96 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:02:45 PM PDT 24
Peak memory 252840 kb
Host smart-8ad5a097-4638-4bc0-81d2-5c64a5c11410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300154887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.300154887
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2286056308
Short name T757
Test name
Test status
Simulation time 79370556609 ps
CPU time 415.69 seconds
Started Mar 26 02:01:56 PM PDT 24
Finished Mar 26 02:08:52 PM PDT 24
Peak memory 252960 kb
Host smart-37936f00-7f87-439e-b27a-3f6e9ae1cc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286056308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2286056308
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3218961282
Short name T555
Test name
Test status
Simulation time 12491732576 ps
CPU time 40.55 seconds
Started Mar 26 02:01:55 PM PDT 24
Finished Mar 26 02:02:36 PM PDT 24
Peak memory 239380 kb
Host smart-562e2b03-1079-4d38-810b-bf4e8f2df637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218961282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3218961282
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2072255434
Short name T545
Test name
Test status
Simulation time 4083250743 ps
CPU time 11.9 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:02:05 PM PDT 24
Peak memory 235300 kb
Host smart-8756727a-c34c-45e0-831a-61428c0dfbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072255434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2072255434
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1811216183
Short name T671
Test name
Test status
Simulation time 798114277 ps
CPU time 5.49 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:01:59 PM PDT 24
Peak memory 232964 kb
Host smart-81ec231a-c766-4a65-a3c4-8dce4e3093d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811216183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1811216183
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3471857452
Short name T480
Test name
Test status
Simulation time 544817961 ps
CPU time 7.36 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:02:01 PM PDT 24
Peak memory 232208 kb
Host smart-a79caa4d-76fa-473e-89a8-49f94ba3a02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471857452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3471857452
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2815705751
Short name T397
Test name
Test status
Simulation time 218115035 ps
CPU time 1.05 seconds
Started Mar 26 02:01:39 PM PDT 24
Finished Mar 26 02:01:40 PM PDT 24
Peak memory 216504 kb
Host smart-d73831fb-a69a-4fe1-9bfd-cd9a73d14114
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815705751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2815705751
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.771447940
Short name T309
Test name
Test status
Simulation time 4827147768 ps
CPU time 5.31 seconds
Started Mar 26 02:01:38 PM PDT 24
Finished Mar 26 02:01:44 PM PDT 24
Peak memory 235396 kb
Host smart-ce9e1b6b-f731-4e5e-8882-fd20df96752d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771447940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
771447940
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1792673496
Short name T467
Test name
Test status
Simulation time 2163622457 ps
CPU time 7.22 seconds
Started Mar 26 02:01:39 PM PDT 24
Finished Mar 26 02:01:46 PM PDT 24
Peak memory 217732 kb
Host smart-dc94c801-b1b4-4be2-b324-356f877ac42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792673496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1792673496
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.2760566980
Short name T416
Test name
Test status
Simulation time 36919867 ps
CPU time 0.75 seconds
Started Mar 26 02:01:39 PM PDT 24
Finished Mar 26 02:01:39 PM PDT 24
Peak memory 216108 kb
Host smart-2213f49d-4436-4c00-b343-155010aa2ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760566980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2760566980
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2237248700
Short name T692
Test name
Test status
Simulation time 763508234 ps
CPU time 5.37 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:01:58 PM PDT 24
Peak memory 222812 kb
Host smart-af47e69f-2b1c-44d2-b870-f2e084f509df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2237248700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2237248700
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1372892431
Short name T259
Test name
Test status
Simulation time 7343746592 ps
CPU time 110.55 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:03:45 PM PDT 24
Peak memory 265364 kb
Host smart-7aef1dd9-a0ec-4205-b36c-b62f74af3541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372892431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1372892431
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4019688996
Short name T362
Test name
Test status
Simulation time 49508965994 ps
CPU time 16.34 seconds
Started Mar 26 02:01:41 PM PDT 24
Finished Mar 26 02:01:57 PM PDT 24
Peak memory 216132 kb
Host smart-9107c56f-005f-40fc-aa42-94983907ae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019688996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4019688996
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2199313353
Short name T914
Test name
Test status
Simulation time 2529058807 ps
CPU time 7.99 seconds
Started Mar 26 02:01:37 PM PDT 24
Finished Mar 26 02:01:46 PM PDT 24
Peak memory 216240 kb
Host smart-6290fb76-db75-428a-98e7-53e519497539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199313353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2199313353
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.102791874
Short name T935
Test name
Test status
Simulation time 52700511 ps
CPU time 1 seconds
Started Mar 26 02:01:37 PM PDT 24
Finished Mar 26 02:01:38 PM PDT 24
Peak memory 206468 kb
Host smart-f8a59116-3fde-4d24-be32-10c6d4c4aa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102791874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.102791874
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1028656000
Short name T559
Test name
Test status
Simulation time 427868289 ps
CPU time 1.03 seconds
Started Mar 26 02:01:31 PM PDT 24
Finished Mar 26 02:01:33 PM PDT 24
Peak memory 206440 kb
Host smart-3cfc3dbf-ea50-4583-8e12-e1efd68b10b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028656000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1028656000
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2969743502
Short name T192
Test name
Test status
Simulation time 2254003154 ps
CPU time 12.77 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:02:07 PM PDT 24
Peak memory 219700 kb
Host smart-13665426-8372-449f-96c5-98eb18da6836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969743502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2969743502
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2442121161
Short name T450
Test name
Test status
Simulation time 31479954 ps
CPU time 0.7 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:01:53 PM PDT 24
Peak memory 205412 kb
Host smart-2b626bcf-e997-4f12-ae3b-820bcba77379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442121161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
442121161
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1094545558
Short name T326
Test name
Test status
Simulation time 546485698 ps
CPU time 3 seconds
Started Mar 26 02:01:52 PM PDT 24
Finished Mar 26 02:01:55 PM PDT 24
Peak memory 235532 kb
Host smart-041be7f1-0d29-410a-a101-cc29d3a28cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094545558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1094545558
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1870778507
Short name T533
Test name
Test status
Simulation time 25085445 ps
CPU time 0.8 seconds
Started Mar 26 02:01:52 PM PDT 24
Finished Mar 26 02:01:53 PM PDT 24
Peak memory 206236 kb
Host smart-48b80901-e117-42b8-a8e4-5854708c68dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870778507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1870778507
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1729491978
Short name T722
Test name
Test status
Simulation time 50952326100 ps
CPU time 143.92 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:04:17 PM PDT 24
Peak memory 248956 kb
Host smart-1b2764da-5033-49d3-9a7d-de2532700ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729491978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1729491978
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.565898764
Short name T245
Test name
Test status
Simulation time 15364805508 ps
CPU time 92.48 seconds
Started Mar 26 02:01:56 PM PDT 24
Finished Mar 26 02:03:29 PM PDT 24
Peak memory 233904 kb
Host smart-4c991164-7dd2-4e2a-a904-184301c0f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565898764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
565898764
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4258315524
Short name T265
Test name
Test status
Simulation time 2248994428 ps
CPU time 19.97 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:02:13 PM PDT 24
Peak memory 239008 kb
Host smart-a623633e-1972-4671-9079-4ed0f0e9926f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258315524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4258315524
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1104281322
Short name T168
Test name
Test status
Simulation time 13187779560 ps
CPU time 9.68 seconds
Started Mar 26 02:01:56 PM PDT 24
Finished Mar 26 02:02:06 PM PDT 24
Peak memory 219748 kb
Host smart-b53b51af-48e7-4478-a6cd-d7bbcba10269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104281322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1104281322
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2119180249
Short name T626
Test name
Test status
Simulation time 2177506902 ps
CPU time 9.76 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:02:04 PM PDT 24
Peak memory 257132 kb
Host smart-83fb1c81-c444-476e-adb9-67519db74514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119180249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2119180249
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.436313267
Short name T437
Test name
Test status
Simulation time 49367167 ps
CPU time 1.07 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:01:55 PM PDT 24
Peak memory 216480 kb
Host smart-cbcc00b4-611d-499b-9834-7dddb7cabbf7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436313267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.436313267
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3354207259
Short name T237
Test name
Test status
Simulation time 15717040429 ps
CPU time 26.05 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:02:20 PM PDT 24
Peak memory 239124 kb
Host smart-2ed99bdc-c54c-4c31-a4ef-c661982b1659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354207259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3354207259
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.365624452
Short name T690
Test name
Test status
Simulation time 16095535483 ps
CPU time 25.63 seconds
Started Mar 26 02:01:55 PM PDT 24
Finished Mar 26 02:02:21 PM PDT 24
Peak memory 232752 kb
Host smart-941c1b2c-1fa2-48e1-91c0-8037f1ac9373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365624452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.365624452
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.2150769515
Short name T597
Test name
Test status
Simulation time 28532319 ps
CPU time 0.73 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:01:54 PM PDT 24
Peak memory 216076 kb
Host smart-4f44ce36-9c30-4e0e-81d1-129303858d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150769515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.2150769515
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4238790213
Short name T120
Test name
Test status
Simulation time 171532802 ps
CPU time 3.32 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:01:57 PM PDT 24
Peak memory 220000 kb
Host smart-8b3428b3-d14d-4e41-9eaa-8a59b51a6b69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4238790213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4238790213
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3119536079
Short name T717
Test name
Test status
Simulation time 63488279 ps
CPU time 1.19 seconds
Started Mar 26 02:01:52 PM PDT 24
Finished Mar 26 02:01:54 PM PDT 24
Peak memory 206436 kb
Host smart-8304912e-4257-4cdf-8db0-ed115f49d82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119536079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3119536079
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.656324499
Short name T269
Test name
Test status
Simulation time 612992500 ps
CPU time 7.98 seconds
Started Mar 26 02:01:55 PM PDT 24
Finished Mar 26 02:02:03 PM PDT 24
Peak memory 215976 kb
Host smart-6ab6b724-0fdc-4221-a3b7-6bb0f114dca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656324499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.656324499
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1704661667
Short name T850
Test name
Test status
Simulation time 9112895138 ps
CPU time 7.56 seconds
Started Mar 26 02:01:55 PM PDT 24
Finished Mar 26 02:02:03 PM PDT 24
Peak memory 216420 kb
Host smart-9e93c0c6-0c6d-4df7-ba13-0be12cae7c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704661667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1704661667
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1061004829
Short name T293
Test name
Test status
Simulation time 141852315 ps
CPU time 2.13 seconds
Started Mar 26 02:01:55 PM PDT 24
Finished Mar 26 02:01:58 PM PDT 24
Peak memory 216116 kb
Host smart-32e6d776-0edc-4d7e-8bee-9d8eb06bc728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061004829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1061004829
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1599021182
Short name T667
Test name
Test status
Simulation time 193571757 ps
CPU time 0.88 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:01:54 PM PDT 24
Peak memory 205548 kb
Host smart-d1bf2662-078d-404f-af40-aa74b3ff8e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599021182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1599021182
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3839901874
Short name T234
Test name
Test status
Simulation time 3893990220 ps
CPU time 11.82 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:02:05 PM PDT 24
Peak memory 228964 kb
Host smart-cbc72408-2215-45fd-b6e1-477d33ef14a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839901874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3839901874
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.333702537
Short name T570
Test name
Test status
Simulation time 16625035 ps
CPU time 0.74 seconds
Started Mar 26 02:02:06 PM PDT 24
Finished Mar 26 02:02:07 PM PDT 24
Peak memory 205160 kb
Host smart-cf2662da-1bb0-4666-bdef-b4537b252605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333702537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.333702537
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2085550226
Short name T965
Test name
Test status
Simulation time 298014366 ps
CPU time 2.12 seconds
Started Mar 26 02:02:08 PM PDT 24
Finished Mar 26 02:02:10 PM PDT 24
Peak memory 216864 kb
Host smart-57d8a935-c104-4414-9e3d-53efaf388ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085550226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2085550226
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1129196287
Short name T50
Test name
Test status
Simulation time 229537042 ps
CPU time 0.79 seconds
Started Mar 26 02:01:55 PM PDT 24
Finished Mar 26 02:01:56 PM PDT 24
Peak memory 206236 kb
Host smart-26c2d2c3-1764-494c-b0bf-e668cbee8683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129196287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1129196287
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3762594660
Short name T760
Test name
Test status
Simulation time 5307079641 ps
CPU time 33.61 seconds
Started Mar 26 02:02:07 PM PDT 24
Finished Mar 26 02:02:40 PM PDT 24
Peak memory 238052 kb
Host smart-a0799d85-e771-411e-b40e-dc623f51eeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762594660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3762594660
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2810395743
Short name T538
Test name
Test status
Simulation time 4485263333 ps
CPU time 93.09 seconds
Started Mar 26 02:02:08 PM PDT 24
Finished Mar 26 02:03:41 PM PDT 24
Peak memory 256004 kb
Host smart-f3fa6d50-aa6e-4cdf-bd0e-d90dfe932172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810395743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2810395743
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2762488458
Short name T25
Test name
Test status
Simulation time 12108184218 ps
CPU time 69.93 seconds
Started Mar 26 02:02:08 PM PDT 24
Finished Mar 26 02:03:18 PM PDT 24
Peak memory 249136 kb
Host smart-9999be62-2a3d-459c-bd7b-990ef2523bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762488458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2762488458
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3354195703
Short name T655
Test name
Test status
Simulation time 1839996706 ps
CPU time 20.2 seconds
Started Mar 26 02:02:06 PM PDT 24
Finished Mar 26 02:02:26 PM PDT 24
Peak memory 237724 kb
Host smart-e80f3020-82a6-444d-85e4-3963b4a1a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354195703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3354195703
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1361582841
Short name T373
Test name
Test status
Simulation time 1536460710 ps
CPU time 4.65 seconds
Started Mar 26 02:02:09 PM PDT 24
Finished Mar 26 02:02:14 PM PDT 24
Peak memory 233272 kb
Host smart-51916d56-b1ec-412e-bb00-3a382c6f385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361582841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1361582841
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2464039071
Short name T698
Test name
Test status
Simulation time 51280279398 ps
CPU time 69.4 seconds
Started Mar 26 02:02:09 PM PDT 24
Finished Mar 26 02:03:18 PM PDT 24
Peak memory 240224 kb
Host smart-d0d07c54-4a91-4e5f-ac04-c2b47c2db1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464039071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2464039071
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3809896844
Short name T848
Test name
Test status
Simulation time 225596400 ps
CPU time 1.08 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:01:55 PM PDT 24
Peak memory 217584 kb
Host smart-726ce37f-0636-47f2-aba4-6731bbb2597a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809896844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3809896844
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2584690370
Short name T575
Test name
Test status
Simulation time 6316753358 ps
CPU time 19.87 seconds
Started Mar 26 02:02:07 PM PDT 24
Finished Mar 26 02:02:27 PM PDT 24
Peak memory 234500 kb
Host smart-31158481-47f5-478d-96ee-02ffebd1f97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584690370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2584690370
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3124923770
Short name T167
Test name
Test status
Simulation time 16594480442 ps
CPU time 19.36 seconds
Started Mar 26 02:01:56 PM PDT 24
Finished Mar 26 02:02:15 PM PDT 24
Peak memory 236104 kb
Host smart-deaefc9e-e109-44fe-8e82-16f13a10a89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124923770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3124923770
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2903463836
Short name T563
Test name
Test status
Simulation time 22656884 ps
CPU time 0.74 seconds
Started Mar 26 02:01:53 PM PDT 24
Finished Mar 26 02:01:54 PM PDT 24
Peak memory 216132 kb
Host smart-1a3bcb70-69b7-4319-85b8-6d9adb64b77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903463836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2903463836
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3729004506
Short name T862
Test name
Test status
Simulation time 528907441 ps
CPU time 4.18 seconds
Started Mar 26 02:02:09 PM PDT 24
Finished Mar 26 02:02:13 PM PDT 24
Peak memory 221456 kb
Host smart-53c8942e-5937-4f28-aa8b-a41e95443e07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3729004506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3729004506
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1910337786
Short name T475
Test name
Test status
Simulation time 4358582033 ps
CPU time 47.56 seconds
Started Mar 26 02:02:07 PM PDT 24
Finished Mar 26 02:02:54 PM PDT 24
Peak memory 251640 kb
Host smart-b738b509-174a-4192-b685-66639fe20c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910337786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1910337786
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1180215134
Short name T577
Test name
Test status
Simulation time 6732940964 ps
CPU time 21.08 seconds
Started Mar 26 02:01:55 PM PDT 24
Finished Mar 26 02:02:16 PM PDT 24
Peak memory 216244 kb
Host smart-ca247095-fdf0-4ef0-a924-a297b48acb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180215134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1180215134
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1679380734
Short name T146
Test name
Test status
Simulation time 3906018991 ps
CPU time 15.91 seconds
Started Mar 26 02:01:55 PM PDT 24
Finished Mar 26 02:02:11 PM PDT 24
Peak memory 216204 kb
Host smart-17a2dfb5-a2ac-4bcd-85d6-740db6634d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679380734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1679380734
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3700478645
Short name T584
Test name
Test status
Simulation time 355232369 ps
CPU time 2.15 seconds
Started Mar 26 02:01:56 PM PDT 24
Finished Mar 26 02:01:58 PM PDT 24
Peak memory 217076 kb
Host smart-91e918f7-31dd-48cc-a031-f8777de922b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700478645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3700478645
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1436135489
Short name T280
Test name
Test status
Simulation time 55953730 ps
CPU time 0.85 seconds
Started Mar 26 02:01:54 PM PDT 24
Finished Mar 26 02:01:54 PM PDT 24
Peak memory 205544 kb
Host smart-91a00be4-7ac0-4974-9303-464949874690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436135489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1436135489
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3362735678
Short name T288
Test name
Test status
Simulation time 984989128 ps
CPU time 8.27 seconds
Started Mar 26 02:02:07 PM PDT 24
Finished Mar 26 02:02:16 PM PDT 24
Peak memory 240452 kb
Host smart-493d819d-2b90-4659-8a8f-f45b7f7fd042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362735678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3362735678
Directory /workspace/9.spi_device_upload/latest
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