Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6396086	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6673254

1

T1

16837

T2

5696

T3

891

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8458143	1			T1	16689		T2	7472		T3	6
values[0x0]	2305242	1			T1	6801		T2	2790		T3	446
values[0x1]	2305955	1			T1	6884		T2	2669		T3	445

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4633453	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8435887

1

T1

20630

T2

7927

T3

892

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54305	1			T1	109		T3	2		T4	119
valid_sources[0x01]	50620	1			T1	106		T2	3		T3	4
valid_sources[0x02]	52614	1			T1	147		T2	132		T3	7
valid_sources[0x03]	51378	1			T1	99		T2	334		T3	8
valid_sources[0x04]	48066	1			T1	113		T2	529		T3	8
valid_sources[0x05]	49943	1			T1	133		T4	41		T5	103
valid_sources[0x06]	50615	1			T1	122		T2	1		T3	4
valid_sources[0x07]	49880	1			T1	121		T4	127		T5	138
valid_sources[0x08]	48919	1			T1	126		T2	198		T3	2
valid_sources[0x09]	51474	1			T1	78		T2	631		T3	1
valid_sources[0x0a]	50609	1			T1	89		T3	2		T4	172
valid_sources[0x0b]	49868	1			T1	173		T2	138		T3	7
valid_sources[0x0c]	50909	1			T1	118		T2	1		T4	136
valid_sources[0x0d]	50249	1			T1	109		T3	1		T4	97
valid_sources[0x0e]	49940	1			T1	114		T3	3		T4	76
valid_sources[0x0f]	52804	1			T1	128		T2	2		T4	84
valid_sources[0x10]	50227	1			T1	93		T3	6		T4	87
valid_sources[0x11]	52864	1			T1	111		T4	36		T5	116
valid_sources[0x12]	51918	1			T1	118		T3	8		T4	32
valid_sources[0x13]	52849	1			T1	111		T3	4		T4	72
valid_sources[0x14]	48627	1			T1	113		T3	1		T4	101
valid_sources[0x15]	48987	1			T1	113		T2	2		T3	13
valid_sources[0x16]	47946	1			T1	153		T2	207		T3	2
valid_sources[0x17]	53897	1			T1	117		T3	2		T4	87
valid_sources[0x18]	58456	1			T1	107		T3	7		T4	93
valid_sources[0x19]	48975	1			T1	101		T3	2		T4	61
valid_sources[0x1a]	48492	1			T1	121		T3	1		T4	73
valid_sources[0x1b]	48732	1			T1	86		T3	8		T4	115
valid_sources[0x1c]	51612	1			T1	153		T3	5		T4	90
valid_sources[0x1d]	51699	1			T1	98		T4	47		T5	168
valid_sources[0x1e]	47353	1			T1	170		T2	3		T3	6
valid_sources[0x1f]	49581	1			T1	90		T3	3		T4	37
valid_sources[0x20]	58566	1			T1	97		T2	6		T4	102
valid_sources[0x21]	49475	1			T1	116		T2	1051		T4	109
valid_sources[0x22]	49119	1			T1	111		T3	14		T4	118
valid_sources[0x23]	49672	1			T1	139		T3	4		T4	102
valid_sources[0x24]	51756	1			T1	108		T3	6		T4	41
valid_sources[0x25]	54348	1			T1	117		T4	88		T5	95
valid_sources[0x26]	51306	1			T1	145		T3	1		T4	56
valid_sources[0x27]	48867	1			T1	110		T3	2		T4	42
valid_sources[0x28]	50120	1			T1	142		T3	5		T4	46
valid_sources[0x29]	51105	1			T1	107		T2	154		T3	5
valid_sources[0x2a]	48015	1			T1	127		T3	9		T4	86
valid_sources[0x2b]	48037	1			T1	101		T3	3		T4	94
valid_sources[0x2c]	49725	1			T1	154		T4	69		T5	134
valid_sources[0x2d]	52773	1			T1	108		T2	69		T3	1
valid_sources[0x2e]	53867	1			T1	119		T2	39		T3	1
valid_sources[0x2f]	48436	1			T1	128		T3	2		T4	119
valid_sources[0x30]	53602	1			T1	104		T2	4		T3	2
valid_sources[0x31]	48725	1			T1	104		T2	1		T3	3
valid_sources[0x32]	50423	1			T1	127		T4	68		T5	132
valid_sources[0x33]	48877	1			T1	121		T3	5		T4	46
valid_sources[0x34]	53110	1			T1	126		T3	3		T4	57
valid_sources[0x35]	51141	1			T1	115		T2	125		T3	5
valid_sources[0x36]	49865	1			T1	137		T3	16		T4	176
valid_sources[0x37]	50612	1			T1	81		T2	4		T3	2
valid_sources[0x38]	50847	1			T1	145		T3	3		T4	147
valid_sources[0x39]	50897	1			T1	117		T3	5		T4	119
valid_sources[0x3a]	49056	1			T1	137		T2	1		T3	8
valid_sources[0x3b]	48620	1			T1	117		T3	9		T4	140
valid_sources[0x3c]	48231	1			T1	119		T2	22		T3	1
valid_sources[0x3d]	59791	1			T1	91		T2	513		T3	2
valid_sources[0x3e]	52890	1			T1	119		T3	1		T4	69
valid_sources[0x3f]	52911	1			T1	131		T2	147		T4	159
valid_sources[0x40]	51143	1			T1	94		T2	85		T3	1
valid_sources[0x41]	56424	1			T1	92		T3	7		T4	109
valid_sources[0x42]	50467	1			T1	112		T2	28		T3	2
valid_sources[0x43]	50185	1			T1	135		T3	6		T4	86
valid_sources[0x44]	51387	1			T1	152		T2	3		T3	1
valid_sources[0x45]	51930	1			T1	119		T2	144		T4	97
valid_sources[0x46]	52006	1			T1	87		T3	6		T4	138
valid_sources[0x47]	67303	1			T1	114		T2	1		T3	9
valid_sources[0x48]	50616	1			T1	135		T2	1		T3	7
valid_sources[0x49]	49644	1			T1	119		T3	2		T4	96
valid_sources[0x4a]	49450	1			T1	132		T3	11		T4	31
valid_sources[0x4b]	48571	1			T1	116		T2	101		T3	6
valid_sources[0x4c]	50882	1			T1	115		T2	4		T3	2
valid_sources[0x4d]	57177	1			T1	118		T3	10		T4	71
valid_sources[0x4e]	52392	1			T1	145		T2	54		T3	2
valid_sources[0x4f]	51742	1			T1	110		T2	321		T3	1
valid_sources[0x50]	50193	1			T1	126		T3	4		T4	127
valid_sources[0x51]	50640	1			T1	121		T3	1		T4	86
valid_sources[0x52]	52388	1			T1	97		T4	81		T5	125
valid_sources[0x53]	51898	1			T1	121		T3	1		T4	95
valid_sources[0x54]	49126	1			T1	130		T2	123		T4	117
valid_sources[0x55]	49838	1			T1	125		T3	7		T4	61
valid_sources[0x56]	49382	1			T1	103		T4	42		T5	121
valid_sources[0x57]	49315	1			T1	112		T3	2		T4	88
valid_sources[0x58]	48787	1			T1	117		T3	5		T4	97
valid_sources[0x59]	54201	1			T1	123		T2	202		T3	6
valid_sources[0x5a]	49373	1			T1	127		T2	1		T3	8
valid_sources[0x5b]	49867	1			T1	85		T3	4		T4	119
valid_sources[0x5c]	53400	1			T1	123		T3	1		T4	44
valid_sources[0x5d]	53825	1			T1	130		T3	5		T4	159
valid_sources[0x5e]	48528	1			T1	116		T4	39		T5	133
valid_sources[0x5f]	50210	1			T1	127		T2	1		T3	4
valid_sources[0x60]	50297	1			T1	129		T2	264		T4	104
valid_sources[0x61]	49627	1			T1	116		T2	1		T3	5
valid_sources[0x62]	50560	1			T1	154		T3	4		T4	98
valid_sources[0x63]	48441	1			T1	85		T3	4		T4	49
valid_sources[0x64]	51773	1			T1	108		T2	1		T3	1
valid_sources[0x65]	50495	1			T1	131		T2	68		T3	5
valid_sources[0x66]	49459	1			T1	121		T3	2		T4	67
valid_sources[0x67]	51544	1			T1	122		T2	3		T3	2
valid_sources[0x68]	50407	1			T1	101		T3	4		T4	84
valid_sources[0x69]	50655	1			T1	146		T2	4		T3	5
valid_sources[0x6a]	50337	1			T1	113		T2	1		T3	3
valid_sources[0x6b]	48120	1			T1	125		T2	106		T3	5
valid_sources[0x6c]	48925	1			T1	143		T2	3		T3	12
valid_sources[0x6d]	51912	1			T1	128		T2	24		T3	3
valid_sources[0x6e]	51265	1			T1	159		T3	4		T4	112
valid_sources[0x6f]	53069	1			T1	81		T2	25		T3	2
valid_sources[0x70]	50345	1			T1	136		T2	4		T3	5
valid_sources[0x71]	49360	1			T1	110		T3	5		T4	131
valid_sources[0x72]	51081	1			T1	110		T2	334		T3	4
valid_sources[0x73]	47854	1			T1	143		T3	1		T4	56
valid_sources[0x74]	50373	1			T1	124		T3	3		T4	29
valid_sources[0x75]	51539	1			T1	142		T2	1		T3	4
valid_sources[0x76]	63098	1			T1	110		T3	4		T4	100
valid_sources[0x77]	47626	1			T1	104		T3	5		T4	128
valid_sources[0x78]	51237	1			T1	140		T3	2		T4	92
valid_sources[0x79]	50516	1			T1	146		T4	90		T5	110
valid_sources[0x7a]	50466	1			T1	110		T3	3		T4	107
valid_sources[0x7b]	49273	1			T1	125		T3	4		T4	135
valid_sources[0x7c]	51919	1			T1	122		T2	1		T4	78
valid_sources[0x7d]	52024	1			T1	148		T2	291		T3	1
valid_sources[0x7e]	48117	1			T1	119		T4	130		T5	106
valid_sources[0x7f]	51336	1			T1	91		T2	105		T3	6
valid_sources[0x80]	50335	1			T1	101		T2	1		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2564521

1

T1

4815

T2

1494

T3

2

values[0x0]

all_enables

biggest_size

2071126

1

T1

6030

T2

2168

T3

445

values[0x1]

all_enables

biggest_size

2037607

1

T1

5992

T2

2034

T3

444