Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6415537

1

T1

13537

T2

7235

T3

6

full_word

6672338

1

T1

16837

T2

5696

T3

891

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	13087445	1			T1	30374		T2	12931		T3	897
auto[TlIntgErrCmd]	153	1			T83	7		T87	6		T88	7
auto[TlIntgErrData]	135	1			T83	12		T87	2		T88	9
auto[TlIntgErrBoth]	142	1			T83	11		T87	2		T88	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8459726

1

T1

16689

T2

7472

T3

6

auto[1]

4628149

1

T1

13685

T2

5459

T3

891

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5894915	1			T1	11874		T2	5978		T3	4
auto[TlIntgErrNone]	partial	auto[1]	520235	1			T1	1663		T2	1257		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	2564628	1			T1	4815		T2	1494		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	4107667	1			T1	12022		T2	4202		T3	889
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T83	3		T87	2		T88	1
auto[TlIntgErrCmd]	partial	auto[1]	90	1			T83	4		T87	3		T88	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T88	1		T104	1		T101	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T87	1		T104	1		T144	2
auto[TlIntgErrData]	partial	auto[0]	64	1			T83	8		T88	7		T103	3
auto[TlIntgErrData]	partial	auto[1]	57	1			T83	2		T87	2		T88	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T104	1		T144	1		T146	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T83	2		T101	1		T143	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T83	3		T87	1		T103	4
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T83	8		T88	4		T103	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T101	1		T143	2		T142	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T87	1		T143	2		T144	1