Module Definition
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Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_scanmode_sync 100.00 100.00



Module Instance : tb.dut.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.69 94.25 84.31 96.94 87.50 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 938 938 0 0
OutputsKnown_A 567023953 566937832 0 0
gen_no_flops.OutputDelay_A 567023953 566937832 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 938 938 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 567023953 566937832 0 0
T1 812032 811976 0 0
T2 488123 488033 0 0
T3 22067 21968 0 0
T4 107352 107345 0 0
T5 429579 429481 0 0
T6 395696 395408 0 0
T7 111283 111276 0 0
T8 142192 142121 0 0
T9 130589 130495 0 0
T10 83133 83059 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 567023953 566937832 0 0
T1 812032 811976 0 0
T2 488123 488033 0 0
T3 22067 21968 0 0
T4 107352 107345 0 0
T5 429579 429481 0 0
T6 395696 395408 0 0
T7 111283 111276 0 0
T8 142192 142121 0 0
T9 130589 130495 0 0
T10 83133 83059 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%