Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	943976853	753491595	0	0
CheckNGreaterZero_A	2814	2814	0	0
GntImpliesReady_A	943976853	4328507	0	0
GntImpliesValid_A	943976853	4328507	0	0
GrantKnown_A	943976853	753491595	0	0
IdxKnown_A	943976853	753491595	0	0
IndexIsCorrect_A	943976853	4328507	0	0
LockArbDecision_A	943976853	0	0	0
NoReadyValidNoGrant_A	943976853	0	0	0
ReadyAndValidImplyGrant_A	943976853	4328507	0	0
ReqAndReadyImplyGrant_A	943976853	4328507	0	0
ReqImpliesValid_A	943976853	4328507	0	0
ReqStaysHighUntilGranted0_M	943976853	0	0	0
RoundRobin_A	943976853	8	0	938
ValidKnown_A	943976853	753491595	0	0
gen_data_port_assertion.DataFlow_A	943976853	4328507	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	753491595	0	0
T1	1629898	1208261	0	0
T2	958397	715977	0	0
T3	79827	50848	0	0
T4	540740	317231	0	0
T5	719913	1867837	0	0
T6	614486	1479621	0	0
T7	388479	249692	0	0
T8	404818	273289	0	0
T9	172805	151603	0	0
T10	368769	225379	0	0
T11	0	92466	0	0
T12	0	61152	0	0
T13	0	332904	0	0
T14	0	462256	0	0
T15	0	142384	0	0
T17	0	48	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2814	2814	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	4328507	0	0
T1	1629898	18395	0	0
T2	958397	11148	0	0
T3	79827	832	0	0
T4	540740	9719	0	0
T5	719913	30272	0	0
T6	614486	22942	0	0
T7	388479	832	0	0
T8	404818	832	0	0
T9	172805	832	0	0
T10	368769	832	0	0
T12	0	8529	0	0
T13	0	14651	0	0
T14	0	5915	0	0
T16	0	5136	0	0
T17	0	1	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	4328507	0	0
T1	1629898	18395	0	0
T2	958397	11148	0	0
T3	79827	832	0	0
T4	540740	9719	0	0
T5	719913	30272	0	0
T6	614486	22942	0	0
T7	388479	832	0	0
T8	404818	832	0	0
T9	172805	832	0	0
T10	368769	832	0	0
T12	0	8529	0	0
T13	0	14651	0	0
T14	0	5915	0	0
T16	0	5136	0	0
T17	0	1	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	753491595	0	0
T1	1629898	1208261	0	0
T2	958397	715977	0	0
T3	79827	50848	0	0
T4	540740	317231	0	0
T5	719913	1867837	0	0
T6	614486	1479621	0	0
T7	388479	249692	0	0
T8	404818	273289	0	0
T9	172805	151603	0	0
T10	368769	225379	0	0
T11	0	92466	0	0
T12	0	61152	0	0
T13	0	332904	0	0
T14	0	462256	0	0
T15	0	142384	0	0
T17	0	48	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	753491595	0	0
T1	1629898	1208261	0	0
T2	958397	715977	0	0
T3	79827	50848	0	0
T4	540740	317231	0	0
T5	719913	1867837	0	0
T6	614486	1479621	0	0
T7	388479	249692	0	0
T8	404818	273289	0	0
T9	172805	151603	0	0
T10	368769	225379	0	0
T11	0	92466	0	0
T12	0	61152	0	0
T13	0	332904	0	0
T14	0	462256	0	0
T15	0	142384	0	0
T17	0	48	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	4328507	0	0
T1	1629898	18395	0	0
T2	958397	11148	0	0
T3	79827	832	0	0
T4	540740	9719	0	0
T5	719913	30272	0	0
T6	614486	22942	0	0
T7	388479	832	0	0
T8	404818	832	0	0
T9	172805	832	0	0
T10	368769	832	0	0
T12	0	8529	0	0
T13	0	14651	0	0
T14	0	5915	0	0
T16	0	5136	0	0
T17	0	1	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	4328507	0	0
T1	1629898	18395	0	0
T2	958397	11148	0	0
T3	79827	832	0	0
T4	540740	9719	0	0
T5	719913	30272	0	0
T6	614486	22942	0	0
T7	388479	832	0	0
T8	404818	832	0	0
T9	172805	832	0	0
T10	368769	832	0	0
T12	0	8529	0	0
T13	0	14651	0	0
T14	0	5915	0	0
T16	0	5136	0	0
T17	0	1	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	4328507	0	0
T1	1629898	18395	0	0
T2	958397	11148	0	0
T3	79827	832	0	0
T4	540740	9719	0	0
T5	719913	30272	0	0
T6	614486	22942	0	0
T7	388479	832	0	0
T8	404818	832	0	0
T9	172805	832	0	0
T10	368769	832	0	0
T12	0	8529	0	0
T13	0	14651	0	0
T14	0	5915	0	0
T16	0	5136	0	0
T17	0	1	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	4328507	0	0
T1	1629898	18395	0	0
T2	958397	11148	0	0
T3	79827	832	0	0
T4	540740	9719	0	0
T5	719913	30272	0	0
T6	614486	22942	0	0
T7	388479	832	0	0
T8	404818	832	0	0
T9	172805	832	0	0
T10	368769	832	0	0
T12	0	8529	0	0
T13	0	14651	0	0
T14	0	5915	0	0
T16	0	5136	0	0
T17	0	1	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	8	0	938
T36	258939	1	0	1
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	143128	0	0	1
T44	151601	0	0	1
T45	1194	0	0	1
T46	1232	0	0	1
T47	958	0	0	1
T48	1004	0	0	1
T49	217936	0	0	1
T50	101279	0	0	1
T51	184934	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	753491595	0	0
T1	1629898	1208261	0	0
T2	958397	715977	0	0
T3	79827	50848	0	0
T4	540740	317231	0	0
T5	719913	1867837	0	0
T6	614486	1479621	0	0
T7	388479	249692	0	0
T8	404818	273289	0	0
T9	172805	151603	0	0
T10	368769	225379	0	0
T11	0	92466	0	0
T12	0	61152	0	0
T13	0	332904	0	0
T14	0	462256	0	0
T15	0	142384	0	0
T17	0	48	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	943976853	4328507	0	0
T1	1629898	18395	0	0
T2	958397	11148	0	0
T3	79827	832	0	0
T4	540740	9719	0	0
T5	719913	30272	0	0
T6	614486	22942	0	0
T7	388479	832	0	0
T8	404818	832	0	0
T9	172805	832	0	0
T10	368769	832	0	0
T12	0	8529	0	0
T13	0	14651	0	0
T14	0	5915	0	0
T16	0	5136	0	0
T17	0	1	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	188476450	44189021	0	0
CheckNGreaterZero_A	938	938	0	0
GntImpliesReady_A	188476450	979707	0	0
GntImpliesValid_A	188476450	979707	0	0
GrantKnown_A	188476450	44189021	0	0
IdxKnown_A	188476450	44189021	0	0
IndexIsCorrect_A	188476450	979707	0	0
LockArbDecision_A	188476450	0	0	0
NoReadyValidNoGrant_A	188476450	0	0	0
ReadyAndValidImplyGrant_A	188476450	979707	0	0
ReqAndReadyImplyGrant_A	188476450	979707	0	0
ReqImpliesValid_A	188476450	979707	0	0
ReqStaysHighUntilGranted0_M	188476450	0	0	0
RoundRobin_A	188476450	0	0	0
ValidKnown_A	188476450	44189021	0	0
gen_data_port_assertion.DataFlow_A	188476450	979707	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	44189021	0	0
T1	408933	167448	0	0
T2	235137	227944	0	0
T3	28880	0	0	0
T4	216694	142944	0	0
T5	145167	754832	0	0
T6	109395	572656	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	61152	0	0
T13	0	332904	0	0
T14	0	462256	0	0
T15	0	142384	0	0
T17	0	48	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938	938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	979707	0	0
T1	408933	5297	0	0
T2	235137	7396	0	0
T3	28880	0	0	0
T4	216694	6051	0	0
T5	145167	7782	0	0
T6	109395	6275	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	2276	0	0
T13	0	13451	0	0
T14	0	5915	0	0
T16	0	4997	0	0
T17	0	1	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	979707	0	0
T1	408933	5297	0	0
T2	235137	7396	0	0
T3	28880	0	0	0
T4	216694	6051	0	0
T5	145167	7782	0	0
T6	109395	6275	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	2276	0	0
T13	0	13451	0	0
T14	0	5915	0	0
T16	0	4997	0	0
T17	0	1	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	44189021	0	0
T1	408933	167448	0	0
T2	235137	227944	0	0
T3	28880	0	0	0
T4	216694	142944	0	0
T5	145167	754832	0	0
T6	109395	572656	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	61152	0	0
T13	0	332904	0	0
T14	0	462256	0	0
T15	0	142384	0	0
T17	0	48	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	44189021	0	0
T1	408933	167448	0	0
T2	235137	227944	0	0
T3	28880	0	0	0
T4	216694	142944	0	0
T5	145167	754832	0	0
T6	109395	572656	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	61152	0	0
T13	0	332904	0	0
T14	0	462256	0	0
T15	0	142384	0	0
T17	0	48	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	979707	0	0
T1	408933	5297	0	0
T2	235137	7396	0	0
T3	28880	0	0	0
T4	216694	6051	0	0
T5	145167	7782	0	0
T6	109395	6275	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	2276	0	0
T13	0	13451	0	0
T14	0	5915	0	0
T16	0	4997	0	0
T17	0	1	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	979707	0	0
T1	408933	5297	0	0
T2	235137	7396	0	0
T3	28880	0	0	0
T4	216694	6051	0	0
T5	145167	7782	0	0
T6	109395	6275	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	2276	0	0
T13	0	13451	0	0
T14	0	5915	0	0
T16	0	4997	0	0
T17	0	1	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	979707	0	0
T1	408933	5297	0	0
T2	235137	7396	0	0
T3	28880	0	0	0
T4	216694	6051	0	0
T5	145167	7782	0	0
T6	109395	6275	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	2276	0	0
T13	0	13451	0	0
T14	0	5915	0	0
T16	0	4997	0	0
T17	0	1	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	979707	0	0
T1	408933	5297	0	0
T2	235137	7396	0	0
T3	28880	0	0	0
T4	216694	6051	0	0
T5	145167	7782	0	0
T6	109395	6275	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	2276	0	0
T13	0	13451	0	0
T14	0	5915	0	0
T16	0	4997	0	0
T17	0	1	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	44189021	0	0
T1	408933	167448	0	0
T2	235137	227944	0	0
T3	28880	0	0	0
T4	216694	142944	0	0
T5	145167	754832	0	0
T6	109395	572656	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	61152	0	0
T13	0	332904	0	0
T14	0	462256	0	0
T15	0	142384	0	0
T17	0	48	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	979707	0	0
T1	408933	5297	0	0
T2	235137	7396	0	0
T3	28880	0	0	0
T4	216694	6051	0	0
T5	145167	7782	0	0
T6	109395	6275	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	2276	0	0
T13	0	13451	0	0
T14	0	5915	0	0
T16	0	4997	0	0
T17	0	1	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	188476450	142364742	0	0
CheckNGreaterZero_A	938	938	0	0
GntImpliesReady_A	188476450	641166	0	0
GntImpliesValid_A	188476450	641166	0	0
GrantKnown_A	188476450	142364742	0	0
IdxKnown_A	188476450	142364742	0	0
IndexIsCorrect_A	188476450	641166	0	0
LockArbDecision_A	188476450	0	0	0
NoReadyValidNoGrant_A	188476450	0	0	0
ReadyAndValidImplyGrant_A	188476450	641166	0	0
ReqAndReadyImplyGrant_A	188476450	641166	0	0
ReqImpliesValid_A	188476450	641166	0	0
ReqStaysHighUntilGranted0_M	188476450	0	0	0
RoundRobin_A	188476450	0	0	0
ValidKnown_A	188476450	142364742	0	0
gen_data_port_assertion.DataFlow_A	188476450	641166	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	142364742	0	0
T1	408933	228837	0	0
T2	235137	0	0	0
T3	28880	28880	0	0
T4	216694	66942	0	0
T5	145167	683524	0	0
T6	109395	511557	0	0
T7	138598	138416	0	0
T8	131313	131168	0	0
T9	21108	21108	0	0
T10	142818	142320	0	0
T11	0	92466	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938	938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	641166	0	0
T1	408933	3595	0	0
T2	235137	0	0	0
T3	28880	0	0	0
T4	216694	0	0	0
T5	145167	5015	0	0
T6	109395	4761	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	6253	0	0
T13	0	1200	0	0
T16	0	139	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	641166	0	0
T1	408933	3595	0	0
T2	235137	0	0	0
T3	28880	0	0	0
T4	216694	0	0	0
T5	145167	5015	0	0
T6	109395	4761	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	6253	0	0
T13	0	1200	0	0
T16	0	139	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	142364742	0	0
T1	408933	228837	0	0
T2	235137	0	0	0
T3	28880	28880	0	0
T4	216694	66942	0	0
T5	145167	683524	0	0
T6	109395	511557	0	0
T7	138598	138416	0	0
T8	131313	131168	0	0
T9	21108	21108	0	0
T10	142818	142320	0	0
T11	0	92466	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	142364742	0	0
T1	408933	228837	0	0
T2	235137	0	0	0
T3	28880	28880	0	0
T4	216694	66942	0	0
T5	145167	683524	0	0
T6	109395	511557	0	0
T7	138598	138416	0	0
T8	131313	131168	0	0
T9	21108	21108	0	0
T10	142818	142320	0	0
T11	0	92466	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	641166	0	0
T1	408933	3595	0	0
T2	235137	0	0	0
T3	28880	0	0	0
T4	216694	0	0	0
T5	145167	5015	0	0
T6	109395	4761	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	6253	0	0
T13	0	1200	0	0
T16	0	139	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	641166	0	0
T1	408933	3595	0	0
T2	235137	0	0	0
T3	28880	0	0	0
T4	216694	0	0	0
T5	145167	5015	0	0
T6	109395	4761	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	6253	0	0
T13	0	1200	0	0
T16	0	139	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	641166	0	0
T1	408933	3595	0	0
T2	235137	0	0	0
T3	28880	0	0	0
T4	216694	0	0	0
T5	145167	5015	0	0
T6	109395	4761	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	6253	0	0
T13	0	1200	0	0
T16	0	139	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	641166	0	0
T1	408933	3595	0	0
T2	235137	0	0	0
T3	28880	0	0	0
T4	216694	0	0	0
T5	145167	5015	0	0
T6	109395	4761	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	6253	0	0
T13	0	1200	0	0
T16	0	139	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	142364742	0	0
T1	408933	228837	0	0
T2	235137	0	0	0
T3	28880	28880	0	0
T4	216694	66942	0	0
T5	145167	683524	0	0
T6	109395	511557	0	0
T7	138598	138416	0	0
T8	131313	131168	0	0
T9	21108	21108	0	0
T10	142818	142320	0	0
T11	0	92466	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188476450	641166	0	0
T1	408933	3595	0	0
T2	235137	0	0	0
T3	28880	0	0	0
T4	216694	0	0	0
T5	145167	5015	0	0
T6	109395	4761	0	0
T7	138598	0	0	0
T8	131313	0	0	0
T9	21108	0	0	0
T10	142818	0	0	0
T12	0	6253	0	0
T13	0	1200	0	0
T16	0	139	0	0
T24	0	3	0	0
T25	0	5332	0	0
T31	0	1884	0	0
T35	0	802	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	567023953	566937832	0	0
CheckNGreaterZero_A	938	938	0	0
GntImpliesReady_A	567023953	2707634	0	0
GntImpliesValid_A	567023953	2707634	0	0
GrantKnown_A	567023953	566937832	0	0
IdxKnown_A	567023953	566937832	0	0
IndexIsCorrect_A	567023953	2707634	0	0
LockArbDecision_A	567023953	0	0	0
NoReadyValidNoGrant_A	567023953	0	0	0
ReadyAndValidImplyGrant_A	567023953	2707634	0	0
ReqAndReadyImplyGrant_A	567023953	2707634	0	0
ReqImpliesValid_A	567023953	2707634	0	0
ReqStaysHighUntilGranted0_M	567023953	0	0	0
RoundRobin_A	567023953	8	0	938
ValidKnown_A	567023953	566937832	0	0
gen_data_port_assertion.DataFlow_A	567023953	2707634	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	566937832	0	0
T1	812032	811976	0	0
T2	488123	488033	0	0
T3	22067	21968	0	0
T4	107352	107345	0	0
T5	429579	429481	0	0
T6	395696	395408	0	0
T7	111283	111276	0	0
T8	142192	142121	0	0
T9	130589	130495	0	0
T10	83133	83059	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938	938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	2707634	0	0
T1	812032	9503	0	0
T2	488123	3752	0	0
T3	22067	832	0	0
T4	107352	3668	0	0
T5	429579	17475	0	0
T6	395696	11906	0	0
T7	111283	832	0	0
T8	142192	832	0	0
T9	130589	832	0	0
T10	83133	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	2707634	0	0
T1	812032	9503	0	0
T2	488123	3752	0	0
T3	22067	832	0	0
T4	107352	3668	0	0
T5	429579	17475	0	0
T6	395696	11906	0	0
T7	111283	832	0	0
T8	142192	832	0	0
T9	130589	832	0	0
T10	83133	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	566937832	0	0
T1	812032	811976	0	0
T2	488123	488033	0	0
T3	22067	21968	0	0
T4	107352	107345	0	0
T5	429579	429481	0	0
T6	395696	395408	0	0
T7	111283	111276	0	0
T8	142192	142121	0	0
T9	130589	130495	0	0
T10	83133	83059	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	566937832	0	0
T1	812032	811976	0	0
T2	488123	488033	0	0
T3	22067	21968	0	0
T4	107352	107345	0	0
T5	429579	429481	0	0
T6	395696	395408	0	0
T7	111283	111276	0	0
T8	142192	142121	0	0
T9	130589	130495	0	0
T10	83133	83059	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	2707634	0	0
T1	812032	9503	0	0
T2	488123	3752	0	0
T3	22067	832	0	0
T4	107352	3668	0	0
T5	429579	17475	0	0
T6	395696	11906	0	0
T7	111283	832	0	0
T8	142192	832	0	0
T9	130589	832	0	0
T10	83133	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	2707634	0	0
T1	812032	9503	0	0
T2	488123	3752	0	0
T3	22067	832	0	0
T4	107352	3668	0	0
T5	429579	17475	0	0
T6	395696	11906	0	0
T7	111283	832	0	0
T8	142192	832	0	0
T9	130589	832	0	0
T10	83133	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	2707634	0	0
T1	812032	9503	0	0
T2	488123	3752	0	0
T3	22067	832	0	0
T4	107352	3668	0	0
T5	429579	17475	0	0
T6	395696	11906	0	0
T7	111283	832	0	0
T8	142192	832	0	0
T9	130589	832	0	0
T10	83133	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	2707634	0	0
T1	812032	9503	0	0
T2	488123	3752	0	0
T3	22067	832	0	0
T4	107352	3668	0	0
T5	429579	17475	0	0
T6	395696	11906	0	0
T7	111283	832	0	0
T8	142192	832	0	0
T9	130589	832	0	0
T10	83133	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	8	0	938
T36	258939	1	0	1
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	143128	0	0	1
T44	151601	0	0	1
T45	1194	0	0	1
T46	1232	0	0	1
T47	958	0	0	1
T48	1004	0	0	1
T49	217936	0	0	1
T50	101279	0	0	1
T51	184934	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	566937832	0	0
T1	812032	811976	0	0
T2	488123	488033	0	0
T3	22067	21968	0	0
T4	107352	107345	0	0
T5	429579	429481	0	0
T6	395696	395408	0	0
T7	111283	111276	0	0
T8	142192	142121	0	0
T9	130589	130495	0	0
T10	83133	83059	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567023953	2707634	0	0
T1	812032	9503	0	0
T2	488123	3752	0	0
T3	22067	832	0	0
T4	107352	3668	0	0
T5	429579	17475	0	0
T6	395696	11906	0	0
T7	111283	832	0	0
T8	142192	832	0	0
T9	130589	832	0	0
T10	83133	832	0	0