| T803 |
/workspace/coverage/default/7.spi_device_flash_and_tpm.929741385 |
|
|
Mar 28 01:36:17 PM PDT 24 |
Mar 28 01:37:10 PM PDT 24 |
15660657168 ps |
| T804 |
/workspace/coverage/default/5.spi_device_stress_all.925549514 |
|
|
Mar 28 01:36:08 PM PDT 24 |
Mar 28 01:42:49 PM PDT 24 |
75286847030 ps |
| T805 |
/workspace/coverage/default/39.spi_device_read_buffer_direct.2115527282 |
|
|
Mar 28 01:38:17 PM PDT 24 |
Mar 28 01:38:20 PM PDT 24 |
169903638 ps |
| T806 |
/workspace/coverage/default/41.spi_device_csb_read.1116771550 |
|
|
Mar 28 01:38:14 PM PDT 24 |
Mar 28 01:38:15 PM PDT 24 |
274871439 ps |
| T807 |
/workspace/coverage/default/26.spi_device_flash_all.3268614233 |
|
|
Mar 28 01:37:22 PM PDT 24 |
Mar 28 01:39:37 PM PDT 24 |
38572488659 ps |
| T808 |
/workspace/coverage/default/18.spi_device_csb_read.3427422759 |
|
|
Mar 28 01:36:55 PM PDT 24 |
Mar 28 01:36:57 PM PDT 24 |
22390748 ps |
| T809 |
/workspace/coverage/default/46.spi_device_csb_read.1693002563 |
|
|
Mar 28 01:38:30 PM PDT 24 |
Mar 28 01:38:31 PM PDT 24 |
83397084 ps |
| T810 |
/workspace/coverage/default/4.spi_device_mailbox.1899518650 |
|
|
Mar 28 01:36:06 PM PDT 24 |
Mar 28 01:36:34 PM PDT 24 |
8443436439 ps |
| T811 |
/workspace/coverage/default/1.spi_device_alert_test.662373036 |
|
|
Mar 28 01:36:00 PM PDT 24 |
Mar 28 01:36:01 PM PDT 24 |
17954827 ps |
| T812 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.723842892 |
|
|
Mar 28 01:36:06 PM PDT 24 |
Mar 28 01:36:16 PM PDT 24 |
6578192734 ps |
| T244 |
/workspace/coverage/default/37.spi_device_flash_and_tpm.82107723 |
|
|
Mar 28 01:37:50 PM PDT 24 |
Mar 28 01:41:22 PM PDT 24 |
34919914979 ps |
| T813 |
/workspace/coverage/default/43.spi_device_tpm_all.4108897781 |
|
|
Mar 28 01:38:27 PM PDT 24 |
Mar 28 01:38:54 PM PDT 24 |
3365123331 ps |
| T814 |
/workspace/coverage/default/17.spi_device_tpm_all.1589648146 |
|
|
Mar 28 01:37:03 PM PDT 24 |
Mar 28 01:37:31 PM PDT 24 |
6981167014 ps |
| T815 |
/workspace/coverage/default/9.spi_device_ram_cfg.1802542173 |
|
|
Mar 28 01:36:18 PM PDT 24 |
Mar 28 01:36:19 PM PDT 24 |
16530152 ps |
| T816 |
/workspace/coverage/default/32.spi_device_flash_mode.3505610176 |
|
|
Mar 28 01:37:49 PM PDT 24 |
Mar 28 01:38:08 PM PDT 24 |
1767336962 ps |
| T817 |
/workspace/coverage/default/2.spi_device_stress_all.1749523340 |
|
|
Mar 28 01:36:04 PM PDT 24 |
Mar 28 01:39:29 PM PDT 24 |
15519207155 ps |
| T818 |
/workspace/coverage/default/13.spi_device_pass_cmd_filtering.1732959406 |
|
|
Mar 28 01:36:39 PM PDT 24 |
Mar 28 01:36:47 PM PDT 24 |
654401445 ps |
| T819 |
/workspace/coverage/default/45.spi_device_tpm_sts_read.2840934707 |
|
|
Mar 28 01:38:37 PM PDT 24 |
Mar 28 01:38:38 PM PDT 24 |
65024596 ps |
| T820 |
/workspace/coverage/default/4.spi_device_stress_all.2938551525 |
|
|
Mar 28 01:36:10 PM PDT 24 |
Mar 28 01:38:33 PM PDT 24 |
23109606764 ps |
| T821 |
/workspace/coverage/default/20.spi_device_csb_read.2231110424 |
|
|
Mar 28 01:36:56 PM PDT 24 |
Mar 28 01:36:57 PM PDT 24 |
14047889 ps |
| T822 |
/workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2484363615 |
|
|
Mar 28 01:36:01 PM PDT 24 |
Mar 28 01:36:39 PM PDT 24 |
10515200962 ps |
| T823 |
/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4004071285 |
|
|
Mar 28 01:37:00 PM PDT 24 |
Mar 28 01:37:43 PM PDT 24 |
59236075277 ps |
| T824 |
/workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.977666509 |
|
|
Mar 28 01:37:36 PM PDT 24 |
Mar 28 01:38:05 PM PDT 24 |
3603879900 ps |
| T825 |
/workspace/coverage/default/47.spi_device_csb_read.4211456248 |
|
|
Mar 28 01:38:33 PM PDT 24 |
Mar 28 01:38:33 PM PDT 24 |
15600306 ps |
| T826 |
/workspace/coverage/default/24.spi_device_tpm_sts_read.516324889 |
|
|
Mar 28 01:37:25 PM PDT 24 |
Mar 28 01:37:26 PM PDT 24 |
969293165 ps |
| T827 |
/workspace/coverage/default/32.spi_device_intercept.654922447 |
|
|
Mar 28 01:37:38 PM PDT 24 |
Mar 28 01:37:47 PM PDT 24 |
3909785648 ps |
| T828 |
/workspace/coverage/default/37.spi_device_csb_read.944742309 |
|
|
Mar 28 01:37:54 PM PDT 24 |
Mar 28 01:37:55 PM PDT 24 |
68502894 ps |
| T829 |
/workspace/coverage/default/44.spi_device_csb_read.36427608 |
|
|
Mar 28 01:38:34 PM PDT 24 |
Mar 28 01:38:36 PM PDT 24 |
16194590 ps |
| T830 |
/workspace/coverage/default/0.spi_device_intercept.539268719 |
|
|
Mar 28 01:35:53 PM PDT 24 |
Mar 28 01:36:00 PM PDT 24 |
7058468879 ps |
| T831 |
/workspace/coverage/default/14.spi_device_pass_cmd_filtering.1369670823 |
|
|
Mar 28 01:36:59 PM PDT 24 |
Mar 28 01:37:03 PM PDT 24 |
905250242 ps |
| T832 |
/workspace/coverage/default/44.spi_device_pass_cmd_filtering.3389157684 |
|
|
Mar 28 01:38:34 PM PDT 24 |
Mar 28 01:38:38 PM PDT 24 |
807044461 ps |
| T833 |
/workspace/coverage/default/45.spi_device_upload.327722631 |
|
|
Mar 28 01:38:38 PM PDT 24 |
Mar 28 01:38:47 PM PDT 24 |
4966256702 ps |
| T834 |
/workspace/coverage/default/20.spi_device_flash_and_tpm.4213185434 |
|
|
Mar 28 01:36:58 PM PDT 24 |
Mar 28 01:38:20 PM PDT 24 |
5186414307 ps |
| T835 |
/workspace/coverage/default/2.spi_device_tpm_rw.2657716020 |
|
|
Mar 28 01:36:04 PM PDT 24 |
Mar 28 01:36:08 PM PDT 24 |
955569271 ps |
| T836 |
/workspace/coverage/default/20.spi_device_intercept.1023105209 |
|
|
Mar 28 01:36:55 PM PDT 24 |
Mar 28 01:37:00 PM PDT 24 |
3581254682 ps |
| T837 |
/workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1344128057 |
|
|
Mar 28 01:38:18 PM PDT 24 |
Mar 28 01:38:22 PM PDT 24 |
410317508 ps |
| T838 |
/workspace/coverage/default/14.spi_device_upload.2101384387 |
|
|
Mar 28 01:36:51 PM PDT 24 |
Mar 28 01:37:19 PM PDT 24 |
9102145042 ps |
| T839 |
/workspace/coverage/default/22.spi_device_intercept.1447514558 |
|
|
Mar 28 01:37:03 PM PDT 24 |
Mar 28 01:37:06 PM PDT 24 |
194468593 ps |
| T840 |
/workspace/coverage/default/4.spi_device_read_buffer_direct.2208282095 |
|
|
Mar 28 01:36:11 PM PDT 24 |
Mar 28 01:36:16 PM PDT 24 |
301154922 ps |
| T841 |
/workspace/coverage/default/39.spi_device_flash_all.1293669382 |
|
|
Mar 28 01:38:21 PM PDT 24 |
Mar 28 01:38:35 PM PDT 24 |
8064183286 ps |
| T245 |
/workspace/coverage/default/41.spi_device_flash_all.3114292419 |
|
|
Mar 28 01:38:18 PM PDT 24 |
Mar 28 01:39:08 PM PDT 24 |
19729250395 ps |
| T842 |
/workspace/coverage/default/14.spi_device_alert_test.4189943940 |
|
|
Mar 28 01:36:53 PM PDT 24 |
Mar 28 01:36:54 PM PDT 24 |
11149684 ps |
| T843 |
/workspace/coverage/default/35.spi_device_cfg_cmd.874649323 |
|
|
Mar 28 01:37:54 PM PDT 24 |
Mar 28 01:37:58 PM PDT 24 |
390381189 ps |
| T844 |
/workspace/coverage/default/16.spi_device_ram_cfg.2751854878 |
|
|
Mar 28 01:37:03 PM PDT 24 |
Mar 28 01:37:04 PM PDT 24 |
27297680 ps |
| T845 |
/workspace/coverage/default/7.spi_device_tpm_rw.803130359 |
|
|
Mar 28 01:36:21 PM PDT 24 |
Mar 28 01:36:24 PM PDT 24 |
290651729 ps |
| T846 |
/workspace/coverage/default/31.spi_device_pass_cmd_filtering.1337009499 |
|
|
Mar 28 01:37:43 PM PDT 24 |
Mar 28 01:38:04 PM PDT 24 |
43620871249 ps |
| T847 |
/workspace/coverage/default/23.spi_device_tpm_sts_read.3959552521 |
|
|
Mar 28 01:37:24 PM PDT 24 |
Mar 28 01:37:25 PM PDT 24 |
39063262 ps |
| T848 |
/workspace/coverage/default/31.spi_device_alert_test.2018460099 |
|
|
Mar 28 01:37:44 PM PDT 24 |
Mar 28 01:37:48 PM PDT 24 |
56914750 ps |
| T849 |
/workspace/coverage/default/40.spi_device_pass_cmd_filtering.1434265178 |
|
|
Mar 28 01:38:18 PM PDT 24 |
Mar 28 01:38:21 PM PDT 24 |
39479337 ps |
| T850 |
/workspace/coverage/default/38.spi_device_intercept.3772254494 |
|
|
Mar 28 01:38:13 PM PDT 24 |
Mar 28 01:38:17 PM PDT 24 |
151889096 ps |
| T851 |
/workspace/coverage/default/22.spi_device_pass_cmd_filtering.436192133 |
|
|
Mar 28 01:37:03 PM PDT 24 |
Mar 28 01:37:12 PM PDT 24 |
20489064120 ps |
| T852 |
/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2052630439 |
|
|
Mar 28 01:38:37 PM PDT 24 |
Mar 28 01:38:59 PM PDT 24 |
6714942189 ps |
| T853 |
/workspace/coverage/default/30.spi_device_csb_read.4018049569 |
|
|
Mar 28 01:37:38 PM PDT 24 |
Mar 28 01:37:41 PM PDT 24 |
75675679 ps |
| T854 |
/workspace/coverage/default/8.spi_device_flash_and_tpm.1038822318 |
|
|
Mar 28 01:36:14 PM PDT 24 |
Mar 28 01:39:33 PM PDT 24 |
19622905524 ps |
| T855 |
/workspace/coverage/default/34.spi_device_tpm_all.1812366076 |
|
|
Mar 28 01:37:53 PM PDT 24 |
Mar 28 01:38:19 PM PDT 24 |
7813682049 ps |
| T856 |
/workspace/coverage/default/3.spi_device_alert_test.2741133223 |
|
|
Mar 28 01:36:00 PM PDT 24 |
Mar 28 01:36:01 PM PDT 24 |
20043781 ps |
| T857 |
/workspace/coverage/default/21.spi_device_csb_read.2060790081 |
|
|
Mar 28 01:36:58 PM PDT 24 |
Mar 28 01:36:59 PM PDT 24 |
37279333 ps |
| T858 |
/workspace/coverage/default/19.spi_device_read_buffer_direct.1188716639 |
|
|
Mar 28 01:36:55 PM PDT 24 |
Mar 28 01:37:04 PM PDT 24 |
1739610644 ps |
| T859 |
/workspace/coverage/default/15.spi_device_alert_test.401077377 |
|
|
Mar 28 01:37:03 PM PDT 24 |
Mar 28 01:37:04 PM PDT 24 |
15848891 ps |
| T860 |
/workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2474358099 |
|
|
Mar 28 01:36:39 PM PDT 24 |
Mar 28 01:37:02 PM PDT 24 |
6008144100 ps |
| T861 |
/workspace/coverage/default/47.spi_device_cfg_cmd.4151332868 |
|
|
Mar 28 01:38:37 PM PDT 24 |
Mar 28 01:38:41 PM PDT 24 |
185228923 ps |
| T862 |
/workspace/coverage/default/22.spi_device_tpm_all.3866694590 |
|
|
Mar 28 01:37:04 PM PDT 24 |
Mar 28 01:37:36 PM PDT 24 |
5741585806 ps |
| T863 |
/workspace/coverage/default/33.spi_device_tpm_all.2160819703 |
|
|
Mar 28 01:37:42 PM PDT 24 |
Mar 28 01:38:15 PM PDT 24 |
10512550868 ps |
| T864 |
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1521253614 |
|
|
Mar 28 01:36:26 PM PDT 24 |
Mar 28 01:36:37 PM PDT 24 |
3511345454 ps |
| T865 |
/workspace/coverage/default/2.spi_device_upload.1664536400 |
|
|
Mar 28 01:36:06 PM PDT 24 |
Mar 28 01:36:23 PM PDT 24 |
5730529580 ps |
| T866 |
/workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3826071537 |
|
|
Mar 28 01:36:37 PM PDT 24 |
Mar 28 01:37:47 PM PDT 24 |
41743127456 ps |
| T867 |
/workspace/coverage/default/1.spi_device_csb_read.1505952546 |
|
|
Mar 28 01:35:52 PM PDT 24 |
Mar 28 01:35:53 PM PDT 24 |
16902827 ps |
| T868 |
/workspace/coverage/default/6.spi_device_alert_test.1388282996 |
|
|
Mar 28 01:36:17 PM PDT 24 |
Mar 28 01:36:18 PM PDT 24 |
39160896 ps |
| T869 |
/workspace/coverage/default/25.spi_device_stress_all.785276619 |
|
|
Mar 28 01:37:23 PM PDT 24 |
Mar 28 01:47:41 PM PDT 24 |
364796714358 ps |
| T870 |
/workspace/coverage/default/36.spi_device_stress_all.2150033988 |
|
|
Mar 28 01:37:56 PM PDT 24 |
Mar 28 01:43:23 PM PDT 24 |
41721925829 ps |
| T871 |
/workspace/coverage/default/29.spi_device_tpm_rw.2800720568 |
|
|
Mar 28 01:37:36 PM PDT 24 |
Mar 28 01:37:37 PM PDT 24 |
51918613 ps |
| T872 |
/workspace/coverage/default/32.spi_device_pass_cmd_filtering.2676493756 |
|
|
Mar 28 01:37:39 PM PDT 24 |
Mar 28 01:37:47 PM PDT 24 |
374857791 ps |
| T873 |
/workspace/coverage/default/1.spi_device_cfg_cmd.2847169156 |
|
|
Mar 28 01:36:05 PM PDT 24 |
Mar 28 01:36:08 PM PDT 24 |
537300995 ps |
| T874 |
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3765444428 |
|
|
Mar 28 01:36:17 PM PDT 24 |
Mar 28 01:36:25 PM PDT 24 |
2302943467 ps |
| T42 |
/workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3844776417 |
|
|
Mar 28 01:36:58 PM PDT 24 |
Mar 28 01:45:44 PM PDT 24 |
361819684835 ps |
| T875 |
/workspace/coverage/default/29.spi_device_tpm_all.3170381150 |
|
|
Mar 28 01:37:36 PM PDT 24 |
Mar 28 01:37:45 PM PDT 24 |
4993272211 ps |
| T876 |
/workspace/coverage/default/48.spi_device_stress_all.2956595352 |
|
|
Mar 28 01:38:49 PM PDT 24 |
Mar 28 01:44:47 PM PDT 24 |
95177507603 ps |
| T877 |
/workspace/coverage/default/44.spi_device_flash_all.593319319 |
|
|
Mar 28 01:38:34 PM PDT 24 |
Mar 28 01:38:46 PM PDT 24 |
3028165032 ps |
| T878 |
/workspace/coverage/default/12.spi_device_tpm_all.1254750076 |
|
|
Mar 28 01:36:34 PM PDT 24 |
Mar 28 01:37:10 PM PDT 24 |
7802137133 ps |
| T879 |
/workspace/coverage/default/44.spi_device_flash_mode.3137942329 |
|
|
Mar 28 01:38:34 PM PDT 24 |
Mar 28 01:39:08 PM PDT 24 |
5535430514 ps |
| T880 |
/workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2332139313 |
|
|
Mar 28 01:35:49 PM PDT 24 |
Mar 28 01:35:53 PM PDT 24 |
1195523335 ps |
| T176 |
/workspace/coverage/default/33.spi_device_stress_all.2644151529 |
|
|
Mar 28 01:37:53 PM PDT 24 |
Mar 28 01:46:26 PM PDT 24 |
78342661492 ps |
| T881 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.4084084503 |
|
|
Mar 28 01:36:06 PM PDT 24 |
Mar 28 01:36:11 PM PDT 24 |
620864940 ps |
| T882 |
/workspace/coverage/default/19.spi_device_tpm_sts_read.1148334406 |
|
|
Mar 28 01:37:03 PM PDT 24 |
Mar 28 01:37:04 PM PDT 24 |
42392564 ps |
| T883 |
/workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1845387008 |
|
|
Mar 28 01:36:57 PM PDT 24 |
Mar 28 01:37:33 PM PDT 24 |
2030773824 ps |
| T249 |
/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1862256934 |
|
|
Mar 28 01:38:49 PM PDT 24 |
Mar 28 01:39:02 PM PDT 24 |
1839303399 ps |
| T248 |
/workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.510834348 |
|
|
Mar 28 01:37:52 PM PDT 24 |
Mar 28 01:41:42 PM PDT 24 |
48330044474 ps |
| T884 |
/workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3570588341 |
|
|
Mar 28 01:37:05 PM PDT 24 |
Mar 28 01:37:34 PM PDT 24 |
3276762625 ps |
| T885 |
/workspace/coverage/default/4.spi_device_tpm_sts_read.2037578122 |
|
|
Mar 28 01:36:00 PM PDT 24 |
Mar 28 01:36:01 PM PDT 24 |
213543112 ps |
| T250 |
/workspace/coverage/default/35.spi_device_stress_all.2670359243 |
|
|
Mar 28 01:37:56 PM PDT 24 |
Mar 28 01:40:35 PM PDT 24 |
47826066140 ps |
| T886 |
/workspace/coverage/default/17.spi_device_stress_all.2375139761 |
|
|
Mar 28 01:36:57 PM PDT 24 |
Mar 28 01:39:36 PM PDT 24 |
60620001806 ps |
| T887 |
/workspace/coverage/default/39.spi_device_alert_test.3167919530 |
|
|
Mar 28 01:38:20 PM PDT 24 |
Mar 28 01:38:21 PM PDT 24 |
101268551 ps |
| T888 |
/workspace/coverage/default/24.spi_device_read_buffer_direct.2640525378 |
|
|
Mar 28 01:37:24 PM PDT 24 |
Mar 28 01:37:32 PM PDT 24 |
1446016277 ps |
| T889 |
/workspace/coverage/default/44.spi_device_upload.3087389686 |
|
|
Mar 28 01:38:38 PM PDT 24 |
Mar 28 01:38:52 PM PDT 24 |
2958714544 ps |
| T890 |
/workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4079260222 |
|
|
Mar 28 01:36:00 PM PDT 24 |
Mar 28 01:36:08 PM PDT 24 |
1033669058 ps |
| T891 |
/workspace/coverage/default/48.spi_device_tpm_all.1448446759 |
|
|
Mar 28 01:38:37 PM PDT 24 |
Mar 28 01:38:41 PM PDT 24 |
258305827 ps |
| T892 |
/workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.806831481 |
|
|
Mar 28 01:36:35 PM PDT 24 |
Mar 28 01:41:38 PM PDT 24 |
79657052472 ps |
| T893 |
/workspace/coverage/default/43.spi_device_upload.1775030786 |
|
|
Mar 28 01:38:32 PM PDT 24 |
Mar 28 01:38:55 PM PDT 24 |
14052765860 ps |
| T894 |
/workspace/coverage/default/36.spi_device_tpm_sts_read.1228151310 |
|
|
Mar 28 01:37:54 PM PDT 24 |
Mar 28 01:37:56 PM PDT 24 |
395022542 ps |
| T895 |
/workspace/coverage/default/20.spi_device_upload.2534046843 |
|
|
Mar 28 01:36:56 PM PDT 24 |
Mar 28 01:37:01 PM PDT 24 |
840402816 ps |
| T896 |
/workspace/coverage/default/41.spi_device_cfg_cmd.3645511121 |
|
|
Mar 28 01:38:16 PM PDT 24 |
Mar 28 01:38:19 PM PDT 24 |
251686340 ps |
| T897 |
/workspace/coverage/default/28.spi_device_tpm_all.187954821 |
|
|
Mar 28 01:37:35 PM PDT 24 |
Mar 28 01:37:58 PM PDT 24 |
7594042110 ps |
| T898 |
/workspace/coverage/default/47.spi_device_intercept.1192046787 |
|
|
Mar 28 01:38:33 PM PDT 24 |
Mar 28 01:38:36 PM PDT 24 |
289847089 ps |
| T899 |
/workspace/coverage/default/0.spi_device_pass_addr_payload_swap.692850390 |
|
|
Mar 28 01:35:50 PM PDT 24 |
Mar 28 01:36:01 PM PDT 24 |
726922049 ps |
| T900 |
/workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2593934752 |
|
|
Mar 28 01:38:38 PM PDT 24 |
Mar 28 01:38:42 PM PDT 24 |
65557244 ps |
| T901 |
/workspace/coverage/default/9.spi_device_tpm_rw.3101596636 |
|
|
Mar 28 01:36:33 PM PDT 24 |
Mar 28 01:36:35 PM PDT 24 |
86252000 ps |
| T902 |
/workspace/coverage/default/26.spi_device_upload.4134663024 |
|
|
Mar 28 01:37:22 PM PDT 24 |
Mar 28 01:37:27 PM PDT 24 |
335756110 ps |
| T903 |
/workspace/coverage/default/45.spi_device_cfg_cmd.3147309610 |
|
|
Mar 28 01:38:38 PM PDT 24 |
Mar 28 01:38:43 PM PDT 24 |
708146666 ps |
| T904 |
/workspace/coverage/default/29.spi_device_read_buffer_direct.2925812565 |
|
|
Mar 28 01:37:38 PM PDT 24 |
Mar 28 01:37:46 PM PDT 24 |
715513737 ps |
| T905 |
/workspace/coverage/default/22.spi_device_upload.2441876073 |
|
|
Mar 28 01:36:56 PM PDT 24 |
Mar 28 01:37:04 PM PDT 24 |
387747335 ps |
| T906 |
/workspace/coverage/default/15.spi_device_tpm_read_hw_reg.734093641 |
|
|
Mar 28 01:36:51 PM PDT 24 |
Mar 28 01:36:59 PM PDT 24 |
7335575291 ps |
| T907 |
/workspace/coverage/default/48.spi_device_tpm_sts_read.2523206280 |
|
|
Mar 28 01:38:38 PM PDT 24 |
Mar 28 01:38:39 PM PDT 24 |
43095216 ps |
| T908 |
/workspace/coverage/default/2.spi_device_mailbox.4208129191 |
|
|
Mar 28 01:36:01 PM PDT 24 |
Mar 28 01:36:09 PM PDT 24 |
465299446 ps |
| T909 |
/workspace/coverage/default/49.spi_device_cfg_cmd.1559895322 |
|
|
Mar 28 01:38:48 PM PDT 24 |
Mar 28 01:38:50 PM PDT 24 |
153525791 ps |
| T910 |
/workspace/coverage/default/37.spi_device_intercept.767331938 |
|
|
Mar 28 01:37:57 PM PDT 24 |
Mar 28 01:38:09 PM PDT 24 |
7563030985 ps |
| T911 |
/workspace/coverage/default/19.spi_device_intercept.2981086055 |
|
|
Mar 28 01:37:04 PM PDT 24 |
Mar 28 01:37:15 PM PDT 24 |
10713441928 ps |
| T912 |
/workspace/coverage/default/9.spi_device_mailbox.3626887232 |
|
|
Mar 28 01:36:12 PM PDT 24 |
Mar 28 01:36:50 PM PDT 24 |
31421238977 ps |
| T913 |
/workspace/coverage/default/19.spi_device_tpm_rw.3227847253 |
|
|
Mar 28 01:37:02 PM PDT 24 |
Mar 28 01:37:10 PM PDT 24 |
1170089504 ps |
| T914 |
/workspace/coverage/default/37.spi_device_cfg_cmd.1416929014 |
|
|
Mar 28 01:37:56 PM PDT 24 |
Mar 28 01:38:02 PM PDT 24 |
2960490115 ps |
| T915 |
/workspace/coverage/default/5.spi_device_tpm_sts_read.999314087 |
|
|
Mar 28 01:36:10 PM PDT 24 |
Mar 28 01:36:11 PM PDT 24 |
92114959 ps |
| T916 |
/workspace/coverage/default/2.spi_device_flash_and_tpm.4229545427 |
|
|
Mar 28 01:36:01 PM PDT 24 |
Mar 28 01:48:10 PM PDT 24 |
101646229546 ps |
| T917 |
/workspace/coverage/default/31.spi_device_tpm_sts_read.136049020 |
|
|
Mar 28 01:37:49 PM PDT 24 |
Mar 28 01:37:51 PM PDT 24 |
80952482 ps |
| T918 |
/workspace/coverage/default/25.spi_device_intercept.2191272286 |
|
|
Mar 28 01:37:22 PM PDT 24 |
Mar 28 01:37:27 PM PDT 24 |
506449411 ps |
| T919 |
/workspace/coverage/default/16.spi_device_pass_cmd_filtering.161371088 |
|
|
Mar 28 01:37:06 PM PDT 24 |
Mar 28 01:37:09 PM PDT 24 |
71488576 ps |
| T253 |
/workspace/coverage/default/30.spi_device_flash_and_tpm.3393660375 |
|
|
Mar 28 01:37:36 PM PDT 24 |
Mar 28 01:40:12 PM PDT 24 |
9712648073 ps |
| T920 |
/workspace/coverage/default/46.spi_device_tpm_sts_read.1011154487 |
|
|
Mar 28 01:38:31 PM PDT 24 |
Mar 28 01:38:32 PM PDT 24 |
28525484 ps |
| T921 |
/workspace/coverage/default/32.spi_device_csb_read.1861536173 |
|
|
Mar 28 01:37:44 PM PDT 24 |
Mar 28 01:37:45 PM PDT 24 |
19236029 ps |
| T922 |
/workspace/coverage/default/35.spi_device_tpm_rw.4115748085 |
|
|
Mar 28 01:37:53 PM PDT 24 |
Mar 28 01:37:54 PM PDT 24 |
16977446 ps |
| T923 |
/workspace/coverage/default/6.spi_device_tpm_sts_read.1134063517 |
|
|
Mar 28 01:36:06 PM PDT 24 |
Mar 28 01:36:07 PM PDT 24 |
177214948 ps |
| T924 |
/workspace/coverage/default/16.spi_device_mem_parity.2802071639 |
|
|
Mar 28 01:37:03 PM PDT 24 |
Mar 28 01:37:04 PM PDT 24 |
47442205 ps |
| T925 |
/workspace/coverage/default/16.spi_device_flash_all.838852634 |
|
|
Mar 28 01:37:02 PM PDT 24 |
Mar 28 01:40:32 PM PDT 24 |
40040779429 ps |
| T926 |
/workspace/coverage/default/30.spi_device_stress_all.873034003 |
|
|
Mar 28 01:37:48 PM PDT 24 |
Mar 28 01:37:49 PM PDT 24 |
39228198 ps |
| T927 |
/workspace/coverage/default/6.spi_device_flash_and_tpm.3562724265 |
|
|
Mar 28 01:36:15 PM PDT 24 |
Mar 28 01:39:04 PM PDT 24 |
73286044985 ps |
| T928 |
/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2747094909 |
|
|
Mar 28 01:37:19 PM PDT 24 |
Mar 28 01:37:23 PM PDT 24 |
775446315 ps |
| T929 |
/workspace/coverage/default/33.spi_device_pass_addr_payload_swap.573930518 |
|
|
Mar 28 01:37:41 PM PDT 24 |
Mar 28 01:37:59 PM PDT 24 |
5646204481 ps |
| T930 |
/workspace/coverage/default/1.spi_device_tpm_sts_read.53061135 |
|
|
Mar 28 01:35:50 PM PDT 24 |
Mar 28 01:35:51 PM PDT 24 |
153989720 ps |
| T931 |
/workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1595300523 |
|
|
Mar 28 01:36:32 PM PDT 24 |
Mar 28 01:36:49 PM PDT 24 |
4020771512 ps |
| T932 |
/workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1679480116 |
|
|
Mar 28 01:37:00 PM PDT 24 |
Mar 28 01:37:09 PM PDT 24 |
2655239691 ps |
| T933 |
/workspace/coverage/default/3.spi_device_ram_cfg.2763012555 |
|
|
Mar 28 01:36:06 PM PDT 24 |
Mar 28 01:36:07 PM PDT 24 |
18482292 ps |
| T934 |
/workspace/coverage/default/20.spi_device_flash_all.2783105604 |
|
|
Mar 28 01:36:55 PM PDT 24 |
Mar 28 01:39:18 PM PDT 24 |
25106209735 ps |
| T935 |
/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3311580656 |
|
|
Mar 28 01:37:20 PM PDT 24 |
Mar 28 01:37:56 PM PDT 24 |
50740157495 ps |
| T936 |
/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4143080631 |
|
|
Mar 28 01:38:39 PM PDT 24 |
Mar 28 01:38:41 PM PDT 24 |
466430222 ps |
| T937 |
/workspace/coverage/default/39.spi_device_tpm_sts_read.3282539540 |
|
|
Mar 28 01:38:19 PM PDT 24 |
Mar 28 01:38:20 PM PDT 24 |
1177618170 ps |
| T938 |
/workspace/coverage/default/15.spi_device_stress_all.2335051233 |
|
|
Mar 28 01:37:03 PM PDT 24 |
Mar 28 01:39:09 PM PDT 24 |
37072033509 ps |
| T939 |
/workspace/coverage/default/41.spi_device_stress_all.1252339685 |
|
|
Mar 28 01:38:17 PM PDT 24 |
Mar 28 01:40:12 PM PDT 24 |
10534476263 ps |
| T940 |
/workspace/coverage/default/41.spi_device_read_buffer_direct.2545070368 |
|
|
Mar 28 01:38:13 PM PDT 24 |
Mar 28 01:38:20 PM PDT 24 |
5767307237 ps |
| T941 |
/workspace/coverage/default/0.spi_device_alert_test.2155107235 |
|
|
Mar 28 01:35:49 PM PDT 24 |
Mar 28 01:35:50 PM PDT 24 |
29372176 ps |
| T942 |
/workspace/coverage/default/2.spi_device_alert_test.671850037 |
|
|
Mar 28 01:36:01 PM PDT 24 |
Mar 28 01:36:02 PM PDT 24 |
32040486 ps |
| T943 |
/workspace/coverage/default/7.spi_device_stress_all.3725727120 |
|
|
Mar 28 01:36:33 PM PDT 24 |
Mar 28 01:37:59 PM PDT 24 |
6973404569 ps |
| T944 |
/workspace/coverage/default/40.spi_device_stress_all.1578555893 |
|
|
Mar 28 01:38:12 PM PDT 24 |
Mar 28 01:42:10 PM PDT 24 |
29154653586 ps |
| T945 |
/workspace/coverage/default/9.spi_device_flash_all.1960784452 |
|
|
Mar 28 01:36:21 PM PDT 24 |
Mar 28 01:37:55 PM PDT 24 |
67389546726 ps |
| T946 |
/workspace/coverage/default/49.spi_device_pass_cmd_filtering.3869542134 |
|
|
Mar 28 01:38:49 PM PDT 24 |
Mar 28 01:39:00 PM PDT 24 |
11516381352 ps |
| T947 |
/workspace/coverage/default/15.spi_device_tpm_sts_read.3665598613 |
|
|
Mar 28 01:36:55 PM PDT 24 |
Mar 28 01:36:57 PM PDT 24 |
201294451 ps |
| T948 |
/workspace/coverage/default/21.spi_device_pass_cmd_filtering.1848260370 |
|
|
Mar 28 01:37:02 PM PDT 24 |
Mar 28 01:37:16 PM PDT 24 |
3231647150 ps |
| T949 |
/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2529846399 |
|
|
Mar 28 01:36:33 PM PDT 24 |
Mar 28 01:37:41 PM PDT 24 |
9909625533 ps |
| T950 |
/workspace/coverage/default/37.spi_device_read_buffer_direct.691922074 |
|
|
Mar 28 01:37:56 PM PDT 24 |
Mar 28 01:38:01 PM PDT 24 |
726435189 ps |
| T951 |
/workspace/coverage/default/8.spi_device_mailbox.1719765374 |
|
|
Mar 28 01:36:15 PM PDT 24 |
Mar 28 01:36:25 PM PDT 24 |
3202567807 ps |
| T952 |
/workspace/coverage/default/28.spi_device_upload.2806380727 |
|
|
Mar 28 01:37:38 PM PDT 24 |
Mar 28 01:37:44 PM PDT 24 |
1568127076 ps |
| T953 |
/workspace/coverage/default/15.spi_device_cfg_cmd.4038985196 |
|
|
Mar 28 01:37:00 PM PDT 24 |
Mar 28 01:37:05 PM PDT 24 |
3626296595 ps |
| T954 |
/workspace/coverage/default/15.spi_device_tpm_rw.4122535175 |
|
|
Mar 28 01:36:53 PM PDT 24 |
Mar 28 01:36:56 PM PDT 24 |
419229640 ps |
| T955 |
/workspace/coverage/default/45.spi_device_flash_and_tpm.752551414 |
|
|
Mar 28 01:38:40 PM PDT 24 |
Mar 28 01:39:44 PM PDT 24 |
78270602929 ps |
| T956 |
/workspace/coverage/default/35.spi_device_upload.1040942277 |
|
|
Mar 28 01:37:49 PM PDT 24 |
Mar 28 01:37:54 PM PDT 24 |
275961705 ps |
| T957 |
/workspace/coverage/default/27.spi_device_flash_mode.2167721060 |
|
|
Mar 28 01:37:23 PM PDT 24 |
Mar 28 01:37:34 PM PDT 24 |
1969664284 ps |
| T958 |
/workspace/coverage/default/3.spi_device_cfg_cmd.2993895656 |
|
|
Mar 28 01:36:01 PM PDT 24 |
Mar 28 01:36:04 PM PDT 24 |
1490841607 ps |
| T959 |
/workspace/coverage/default/17.spi_device_flash_mode.3023704665 |
|
|
Mar 28 01:36:52 PM PDT 24 |
Mar 28 01:37:22 PM PDT 24 |
7215804193 ps |
| T960 |
/workspace/coverage/default/6.spi_device_csb_read.722662212 |
|
|
Mar 28 01:36:09 PM PDT 24 |
Mar 28 01:36:10 PM PDT 24 |
46273257 ps |
| T961 |
/workspace/coverage/default/39.spi_device_mailbox.1606106456 |
|
|
Mar 28 01:38:18 PM PDT 24 |
Mar 28 01:38:55 PM PDT 24 |
11270480633 ps |
| T962 |
/workspace/coverage/default/14.spi_device_mailbox.3586142436 |
|
|
Mar 28 01:36:53 PM PDT 24 |
Mar 28 01:37:01 PM PDT 24 |
904080355 ps |
| T963 |
/workspace/coverage/default/44.spi_device_tpm_all.4105262255 |
|
|
Mar 28 01:38:34 PM PDT 24 |
Mar 28 01:39:22 PM PDT 24 |
36881960720 ps |
| T964 |
/workspace/coverage/default/7.spi_device_ram_cfg.3053185986 |
|
|
Mar 28 01:36:13 PM PDT 24 |
Mar 28 01:36:14 PM PDT 24 |
20136471 ps |
| T965 |
/workspace/coverage/default/5.spi_device_tpm_rw.2373249596 |
|
|
Mar 28 01:36:10 PM PDT 24 |
Mar 28 01:36:15 PM PDT 24 |
214703635 ps |
| T966 |
/workspace/coverage/default/34.spi_device_intercept.1909290939 |
|
|
Mar 28 01:37:50 PM PDT 24 |
Mar 28 01:37:54 PM PDT 24 |
388890588 ps |
| T967 |
/workspace/coverage/default/12.spi_device_read_buffer_direct.4007197469 |
|
|
Mar 28 01:36:34 PM PDT 24 |
Mar 28 01:36:39 PM PDT 24 |
218690859 ps |
| T968 |
/workspace/coverage/default/20.spi_device_tpm_sts_read.2583535531 |
|
|
Mar 28 01:36:54 PM PDT 24 |
Mar 28 01:36:55 PM PDT 24 |
79173412 ps |
| T969 |
/workspace/coverage/default/47.spi_device_flash_all.665089551 |
|
|
Mar 28 01:38:37 PM PDT 24 |
Mar 28 01:38:50 PM PDT 24 |
5081765236 ps |
| T970 |
/workspace/coverage/default/4.spi_device_alert_test.1296375167 |
|
|
Mar 28 01:36:00 PM PDT 24 |
Mar 28 01:36:01 PM PDT 24 |
34019272 ps |
| T971 |
/workspace/coverage/default/17.spi_device_intercept.913062192 |
|
|
Mar 28 01:36:57 PM PDT 24 |
Mar 28 01:37:07 PM PDT 24 |
2855446365 ps |
| T972 |
/workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3551820169 |
|
|
Mar 28 01:37:22 PM PDT 24 |
Mar 28 01:37:50 PM PDT 24 |
9609405580 ps |
| T973 |
/workspace/coverage/default/14.spi_device_flash_all.3045293501 |
|
|
Mar 28 01:36:50 PM PDT 24 |
Mar 28 01:37:19 PM PDT 24 |
3569338951 ps |
| T974 |
/workspace/coverage/default/11.spi_device_pass_cmd_filtering.3692294810 |
|
|
Mar 28 01:36:37 PM PDT 24 |
Mar 28 01:36:58 PM PDT 24 |
22131256473 ps |
| T975 |
/workspace/coverage/default/12.spi_device_tpm_rw.3988838842 |
|
|
Mar 28 01:36:35 PM PDT 24 |
Mar 28 01:36:37 PM PDT 24 |
63925408 ps |
| T976 |
/workspace/coverage/default/41.spi_device_intercept.635852076 |
|
|
Mar 28 01:38:17 PM PDT 24 |
Mar 28 01:38:25 PM PDT 24 |
885450179 ps |
| T977 |
/workspace/coverage/default/43.spi_device_alert_test.3553807999 |
|
|
Mar 28 01:38:33 PM PDT 24 |
Mar 28 01:38:34 PM PDT 24 |
63555863 ps |
| T978 |
/workspace/coverage/default/47.spi_device_tpm_all.3502849222 |
|
|
Mar 28 01:38:36 PM PDT 24 |
Mar 28 01:39:07 PM PDT 24 |
5948198279 ps |
| T979 |
/workspace/coverage/default/10.spi_device_upload.2047484043 |
|
|
Mar 28 01:36:37 PM PDT 24 |
Mar 28 01:36:41 PM PDT 24 |
5524801242 ps |
| T980 |
/workspace/coverage/default/1.spi_device_flash_mode.593896125 |
|
|
Mar 28 01:35:59 PM PDT 24 |
Mar 28 01:36:13 PM PDT 24 |
1044680997 ps |
| T981 |
/workspace/coverage/default/36.spi_device_intercept.3412974458 |
|
|
Mar 28 01:37:56 PM PDT 24 |
Mar 28 01:38:02 PM PDT 24 |
820132655 ps |
| T982 |
/workspace/coverage/default/24.spi_device_csb_read.4171262701 |
|
|
Mar 28 01:37:21 PM PDT 24 |
Mar 28 01:37:22 PM PDT 24 |
26707696 ps |
| T983 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1738809164 |
|
|
Mar 28 12:50:47 PM PDT 24 |
Mar 28 12:50:48 PM PDT 24 |
11594562 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.652126708 |
|
|
Mar 28 12:50:29 PM PDT 24 |
Mar 28 12:50:52 PM PDT 24 |
1069176847 ps |
| T84 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4234172539 |
|
|
Mar 28 12:50:28 PM PDT 24 |
Mar 28 12:50:32 PM PDT 24 |
117324933 ps |
| T85 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3402893236 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:28 PM PDT 24 |
186953579 ps |
| T105 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1810847501 |
|
|
Mar 28 12:50:28 PM PDT 24 |
Mar 28 12:50:30 PM PDT 24 |
170666617 ps |
| T984 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.1450097340 |
|
|
Mar 28 12:50:48 PM PDT 24 |
Mar 28 12:50:49 PM PDT 24 |
17880160 ps |
| T985 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.3249240851 |
|
|
Mar 28 12:50:49 PM PDT 24 |
Mar 28 12:50:50 PM PDT 24 |
12645756 ps |
| T106 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.358243535 |
|
|
Mar 28 12:50:28 PM PDT 24 |
Mar 28 12:50:51 PM PDT 24 |
714113881 ps |
| T87 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4258760740 |
|
|
Mar 28 12:50:23 PM PDT 24 |
Mar 28 12:50:32 PM PDT 24 |
5511338419 ps |
| T86 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1213639743 |
|
|
Mar 28 12:50:25 PM PDT 24 |
Mar 28 12:50:27 PM PDT 24 |
28194209 ps |
| T89 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1911389422 |
|
|
Mar 28 12:50:43 PM PDT 24 |
Mar 28 12:50:47 PM PDT 24 |
266381270 ps |
| T88 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2496096287 |
|
|
Mar 28 12:50:47 PM PDT 24 |
Mar 28 12:51:05 PM PDT 24 |
14424139026 ps |
| T986 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2415727821 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:30 PM PDT 24 |
187864531 ps |
| T90 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2772722284 |
|
|
Mar 28 12:50:44 PM PDT 24 |
Mar 28 12:50:46 PM PDT 24 |
61204622 ps |
| T987 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3669774805 |
|
|
Mar 28 12:50:53 PM PDT 24 |
Mar 28 12:50:54 PM PDT 24 |
14585727 ps |
| T107 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.801185414 |
|
|
Mar 28 12:50:29 PM PDT 24 |
Mar 28 12:50:31 PM PDT 24 |
324892645 ps |
| T102 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2444163061 |
|
|
Mar 28 12:50:45 PM PDT 24 |
Mar 28 12:50:47 PM PDT 24 |
52826071 ps |
| T108 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1411473787 |
|
|
Mar 28 12:50:23 PM PDT 24 |
Mar 28 12:50:26 PM PDT 24 |
121382340 ps |
| T988 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.4258249396 |
|
|
Mar 28 12:50:44 PM PDT 24 |
Mar 28 12:50:44 PM PDT 24 |
14072707 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.4263244679 |
|
|
Mar 28 12:50:42 PM PDT 24 |
Mar 28 12:50:43 PM PDT 24 |
14894133 ps |
| T990 |
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.1088836384 |
|
|
Mar 28 12:50:49 PM PDT 24 |
Mar 28 12:50:50 PM PDT 24 |
15312811 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.807921587 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:28 PM PDT 24 |
95177740 ps |
| T103 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3771498467 |
|
|
Mar 28 12:50:27 PM PDT 24 |
Mar 28 12:50:42 PM PDT 24 |
666017379 ps |
| T992 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2789885649 |
|
|
Mar 28 12:50:47 PM PDT 24 |
Mar 28 12:50:49 PM PDT 24 |
89741641 ps |
| T91 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1555024899 |
|
|
Mar 28 12:50:41 PM PDT 24 |
Mar 28 12:50:45 PM PDT 24 |
593021665 ps |
| T993 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2866393364 |
|
|
Mar 28 12:50:40 PM PDT 24 |
Mar 28 12:50:41 PM PDT 24 |
123804211 ps |
| T994 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.3728775152 |
|
|
Mar 28 12:50:52 PM PDT 24 |
Mar 28 12:50:53 PM PDT 24 |
15521570 ps |
| T995 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.4138186684 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:27 PM PDT 24 |
34358318 ps |
| T92 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1845122674 |
|
|
Mar 28 12:50:45 PM PDT 24 |
Mar 28 12:50:49 PM PDT 24 |
1998297425 ps |
| T104 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2220623683 |
|
|
Mar 28 12:50:44 PM PDT 24 |
Mar 28 12:50:58 PM PDT 24 |
2013392974 ps |
| T109 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.622417262 |
|
|
Mar 28 12:50:23 PM PDT 24 |
Mar 28 12:50:51 PM PDT 24 |
13902235440 ps |
| T996 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.910034165 |
|
|
Mar 28 12:50:31 PM PDT 24 |
Mar 28 12:50:54 PM PDT 24 |
1582937133 ps |
| T100 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2550541385 |
|
|
Mar 28 12:50:33 PM PDT 24 |
Mar 28 12:50:36 PM PDT 24 |
439670297 ps |
| T72 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4012749117 |
|
|
Mar 28 12:50:21 PM PDT 24 |
Mar 28 12:50:23 PM PDT 24 |
37884879 ps |
| T101 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1406568578 |
|
|
Mar 28 12:50:25 PM PDT 24 |
Mar 28 12:50:41 PM PDT 24 |
646356776 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.301531860 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:29 PM PDT 24 |
249739435 ps |
| T110 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2075461895 |
|
|
Mar 28 12:50:31 PM PDT 24 |
Mar 28 12:50:33 PM PDT 24 |
68579192 ps |
| T126 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2900049009 |
|
|
Mar 28 12:50:21 PM PDT 24 |
Mar 28 12:50:36 PM PDT 24 |
711152469 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3933613427 |
|
|
Mar 28 12:50:23 PM PDT 24 |
Mar 28 12:50:39 PM PDT 24 |
210437344 ps |
| T93 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2369571142 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:30 PM PDT 24 |
497409448 ps |
| T998 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.3982377401 |
|
|
Mar 28 12:50:51 PM PDT 24 |
Mar 28 12:50:52 PM PDT 24 |
12775871 ps |
| T143 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1198514885 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:47 PM PDT 24 |
3648540338 ps |
| T144 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1605917054 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:48 PM PDT 24 |
4188693188 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.666634581 |
|
|
Mar 28 12:50:27 PM PDT 24 |
Mar 28 12:50:31 PM PDT 24 |
515622698 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3425347095 |
|
|
Mar 28 12:50:28 PM PDT 24 |
Mar 28 12:50:29 PM PDT 24 |
12279518 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.1597040898 |
|
|
Mar 28 12:50:23 PM PDT 24 |
Mar 28 12:50:24 PM PDT 24 |
13665840 ps |
| T145 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3451117340 |
|
|
Mar 28 12:50:43 PM PDT 24 |
Mar 28 12:50:59 PM PDT 24 |
2681480973 ps |
| T111 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.562469475 |
|
|
Mar 28 12:50:41 PM PDT 24 |
Mar 28 12:50:43 PM PDT 24 |
21776267 ps |
| T112 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3659243965 |
|
|
Mar 28 12:50:30 PM PDT 24 |
Mar 28 12:50:54 PM PDT 24 |
935729023 ps |
| T1001 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.3483041957 |
|
|
Mar 28 12:50:51 PM PDT 24 |
Mar 28 12:50:52 PM PDT 24 |
53894808 ps |
| T1002 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2496311459 |
|
|
Mar 28 12:50:24 PM PDT 24 |
Mar 28 12:50:27 PM PDT 24 |
81599166 ps |
| T1003 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1942407676 |
|
|
Mar 28 12:50:56 PM PDT 24 |
Mar 28 12:51:16 PM PDT 24 |
304614749 ps |
| T113 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1570916578 |
|
|
Mar 28 12:50:42 PM PDT 24 |
Mar 28 12:50:45 PM PDT 24 |
105088224 ps |
| T95 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1790591949 |
|
|
Mar 28 12:50:31 PM PDT 24 |
Mar 28 12:50:34 PM PDT 24 |
126544645 ps |
| T73 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1064484568 |
|
|
Mar 28 12:50:27 PM PDT 24 |
Mar 28 12:50:29 PM PDT 24 |
42516816 ps |
| T98 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2979051701 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:31 PM PDT 24 |
333492870 ps |
| T1004 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2811520827 |
|
|
Mar 28 12:50:19 PM PDT 24 |
Mar 28 12:50:22 PM PDT 24 |
63113431 ps |
| T1005 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.2860210197 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:27 PM PDT 24 |
34221255 ps |
| T97 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1705096932 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:30 PM PDT 24 |
99877625 ps |
| T1006 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.379195785 |
|
|
Mar 28 12:50:24 PM PDT 24 |
Mar 28 12:50:25 PM PDT 24 |
17518348 ps |
| T99 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2954564389 |
|
|
Mar 28 12:50:33 PM PDT 24 |
Mar 28 12:50:38 PM PDT 24 |
209011908 ps |
| T1007 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2553819953 |
|
|
Mar 28 12:50:26 PM PDT 24 |
Mar 28 12:50:30 PM PDT 24 |
1051776612 ps |