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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 98.37 94.16 98.61 89.36 97.10 95.82 98.22


Total test records in report: 1113
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T1008 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2371705507 Mar 28 12:50:45 PM PDT 24 Mar 28 12:50:47 PM PDT 24 51068047 ps
T74 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1432024258 Mar 28 12:50:28 PM PDT 24 Mar 28 12:50:29 PM PDT 24 45209456 ps
T1009 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2876955459 Mar 28 12:50:36 PM PDT 24 Mar 28 12:50:40 PM PDT 24 56696545 ps
T1010 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4245154085 Mar 28 12:50:45 PM PDT 24 Mar 28 12:50:46 PM PDT 24 45423515 ps
T1011 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2145149561 Mar 28 12:50:31 PM PDT 24 Mar 28 12:50:33 PM PDT 24 117137881 ps
T1012 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2794594238 Mar 28 12:50:23 PM PDT 24 Mar 28 12:50:24 PM PDT 24 12509766 ps
T1013 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3029920124 Mar 28 12:50:47 PM PDT 24 Mar 28 12:50:49 PM PDT 24 185617120 ps
T1014 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1476445132 Mar 28 12:50:29 PM PDT 24 Mar 28 12:50:33 PM PDT 24 57712664 ps
T1015 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2253522156 Mar 28 12:50:30 PM PDT 24 Mar 28 12:50:31 PM PDT 24 10931171 ps
T1016 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3896333732 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:47 PM PDT 24 154673694 ps
T1017 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2684349122 Mar 28 12:50:29 PM PDT 24 Mar 28 12:50:32 PM PDT 24 421822427 ps
T1018 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.972599662 Mar 28 12:50:24 PM PDT 24 Mar 28 12:50:25 PM PDT 24 46330963 ps
T1019 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2403280769 Mar 28 12:50:45 PM PDT 24 Mar 28 12:50:45 PM PDT 24 29914942 ps
T1020 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1621494505 Mar 28 12:50:47 PM PDT 24 Mar 28 12:50:49 PM PDT 24 1436159292 ps
T114 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2908460885 Mar 28 12:50:22 PM PDT 24 Mar 28 12:50:25 PM PDT 24 404786635 ps
T1021 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.374714419 Mar 28 12:50:24 PM PDT 24 Mar 28 12:50:25 PM PDT 24 29422254 ps
T1022 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.746622509 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:45 PM PDT 24 11169541 ps
T1023 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1179728066 Mar 28 12:50:48 PM PDT 24 Mar 28 12:50:49 PM PDT 24 148996257 ps
T1024 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.142034196 Mar 28 12:50:42 PM PDT 24 Mar 28 12:50:45 PM PDT 24 85683565 ps
T142 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2411983334 Mar 28 12:50:25 PM PDT 24 Mar 28 12:50:39 PM PDT 24 928122444 ps
T141 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.547133502 Mar 28 12:50:25 PM PDT 24 Mar 28 12:50:29 PM PDT 24 125539208 ps
T1025 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.351880860 Mar 28 12:50:43 PM PDT 24 Mar 28 12:50:46 PM PDT 24 280794810 ps
T1026 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1716818994 Mar 28 12:50:42 PM PDT 24 Mar 28 12:50:46 PM PDT 24 92605044 ps
T115 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2977374900 Mar 28 12:50:36 PM PDT 24 Mar 28 12:50:37 PM PDT 24 35785074 ps
T1027 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.316319777 Mar 28 12:50:33 PM PDT 24 Mar 28 12:50:34 PM PDT 24 189021677 ps
T1028 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1927761611 Mar 28 12:50:47 PM PDT 24 Mar 28 12:50:48 PM PDT 24 16485594 ps
T1029 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3476958780 Mar 28 12:50:40 PM PDT 24 Mar 28 12:50:43 PM PDT 24 29450170 ps
T1030 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2101725960 Mar 28 12:50:43 PM PDT 24 Mar 28 12:50:46 PM PDT 24 163190199 ps
T1031 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2699201420 Mar 28 12:50:24 PM PDT 24 Mar 28 12:50:31 PM PDT 24 256843407 ps
T1032 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1841884379 Mar 28 12:50:24 PM PDT 24 Mar 28 12:50:25 PM PDT 24 11996699 ps
T1033 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4235287375 Mar 28 12:50:21 PM PDT 24 Mar 28 12:50:23 PM PDT 24 57663895 ps
T1034 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3472446 Mar 28 12:50:34 PM PDT 24 Mar 28 12:50:36 PM PDT 24 766546935 ps
T1035 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2085104098 Mar 28 12:50:31 PM PDT 24 Mar 28 12:50:33 PM PDT 24 63680338 ps
T1036 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3261028740 Mar 28 12:50:36 PM PDT 24 Mar 28 12:50:40 PM PDT 24 61558911 ps
T1037 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1722897463 Mar 28 12:50:30 PM PDT 24 Mar 28 12:50:32 PM PDT 24 37601741 ps
T1038 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2343085597 Mar 28 12:50:27 PM PDT 24 Mar 28 12:50:50 PM PDT 24 947273401 ps
T1039 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1413600757 Mar 28 12:50:42 PM PDT 24 Mar 28 12:50:43 PM PDT 24 27776451 ps
T1040 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1144426442 Mar 28 12:50:48 PM PDT 24 Mar 28 12:50:49 PM PDT 24 13416832 ps
T1041 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1111387168 Mar 28 12:50:23 PM PDT 24 Mar 28 12:50:25 PM PDT 24 134231133 ps
T1042 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1292041285 Mar 28 12:50:49 PM PDT 24 Mar 28 12:50:50 PM PDT 24 13342550 ps
T1043 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1073448019 Mar 28 12:50:28 PM PDT 24 Mar 28 12:50:29 PM PDT 24 14929989 ps
T1044 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3228966269 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:45 PM PDT 24 12873603 ps
T1045 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1689480663 Mar 28 12:50:43 PM PDT 24 Mar 28 12:50:45 PM PDT 24 245989070 ps
T1046 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3603931317 Mar 28 12:50:56 PM PDT 24 Mar 28 12:50:57 PM PDT 24 41645456 ps
T1047 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1666174512 Mar 28 12:50:49 PM PDT 24 Mar 28 12:50:50 PM PDT 24 11584634 ps
T1048 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3403009398 Mar 28 12:50:25 PM PDT 24 Mar 28 12:50:27 PM PDT 24 100749628 ps
T1049 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3259990207 Mar 28 12:50:40 PM PDT 24 Mar 28 12:50:41 PM PDT 24 49228330 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4138206571 Mar 28 12:50:24 PM PDT 24 Mar 28 12:50:25 PM PDT 24 15957302 ps
T1051 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3414189434 Mar 28 12:50:30 PM PDT 24 Mar 28 12:50:32 PM PDT 24 33313528 ps
T1052 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4021456630 Mar 28 12:50:23 PM PDT 24 Mar 28 12:50:28 PM PDT 24 3392302188 ps
T1053 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2750712979 Mar 28 12:50:31 PM PDT 24 Mar 28 12:50:50 PM PDT 24 290750613 ps
T1054 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2876831110 Mar 28 12:50:26 PM PDT 24 Mar 28 12:50:28 PM PDT 24 73368247 ps
T1055 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3792942183 Mar 28 12:50:36 PM PDT 24 Mar 28 12:50:40 PM PDT 24 650911869 ps
T1056 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.832490058 Mar 28 12:50:34 PM PDT 24 Mar 28 12:50:35 PM PDT 24 26991191 ps
T1057 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.210160990 Mar 28 12:50:29 PM PDT 24 Mar 28 12:50:32 PM PDT 24 213781117 ps
T1058 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2041713993 Mar 28 12:50:45 PM PDT 24 Mar 28 12:50:46 PM PDT 24 51560502 ps
T146 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3434357787 Mar 28 12:50:25 PM PDT 24 Mar 28 12:50:48 PM PDT 24 4274335914 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.787317013 Mar 28 12:50:26 PM PDT 24 Mar 28 12:50:28 PM PDT 24 88667145 ps
T1060 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1823441370 Mar 28 12:50:23 PM PDT 24 Mar 28 12:50:26 PM PDT 24 151445179 ps
T1061 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2410983825 Mar 28 12:50:48 PM PDT 24 Mar 28 12:50:49 PM PDT 24 37814432 ps
T1062 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3514447993 Mar 28 12:50:56 PM PDT 24 Mar 28 12:50:57 PM PDT 24 43717209 ps
T1063 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3556504184 Mar 28 12:50:43 PM PDT 24 Mar 28 12:50:47 PM PDT 24 878272367 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1070688205 Mar 28 12:50:31 PM PDT 24 Mar 28 12:51:06 PM PDT 24 647163633 ps
T1065 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3952545237 Mar 28 12:50:26 PM PDT 24 Mar 28 12:50:28 PM PDT 24 62667128 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.861964259 Mar 28 12:50:28 PM PDT 24 Mar 28 12:51:04 PM PDT 24 7550175291 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.350123473 Mar 28 12:50:28 PM PDT 24 Mar 28 12:50:29 PM PDT 24 12533449 ps
T1068 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2037824685 Mar 28 12:50:31 PM PDT 24 Mar 28 12:50:34 PM PDT 24 140011816 ps
T1069 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4154501677 Mar 28 12:50:47 PM PDT 24 Mar 28 12:50:48 PM PDT 24 23275450 ps
T1070 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1773508019 Mar 28 12:50:33 PM PDT 24 Mar 28 12:50:34 PM PDT 24 15634390 ps
T1071 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2955313795 Mar 28 12:50:33 PM PDT 24 Mar 28 12:50:35 PM PDT 24 93195302 ps
T1072 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.954858062 Mar 28 12:50:28 PM PDT 24 Mar 28 12:50:43 PM PDT 24 573712059 ps
T1073 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.164534143 Mar 28 12:50:31 PM PDT 24 Mar 28 12:50:35 PM PDT 24 261403175 ps
T1074 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1983943201 Mar 28 12:50:43 PM PDT 24 Mar 28 12:50:58 PM PDT 24 592923478 ps
T1075 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.395799087 Mar 28 12:50:43 PM PDT 24 Mar 28 12:50:48 PM PDT 24 657576658 ps
T1076 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3361439952 Mar 28 12:50:45 PM PDT 24 Mar 28 12:50:46 PM PDT 24 55226593 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1304610838 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:59 PM PDT 24 683908586 ps
T1078 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4187537436 Mar 28 12:50:31 PM PDT 24 Mar 28 12:50:56 PM PDT 24 1208369562 ps
T1079 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1668691035 Mar 28 12:50:43 PM PDT 24 Mar 28 12:50:44 PM PDT 24 60036241 ps
T1080 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1686143006 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:45 PM PDT 24 27709935 ps
T1081 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2593011820 Mar 28 12:50:46 PM PDT 24 Mar 28 12:50:47 PM PDT 24 16975337 ps
T1082 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1941081861 Mar 28 12:50:30 PM PDT 24 Mar 28 12:50:50 PM PDT 24 1298606388 ps
T1083 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.293094920 Mar 28 12:50:25 PM PDT 24 Mar 28 12:50:30 PM PDT 24 334162431 ps
T1084 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2462385274 Mar 28 12:50:28 PM PDT 24 Mar 28 12:50:29 PM PDT 24 38272715 ps
T1085 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1149701304 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:44 PM PDT 24 35348158 ps
T1086 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1852936107 Mar 28 12:50:43 PM PDT 24 Mar 28 12:50:47 PM PDT 24 581108982 ps
T1087 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.51842790 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:45 PM PDT 24 41881090 ps
T1088 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3843585235 Mar 28 12:50:39 PM PDT 24 Mar 28 12:50:42 PM PDT 24 421913040 ps
T1089 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2440698733 Mar 28 12:50:40 PM PDT 24 Mar 28 12:50:43 PM PDT 24 983540153 ps
T1090 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2817955107 Mar 28 12:50:48 PM PDT 24 Mar 28 12:50:55 PM PDT 24 219039446 ps
T1091 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3078844634 Mar 28 12:50:26 PM PDT 24 Mar 28 12:50:28 PM PDT 24 52499701 ps
T1092 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3980548997 Mar 28 12:50:28 PM PDT 24 Mar 28 12:50:33 PM PDT 24 422295309 ps
T1093 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1367699606 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:45 PM PDT 24 46810165 ps
T1094 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.168189307 Mar 28 12:50:43 PM PDT 24 Mar 28 12:50:50 PM PDT 24 602544190 ps
T1095 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3138330464 Mar 28 12:50:37 PM PDT 24 Mar 28 12:50:38 PM PDT 24 86907923 ps
T1096 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2558551598 Mar 28 12:50:42 PM PDT 24 Mar 28 12:50:43 PM PDT 24 33335155 ps
T1097 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3782219489 Mar 28 12:50:47 PM PDT 24 Mar 28 12:50:48 PM PDT 24 56519385 ps
T1098 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.621316009 Mar 28 12:50:33 PM PDT 24 Mar 28 12:50:35 PM PDT 24 27703457 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2231477577 Mar 28 12:50:21 PM PDT 24 Mar 28 12:50:22 PM PDT 24 47840288 ps
T1100 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1188485618 Mar 28 12:50:24 PM PDT 24 Mar 28 12:50:26 PM PDT 24 40613915 ps
T1101 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1627552527 Mar 28 12:50:26 PM PDT 24 Mar 28 12:50:28 PM PDT 24 238079003 ps
T1102 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2537633966 Mar 28 12:50:57 PM PDT 24 Mar 28 12:50:58 PM PDT 24 14436787 ps
T1103 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4036449841 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:46 PM PDT 24 397563971 ps
T1104 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1972200245 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:45 PM PDT 24 15229722 ps
T1105 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2823743111 Mar 28 12:50:44 PM PDT 24 Mar 28 12:50:45 PM PDT 24 13386483 ps
T1106 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2178204228 Mar 28 12:50:33 PM PDT 24 Mar 28 12:50:34 PM PDT 24 14047277 ps
T75 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.14534450 Mar 28 12:50:27 PM PDT 24 Mar 28 12:50:28 PM PDT 24 83050811 ps
T1107 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1453518201 Mar 28 12:50:26 PM PDT 24 Mar 28 12:50:27 PM PDT 24 127328570 ps
T1108 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2815294090 Mar 28 12:50:24 PM PDT 24 Mar 28 12:50:25 PM PDT 24 158209429 ps
T1109 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.550611971 Mar 28 12:50:34 PM PDT 24 Mar 28 12:50:37 PM PDT 24 43281484 ps
T1110 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.188434641 Mar 28 12:50:33 PM PDT 24 Mar 28 12:50:35 PM PDT 24 105760637 ps
T1111 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3351776749 Mar 28 12:50:27 PM PDT 24 Mar 28 12:50:29 PM PDT 24 839352115 ps
T1112 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.706878141 Mar 28 12:50:25 PM PDT 24 Mar 28 12:50:30 PM PDT 24 200153590 ps
T1113 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1831406975 Mar 28 12:50:27 PM PDT 24 Mar 28 12:50:30 PM PDT 24 464984407 ps

Test location /workspace/coverage/default/8.spi_device_stress_all.1994456391
Short name T6
Test name
Test status
Simulation time 17986455673 ps
CPU time 90.97 seconds
Started Mar 28 01:36:18 PM PDT 24
Finished Mar 28 01:37:49 PM PDT 24
Peak memory 258388 kb
Host smart-2c0eb49b-ed08-4051-b436-2facd1fe349a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994456391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1994456391
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2090522790
Short name T13
Test name
Test status
Simulation time 57357018474 ps
CPU time 403 seconds
Started Mar 28 01:37:39 PM PDT 24
Finished Mar 28 01:44:23 PM PDT 24
Peak memory 251464 kb
Host smart-9d6d9288-c8e0-49f4-8780-27742a4e8c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090522790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2090522790
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.652126708
Short name T83
Test name
Test status
Simulation time 1069176847 ps
CPU time 23.42 seconds
Started Mar 28 12:50:29 PM PDT 24
Finished Mar 28 12:50:52 PM PDT 24
Peak memory 215468 kb
Host smart-e67efe77-b29b-4128-963f-a31d952160ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652126708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.652126708
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2391496562
Short name T28
Test name
Test status
Simulation time 105746211051 ps
CPU time 765.01 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:49:48 PM PDT 24
Peak memory 268796 kb
Host smart-6e0a7374-cb0a-4653-89e7-a941269ad4a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391496562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2391496562
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1872012678
Short name T157
Test name
Test status
Simulation time 76201622675 ps
CPU time 593.93 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:48:10 PM PDT 24
Peak memory 283152 kb
Host smart-a7cc4aed-983e-4e4c-8c17-9372f238db66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872012678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1872012678
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2340151203
Short name T47
Test name
Test status
Simulation time 43647855 ps
CPU time 0.75 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:49 PM PDT 24
Peak memory 216072 kb
Host smart-68f15aca-4692-4eca-9e16-5ad5dcbd75c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340151203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2340151203
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1168904305
Short name T12
Test name
Test status
Simulation time 86481190685 ps
CPU time 172.53 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:39:27 PM PDT 24
Peak memory 257272 kb
Host smart-00faa9bc-c88f-475a-9ef2-967ed72a2b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168904305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1168904305
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.302083674
Short name T152
Test name
Test status
Simulation time 43774944461 ps
CPU time 87.75 seconds
Started Mar 28 01:36:32 PM PDT 24
Finished Mar 28 01:38:00 PM PDT 24
Peak memory 271712 kb
Host smart-b7f14e8a-5637-4a01-836d-3e1676c2d178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302083674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.302083674
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1555024899
Short name T91
Test name
Test status
Simulation time 593021665 ps
CPU time 4.23 seconds
Started Mar 28 12:50:41 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 215452 kb
Host smart-d49069b7-727e-401b-8163-9d1c06486e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555024899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1555024899
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3190979072
Short name T59
Test name
Test status
Simulation time 62688403 ps
CPU time 1 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:36:02 PM PDT 24
Peak memory 235300 kb
Host smart-39195f11-0330-4d8a-9900-e3a5c5c410c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190979072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3190979072
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3324134441
Short name T121
Test name
Test status
Simulation time 496089290 ps
CPU time 11.32 seconds
Started Mar 28 01:36:30 PM PDT 24
Finished Mar 28 01:36:42 PM PDT 24
Peak memory 237336 kb
Host smart-9f5dec0a-fb87-4109-98aa-9f3328879410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324134441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3324134441
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.150463184
Short name T217
Test name
Test status
Simulation time 118865683806 ps
CPU time 606.05 seconds
Started Mar 28 01:37:57 PM PDT 24
Finished Mar 28 01:48:04 PM PDT 24
Peak memory 306228 kb
Host smart-49159086-1a12-406c-9eac-bf104a268977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150463184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.150463184
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2991356850
Short name T25
Test name
Test status
Simulation time 53925197557 ps
CPU time 134.25 seconds
Started Mar 28 01:36:08 PM PDT 24
Finished Mar 28 01:38:23 PM PDT 24
Peak memory 254924 kb
Host smart-bfa7b85f-c922-493f-9381-01cff3810850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991356850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2991356850
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1848914165
Short name T36
Test name
Test status
Simulation time 26973744969 ps
CPU time 270.54 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:43:05 PM PDT 24
Peak memory 272924 kb
Host smart-9681115b-6ce2-49f2-9895-1c7c21a7c186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848914165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1848914165
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.358243535
Short name T106
Test name
Test status
Simulation time 714113881 ps
CPU time 22.86 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:51 PM PDT 24
Peak memory 207048 kb
Host smart-a94c83bc-395e-4bce-b57b-409998857391
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358243535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.358243535
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2857978649
Short name T150
Test name
Test status
Simulation time 359440352618 ps
CPU time 421.58 seconds
Started Mar 28 01:38:48 PM PDT 24
Finished Mar 28 01:45:50 PM PDT 24
Peak memory 267004 kb
Host smart-2669fee0-4f81-404b-ac6a-da86df6e4e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857978649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2857978649
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.109142326
Short name T331
Test name
Test status
Simulation time 82656817 ps
CPU time 1.1 seconds
Started Mar 28 01:35:55 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 216516 kb
Host smart-fa190ceb-f458-412f-ac04-83e5625c0e18
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109142326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.109142326
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1526822421
Short name T170
Test name
Test status
Simulation time 51029383227 ps
CPU time 146.94 seconds
Started Mar 28 01:37:26 PM PDT 24
Finished Mar 28 01:39:53 PM PDT 24
Peak memory 254120 kb
Host smart-16681d5f-23bf-47ea-887b-e4af6d4723aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526822421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1526822421
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2341281730
Short name T228
Test name
Test status
Simulation time 193255115739 ps
CPU time 689.13 seconds
Started Mar 28 01:36:59 PM PDT 24
Finished Mar 28 01:48:29 PM PDT 24
Peak memory 270392 kb
Host smart-e1268e2c-7bf2-4151-bfb8-52822236ba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341281730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2341281730
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2866153481
Short name T117
Test name
Test status
Simulation time 58351586399 ps
CPU time 143.08 seconds
Started Mar 28 01:36:54 PM PDT 24
Finished Mar 28 01:39:18 PM PDT 24
Peak memory 268668 kb
Host smart-f51ee045-f8a1-4a73-8bdb-6345bec131f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866153481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2866153481
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.384414086
Short name T71
Test name
Test status
Simulation time 190063325446 ps
CPU time 197.41 seconds
Started Mar 28 01:36:02 PM PDT 24
Finished Mar 28 01:39:20 PM PDT 24
Peak memory 265504 kb
Host smart-5fcf5c6d-922b-4c0a-a30d-bebcb71d8c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384414086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
384414086
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3591878609
Short name T200
Test name
Test status
Simulation time 270050476438 ps
CPU time 383.26 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:43:46 PM PDT 24
Peak memory 265016 kb
Host smart-b0def0c8-449d-4677-98f5-57b2ed6b133d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591878609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3591878609
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1661973591
Short name T216
Test name
Test status
Simulation time 14911225194 ps
CPU time 148.93 seconds
Started Mar 28 01:36:18 PM PDT 24
Finished Mar 28 01:38:47 PM PDT 24
Peak memory 268692 kb
Host smart-9709430f-4a10-40e7-ada8-d7a87ccd7b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661973591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1661973591
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2979051701
Short name T98
Test name
Test status
Simulation time 333492870 ps
CPU time 4.57 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 215560 kb
Host smart-1c4e7e22-f977-465b-a99b-90d3f8fa6f8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979051701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2979051701
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1340529694
Short name T270
Test name
Test status
Simulation time 27707287 ps
CPU time 0.74 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 205504 kb
Host smart-65b21baf-1058-4984-8962-018cdc681c16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340529694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1340529694
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2411983334
Short name T142
Test name
Test status
Simulation time 928122444 ps
CPU time 12.99 seconds
Started Mar 28 12:50:25 PM PDT 24
Finished Mar 28 12:50:39 PM PDT 24
Peak memory 215916 kb
Host smart-52927c5b-7c68-4264-8883-24ebab532d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411983334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2411983334
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.915921716
Short name T138
Test name
Test status
Simulation time 96414731393 ps
CPU time 230.61 seconds
Started Mar 28 01:36:50 PM PDT 24
Finished Mar 28 01:40:43 PM PDT 24
Peak memory 254424 kb
Host smart-c41d175c-37e7-4f6d-b5aa-77fbea8061dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915921716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.915921716
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2644151529
Short name T176
Test name
Test status
Simulation time 78342661492 ps
CPU time 512.63 seconds
Started Mar 28 01:37:53 PM PDT 24
Finished Mar 28 01:46:26 PM PDT 24
Peak memory 273380 kb
Host smart-a885f7b8-94e5-4577-88fa-6a1348295d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644151529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2644151529
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3196236983
Short name T447
Test name
Test status
Simulation time 12347742561 ps
CPU time 27.52 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:38:46 PM PDT 24
Peak memory 233776 kb
Host smart-8e610e6c-c483-4694-8cfc-e6af45d96c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196236983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3196236983
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1317357079
Short name T8
Test name
Test status
Simulation time 4903282778 ps
CPU time 11.08 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:31 PM PDT 24
Peak memory 224452 kb
Host smart-2cf63cd3-7b44-4b59-a28e-1e0022f7d4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317357079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1317357079
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3434357787
Short name T146
Test name
Test status
Simulation time 4274335914 ps
CPU time 22.8 seconds
Started Mar 28 12:50:25 PM PDT 24
Finished Mar 28 12:50:48 PM PDT 24
Peak memory 215396 kb
Host smart-e930a198-8954-451f-9b21-f5059d9bb16a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434357787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3434357787
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1616460455
Short name T236
Test name
Test status
Simulation time 49956741073 ps
CPU time 418.33 seconds
Started Mar 28 01:36:54 PM PDT 24
Finished Mar 28 01:43:52 PM PDT 24
Peak memory 266876 kb
Host smart-d58724a0-d05b-4860-bb57-1fc0deca00aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616460455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1616460455
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.352626425
Short name T239
Test name
Test status
Simulation time 6127495051 ps
CPU time 111.09 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:39:11 PM PDT 24
Peak memory 261004 kb
Host smart-bcbf70e7-1923-454c-bd27-abc52cf08a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352626425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.352626425
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.140630312
Short name T242
Test name
Test status
Simulation time 196859550120 ps
CPU time 665.92 seconds
Started Mar 28 01:37:37 PM PDT 24
Finished Mar 28 01:48:43 PM PDT 24
Peak memory 269568 kb
Host smart-dccbcb41-6463-47ff-8c19-a989dd40f451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140630312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.140630312
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.554411691
Short name T78
Test name
Test status
Simulation time 82714639474 ps
CPU time 171.93 seconds
Started Mar 28 01:37:39 PM PDT 24
Finished Mar 28 01:40:32 PM PDT 24
Peak memory 256080 kb
Host smart-54b940b4-40c7-47a4-afd5-0963a8c46279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554411691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.554411691
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2076103704
Short name T20
Test name
Test status
Simulation time 37986484064 ps
CPU time 252.7 seconds
Started Mar 28 01:37:51 PM PDT 24
Finished Mar 28 01:42:04 PM PDT 24
Peak memory 271960 kb
Host smart-66551707-f119-4eb9-9c25-9dadf471782f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076103704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2076103704
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1720224948
Short name T44
Test name
Test status
Simulation time 54143005375 ps
CPU time 192.58 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:40:36 PM PDT 24
Peak memory 273260 kb
Host smart-f0455056-7517-48a0-91af-333a8e0e48d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720224948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1720224948
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.601374180
Short name T251
Test name
Test status
Simulation time 182002041452 ps
CPU time 152.28 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:40:10 PM PDT 24
Peak memory 240788 kb
Host smart-c1e10438-9d03-45f5-b005-1835fd015297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601374180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.601374180
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3663290430
Short name T213
Test name
Test status
Simulation time 32343137046 ps
CPU time 205.36 seconds
Started Mar 28 01:38:31 PM PDT 24
Finished Mar 28 01:41:57 PM PDT 24
Peak memory 255216 kb
Host smart-da769aa5-9aed-4901-a3c0-a43951dfd92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663290430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3663290430
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2277875527
Short name T79
Test name
Test status
Simulation time 762340829 ps
CPU time 3.55 seconds
Started Mar 28 01:37:35 PM PDT 24
Finished Mar 28 01:37:38 PM PDT 24
Peak memory 218512 kb
Host smart-eeac1326-fc87-474c-8c1e-96aa36042a80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2277875527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2277875527
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.14534450
Short name T75
Test name
Test status
Simulation time 83050811 ps
CPU time 1.4 seconds
Started Mar 28 12:50:27 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 207172 kb
Host smart-e02cb808-f210-4fe2-b955-5af60f1ace96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14534450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
hw_reset.14534450
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1716818994
Short name T1026
Test name
Test status
Simulation time 92605044 ps
CPU time 4.09 seconds
Started Mar 28 12:50:42 PM PDT 24
Finished Mar 28 12:50:46 PM PDT 24
Peak memory 215560 kb
Host smart-6d8806fa-fe01-4c21-ae17-93398196d0dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716818994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1716818994
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3933613427
Short name T997
Test name
Test status
Simulation time 210437344 ps
CPU time 15.78 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:39 PM PDT 24
Peak memory 215396 kb
Host smart-cc094bf6-9b5d-4e95-8c13-4588efd47024
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933613427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3933613427
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1188485618
Short name T1100
Test name
Test status
Simulation time 40613915 ps
CPU time 1.78 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:26 PM PDT 24
Peak memory 215428 kb
Host smart-01210749-48c7-46bd-8068-8574ebafad87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188485618 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1188485618
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2908460885
Short name T114
Test name
Test status
Simulation time 404786635 ps
CPU time 2.13 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 215356 kb
Host smart-d917be27-3233-4bf9-b327-5b5992823eb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908460885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
908460885
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2231477577
Short name T1099
Test name
Test status
Simulation time 47840288 ps
CPU time 0.68 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:22 PM PDT 24
Peak memory 203456 kb
Host smart-4eb50e85-1ddd-47ea-bb7e-2d86f934761e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231477577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
231477577
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4235287375
Short name T1033
Test name
Test status
Simulation time 57663895 ps
CPU time 1.25 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:23 PM PDT 24
Peak memory 215384 kb
Host smart-edd01b26-8e9e-4d52-9931-de61e7352199
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235287375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4235287375
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1841884379
Short name T1032
Test name
Test status
Simulation time 11996699 ps
CPU time 0.68 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 203388 kb
Host smart-b3891949-54fb-4756-bc6e-86d66ce678d5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841884379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1841884379
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2496311459
Short name T1002
Test name
Test status
Simulation time 81599166 ps
CPU time 2.71 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:27 PM PDT 24
Peak memory 215380 kb
Host smart-ff013d9a-57ed-470d-b218-04227a427990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496311459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2496311459
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.547133502
Short name T141
Test name
Test status
Simulation time 125539208 ps
CPU time 3.79 seconds
Started Mar 28 12:50:25 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 215464 kb
Host smart-cdffff4c-0f35-47d2-807f-5e4ea1330d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547133502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.547133502
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.910034165
Short name T996
Test name
Test status
Simulation time 1582937133 ps
CPU time 23.21 seconds
Started Mar 28 12:50:31 PM PDT 24
Finished Mar 28 12:50:54 PM PDT 24
Peak memory 207072 kb
Host smart-ecc05205-cd2f-4347-806e-eb8b415c75c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910034165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.910034165
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.861964259
Short name T1066
Test name
Test status
Simulation time 7550175291 ps
CPU time 35.62 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:51:04 PM PDT 24
Peak memory 207216 kb
Host smart-5ee066b8-89a4-4e28-bd89-cdbb053a46b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861964259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.861964259
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1064484568
Short name T73
Test name
Test status
Simulation time 42516816 ps
CPU time 1.34 seconds
Started Mar 28 12:50:27 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 216436 kb
Host smart-72d8655e-5f3f-4ad5-93c4-a2da288ff6da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064484568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1064484568
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2684349122
Short name T1017
Test name
Test status
Simulation time 421822427 ps
CPU time 2.88 seconds
Started Mar 28 12:50:29 PM PDT 24
Finished Mar 28 12:50:32 PM PDT 24
Peak memory 216360 kb
Host smart-8e408a32-49fc-477c-b3af-592147bc477a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684349122 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2684349122
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.210160990
Short name T1057
Test name
Test status
Simulation time 213781117 ps
CPU time 2.84 seconds
Started Mar 28 12:50:29 PM PDT 24
Finished Mar 28 12:50:32 PM PDT 24
Peak memory 207172 kb
Host smart-2d7a6cda-0db9-47b8-8bd1-1b37918e52fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210160990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.210160990
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.350123473
Short name T1067
Test name
Test status
Simulation time 12533449 ps
CPU time 0.71 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 203396 kb
Host smart-ac048e02-6734-4ba6-b8b1-1f6e0b994d5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350123473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.350123473
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2075461895
Short name T110
Test name
Test status
Simulation time 68579192 ps
CPU time 2.25 seconds
Started Mar 28 12:50:31 PM PDT 24
Finished Mar 28 12:50:33 PM PDT 24
Peak memory 215240 kb
Host smart-9b80e2a0-0734-4319-ab39-6aa47815ef78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075461895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2075461895
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1453518201
Short name T1107
Test name
Test status
Simulation time 127328570 ps
CPU time 0.66 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:27 PM PDT 24
Peak memory 203404 kb
Host smart-c211d750-e9c6-4d08-83e4-6926f89b1ad9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453518201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1453518201
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1476445132
Short name T1014
Test name
Test status
Simulation time 57712664 ps
CPU time 3.74 seconds
Started Mar 28 12:50:29 PM PDT 24
Finished Mar 28 12:50:33 PM PDT 24
Peak memory 215352 kb
Host smart-f153a27a-a1a9-4aa0-a7b0-f8b2e365f93e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476445132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1476445132
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.301531860
Short name T96
Test name
Test status
Simulation time 249739435 ps
CPU time 2.09 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 215420 kb
Host smart-578c3623-b639-4d04-92ed-af4b9163d695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301531860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.301531860
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1198514885
Short name T143
Test name
Test status
Simulation time 3648540338 ps
CPU time 20.11 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 215564 kb
Host smart-241dfd2d-7298-43ca-b8ba-55e74f311faf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198514885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1198514885
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1213639743
Short name T86
Test name
Test status
Simulation time 28194209 ps
CPU time 2.07 seconds
Started Mar 28 12:50:25 PM PDT 24
Finished Mar 28 12:50:27 PM PDT 24
Peak memory 215316 kb
Host smart-ddcf5f14-2a6e-4f10-ae69-98e4bc6c5ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213639743 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1213639743
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1411473787
Short name T108
Test name
Test status
Simulation time 121382340 ps
CPU time 2.86 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:26 PM PDT 24
Peak memory 215396 kb
Host smart-b90a6913-7fbf-42ec-a953-96fb8887b4ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411473787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1411473787
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.379195785
Short name T1006
Test name
Test status
Simulation time 17518348 ps
CPU time 0.77 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 203768 kb
Host smart-d26ee41d-6fed-48c1-abbb-dde01a778e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379195785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.379195785
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2415727821
Short name T986
Test name
Test status
Simulation time 187864531 ps
CPU time 2.9 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 215404 kb
Host smart-9ad70e1b-6e70-4be3-8f45-6704b802856e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415727821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2415727821
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2954564389
Short name T99
Test name
Test status
Simulation time 209011908 ps
CPU time 4.97 seconds
Started Mar 28 12:50:33 PM PDT 24
Finished Mar 28 12:50:38 PM PDT 24
Peak memory 215464 kb
Host smart-4f78a0f4-5aa6-4ab0-8495-5dc9fc18a9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954564389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2954564389
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1941081861
Short name T1082
Test name
Test status
Simulation time 1298606388 ps
CPU time 19.82 seconds
Started Mar 28 12:50:30 PM PDT 24
Finished Mar 28 12:50:50 PM PDT 24
Peak memory 215476 kb
Host smart-5afaab6a-ef44-4007-8708-8abcd86ca955
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941081861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1941081861
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3792942183
Short name T1055
Test name
Test status
Simulation time 650911869 ps
CPU time 3.98 seconds
Started Mar 28 12:50:36 PM PDT 24
Finished Mar 28 12:50:40 PM PDT 24
Peak memory 217584 kb
Host smart-5513b304-ab86-428f-9f45-844ff9700173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792942183 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3792942183
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2876831110
Short name T1054
Test name
Test status
Simulation time 73368247 ps
CPU time 2.14 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 207164 kb
Host smart-4ed8baa9-9c71-4144-ad58-3cecd0e4318e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876831110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2876831110
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.972599662
Short name T1018
Test name
Test status
Simulation time 46330963 ps
CPU time 0.75 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 203460 kb
Host smart-ee5a3aa4-f4a3-42d2-b5fa-85117a258ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972599662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.972599662
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3952545237
Short name T1065
Test name
Test status
Simulation time 62667128 ps
CPU time 1.68 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 215316 kb
Host smart-e74deaa2-d799-47a5-b9a8-d05f8a845c79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952545237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3952545237
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2699201420
Short name T1031
Test name
Test status
Simulation time 256843407 ps
CPU time 7.21 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 215428 kb
Host smart-2b223ee8-d852-465b-a390-71a66c490753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699201420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2699201420
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1911389422
Short name T89
Test name
Test status
Simulation time 266381270 ps
CPU time 3.69 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 216676 kb
Host smart-6a14d203-c25d-42b3-b373-f1c45b37b5a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911389422 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1911389422
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2977374900
Short name T115
Test name
Test status
Simulation time 35785074 ps
CPU time 1.31 seconds
Started Mar 28 12:50:36 PM PDT 24
Finished Mar 28 12:50:37 PM PDT 24
Peak memory 207136 kb
Host smart-2a9eb85e-22b0-4eec-a7ec-471072cd5398
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977374900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2977374900
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2866393364
Short name T993
Test name
Test status
Simulation time 123804211 ps
CPU time 0.7 seconds
Started Mar 28 12:50:40 PM PDT 24
Finished Mar 28 12:50:41 PM PDT 24
Peak memory 203452 kb
Host smart-e1ba8463-25d6-449f-930e-6faf6c48ea43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866393364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2866393364
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1852936107
Short name T1086
Test name
Test status
Simulation time 581108982 ps
CPU time 4.37 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 215424 kb
Host smart-d6d4aa73-ad61-4bc3-b178-a015205c2615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852936107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1852936107
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1845122674
Short name T92
Test name
Test status
Simulation time 1998297425 ps
CPU time 4.15 seconds
Started Mar 28 12:50:45 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 215636 kb
Host smart-397d4aba-104c-417e-a34d-ac4f847e1131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845122674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1845122674
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1942407676
Short name T1003
Test name
Test status
Simulation time 304614749 ps
CPU time 19.71 seconds
Started Mar 28 12:50:56 PM PDT 24
Finished Mar 28 12:51:16 PM PDT 24
Peak memory 215356 kb
Host smart-dbeb224c-bb33-4318-8394-443a45fa4bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942407676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1942407676
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4036449841
Short name T1103
Test name
Test status
Simulation time 397563971 ps
CPU time 1.98 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:46 PM PDT 24
Peak memory 215360 kb
Host smart-c6a3d3c4-92d7-471b-b7f1-b08572107cca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036449841 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4036449841
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1179728066
Short name T1023
Test name
Test status
Simulation time 148996257 ps
CPU time 1.23 seconds
Started Mar 28 12:50:48 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 207088 kb
Host smart-11a438a8-5da9-4b3b-9aad-f2400065556f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179728066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1179728066
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1972200245
Short name T1104
Test name
Test status
Simulation time 15229722 ps
CPU time 0.76 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 203360 kb
Host smart-8e2d1779-c18b-4bb2-9a12-77f31ae300da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972200245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1972200245
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3261028740
Short name T1036
Test name
Test status
Simulation time 61558911 ps
CPU time 3.65 seconds
Started Mar 28 12:50:36 PM PDT 24
Finished Mar 28 12:50:40 PM PDT 24
Peak memory 215412 kb
Host smart-7b829d59-75b2-4046-8d1e-00e779f4c668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261028740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3261028740
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3476958780
Short name T1029
Test name
Test status
Simulation time 29450170 ps
CPU time 2.18 seconds
Started Mar 28 12:50:40 PM PDT 24
Finished Mar 28 12:50:43 PM PDT 24
Peak memory 215492 kb
Host smart-ad129775-5c8b-4eac-9b80-2412d1e9ed62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476958780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3476958780
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3451117340
Short name T145
Test name
Test status
Simulation time 2681480973 ps
CPU time 15.87 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:59 PM PDT 24
Peak memory 217960 kb
Host smart-8bade295-f712-403e-8636-1b68fdf5f0ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451117340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3451117340
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2876955459
Short name T1009
Test name
Test status
Simulation time 56696545 ps
CPU time 3.79 seconds
Started Mar 28 12:50:36 PM PDT 24
Finished Mar 28 12:50:40 PM PDT 24
Peak memory 218080 kb
Host smart-cf67fa8b-5e9d-49c6-b8c5-1d1daeda6617
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876955459 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2876955459
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1570916578
Short name T113
Test name
Test status
Simulation time 105088224 ps
CPU time 2.49 seconds
Started Mar 28 12:50:42 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 207172 kb
Host smart-9692c9bb-b622-4288-999b-28617ceeeb03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570916578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1570916578
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1668691035
Short name T1079
Test name
Test status
Simulation time 60036241 ps
CPU time 0.74 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:44 PM PDT 24
Peak memory 203336 kb
Host smart-02033802-dedd-459d-8a9d-fd8cbabff73e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668691035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1668691035
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2101725960
Short name T1030
Test name
Test status
Simulation time 163190199 ps
CPU time 2.78 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:46 PM PDT 24
Peak memory 215264 kb
Host smart-69240619-c4ce-411a-bb41-1effc3b1c994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101725960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2101725960
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3556504184
Short name T1063
Test name
Test status
Simulation time 878272367 ps
CPU time 3.32 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 214176 kb
Host smart-47b156cf-cd3f-4410-b4a1-dbac47df91ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556504184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3556504184
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2817955107
Short name T1090
Test name
Test status
Simulation time 219039446 ps
CPU time 7.07 seconds
Started Mar 28 12:50:48 PM PDT 24
Finished Mar 28 12:50:55 PM PDT 24
Peak memory 216900 kb
Host smart-f460ee6f-d980-4772-a199-c3510b6673f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817955107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2817955107
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2444163061
Short name T102
Test name
Test status
Simulation time 52826071 ps
CPU time 1.84 seconds
Started Mar 28 12:50:45 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 215448 kb
Host smart-536ac5f3-7ea0-4753-a61c-841b186b4e4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444163061 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2444163061
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1689480663
Short name T1045
Test name
Test status
Simulation time 245989070 ps
CPU time 1.98 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 215340 kb
Host smart-bc116a50-9c94-4adf-aea1-a211e1fda8b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689480663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1689480663
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.832490058
Short name T1056
Test name
Test status
Simulation time 26991191 ps
CPU time 0.72 seconds
Started Mar 28 12:50:34 PM PDT 24
Finished Mar 28 12:50:35 PM PDT 24
Peak memory 203728 kb
Host smart-c6ad1d29-7bc7-426a-94af-710c82f8d872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832490058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.832490058
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2440698733
Short name T1089
Test name
Test status
Simulation time 983540153 ps
CPU time 3.16 seconds
Started Mar 28 12:50:40 PM PDT 24
Finished Mar 28 12:50:43 PM PDT 24
Peak memory 215580 kb
Host smart-220ce2b5-a0c8-4847-b07f-8aba4e18538f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440698733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2440698733
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1983943201
Short name T1074
Test name
Test status
Simulation time 592923478 ps
CPU time 14.23 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:58 PM PDT 24
Peak memory 215836 kb
Host smart-0f6b9a1c-2c89-4a53-8d77-0bf0cf08652b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983943201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1983943201
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3029920124
Short name T1013
Test name
Test status
Simulation time 185617120 ps
CPU time 1.7 seconds
Started Mar 28 12:50:47 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 216392 kb
Host smart-81910551-96e5-4146-adde-c7546efa4dd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029920124 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3029920124
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1621494505
Short name T1020
Test name
Test status
Simulation time 1436159292 ps
CPU time 2.15 seconds
Started Mar 28 12:50:47 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 207056 kb
Host smart-edd7338f-c923-4471-a72f-2cf9dfc622a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621494505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1621494505
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2178204228
Short name T1106
Test name
Test status
Simulation time 14047277 ps
CPU time 0.72 seconds
Started Mar 28 12:50:33 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 203464 kb
Host smart-5407b891-46ce-4d8d-9590-211576d3db7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178204228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2178204228
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3138330464
Short name T1095
Test name
Test status
Simulation time 86907923 ps
CPU time 1.63 seconds
Started Mar 28 12:50:37 PM PDT 24
Finished Mar 28 12:50:38 PM PDT 24
Peak memory 215432 kb
Host smart-597483af-a3a1-40fa-a8a1-3a5969551e6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138330464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3138330464
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2496096287
Short name T88
Test name
Test status
Simulation time 14424139026 ps
CPU time 17.58 seconds
Started Mar 28 12:50:47 PM PDT 24
Finished Mar 28 12:51:05 PM PDT 24
Peak memory 215492 kb
Host smart-e5598a07-d7f2-4a48-9727-f06caa7ec8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496096287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2496096287
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.142034196
Short name T1024
Test name
Test status
Simulation time 85683565 ps
CPU time 2.62 seconds
Started Mar 28 12:50:42 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 216960 kb
Host smart-787b9147-51dc-456f-bf04-c6bb42e7ace9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142034196 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.142034196
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.562469475
Short name T111
Test name
Test status
Simulation time 21776267 ps
CPU time 1.26 seconds
Started Mar 28 12:50:41 PM PDT 24
Finished Mar 28 12:50:43 PM PDT 24
Peak memory 207172 kb
Host smart-29d864e1-ba65-4271-84cb-9b1f8bd8f8a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562469475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.562469475
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4263244679
Short name T989
Test name
Test status
Simulation time 14894133 ps
CPU time 0.73 seconds
Started Mar 28 12:50:42 PM PDT 24
Finished Mar 28 12:50:43 PM PDT 24
Peak memory 203744 kb
Host smart-f053b3c7-c48b-463e-b4a0-11049dd07d1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263244679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4263244679
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1413600757
Short name T1039
Test name
Test status
Simulation time 27776451 ps
CPU time 1.69 seconds
Started Mar 28 12:50:42 PM PDT 24
Finished Mar 28 12:50:43 PM PDT 24
Peak memory 207192 kb
Host smart-874d5164-0f98-49f6-a170-51ec7403157a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413600757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1413600757
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3843585235
Short name T1088
Test name
Test status
Simulation time 421913040 ps
CPU time 2.69 seconds
Started Mar 28 12:50:39 PM PDT 24
Finished Mar 28 12:50:42 PM PDT 24
Peak memory 215556 kb
Host smart-34374e98-d823-42b8-a5e2-f8846e0a66d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843585235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3843585235
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2220623683
Short name T104
Test name
Test status
Simulation time 2013392974 ps
CPU time 14.41 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:58 PM PDT 24
Peak memory 215468 kb
Host smart-ad46a188-7430-4187-96c2-2cecad67eec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220623683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2220623683
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2772722284
Short name T90
Test name
Test status
Simulation time 61204622 ps
CPU time 1.88 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:46 PM PDT 24
Peak memory 215324 kb
Host smart-b1f02233-3874-46fa-81ec-4f61db3a58c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772722284 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2772722284
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3361439952
Short name T1076
Test name
Test status
Simulation time 55226593 ps
CPU time 1.22 seconds
Started Mar 28 12:50:45 PM PDT 24
Finished Mar 28 12:50:46 PM PDT 24
Peak memory 207140 kb
Host smart-b630e4d2-0735-4bb6-a87b-69d129cccbca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361439952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3361439952
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2558551598
Short name T1096
Test name
Test status
Simulation time 33335155 ps
CPU time 0.69 seconds
Started Mar 28 12:50:42 PM PDT 24
Finished Mar 28 12:50:43 PM PDT 24
Peak memory 203432 kb
Host smart-66cbc362-60ec-4449-89d0-bee67be81fdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558551598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2558551598
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.351880860
Short name T1025
Test name
Test status
Simulation time 280794810 ps
CPU time 2.87 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:46 PM PDT 24
Peak memory 215076 kb
Host smart-66a3bfef-1523-469f-9908-2546a832cfd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351880860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.351880860
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.395799087
Short name T1075
Test name
Test status
Simulation time 657576658 ps
CPU time 4.65 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:48 PM PDT 24
Peak memory 214040 kb
Host smart-46c60ec7-eb84-43a5-98a9-bab833365d39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395799087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.395799087
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1304610838
Short name T1077
Test name
Test status
Simulation time 683908586 ps
CPU time 15.9 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:59 PM PDT 24
Peak memory 215308 kb
Host smart-9b0e7e19-6071-449c-97f0-aa386cb71634
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304610838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1304610838
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3896333732
Short name T1016
Test name
Test status
Simulation time 154673694 ps
CPU time 2.71 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 216800 kb
Host smart-2561b202-c7a1-4aef-a779-0917f098571d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896333732 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3896333732
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3259990207
Short name T1049
Test name
Test status
Simulation time 49228330 ps
CPU time 1.25 seconds
Started Mar 28 12:50:40 PM PDT 24
Finished Mar 28 12:50:41 PM PDT 24
Peak memory 207188 kb
Host smart-573365a5-99bf-4c87-9758-2b6fe73b95f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259990207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3259990207
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2371705507
Short name T1008
Test name
Test status
Simulation time 51068047 ps
CPU time 0.76 seconds
Started Mar 28 12:50:45 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 203456 kb
Host smart-26ca0113-21cf-48f1-b96a-3c532e4cf067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371705507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2371705507
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2789885649
Short name T992
Test name
Test status
Simulation time 89741641 ps
CPU time 2.66 seconds
Started Mar 28 12:50:47 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 215260 kb
Host smart-19c0eb63-6ab4-4136-a8a7-1a800297f05e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789885649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2789885649
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3472446
Short name T1034
Test name
Test status
Simulation time 766546935 ps
CPU time 2.35 seconds
Started Mar 28 12:50:34 PM PDT 24
Finished Mar 28 12:50:36 PM PDT 24
Peak memory 215376 kb
Host smart-746328d9-3c89-4f85-9c52-75415f62e5e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.3472446
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.168189307
Short name T1094
Test name
Test status
Simulation time 602544190 ps
CPU time 7.53 seconds
Started Mar 28 12:50:43 PM PDT 24
Finished Mar 28 12:50:50 PM PDT 24
Peak memory 215488 kb
Host smart-c0d3d6d7-3847-4c43-bd0d-cd4b3152a5c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168189307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.168189307
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2343085597
Short name T1038
Test name
Test status
Simulation time 947273401 ps
CPU time 22.99 seconds
Started Mar 28 12:50:27 PM PDT 24
Finished Mar 28 12:50:50 PM PDT 24
Peak memory 207064 kb
Host smart-1fd0589c-d653-4ac6-bc79-6e3a4d5670c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343085597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2343085597
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4187537436
Short name T1078
Test name
Test status
Simulation time 1208369562 ps
CPU time 24.86 seconds
Started Mar 28 12:50:31 PM PDT 24
Finished Mar 28 12:50:56 PM PDT 24
Peak memory 207056 kb
Host smart-295ad1f1-e832-4007-a0ba-b2c05910bece
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187537436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4187537436
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1432024258
Short name T74
Test name
Test status
Simulation time 45209456 ps
CPU time 1.37 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 216476 kb
Host smart-463b553d-ff40-41cd-a6f0-70960f778510
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432024258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1432024258
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.188434641
Short name T1110
Test name
Test status
Simulation time 105760637 ps
CPU time 1.87 seconds
Started Mar 28 12:50:33 PM PDT 24
Finished Mar 28 12:50:35 PM PDT 24
Peak memory 215392 kb
Host smart-cd3fb46a-95d7-4228-8b1c-63a8818e48a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188434641 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.188434641
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.621316009
Short name T1098
Test name
Test status
Simulation time 27703457 ps
CPU time 1.83 seconds
Started Mar 28 12:50:33 PM PDT 24
Finished Mar 28 12:50:35 PM PDT 24
Peak memory 207052 kb
Host smart-0ee7d8aa-2112-48b9-88a2-4ed259b5acff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621316009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.621316009
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2462385274
Short name T1084
Test name
Test status
Simulation time 38272715 ps
CPU time 0.72 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 203480 kb
Host smart-7474d890-fa60-48a7-9d59-718a334830c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462385274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
462385274
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1810847501
Short name T105
Test name
Test status
Simulation time 170666617 ps
CPU time 1.91 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 215236 kb
Host smart-2ed8166c-fca0-44e5-a978-9357b8ebde09
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810847501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1810847501
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3425347095
Short name T999
Test name
Test status
Simulation time 12279518 ps
CPU time 0.7 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 203420 kb
Host smart-b98711ec-831b-4311-8bab-b8dece0af716
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425347095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3425347095
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2145149561
Short name T1011
Test name
Test status
Simulation time 117137881 ps
CPU time 1.97 seconds
Started Mar 28 12:50:31 PM PDT 24
Finished Mar 28 12:50:33 PM PDT 24
Peak memory 207220 kb
Host smart-7971b896-45ae-464b-97f3-32c925d013b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145149561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2145149561
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4234172539
Short name T84
Test name
Test status
Simulation time 117324933 ps
CPU time 3.74 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:32 PM PDT 24
Peak memory 216680 kb
Host smart-873b14ef-e58a-4ec7-a5a5-640dd118e3bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234172539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
234172539
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3669774805
Short name T987
Test name
Test status
Simulation time 14585727 ps
CPU time 0.7 seconds
Started Mar 28 12:50:53 PM PDT 24
Finished Mar 28 12:50:54 PM PDT 24
Peak memory 203776 kb
Host smart-baf74f6b-016a-4920-9a4e-4a5ee8add90d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669774805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3669774805
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3982377401
Short name T998
Test name
Test status
Simulation time 12775871 ps
CPU time 0.69 seconds
Started Mar 28 12:50:51 PM PDT 24
Finished Mar 28 12:50:52 PM PDT 24
Peak memory 203352 kb
Host smart-eccc4ab7-0e05-4216-be36-10553c518a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982377401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3982377401
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2403280769
Short name T1019
Test name
Test status
Simulation time 29914942 ps
CPU time 0.76 seconds
Started Mar 28 12:50:45 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 203480 kb
Host smart-70fea420-89b2-4b5b-81f4-a1abf9d7b2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403280769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2403280769
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.51842790
Short name T1087
Test name
Test status
Simulation time 41881090 ps
CPU time 0.78 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 203632 kb
Host smart-93b80581-ce45-416d-9f76-ca155abedfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51842790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.51842790
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2410983825
Short name T1061
Test name
Test status
Simulation time 37814432 ps
CPU time 0.77 seconds
Started Mar 28 12:50:48 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 203352 kb
Host smart-d3685dcf-22de-415e-838e-1a0523b00936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410983825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2410983825
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1149701304
Short name T1085
Test name
Test status
Simulation time 35348158 ps
CPU time 0.71 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:44 PM PDT 24
Peak memory 203344 kb
Host smart-182d5841-a76f-4298-afd8-d8a0aa59e3c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149701304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1149701304
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1686143006
Short name T1080
Test name
Test status
Simulation time 27709935 ps
CPU time 0.75 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 203328 kb
Host smart-e3215729-a078-4831-a74d-a05fba37323a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686143006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1686143006
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1738809164
Short name T983
Test name
Test status
Simulation time 11594562 ps
CPU time 0.71 seconds
Started Mar 28 12:50:47 PM PDT 24
Finished Mar 28 12:50:48 PM PDT 24
Peak memory 203680 kb
Host smart-85f4f28c-e546-43a0-a633-500d7bd4c229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738809164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1738809164
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1367699606
Short name T1093
Test name
Test status
Simulation time 46810165 ps
CPU time 0.79 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 203344 kb
Host smart-40df7f32-67b4-40a9-a37d-c893a88f0bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367699606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1367699606
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4245154085
Short name T1010
Test name
Test status
Simulation time 45423515 ps
CPU time 0.74 seconds
Started Mar 28 12:50:45 PM PDT 24
Finished Mar 28 12:50:46 PM PDT 24
Peak memory 203460 kb
Host smart-19973f97-6e6a-4615-b233-2b12f52716c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245154085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4245154085
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3659243965
Short name T112
Test name
Test status
Simulation time 935729023 ps
CPU time 24.4 seconds
Started Mar 28 12:50:30 PM PDT 24
Finished Mar 28 12:50:54 PM PDT 24
Peak memory 207184 kb
Host smart-1e6d3b98-24a4-4e2b-9a6d-509f0fb869e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659243965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3659243965
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1070688205
Short name T1064
Test name
Test status
Simulation time 647163633 ps
CPU time 35.09 seconds
Started Mar 28 12:50:31 PM PDT 24
Finished Mar 28 12:51:06 PM PDT 24
Peak memory 207224 kb
Host smart-7070f836-a320-4ac9-a215-c84659f95e7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070688205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1070688205
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4012749117
Short name T72
Test name
Test status
Simulation time 37884879 ps
CPU time 1.21 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:23 PM PDT 24
Peak memory 207076 kb
Host smart-6a1d18df-1200-4821-b02b-80d81a467ebb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012749117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4012749117
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.706878141
Short name T1112
Test name
Test status
Simulation time 200153590 ps
CPU time 3.92 seconds
Started Mar 28 12:50:25 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 217096 kb
Host smart-32fd068f-2367-4bdb-b6d3-603d3705a92f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706878141 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.706878141
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2085104098
Short name T1035
Test name
Test status
Simulation time 63680338 ps
CPU time 1.69 seconds
Started Mar 28 12:50:31 PM PDT 24
Finished Mar 28 12:50:33 PM PDT 24
Peak memory 215396 kb
Host smart-d7d0b589-c711-4193-9053-ec794c7b3204
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085104098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
085104098
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4138206571
Short name T1050
Test name
Test status
Simulation time 15957302 ps
CPU time 0.75 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 203480 kb
Host smart-6fe06e13-321a-4bad-a4cf-234e3a9fbba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138206571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
138206571
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3414189434
Short name T1051
Test name
Test status
Simulation time 33313528 ps
CPU time 1.31 seconds
Started Mar 28 12:50:30 PM PDT 24
Finished Mar 28 12:50:32 PM PDT 24
Peak memory 215388 kb
Host smart-7ee6a0f4-e574-41b7-ac9d-9c9309ef9ece
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414189434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3414189434
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2253522156
Short name T1015
Test name
Test status
Simulation time 10931171 ps
CPU time 0.67 seconds
Started Mar 28 12:50:30 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 203380 kb
Host smart-d4ab5f5b-8d6e-46fa-bcdf-9419292d9290
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253522156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2253522156
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2553819953
Short name T1007
Test name
Test status
Simulation time 1051776612 ps
CPU time 3.47 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 215468 kb
Host smart-3c60b161-8e92-487a-bec2-c110e5dbd968
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553819953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2553819953
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.666634581
Short name T94
Test name
Test status
Simulation time 515622698 ps
CPU time 3.39 seconds
Started Mar 28 12:50:27 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 216596 kb
Host smart-324be871-7257-4d8d-bde7-c12f6a4e7a02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666634581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.666634581
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1450097340
Short name T984
Test name
Test status
Simulation time 17880160 ps
CPU time 0.7 seconds
Started Mar 28 12:50:48 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 203456 kb
Host smart-9b69cf69-7048-4a87-8d03-0b58a013009e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450097340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1450097340
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4154501677
Short name T1069
Test name
Test status
Simulation time 23275450 ps
CPU time 0.71 seconds
Started Mar 28 12:50:47 PM PDT 24
Finished Mar 28 12:50:48 PM PDT 24
Peak memory 203368 kb
Host smart-f8e757b5-50de-4590-86a7-853ba448cccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154501677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4154501677
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2593011820
Short name T1081
Test name
Test status
Simulation time 16975337 ps
CPU time 0.75 seconds
Started Mar 28 12:50:46 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 203632 kb
Host smart-4c0ae044-9cc5-4c84-9570-86f1b3132c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593011820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2593011820
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2041713993
Short name T1058
Test name
Test status
Simulation time 51560502 ps
CPU time 0.77 seconds
Started Mar 28 12:50:45 PM PDT 24
Finished Mar 28 12:50:46 PM PDT 24
Peak memory 203648 kb
Host smart-64fa3fda-328e-472c-9dea-5214103e86f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041713993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2041713993
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2823743111
Short name T1105
Test name
Test status
Simulation time 13386483 ps
CPU time 0.75 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 203300 kb
Host smart-8d7cd953-5c88-4ae7-ad58-0b7e3f5f5874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823743111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2823743111
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3228966269
Short name T1044
Test name
Test status
Simulation time 12873603 ps
CPU time 0.81 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 203284 kb
Host smart-3c19ff3e-bb9f-437b-84b5-4740851f9acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228966269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3228966269
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3249240851
Short name T985
Test name
Test status
Simulation time 12645756 ps
CPU time 0.68 seconds
Started Mar 28 12:50:49 PM PDT 24
Finished Mar 28 12:50:50 PM PDT 24
Peak memory 203744 kb
Host smart-99637110-84e9-4bf2-8e0d-505ef3113fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249240851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3249240851
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.746622509
Short name T1022
Test name
Test status
Simulation time 11169541 ps
CPU time 0.68 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 203252 kb
Host smart-ad203d7d-ccd4-4d96-bc21-1060b3d04277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746622509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.746622509
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3782219489
Short name T1097
Test name
Test status
Simulation time 56519385 ps
CPU time 0.75 seconds
Started Mar 28 12:50:47 PM PDT 24
Finished Mar 28 12:50:48 PM PDT 24
Peak memory 203300 kb
Host smart-a29ae775-7214-4d17-bc60-c79412a50e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782219489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3782219489
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1292041285
Short name T1042
Test name
Test status
Simulation time 13342550 ps
CPU time 0.74 seconds
Started Mar 28 12:50:49 PM PDT 24
Finished Mar 28 12:50:50 PM PDT 24
Peak memory 203748 kb
Host smart-958e63c7-d4ca-47ea-ba1e-4290d761a71f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292041285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1292041285
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2900049009
Short name T126
Test name
Test status
Simulation time 711152469 ps
CPU time 15.29 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:36 PM PDT 24
Peak memory 215356 kb
Host smart-0cfdd47d-ab7d-4716-8bff-6aba15b3fc0a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900049009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2900049009
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.622417262
Short name T109
Test name
Test status
Simulation time 13902235440 ps
CPU time 27.97 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:51 PM PDT 24
Peak memory 207220 kb
Host smart-3d00372e-b071-4e0c-9d73-99dfc45461d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622417262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.622417262
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2815294090
Short name T1108
Test name
Test status
Simulation time 158209429 ps
CPU time 0.93 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 206600 kb
Host smart-36f97a79-9b75-4411-8ff9-4704cf3e72dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815294090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2815294090
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.293094920
Short name T1083
Test name
Test status
Simulation time 334162431 ps
CPU time 3.73 seconds
Started Mar 28 12:50:25 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 217192 kb
Host smart-44002551-634e-4f96-b896-982df842f2d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293094920 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.293094920
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3078844634
Short name T1091
Test name
Test status
Simulation time 52499701 ps
CPU time 1.74 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 215292 kb
Host smart-127db4ec-e71e-4cf7-a475-7d73f73770fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078844634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
078844634
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1597040898
Short name T1000
Test name
Test status
Simulation time 13665840 ps
CPU time 0.79 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:24 PM PDT 24
Peak memory 203432 kb
Host smart-dc5a2c62-e153-43ca-a7cb-dc0efbbe7a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597040898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
597040898
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1823441370
Short name T1060
Test name
Test status
Simulation time 151445179 ps
CPU time 1.69 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:26 PM PDT 24
Peak memory 215320 kb
Host smart-1cfda23d-d10b-4c86-8dbe-5bc5c80ef110
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823441370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1823441370
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.374714419
Short name T1021
Test name
Test status
Simulation time 29422254 ps
CPU time 0.69 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 203716 kb
Host smart-6f7b9720-ff29-4df5-b612-2aa18216eafe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374714419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.374714419
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.807921587
Short name T991
Test name
Test status
Simulation time 95177740 ps
CPU time 1.78 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 215408 kb
Host smart-523aa7f3-620c-4b76-ac83-0bdf9cf08580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807921587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.807921587
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1627552527
Short name T1101
Test name
Test status
Simulation time 238079003 ps
CPU time 2.31 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 215548 kb
Host smart-be8dbfe4-7530-448d-adce-8b68363da9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627552527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
627552527
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4258760740
Short name T87
Test name
Test status
Simulation time 5511338419 ps
CPU time 7.9 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:32 PM PDT 24
Peak memory 215428 kb
Host smart-0657da55-568a-40da-bf2f-d96de55c11cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258760740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4258760740
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4258249396
Short name T988
Test name
Test status
Simulation time 14072707 ps
CPU time 0.68 seconds
Started Mar 28 12:50:44 PM PDT 24
Finished Mar 28 12:50:44 PM PDT 24
Peak memory 203280 kb
Host smart-fde9c87f-005e-4a29-a5b4-c3062078330e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258249396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4258249396
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3603931317
Short name T1046
Test name
Test status
Simulation time 41645456 ps
CPU time 0.67 seconds
Started Mar 28 12:50:56 PM PDT 24
Finished Mar 28 12:50:57 PM PDT 24
Peak memory 203432 kb
Host smart-83096e0d-e593-4d4a-a9dc-83c43c9cb5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603931317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3603931317
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3728775152
Short name T994
Test name
Test status
Simulation time 15521570 ps
CPU time 0.73 seconds
Started Mar 28 12:50:52 PM PDT 24
Finished Mar 28 12:50:53 PM PDT 24
Peak memory 203424 kb
Host smart-ae11165e-3336-4623-b0a0-0b2729660f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728775152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3728775152
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3483041957
Short name T1001
Test name
Test status
Simulation time 53894808 ps
CPU time 0.71 seconds
Started Mar 28 12:50:51 PM PDT 24
Finished Mar 28 12:50:52 PM PDT 24
Peak memory 203612 kb
Host smart-bee48418-07df-41a2-872e-927e06d9ae82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483041957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3483041957
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1666174512
Short name T1047
Test name
Test status
Simulation time 11584634 ps
CPU time 0.76 seconds
Started Mar 28 12:50:49 PM PDT 24
Finished Mar 28 12:50:50 PM PDT 24
Peak memory 203456 kb
Host smart-a20ad882-8cb4-4e68-9980-2c0b1563a91b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666174512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1666174512
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1927761611
Short name T1028
Test name
Test status
Simulation time 16485594 ps
CPU time 0.72 seconds
Started Mar 28 12:50:47 PM PDT 24
Finished Mar 28 12:50:48 PM PDT 24
Peak memory 203448 kb
Host smart-963f2576-d917-41c3-a78c-0b252ee78c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927761611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1927761611
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1088836384
Short name T990
Test name
Test status
Simulation time 15312811 ps
CPU time 0.75 seconds
Started Mar 28 12:50:49 PM PDT 24
Finished Mar 28 12:50:50 PM PDT 24
Peak memory 203448 kb
Host smart-1953d4bc-f734-45ee-8440-904b6da23648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088836384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1088836384
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2537633966
Short name T1102
Test name
Test status
Simulation time 14436787 ps
CPU time 0.76 seconds
Started Mar 28 12:50:57 PM PDT 24
Finished Mar 28 12:50:58 PM PDT 24
Peak memory 203436 kb
Host smart-b99275a2-340a-4df9-9784-5010fc2cf525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537633966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2537633966
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3514447993
Short name T1062
Test name
Test status
Simulation time 43717209 ps
CPU time 0.7 seconds
Started Mar 28 12:50:56 PM PDT 24
Finished Mar 28 12:50:57 PM PDT 24
Peak memory 203432 kb
Host smart-40d95504-c9ee-4a70-a174-346af87ea371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514447993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3514447993
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1144426442
Short name T1040
Test name
Test status
Simulation time 13416832 ps
CPU time 0.71 seconds
Started Mar 28 12:50:48 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 203440 kb
Host smart-d01e60e1-e386-453c-a8f8-bfa0f2983421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144426442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1144426442
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.787317013
Short name T1059
Test name
Test status
Simulation time 88667145 ps
CPU time 1.84 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 215428 kb
Host smart-5cb3b3b0-3ec6-4579-bb20-e7eeba200f55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787317013 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.787317013
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1111387168
Short name T1041
Test name
Test status
Simulation time 134231133 ps
CPU time 1.9 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 207168 kb
Host smart-a9dc03c7-d163-47c6-b9c3-9a2202810f9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111387168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
111387168
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2794594238
Short name T1012
Test name
Test status
Simulation time 12509766 ps
CPU time 0.76 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:24 PM PDT 24
Peak memory 203464 kb
Host smart-925fab87-5a54-4185-97b3-c75d9d04d09c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794594238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
794594238
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3980548997
Short name T1092
Test name
Test status
Simulation time 422295309 ps
CPU time 4.26 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:33 PM PDT 24
Peak memory 215408 kb
Host smart-41dc1388-e4a8-41c7-a3e5-0752258c5bdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980548997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3980548997
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3403009398
Short name T1048
Test name
Test status
Simulation time 100749628 ps
CPU time 1.6 seconds
Started Mar 28 12:50:25 PM PDT 24
Finished Mar 28 12:50:27 PM PDT 24
Peak memory 215472 kb
Host smart-95814981-0306-4ef4-aed2-f58afaf3adaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403009398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
403009398
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1406568578
Short name T101
Test name
Test status
Simulation time 646356776 ps
CPU time 14.24 seconds
Started Mar 28 12:50:25 PM PDT 24
Finished Mar 28 12:50:41 PM PDT 24
Peak memory 215800 kb
Host smart-be2ab790-b3cb-42fd-b43e-97ad999c5ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406568578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1406568578
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3402893236
Short name T85
Test name
Test status
Simulation time 186953579 ps
CPU time 1.73 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 215524 kb
Host smart-45ad6e50-6695-4a01-8419-e7ecfc4cac14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402893236 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3402893236
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.801185414
Short name T107
Test name
Test status
Simulation time 324892645 ps
CPU time 2.17 seconds
Started Mar 28 12:50:29 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 215396 kb
Host smart-f0abd469-2822-4019-abee-fe02ce28c41c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801185414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.801185414
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2860210197
Short name T1005
Test name
Test status
Simulation time 34221255 ps
CPU time 0.75 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:27 PM PDT 24
Peak memory 203456 kb
Host smart-6b94c7d4-25e2-4047-ab65-d73f40df893f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860210197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
860210197
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.550611971
Short name T1109
Test name
Test status
Simulation time 43281484 ps
CPU time 2.77 seconds
Started Mar 28 12:50:34 PM PDT 24
Finished Mar 28 12:50:37 PM PDT 24
Peak memory 215356 kb
Host smart-6ee14ecb-88ff-404d-8f21-f0bc4305b5d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550611971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.550611971
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2369571142
Short name T93
Test name
Test status
Simulation time 497409448 ps
CPU time 3.6 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 215540 kb
Host smart-4b593ae3-6023-48a3-b0b9-a2d00c1045c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369571142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
369571142
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1605917054
Short name T144
Test name
Test status
Simulation time 4188693188 ps
CPU time 21.54 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:48 PM PDT 24
Peak memory 215924 kb
Host smart-5c87eee0-640b-42d6-b185-fb668efdb031
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605917054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1605917054
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.164534143
Short name T1073
Test name
Test status
Simulation time 261403175 ps
CPU time 3.63 seconds
Started Mar 28 12:50:31 PM PDT 24
Finished Mar 28 12:50:35 PM PDT 24
Peak memory 216456 kb
Host smart-25adedec-5f88-4ce3-8f93-7b174adfe825
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164534143 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.164534143
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2037824685
Short name T1068
Test name
Test status
Simulation time 140011816 ps
CPU time 2.32 seconds
Started Mar 28 12:50:31 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 215436 kb
Host smart-d47a837a-0803-434b-bffe-d8fb0b2a1d05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037824685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
037824685
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4138186684
Short name T995
Test name
Test status
Simulation time 34358318 ps
CPU time 0.73 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:27 PM PDT 24
Peak memory 203772 kb
Host smart-7beaed39-cb39-4776-bd7e-0d8fe202ef5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138186684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
138186684
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1831406975
Short name T1113
Test name
Test status
Simulation time 464984407 ps
CPU time 2.9 seconds
Started Mar 28 12:50:27 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 215268 kb
Host smart-fe9070a1-a9e7-428a-8a8b-b8c601292293
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831406975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1831406975
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1705096932
Short name T97
Test name
Test status
Simulation time 99877625 ps
CPU time 3.41 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 215508 kb
Host smart-ed2aa4a6-12b4-4d45-a10b-b3e8d025609b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705096932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
705096932
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.954858062
Short name T1072
Test name
Test status
Simulation time 573712059 ps
CPU time 14.85 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:43 PM PDT 24
Peak memory 215576 kb
Host smart-6c9da104-d985-4186-b21a-f93a22eaa39d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954858062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.954858062
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.316319777
Short name T1027
Test name
Test status
Simulation time 189021677 ps
CPU time 1.72 seconds
Started Mar 28 12:50:33 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 215332 kb
Host smart-ed126a96-ded1-4d19-b3c3-00799d33c52f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316319777 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.316319777
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3351776749
Short name T1111
Test name
Test status
Simulation time 839352115 ps
CPU time 2.02 seconds
Started Mar 28 12:50:27 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 207016 kb
Host smart-904ad470-cb6e-4019-8491-9dc0237d2934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351776749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
351776749
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1073448019
Short name T1043
Test name
Test status
Simulation time 14929989 ps
CPU time 0.76 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 203804 kb
Host smart-9e197bfc-3693-48c5-b888-04063e3d9bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073448019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
073448019
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4021456630
Short name T1052
Test name
Test status
Simulation time 3392302188 ps
CPU time 4.32 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 215408 kb
Host smart-bb7f9ff1-5b3d-4364-88dc-2b4f2019469d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021456630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4021456630
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1790591949
Short name T95
Test name
Test status
Simulation time 126544645 ps
CPU time 2.38 seconds
Started Mar 28 12:50:31 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 215428 kb
Host smart-96b61474-ab2a-43c6-82ab-b157dd4b33ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790591949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
790591949
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3771498467
Short name T103
Test name
Test status
Simulation time 666017379 ps
CPU time 14.63 seconds
Started Mar 28 12:50:27 PM PDT 24
Finished Mar 28 12:50:42 PM PDT 24
Peak memory 215480 kb
Host smart-ee2c6688-8d56-478f-8893-3653dc016553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771498467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3771498467
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2550541385
Short name T100
Test name
Test status
Simulation time 439670297 ps
CPU time 2.93 seconds
Started Mar 28 12:50:33 PM PDT 24
Finished Mar 28 12:50:36 PM PDT 24
Peak memory 216372 kb
Host smart-433729ae-1b26-4748-bda8-4cfb2d4185c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550541385 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2550541385
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1722897463
Short name T1037
Test name
Test status
Simulation time 37601741 ps
CPU time 1.14 seconds
Started Mar 28 12:50:30 PM PDT 24
Finished Mar 28 12:50:32 PM PDT 24
Peak memory 207136 kb
Host smart-67ff4e17-11c0-4e83-ad8c-9d7440819a6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722897463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
722897463
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1773508019
Short name T1070
Test name
Test status
Simulation time 15634390 ps
CPU time 0.75 seconds
Started Mar 28 12:50:33 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 203364 kb
Host smart-f4749f0a-6402-4630-b026-0eded12eceb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773508019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
773508019
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2811520827
Short name T1004
Test name
Test status
Simulation time 63113431 ps
CPU time 1.84 seconds
Started Mar 28 12:50:19 PM PDT 24
Finished Mar 28 12:50:22 PM PDT 24
Peak memory 215464 kb
Host smart-52227228-6f65-48b9-8119-f229487d639e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811520827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2811520827
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2955313795
Short name T1071
Test name
Test status
Simulation time 93195302 ps
CPU time 1.88 seconds
Started Mar 28 12:50:33 PM PDT 24
Finished Mar 28 12:50:35 PM PDT 24
Peak memory 215432 kb
Host smart-8a6d85be-548f-48de-9e8e-5ab133b29e14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955313795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
955313795
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2750712979
Short name T1053
Test name
Test status
Simulation time 290750613 ps
CPU time 18.74 seconds
Started Mar 28 12:50:31 PM PDT 24
Finished Mar 28 12:50:50 PM PDT 24
Peak memory 215340 kb
Host smart-ee2d7913-4b6b-409a-a47b-0d10be3e6e81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750712979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2750712979
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2155107235
Short name T941
Test name
Test status
Simulation time 29372176 ps
CPU time 0.7 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:50 PM PDT 24
Peak memory 205080 kb
Host smart-0a092fe6-7105-478b-97eb-9fae72f0a99b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155107235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
155107235
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3192101617
Short name T323
Test name
Test status
Simulation time 501621976 ps
CPU time 3.95 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 218760 kb
Host smart-ca695dea-a859-434b-b146-666889ebb422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192101617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3192101617
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2487813427
Short name T45
Test name
Test status
Simulation time 47839536 ps
CPU time 0.76 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:49 PM PDT 24
Peak memory 205188 kb
Host smart-81a2b560-d94a-4818-a829-bd5c9e404289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487813427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2487813427
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1838351301
Short name T31
Test name
Test status
Simulation time 30710486891 ps
CPU time 70.16 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:37:01 PM PDT 24
Peak memory 249028 kb
Host smart-b0690ee6-f864-4338-bf29-777eb0b14b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838351301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1838351301
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3686031287
Short name T554
Test name
Test status
Simulation time 23127771941 ps
CPU time 55.98 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:36:47 PM PDT 24
Peak memory 252320 kb
Host smart-b9a90990-0fcb-4d6e-956f-24f1547c8f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686031287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3686031287
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2071864145
Short name T1
Test name
Test status
Simulation time 101504275237 ps
CPU time 93.56 seconds
Started Mar 28 01:35:51 PM PDT 24
Finished Mar 28 01:37:25 PM PDT 24
Peak memory 252948 kb
Host smart-951cef65-6015-4da2-9cd1-00203fcfb23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071864145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2071864145
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2463222412
Short name T704
Test name
Test status
Simulation time 91848340286 ps
CPU time 67.27 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:36:57 PM PDT 24
Peak memory 249968 kb
Host smart-aef8e962-4ff0-4825-82d0-935f6ccb45f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463222412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2463222412
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.539268719
Short name T830
Test name
Test status
Simulation time 7058468879 ps
CPU time 6.69 seconds
Started Mar 28 01:35:53 PM PDT 24
Finished Mar 28 01:36:00 PM PDT 24
Peak memory 224448 kb
Host smart-16f12530-9408-4466-9288-72d2c2e01147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539268719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.539268719
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3628369053
Short name T613
Test name
Test status
Simulation time 55659591 ps
CPU time 2.43 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 232624 kb
Host smart-da9e7c5a-ce19-414a-8803-7a014ca44b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628369053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3628369053
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.4149530509
Short name T741
Test name
Test status
Simulation time 50901984 ps
CPU time 0.99 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:48 PM PDT 24
Peak memory 216520 kb
Host smart-be00c1e2-cd92-419d-a40b-0ac133bfed4d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149530509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.4149530509
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.692850390
Short name T899
Test name
Test status
Simulation time 726922049 ps
CPU time 11.04 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:36:01 PM PDT 24
Peak memory 240780 kb
Host smart-0623cfb9-32b1-4572-bfc2-0107f1e2cd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692850390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
692850390
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2892976865
Short name T654
Test name
Test status
Simulation time 8583117290 ps
CPU time 13.4 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:36:01 PM PDT 24
Peak memory 224136 kb
Host smart-3e3d0d3e-e4d1-4d68-931c-ecf6efe6719d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892976865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2892976865
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.605410370
Short name T563
Test name
Test status
Simulation time 3516217603 ps
CPU time 5.79 seconds
Started Mar 28 01:35:51 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 222264 kb
Host smart-cc6ada69-d651-4435-8fb8-8e90d3fc66e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=605410370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.605410370
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3979381276
Short name T62
Test name
Test status
Simulation time 62121788 ps
CPU time 1.06 seconds
Started Mar 28 01:35:51 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 235368 kb
Host smart-b07e64f4-815a-4b5b-a626-51e0eb1d5297
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979381276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3979381276
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4096107448
Short name T129
Test name
Test status
Simulation time 210529454 ps
CPU time 1.1 seconds
Started Mar 28 01:35:51 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 206660 kb
Host smart-943c10e4-dbee-4c04-a89a-a1893b9e1918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096107448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4096107448
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2925501146
Short name T527
Test name
Test status
Simulation time 27877764370 ps
CPU time 30.39 seconds
Started Mar 28 01:35:53 PM PDT 24
Finished Mar 28 01:36:23 PM PDT 24
Peak memory 216208 kb
Host smart-7125b82c-62ea-4dee-aff3-7822d43ed655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925501146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2925501146
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.39533495
Short name T316
Test name
Test status
Simulation time 18858365546 ps
CPU time 21.56 seconds
Started Mar 28 01:35:53 PM PDT 24
Finished Mar 28 01:36:14 PM PDT 24
Peak memory 216228 kb
Host smart-cbbd3b86-09fc-435e-90ca-6c811e642b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39533495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.39533495
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.999031863
Short name T17
Test name
Test status
Simulation time 223447159 ps
CPU time 0.79 seconds
Started Mar 28 01:35:53 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 205540 kb
Host smart-a6d1574a-3545-4a6d-b76b-f90d6e4328e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999031863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.999031863
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2004670687
Short name T285
Test name
Test status
Simulation time 97119317 ps
CPU time 1.07 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:51 PM PDT 24
Peak memory 206556 kb
Host smart-4fabec8f-2128-42f6-88e0-1a1e6f3af9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004670687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2004670687
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.662373036
Short name T811
Test name
Test status
Simulation time 17954827 ps
CPU time 0.75 seconds
Started Mar 28 01:36:00 PM PDT 24
Finished Mar 28 01:36:01 PM PDT 24
Peak memory 204544 kb
Host smart-9192732d-fdf2-4f27-9558-d39b0dc55daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662373036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.662373036
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2847169156
Short name T873
Test name
Test status
Simulation time 537300995 ps
CPU time 2.86 seconds
Started Mar 28 01:36:05 PM PDT 24
Finished Mar 28 01:36:08 PM PDT 24
Peak memory 218276 kb
Host smart-362a5144-33b5-4fde-bfff-ab7412cd35a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847169156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2847169156
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1505952546
Short name T867
Test name
Test status
Simulation time 16902827 ps
CPU time 0.79 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 205196 kb
Host smart-e93e87a3-a108-4e7d-86f9-de185b39aa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505952546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1505952546
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.593896125
Short name T980
Test name
Test status
Simulation time 1044680997 ps
CPU time 14.2 seconds
Started Mar 28 01:35:59 PM PDT 24
Finished Mar 28 01:36:13 PM PDT 24
Peak memory 236260 kb
Host smart-834f4cc1-f70f-42e7-a0d9-bd34422382bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593896125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.593896125
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.582224721
Short name T349
Test name
Test status
Simulation time 4864727079 ps
CPU time 15.95 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:25 PM PDT 24
Peak memory 234136 kb
Host smart-16f4c187-005d-4355-b1b0-eea4ad83c91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582224721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.582224721
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1257775031
Short name T573
Test name
Test status
Simulation time 10454975819 ps
CPU time 19.42 seconds
Started Mar 28 01:36:00 PM PDT 24
Finished Mar 28 01:36:19 PM PDT 24
Peak memory 240864 kb
Host smart-2739f131-8e85-4e08-8f08-96e35b5d3177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257775031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1257775031
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2332139313
Short name T880
Test name
Test status
Simulation time 1195523335 ps
CPU time 4.14 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 218196 kb
Host smart-6c8abc38-9706-4ece-a863-dad37255f54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332139313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2332139313
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2143149591
Short name T372
Test name
Test status
Simulation time 1405870830 ps
CPU time 4.6 seconds
Started Mar 28 01:35:51 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 224396 kb
Host smart-49cfdfa9-8e88-43b0-bcea-3f40e0eeb66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143149591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2143149591
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.3726406750
Short name T456
Test name
Test status
Simulation time 39803334 ps
CPU time 0.75 seconds
Started Mar 28 01:35:51 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 216148 kb
Host smart-dc3f7283-1fa2-4777-9bb9-f406be1a7add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726406750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.3726406750
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3556893555
Short name T300
Test name
Test status
Simulation time 692154162 ps
CPU time 3.63 seconds
Started Mar 28 01:36:02 PM PDT 24
Finished Mar 28 01:36:06 PM PDT 24
Peak memory 222004 kb
Host smart-ffecfce3-7b01-466a-b3ad-ddd513c3e329
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3556893555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3556893555
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.250395390
Short name T60
Test name
Test status
Simulation time 62581810 ps
CPU time 1.06 seconds
Started Mar 28 01:36:04 PM PDT 24
Finished Mar 28 01:36:05 PM PDT 24
Peak memory 235336 kb
Host smart-b6d4d894-1cc5-489e-9d8b-9aa164d6182b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250395390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.250395390
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.275922255
Short name T195
Test name
Test status
Simulation time 36619846847 ps
CPU time 319.29 seconds
Started Mar 28 01:36:07 PM PDT 24
Finished Mar 28 01:41:26 PM PDT 24
Peak memory 286948 kb
Host smart-3752c48c-5cc4-4d89-9ba6-16944010ff34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275922255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.275922255
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.671481436
Short name T660
Test name
Test status
Simulation time 33117316404 ps
CPU time 17.82 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 216312 kb
Host smart-4ce1e106-10ea-4fdb-bc42-aa137be5253f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671481436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.671481436
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1479287766
Short name T275
Test name
Test status
Simulation time 2283555568 ps
CPU time 2.98 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:51 PM PDT 24
Peak memory 216052 kb
Host smart-5341852b-4b52-43b7-a55c-25cd7d54edc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479287766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1479287766
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1937538721
Short name T363
Test name
Test status
Simulation time 120459166 ps
CPU time 0.93 seconds
Started Mar 28 01:35:51 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 206948 kb
Host smart-6deb9c00-a772-4a26-b988-418c9da98301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937538721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1937538721
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.53061135
Short name T930
Test name
Test status
Simulation time 153989720 ps
CPU time 1.1 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:51 PM PDT 24
Peak memory 205524 kb
Host smart-bc6891f3-fab6-4bf2-921b-367d0d5c255a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53061135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.53061135
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.717271319
Short name T625
Test name
Test status
Simulation time 17197173573 ps
CPU time 5.61 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:36:06 PM PDT 24
Peak memory 232684 kb
Host smart-eb950bac-84c5-430d-8110-da006c8b38cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717271319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.717271319
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4087738956
Short name T402
Test name
Test status
Simulation time 19747443 ps
CPU time 0.73 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:36:36 PM PDT 24
Peak memory 205144 kb
Host smart-1bf578a0-f8ea-40ef-819f-a7b7d7f11ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087738956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4087738956
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.348975598
Short name T214
Test name
Test status
Simulation time 199153788 ps
CPU time 3.21 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:38 PM PDT 24
Peak memory 219488 kb
Host smart-156071cd-29e6-4fa5-bc3a-a11b4c495ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348975598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.348975598
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2429648129
Short name T378
Test name
Test status
Simulation time 59178861 ps
CPU time 0.79 seconds
Started Mar 28 01:36:33 PM PDT 24
Finished Mar 28 01:36:35 PM PDT 24
Peak memory 205064 kb
Host smart-24053086-0471-4bcf-a6d1-1e4c1358eb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429648129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2429648129
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4048663373
Short name T66
Test name
Test status
Simulation time 5603921715 ps
CPU time 98.9 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:38:18 PM PDT 24
Peak memory 252652 kb
Host smart-f0eb4d29-d68a-42ca-a9ee-3228f231bf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048663373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4048663373
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3826071537
Short name T866
Test name
Test status
Simulation time 41743127456 ps
CPU time 70.02 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:37:47 PM PDT 24
Peak memory 231716 kb
Host smart-3408bd5c-3888-4e1a-945d-afa0f77b3117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826071537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3826071537
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2450228742
Short name T403
Test name
Test status
Simulation time 518184031 ps
CPU time 18.92 seconds
Started Mar 28 01:36:41 PM PDT 24
Finished Mar 28 01:37:00 PM PDT 24
Peak memory 232624 kb
Host smart-a31020d3-0289-447b-a302-8cc63420d2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450228742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2450228742
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3419608712
Short name T453
Test name
Test status
Simulation time 179371653 ps
CPU time 3.14 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:40 PM PDT 24
Peak memory 218160 kb
Host smart-60073626-2a73-40b0-8c05-baab586907aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419608712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3419608712
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2029900443
Short name T166
Test name
Test status
Simulation time 20641764509 ps
CPU time 27.09 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:37:02 PM PDT 24
Peak memory 231228 kb
Host smart-d86cb3a0-78f8-4eb2-9601-cab76c6d6cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029900443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2029900443
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2989633091
Short name T575
Test name
Test status
Simulation time 17573630 ps
CPU time 1.08 seconds
Started Mar 28 01:36:33 PM PDT 24
Finished Mar 28 01:36:35 PM PDT 24
Peak memory 216364 kb
Host smart-5230dea0-d0ec-4f29-9cb7-a11e8a49e78c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989633091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2989633091
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1086696651
Short name T781
Test name
Test status
Simulation time 2117611913 ps
CPU time 7.56 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:36:45 PM PDT 24
Peak memory 224460 kb
Host smart-d1b034a7-26b2-4a54-9a42-048396dffa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086696651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1086696651
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2250298130
Short name T440
Test name
Test status
Simulation time 50363241165 ps
CPU time 36.18 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:37:13 PM PDT 24
Peak memory 233408 kb
Host smart-a4f06315-680d-4cba-8949-5d7738d716a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250298130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2250298130
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.566582426
Short name T57
Test name
Test status
Simulation time 18513246 ps
CPU time 0.74 seconds
Started Mar 28 01:36:31 PM PDT 24
Finished Mar 28 01:36:32 PM PDT 24
Peak memory 216088 kb
Host smart-58be85ef-aa48-4f28-b245-2faa3a606345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566582426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.566582426
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1233501249
Short name T471
Test name
Test status
Simulation time 351425142 ps
CPU time 3.91 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:36:41 PM PDT 24
Peak memory 218696 kb
Host smart-78e7c61c-8558-4188-bf85-a0c447898a5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1233501249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1233501249
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2681859248
Short name T131
Test name
Test status
Simulation time 82009410 ps
CPU time 0.94 seconds
Started Mar 28 01:36:33 PM PDT 24
Finished Mar 28 01:36:34 PM PDT 24
Peak memory 205204 kb
Host smart-b689b644-6f7b-46b2-b637-82d0818ef612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681859248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2681859248
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1061338075
Short name T362
Test name
Test status
Simulation time 4885714312 ps
CPU time 12.57 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:49 PM PDT 24
Peak memory 216164 kb
Host smart-ae3b7f1b-d3f5-48c8-a1fb-a1fc36318173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061338075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1061338075
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3464068431
Short name T294
Test name
Test status
Simulation time 41106756825 ps
CPU time 33.53 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:37:13 PM PDT 24
Peak memory 216192 kb
Host smart-fc4e0201-01da-4b2e-a456-d365c5382f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464068431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3464068431
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2509978038
Short name T436
Test name
Test status
Simulation time 344247531 ps
CPU time 6.87 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:42 PM PDT 24
Peak memory 216128 kb
Host smart-d4981a02-838d-4fdf-9b75-246d86ec40da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509978038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2509978038
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.106380939
Short name T597
Test name
Test status
Simulation time 162536447 ps
CPU time 0.91 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:36 PM PDT 24
Peak memory 206556 kb
Host smart-8caf43f8-890d-4505-a22e-df02a1fe787e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106380939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.106380939
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2047484043
Short name T979
Test name
Test status
Simulation time 5524801242 ps
CPU time 3.83 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:36:41 PM PDT 24
Peak memory 217676 kb
Host smart-2e4f07ca-29b3-4659-b540-285e7407875a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047484043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2047484043
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1200824296
Short name T572
Test name
Test status
Simulation time 14537431 ps
CPU time 0.79 seconds
Started Mar 28 01:36:38 PM PDT 24
Finished Mar 28 01:36:40 PM PDT 24
Peak memory 205144 kb
Host smart-df82890a-56bb-48a8-8009-722e7d07f83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200824296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1200824296
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3228747153
Short name T782
Test name
Test status
Simulation time 64352776 ps
CPU time 2.7 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:37 PM PDT 24
Peak memory 233296 kb
Host smart-3c396959-2049-4352-b5d3-0edf6b098f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228747153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3228747153
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1375401899
Short name T772
Test name
Test status
Simulation time 14031703 ps
CPU time 0.79 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:36 PM PDT 24
Peak memory 206212 kb
Host smart-0c3b54c1-7ab4-4a99-a9c9-b3d110209b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375401899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1375401899
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3709727774
Short name T416
Test name
Test status
Simulation time 2372104345 ps
CPU time 33.21 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:37:13 PM PDT 24
Peak memory 240868 kb
Host smart-d2da8e86-8540-472f-a670-0cbff56a37fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709727774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3709727774
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1875845400
Short name T136
Test name
Test status
Simulation time 27763183339 ps
CPU time 49.59 seconds
Started Mar 28 01:36:33 PM PDT 24
Finished Mar 28 01:37:23 PM PDT 24
Peak memory 232732 kb
Host smart-fc9af729-336c-4d54-a59c-6e54abac7d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875845400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1875845400
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.19165273
Short name T407
Test name
Test status
Simulation time 21913364837 ps
CPU time 155.81 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:39:12 PM PDT 24
Peak memory 255012 kb
Host smart-07a994b4-5736-412b-a9cd-bb52c9201682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19165273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.19165273
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1969384283
Short name T663
Test name
Test status
Simulation time 2356882409 ps
CPU time 11.71 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:48 PM PDT 24
Peak memory 239784 kb
Host smart-f044f4ac-8b6d-41c2-b94d-2c662cf6fbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969384283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1969384283
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3406774461
Short name T562
Test name
Test status
Simulation time 85205982 ps
CPU time 2.66 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:39 PM PDT 24
Peak memory 224436 kb
Host smart-25ef5415-c4d4-4f1d-81f9-270fb27a383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406774461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3406774461
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3934598203
Short name T161
Test name
Test status
Simulation time 18725471742 ps
CPU time 23.6 seconds
Started Mar 28 01:36:40 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 232588 kb
Host smart-8470d9ac-f667-4e44-be76-7816318ce64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934598203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3934598203
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3944184415
Short name T748
Test name
Test status
Simulation time 31448157 ps
CPU time 1.13 seconds
Started Mar 28 01:36:41 PM PDT 24
Finished Mar 28 01:36:42 PM PDT 24
Peak memory 217712 kb
Host smart-39e5529e-ed98-4a3f-a244-5b844fc6b643
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944184415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3944184415
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.896890671
Short name T356
Test name
Test status
Simulation time 3304251064 ps
CPU time 15.12 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:52 PM PDT 24
Peak memory 240816 kb
Host smart-ae6e835d-7fa4-4448-aaff-1846d8328177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896890671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.896890671
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3692294810
Short name T974
Test name
Test status
Simulation time 22131256473 ps
CPU time 21.5 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:36:58 PM PDT 24
Peak memory 220416 kb
Host smart-97f2bf94-814b-414a-b356-b5403ad46dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692294810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3692294810
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.1717795843
Short name T716
Test name
Test status
Simulation time 14637174 ps
CPU time 0.82 seconds
Started Mar 28 01:36:30 PM PDT 24
Finished Mar 28 01:36:31 PM PDT 24
Peak memory 216104 kb
Host smart-a6d0ae0b-abdf-42a6-ad3d-862cf3d07c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717795843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.1717795843
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3957809491
Short name T635
Test name
Test status
Simulation time 4187998351 ps
CPU time 5.38 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:40 PM PDT 24
Peak memory 220720 kb
Host smart-278eee14-2930-4aac-8daa-251806e47490
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3957809491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3957809491
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1412379744
Short name T462
Test name
Test status
Simulation time 341075998 ps
CPU time 1.06 seconds
Started Mar 28 01:36:38 PM PDT 24
Finished Mar 28 01:36:39 PM PDT 24
Peak memory 206384 kb
Host smart-8312ade1-055a-410e-a097-a2b1eacd3e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412379744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1412379744
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2220997924
Short name T617
Test name
Test status
Simulation time 3798681575 ps
CPU time 20.84 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:36:58 PM PDT 24
Peak memory 216284 kb
Host smart-eb40051b-9a04-4553-9ce1-491fdc1b2f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220997924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2220997924
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1595300523
Short name T931
Test name
Test status
Simulation time 4020771512 ps
CPU time 16.35 seconds
Started Mar 28 01:36:32 PM PDT 24
Finished Mar 28 01:36:49 PM PDT 24
Peak memory 216280 kb
Host smart-2228eccf-5661-40ba-b73d-c6d52e6606ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595300523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1595300523
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4018797457
Short name T608
Test name
Test status
Simulation time 566128538 ps
CPU time 10.34 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:36:46 PM PDT 24
Peak memory 216200 kb
Host smart-2ad41c94-d991-483d-806e-bba993584697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018797457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4018797457
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3795503859
Short name T576
Test name
Test status
Simulation time 39653796 ps
CPU time 0.75 seconds
Started Mar 28 01:36:33 PM PDT 24
Finished Mar 28 01:36:34 PM PDT 24
Peak memory 205508 kb
Host smart-5e13dbce-905a-4438-8ca5-2fd73a0c4816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795503859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3795503859
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3445644758
Short name T698
Test name
Test status
Simulation time 1943742977 ps
CPU time 11.31 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:36:48 PM PDT 24
Peak memory 231712 kb
Host smart-1cf9c225-e554-44f7-a607-4c737a516bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445644758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3445644758
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3999292518
Short name T736
Test name
Test status
Simulation time 33507679 ps
CPU time 0.7 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:36:37 PM PDT 24
Peak memory 205184 kb
Host smart-d9b5e844-cd67-4c08-967e-058e74dcf544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999292518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3999292518
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.297388802
Short name T333
Test name
Test status
Simulation time 8070709051 ps
CPU time 6.33 seconds
Started Mar 28 01:36:31 PM PDT 24
Finished Mar 28 01:36:37 PM PDT 24
Peak memory 234056 kb
Host smart-61fca948-2744-4e65-9290-83557037dc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297388802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.297388802
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3122622909
Short name T446
Test name
Test status
Simulation time 18806293 ps
CPU time 0.84 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:37 PM PDT 24
Peak memory 206252 kb
Host smart-b3173cf5-32a6-4fdd-82e9-777574e43524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122622909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3122622909
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2813684984
Short name T611
Test name
Test status
Simulation time 15277111349 ps
CPU time 21.04 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:36:56 PM PDT 24
Peak memory 232692 kb
Host smart-5b77c924-bb42-4175-b3b0-3e9346b33519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813684984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2813684984
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2869812647
Short name T26
Test name
Test status
Simulation time 83702438845 ps
CPU time 149.07 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:39:05 PM PDT 24
Peak memory 251092 kb
Host smart-a995706a-ec5f-4b69-888b-9a08b992377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869812647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2869812647
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.806831481
Short name T892
Test name
Test status
Simulation time 79657052472 ps
CPU time 303.37 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:41:38 PM PDT 24
Peak memory 251848 kb
Host smart-950c0ccc-f9c2-451a-b245-ee4ce186155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806831481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.806831481
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2884069963
Short name T448
Test name
Test status
Simulation time 268832016 ps
CPU time 4.27 seconds
Started Mar 28 01:36:41 PM PDT 24
Finished Mar 28 01:36:45 PM PDT 24
Peak memory 218752 kb
Host smart-a45ef3ed-e9a2-4951-83de-0c783b1068cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884069963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2884069963
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4063769983
Short name T497
Test name
Test status
Simulation time 15592655049 ps
CPU time 21.09 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:37:02 PM PDT 24
Peak memory 228592 kb
Host smart-4ef16746-0c8d-4757-9bdf-20109ad930ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063769983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4063769983
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.856046975
Short name T306
Test name
Test status
Simulation time 362606731 ps
CPU time 1.04 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:36:36 PM PDT 24
Peak memory 216496 kb
Host smart-94d832e4-d977-4aee-b0f2-2b440f150f11
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856046975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.856046975
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.623887709
Short name T775
Test name
Test status
Simulation time 597402771 ps
CPU time 7.19 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:36:44 PM PDT 24
Peak memory 218448 kb
Host smart-3c4fc2a6-87bc-41ec-b2db-a3a2c0e1be36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623887709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.623887709
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3521574361
Short name T360
Test name
Test status
Simulation time 64093383094 ps
CPU time 27.99 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 240228 kb
Host smart-fe9debfc-1b81-4eb8-a62b-c68c27ff092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521574361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3521574361
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.774577806
Short name T48
Test name
Test status
Simulation time 27145098 ps
CPU time 0.74 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:35 PM PDT 24
Peak memory 215896 kb
Host smart-8e28967e-a42f-4afc-9567-1a88296b3e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774577806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.774577806
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4007197469
Short name T967
Test name
Test status
Simulation time 218690859 ps
CPU time 4.38 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:39 PM PDT 24
Peak memory 222096 kb
Host smart-723c077e-4109-4c08-9223-45303297a366
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4007197469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4007197469
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1100300002
Short name T56
Test name
Test status
Simulation time 527205564 ps
CPU time 1.06 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:36:36 PM PDT 24
Peak memory 206452 kb
Host smart-1444e4d9-d2ae-45ad-a347-989c0a095e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100300002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1100300002
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1254750076
Short name T878
Test name
Test status
Simulation time 7802137133 ps
CPU time 35.57 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:37:10 PM PDT 24
Peak memory 216280 kb
Host smart-e691dc35-8667-4105-a6aa-33a66546b4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254750076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1254750076
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2139508436
Short name T345
Test name
Test status
Simulation time 2249212499 ps
CPU time 7.04 seconds
Started Mar 28 01:36:41 PM PDT 24
Finished Mar 28 01:36:48 PM PDT 24
Peak memory 216040 kb
Host smart-620abcd6-9723-4aab-9bdd-aba1dd05c1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139508436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2139508436
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3988838842
Short name T975
Test name
Test status
Simulation time 63925408 ps
CPU time 1.84 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:36:37 PM PDT 24
Peak memory 216132 kb
Host smart-53e923e7-f459-4860-8da9-47fd48cf2a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988838842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3988838842
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1479350076
Short name T282
Test name
Test status
Simulation time 18683424 ps
CPU time 0.74 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:35 PM PDT 24
Peak memory 205504 kb
Host smart-f84f0c9f-c399-41e4-a7b0-b1d4d6c5613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479350076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1479350076
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.662887906
Short name T203
Test name
Test status
Simulation time 2111341193 ps
CPU time 4.01 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:39 PM PDT 24
Peak memory 224420 kb
Host smart-77dfdbb8-e581-4a86-8dd9-b9500cf37ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662887906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.662887906
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1210578924
Short name T305
Test name
Test status
Simulation time 18555214 ps
CPU time 0.73 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:36:40 PM PDT 24
Peak memory 205140 kb
Host smart-8875f9c2-b596-439f-9522-2d95a00bd529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210578924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1210578924
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2825019146
Short name T463
Test name
Test status
Simulation time 2021202476 ps
CPU time 4.81 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:36:45 PM PDT 24
Peak memory 233456 kb
Host smart-ebea687f-37c2-4dc5-ac94-ce12a8df86e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825019146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2825019146
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4278136734
Short name T566
Test name
Test status
Simulation time 25437606 ps
CPU time 0.76 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:36:38 PM PDT 24
Peak memory 206556 kb
Host smart-5024fb20-2607-4ac4-a98e-c0a0b7672fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278136734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4278136734
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.242957135
Short name T589
Test name
Test status
Simulation time 63721935074 ps
CPU time 102.91 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 249040 kb
Host smart-e58fdf19-5db9-4ad8-a1fd-72050c26e486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242957135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.242957135
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1274418374
Short name T695
Test name
Test status
Simulation time 8432478342 ps
CPU time 45.88 seconds
Started Mar 28 01:36:33 PM PDT 24
Finished Mar 28 01:37:19 PM PDT 24
Peak memory 251868 kb
Host smart-812e1934-7d8c-48db-9066-fc7d94ed038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274418374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1274418374
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2831235347
Short name T181
Test name
Test status
Simulation time 25023804799 ps
CPU time 164.88 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:39:26 PM PDT 24
Peak memory 257020 kb
Host smart-8230cee6-185c-4755-b11a-9af95a73d65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831235347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2831235347
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.699518099
Short name T545
Test name
Test status
Simulation time 12152487118 ps
CPU time 37.98 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:37:15 PM PDT 24
Peak memory 240688 kb
Host smart-88902351-c07f-4fdf-a1bf-cebaccc94cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699518099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.699518099
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.697893219
Short name T761
Test name
Test status
Simulation time 818984578 ps
CPU time 5.83 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:36:43 PM PDT 24
Peak memory 233584 kb
Host smart-28d41472-03c0-4f0d-81a9-1207cc1f6563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697893219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.697893219
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3907879650
Short name T676
Test name
Test status
Simulation time 4585218812 ps
CPU time 16.22 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:36:57 PM PDT 24
Peak memory 218324 kb
Host smart-641210a8-220d-4010-8a8e-8f0bc44219b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907879650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3907879650
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1159721608
Short name T580
Test name
Test status
Simulation time 81854509 ps
CPU time 1.08 seconds
Started Mar 28 01:36:34 PM PDT 24
Finished Mar 28 01:36:36 PM PDT 24
Peak memory 216528 kb
Host smart-8e1709bb-5dbf-4eeb-9d13-dd54f020c17d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159721608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1159721608
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2918197793
Short name T725
Test name
Test status
Simulation time 3895539879 ps
CPU time 3.97 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:41 PM PDT 24
Peak memory 232888 kb
Host smart-d457dd14-0ca3-4544-8ee7-e2fc435d77d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918197793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2918197793
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1732959406
Short name T818
Test name
Test status
Simulation time 654401445 ps
CPU time 5.84 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:36:47 PM PDT 24
Peak memory 224404 kb
Host smart-fa7732f4-82cf-48f1-b45d-bf3c52026403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732959406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1732959406
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.2841775232
Short name T606
Test name
Test status
Simulation time 44813479 ps
CPU time 0.74 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:36:40 PM PDT 24
Peak memory 216080 kb
Host smart-017b0970-1cb7-4232-867f-9c6cb42e3d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841775232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2841775232
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2665633443
Short name T515
Test name
Test status
Simulation time 4519103207 ps
CPU time 5.55 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:36:46 PM PDT 24
Peak memory 222676 kb
Host smart-087e687a-494d-47b7-a5cd-c66fd3c88293
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2665633443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2665633443
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2088161206
Short name T784
Test name
Test status
Simulation time 1410219039 ps
CPU time 4.45 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:41 PM PDT 24
Peak memory 215824 kb
Host smart-2006cc6c-a81c-4725-8c79-1e73564a2e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088161206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2088161206
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.492036607
Short name T417
Test name
Test status
Simulation time 21082875129 ps
CPU time 29.06 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 216248 kb
Host smart-19c062ae-98da-43ce-be40-11ae714a19d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492036607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.492036607
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3994431536
Short name T435
Test name
Test status
Simulation time 782070269 ps
CPU time 5.28 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:42 PM PDT 24
Peak memory 216216 kb
Host smart-1d337c5e-0cfe-4a25-93d2-715444d825f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994431536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3994431536
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1764900735
Short name T309
Test name
Test status
Simulation time 363291820 ps
CPU time 0.79 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:36:37 PM PDT 24
Peak memory 205512 kb
Host smart-f2ad5a88-2789-49fd-b3d1-c30ac3949c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764900735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1764900735
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2590803368
Short name T423
Test name
Test status
Simulation time 1248258031 ps
CPU time 9.57 seconds
Started Mar 28 01:36:37 PM PDT 24
Finished Mar 28 01:36:47 PM PDT 24
Peak memory 239848 kb
Host smart-5de6197f-5f9f-4f15-b9d8-99e6b15ce351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590803368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2590803368
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4189943940
Short name T842
Test name
Test status
Simulation time 11149684 ps
CPU time 0.71 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:36:54 PM PDT 24
Peak memory 205104 kb
Host smart-09aa910d-6261-4e3f-8d67-8afd65e69ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189943940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4189943940
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1923058701
Short name T409
Test name
Test status
Simulation time 788691422 ps
CPU time 4.22 seconds
Started Mar 28 01:36:51 PM PDT 24
Finished Mar 28 01:36:57 PM PDT 24
Peak memory 233576 kb
Host smart-551dfb04-b108-497c-a393-cfae33b8b888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923058701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1923058701
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1318800396
Short name T335
Test name
Test status
Simulation time 19570244 ps
CPU time 0.74 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:36:40 PM PDT 24
Peak memory 205228 kb
Host smart-2277b66c-6950-4654-97bb-e69332b0c802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318800396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1318800396
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3045293501
Short name T973
Test name
Test status
Simulation time 3569338951 ps
CPU time 29.13 seconds
Started Mar 28 01:36:50 PM PDT 24
Finished Mar 28 01:37:19 PM PDT 24
Peak memory 234472 kb
Host smart-1931f854-6e07-4207-94ba-0cefa35b566c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045293501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3045293501
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3465800840
Short name T116
Test name
Test status
Simulation time 106054862674 ps
CPU time 103.28 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:38:39 PM PDT 24
Peak memory 256480 kb
Host smart-f9cb0f18-c268-4c20-b5ee-12e4e6934549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465800840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3465800840
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3582995548
Short name T241
Test name
Test status
Simulation time 27389806301 ps
CPU time 105.25 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:38:42 PM PDT 24
Peak memory 240660 kb
Host smart-2acbf2d5-59a5-480b-b54b-558dd23110d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582995548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3582995548
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3573651181
Short name T288
Test name
Test status
Simulation time 11919476257 ps
CPU time 18.53 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:37:12 PM PDT 24
Peak memory 246472 kb
Host smart-594b61a7-faf9-485a-8201-2f926d6fc882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573651181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3573651181
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3686069432
Short name T603
Test name
Test status
Simulation time 1057408714 ps
CPU time 4.83 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:36:59 PM PDT 24
Peak memory 218572 kb
Host smart-fec82065-e040-4f79-ac16-4de356ca03a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686069432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3686069432
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3586142436
Short name T962
Test name
Test status
Simulation time 904080355 ps
CPU time 6.87 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:37:01 PM PDT 24
Peak memory 235096 kb
Host smart-858e3b6d-cdce-40a7-b1af-c24cc8b1b40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586142436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3586142436
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1949984929
Short name T21
Test name
Test status
Simulation time 169798364 ps
CPU time 1.05 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:38 PM PDT 24
Peak memory 216420 kb
Host smart-ab0ba824-9963-462a-baf4-f8a1d12035f6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949984929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1949984929
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3657038065
Short name T343
Test name
Test status
Simulation time 4517164771 ps
CPU time 17.09 seconds
Started Mar 28 01:36:54 PM PDT 24
Finished Mar 28 01:37:11 PM PDT 24
Peak memory 233352 kb
Host smart-736f4f62-1028-4e92-a60e-96a55279aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657038065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3657038065
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1369670823
Short name T831
Test name
Test status
Simulation time 905250242 ps
CPU time 4.07 seconds
Started Mar 28 01:36:59 PM PDT 24
Finished Mar 28 01:37:03 PM PDT 24
Peak memory 233708 kb
Host smart-995a3f65-b3c8-4e50-b1d5-036cac05f6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369670823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1369670823
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1627960394
Short name T473
Test name
Test status
Simulation time 45214406 ps
CPU time 0.72 seconds
Started Mar 28 01:36:36 PM PDT 24
Finished Mar 28 01:36:37 PM PDT 24
Peak memory 216008 kb
Host smart-af620e95-ccbc-4d14-a14a-10067a0a3110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627960394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1627960394
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1424386906
Short name T34
Test name
Test status
Simulation time 523369633 ps
CPU time 3.55 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:01 PM PDT 24
Peak memory 218588 kb
Host smart-e96d807f-fed5-427d-83c4-50db955f97d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1424386906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1424386906
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2531538138
Short name T132
Test name
Test status
Simulation time 54353867862 ps
CPU time 119.48 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:38:57 PM PDT 24
Peak memory 249076 kb
Host smart-4f926a69-23ac-4923-a8b4-8b4ef6047da5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531538138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2531538138
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3450929397
Short name T259
Test name
Test status
Simulation time 1785210681 ps
CPU time 27.36 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:37:08 PM PDT 24
Peak memory 216156 kb
Host smart-54a2733b-d6cf-4722-8875-5c6f0222887d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450929397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3450929397
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2474358099
Short name T860
Test name
Test status
Simulation time 6008144100 ps
CPU time 21.76 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:37:02 PM PDT 24
Peak memory 216132 kb
Host smart-dfde4b85-0684-4ad9-9c94-0915b90ae527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474358099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2474358099
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2101344969
Short name T421
Test name
Test status
Simulation time 168942825 ps
CPU time 2.83 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:36:57 PM PDT 24
Peak memory 216200 kb
Host smart-f04f9aa6-7406-43ec-a8e7-a6a67f073319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101344969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2101344969
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2410266974
Short name T728
Test name
Test status
Simulation time 124195050 ps
CPU time 0.79 seconds
Started Mar 28 01:36:39 PM PDT 24
Finished Mar 28 01:36:42 PM PDT 24
Peak memory 205488 kb
Host smart-27c33399-bf19-4d58-b400-8cefa2631c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410266974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2410266974
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2101384387
Short name T838
Test name
Test status
Simulation time 9102145042 ps
CPU time 26.73 seconds
Started Mar 28 01:36:51 PM PDT 24
Finished Mar 28 01:37:19 PM PDT 24
Peak memory 223804 kb
Host smart-3fa5b5dd-5e78-404c-ba0a-7934f1d96bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101384387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2101384387
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.401077377
Short name T859
Test name
Test status
Simulation time 15848891 ps
CPU time 0.74 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 205136 kb
Host smart-ba3ba357-894f-4716-8be2-857737ed5b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401077377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.401077377
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4038985196
Short name T953
Test name
Test status
Simulation time 3626296595 ps
CPU time 5.02 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 220336 kb
Host smart-d5c65b03-bfa6-4b71-a1f4-bf1c9582d13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038985196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4038985196
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2203533106
Short name T344
Test name
Test status
Simulation time 41516344 ps
CPU time 0.77 seconds
Started Mar 28 01:36:54 PM PDT 24
Finished Mar 28 01:36:55 PM PDT 24
Peak memory 206248 kb
Host smart-9a667bd3-3d92-48d5-ae27-fc511e4380c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203533106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2203533106
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1300155668
Short name T732
Test name
Test status
Simulation time 1451194712 ps
CPU time 24.98 seconds
Started Mar 28 01:37:04 PM PDT 24
Finished Mar 28 01:37:29 PM PDT 24
Peak memory 253064 kb
Host smart-882afcfe-9e46-404c-95c8-a59264ac2d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300155668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1300155668
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1949987959
Short name T302
Test name
Test status
Simulation time 7344256666 ps
CPU time 55.19 seconds
Started Mar 28 01:36:59 PM PDT 24
Finished Mar 28 01:37:55 PM PDT 24
Peak memory 251676 kb
Host smart-a53c8af4-a6c2-40a9-9bf1-e0f6a5813a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949987959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1949987959
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2535878228
Short name T41
Test name
Test status
Simulation time 5268136678 ps
CPU time 126.78 seconds
Started Mar 28 01:36:59 PM PDT 24
Finished Mar 28 01:39:06 PM PDT 24
Peak memory 254752 kb
Host smart-5cb06cd8-aeb4-4e21-8d98-e44c15b77e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535878228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2535878228
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.243858210
Short name T701
Test name
Test status
Simulation time 12155744462 ps
CPU time 23.54 seconds
Started Mar 28 01:36:58 PM PDT 24
Finished Mar 28 01:37:22 PM PDT 24
Peak memory 240824 kb
Host smart-00b6a5be-0e73-498e-ad27-b0c2410b6ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243858210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.243858210
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.190839998
Short name T738
Test name
Test status
Simulation time 460790177 ps
CPU time 2.36 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:00 PM PDT 24
Peak memory 224332 kb
Host smart-2e9f1336-1d4a-4397-9ce5-23659d347a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190839998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.190839998
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3606698451
Short name T634
Test name
Test status
Simulation time 7732391995 ps
CPU time 8.1 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 219400 kb
Host smart-0a7425c7-5d40-48ec-a467-3796eb77bd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606698451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3606698451
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3788134727
Short name T777
Test name
Test status
Simulation time 164542428 ps
CPU time 1.08 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:36:58 PM PDT 24
Peak memory 217724 kb
Host smart-89e1c9af-40f9-4062-81b3-75095ce5b9e0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788134727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3788134727
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.727568946
Short name T601
Test name
Test status
Simulation time 8853481271 ps
CPU time 10.97 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:37:07 PM PDT 24
Peak memory 233636 kb
Host smart-41ea007a-6b85-428e-9afb-6bee8a0d0921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727568946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.727568946
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2331203778
Short name T205
Test name
Test status
Simulation time 6449941846 ps
CPU time 22.77 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:21 PM PDT 24
Peak memory 227644 kb
Host smart-d6c0fc6f-45c8-4821-9cb4-04a36ad18c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331203778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2331203778
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.623045362
Short name T341
Test name
Test status
Simulation time 26507868 ps
CPU time 0.73 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:36:54 PM PDT 24
Peak memory 215792 kb
Host smart-12c9a63a-de25-447e-a970-257a9f7327b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623045362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.623045362
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2519111614
Short name T507
Test name
Test status
Simulation time 1145095367 ps
CPU time 6.01 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:09 PM PDT 24
Peak memory 222656 kb
Host smart-d4431cd0-e702-492b-80b3-f8b6a63e6326
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2519111614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2519111614
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2335051233
Short name T938
Test name
Test status
Simulation time 37072033509 ps
CPU time 125.94 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:39:09 PM PDT 24
Peak memory 265548 kb
Host smart-55e181af-ac4f-4c2d-ac8b-c540df09589d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335051233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2335051233
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.918358997
Short name T720
Test name
Test status
Simulation time 6449112096 ps
CPU time 37.61 seconds
Started Mar 28 01:36:52 PM PDT 24
Finished Mar 28 01:37:31 PM PDT 24
Peak memory 216228 kb
Host smart-2ff1a1fe-f403-4a41-b2c3-4246c73672a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918358997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.918358997
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.734093641
Short name T906
Test name
Test status
Simulation time 7335575291 ps
CPU time 6.01 seconds
Started Mar 28 01:36:51 PM PDT 24
Finished Mar 28 01:36:59 PM PDT 24
Peak memory 216272 kb
Host smart-4943453b-3470-4425-8c3a-1c075c980d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734093641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.734093641
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4122535175
Short name T954
Test name
Test status
Simulation time 419229640 ps
CPU time 2.5 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:36:56 PM PDT 24
Peak memory 216212 kb
Host smart-01c666e7-251b-4624-9770-2476f5f06475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122535175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4122535175
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3665598613
Short name T947
Test name
Test status
Simulation time 201294451 ps
CPU time 1.08 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:36:57 PM PDT 24
Peak memory 205580 kb
Host smart-b03bd41a-be9b-4923-8a7d-60ec84f49ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665598613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3665598613
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.83131463
Short name T223
Test name
Test status
Simulation time 1538440493 ps
CPU time 9.73 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:08 PM PDT 24
Peak memory 246512 kb
Host smart-d6dd13a8-8fc3-4e6d-9ca3-aedaf0e8b938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83131463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.83131463
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4201279569
Short name T645
Test name
Test status
Simulation time 250944242 ps
CPU time 2.68 seconds
Started Mar 28 01:37:01 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 218500 kb
Host smart-1e2e1b49-3582-4c23-aaa8-436f9d035ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201279569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4201279569
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2667622523
Short name T327
Test name
Test status
Simulation time 65354965 ps
CPU time 0.8 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 206552 kb
Host smart-a9d761bc-338b-4b72-9833-25de2a75e777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667622523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2667622523
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.838852634
Short name T925
Test name
Test status
Simulation time 40040779429 ps
CPU time 208.43 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:40:32 PM PDT 24
Peak memory 257240 kb
Host smart-45d5b244-260c-4e0f-90aa-11e373f59878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838852634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.838852634
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4092039982
Short name T443
Test name
Test status
Simulation time 13249686837 ps
CPU time 77.03 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 250512 kb
Host smart-98d05cc8-c45a-4ece-ae79-769c7bd7bd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092039982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4092039982
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.181172499
Short name T682
Test name
Test status
Simulation time 10726543882 ps
CPU time 21.5 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:37:18 PM PDT 24
Peak memory 235796 kb
Host smart-cbf72515-3390-4dc4-9d8f-12c09a567756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181172499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.181172499
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.632898999
Short name T449
Test name
Test status
Simulation time 859030666 ps
CPU time 12.51 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:13 PM PDT 24
Peak memory 222428 kb
Host smart-5b43b6d2-a580-44b2-8d61-3183771f9ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632898999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.632898999
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3766155550
Short name T183
Test name
Test status
Simulation time 810525112 ps
CPU time 5.82 seconds
Started Mar 28 01:37:05 PM PDT 24
Finished Mar 28 01:37:11 PM PDT 24
Peak memory 233476 kb
Host smart-46014865-8e5f-4581-badb-57015b2ad796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766155550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3766155550
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3743721436
Short name T50
Test name
Test status
Simulation time 10440953050 ps
CPU time 26.28 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:30 PM PDT 24
Peak memory 232492 kb
Host smart-e0c5a6d6-5fca-4842-8553-ed5c4fc43214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743721436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3743721436
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2802071639
Short name T924
Test name
Test status
Simulation time 47442205 ps
CPU time 1.12 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 216512 kb
Host smart-bb6e92dc-6180-4793-a960-2becfccd9871
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802071639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2802071639
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1679480116
Short name T932
Test name
Test status
Simulation time 2655239691 ps
CPU time 8.69 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:09 PM PDT 24
Peak memory 232772 kb
Host smart-d4564256-9f77-452b-89ad-771efdc1cf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679480116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1679480116
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.161371088
Short name T919
Test name
Test status
Simulation time 71488576 ps
CPU time 2.96 seconds
Started Mar 28 01:37:06 PM PDT 24
Finished Mar 28 01:37:09 PM PDT 24
Peak memory 233480 kb
Host smart-e9e97e39-fa8a-4456-acef-b07bc58a4a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161371088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.161371088
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2751854878
Short name T844
Test name
Test status
Simulation time 27297680 ps
CPU time 0.74 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 216076 kb
Host smart-3052de5d-00dd-4007-bcd8-b50a97c985c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751854878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2751854878
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1372229394
Short name T653
Test name
Test status
Simulation time 2738737541 ps
CPU time 5.43 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:06 PM PDT 24
Peak memory 220532 kb
Host smart-d917d401-14e5-4d09-baeb-cca4b221a13f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1372229394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1372229394
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4235324413
Short name T418
Test name
Test status
Simulation time 319626829634 ps
CPU time 566.72 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:46:30 PM PDT 24
Peak memory 273496 kb
Host smart-83f7aee6-e8c8-4cc3-83c2-4f9ff641c8d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235324413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4235324413
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2810559656
Short name T768
Test name
Test status
Simulation time 18492131577 ps
CPU time 33.92 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:34 PM PDT 24
Peak memory 218648 kb
Host smart-8bbe567d-8cc6-456f-9678-ffe7c6064063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810559656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2810559656
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1931905463
Short name T571
Test name
Test status
Simulation time 4994167611 ps
CPU time 14.61 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:16 PM PDT 24
Peak memory 215004 kb
Host smart-4a772e30-fcd9-4b76-b2b5-c2dc7e7e07d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931905463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1931905463
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2411406361
Short name T599
Test name
Test status
Simulation time 2150130548 ps
CPU time 19.86 seconds
Started Mar 28 01:36:54 PM PDT 24
Finished Mar 28 01:37:14 PM PDT 24
Peak memory 216212 kb
Host smart-23b3db51-dded-4888-986c-77988380ec7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411406361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2411406361
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3102618215
Short name T662
Test name
Test status
Simulation time 101814096 ps
CPU time 0.78 seconds
Started Mar 28 01:37:05 PM PDT 24
Finished Mar 28 01:37:06 PM PDT 24
Peak memory 205560 kb
Host smart-ba81b712-e5fc-44f3-9ab1-dd82358deb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102618215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3102618215
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1026515331
Short name T408
Test name
Test status
Simulation time 39778254214 ps
CPU time 34.33 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:38 PM PDT 24
Peak memory 246500 kb
Host smart-d6585c1f-9ca4-4ba1-bc9d-02b8728e6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026515331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1026515331
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1868678300
Short name T295
Test name
Test status
Simulation time 31551975 ps
CPU time 0.8 seconds
Started Mar 28 01:36:58 PM PDT 24
Finished Mar 28 01:36:59 PM PDT 24
Peak memory 204596 kb
Host smart-91d85995-4196-4cc0-987f-58cda4af2ff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868678300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1868678300
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2974233159
Short name T685
Test name
Test status
Simulation time 665664716 ps
CPU time 3.62 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:36:59 PM PDT 24
Peak memory 233560 kb
Host smart-470a0d6f-cfe3-4b95-bf37-7cf8cb23f058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974233159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2974233159
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2715432777
Short name T713
Test name
Test status
Simulation time 16703807 ps
CPU time 0.77 seconds
Started Mar 28 01:37:04 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 205536 kb
Host smart-624a2683-ca0a-40d4-a36f-d66120b58ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715432777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2715432777
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2107142095
Short name T197
Test name
Test status
Simulation time 18835610620 ps
CPU time 45.93 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:44 PM PDT 24
Peak memory 239164 kb
Host smart-b170482c-d1c8-41b6-b04d-89bae7fce2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107142095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2107142095
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.4251598027
Short name T261
Test name
Test status
Simulation time 2761025751 ps
CPU time 32.42 seconds
Started Mar 28 01:36:59 PM PDT 24
Finished Mar 28 01:37:32 PM PDT 24
Peak memory 233772 kb
Host smart-a18a9c92-46a1-434c-ab24-e5919460b846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251598027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4251598027
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1845387008
Short name T883
Test name
Test status
Simulation time 2030773824 ps
CPU time 34.53 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:33 PM PDT 24
Peak memory 224428 kb
Host smart-edbab5b6-cfa4-48a4-96e6-4410ad5261f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845387008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1845387008
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3023704665
Short name T959
Test name
Test status
Simulation time 7215804193 ps
CPU time 29.75 seconds
Started Mar 28 01:36:52 PM PDT 24
Finished Mar 28 01:37:22 PM PDT 24
Peak memory 240772 kb
Host smart-4c0907a1-3457-4649-a44c-b5191e14655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023704665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3023704665
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.913062192
Short name T971
Test name
Test status
Simulation time 2855446365 ps
CPU time 10.13 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:07 PM PDT 24
Peak memory 218844 kb
Host smart-2ef4c8c6-01e5-44c7-b1cb-c3d852454e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913062192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.913062192
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3132598524
Short name T393
Test name
Test status
Simulation time 7676723610 ps
CPU time 15.23 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:37:09 PM PDT 24
Peak memory 236572 kb
Host smart-fcddc9bd-6bca-479e-8be1-2ec3d7a9b675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132598524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3132598524
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4244390753
Short name T434
Test name
Test status
Simulation time 152692622 ps
CPU time 1.01 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:36:58 PM PDT 24
Peak memory 217740 kb
Host smart-a71bf607-c4af-4c6a-b912-a8b0030e0a50
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244390753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4244390753
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1689767618
Short name T29
Test name
Test status
Simulation time 3925541386 ps
CPU time 9.96 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:37:03 PM PDT 24
Peak memory 227544 kb
Host smart-d9fbab4d-dee6-4494-8413-dd6a9b5799c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689767618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1689767618
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.832934335
Short name T801
Test name
Test status
Simulation time 15075042521 ps
CPU time 11.8 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:09 PM PDT 24
Peak memory 240668 kb
Host smart-5fa450e0-b249-4b04-bb0c-01734a7fa5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832934335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.832934335
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.2304115234
Short name T593
Test name
Test status
Simulation time 41471515 ps
CPU time 0.74 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 216072 kb
Host smart-a72e5c15-bf0b-4f37-8ca5-7c1876e6e0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304115234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.2304115234
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2836919515
Short name T674
Test name
Test status
Simulation time 1253384958 ps
CPU time 6.21 seconds
Started Mar 28 01:36:52 PM PDT 24
Finished Mar 28 01:36:59 PM PDT 24
Peak memory 221604 kb
Host smart-a55432e6-a101-45c4-82a3-5ce35d1bfa98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2836919515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2836919515
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2375139761
Short name T886
Test name
Test status
Simulation time 60620001806 ps
CPU time 158.02 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:39:36 PM PDT 24
Peak memory 265552 kb
Host smart-74ea124f-b566-4e7b-936f-6b3b600a0bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375139761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2375139761
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1589648146
Short name T814
Test name
Test status
Simulation time 6981167014 ps
CPU time 27.86 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:31 PM PDT 24
Peak memory 216192 kb
Host smart-12e1e889-c0ad-45de-9e7e-bcbc42a21499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589648146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1589648146
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1420362416
Short name T510
Test name
Test status
Simulation time 6429753901 ps
CPU time 9.34 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:13 PM PDT 24
Peak memory 216252 kb
Host smart-c5247b81-91b0-412a-9900-787c1b75efe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420362416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1420362416
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.460937868
Short name T379
Test name
Test status
Simulation time 212656913 ps
CPU time 8.08 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:09 PM PDT 24
Peak memory 216144 kb
Host smart-68c7e0e4-cdae-4e85-9f61-bd8f18d782b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460937868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.460937868
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1513816192
Short name T80
Test name
Test status
Simulation time 152240550 ps
CPU time 0.99 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:36:55 PM PDT 24
Peak memory 206564 kb
Host smart-59dca5a1-daed-455c-9e4b-8d16c725739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513816192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1513816192
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.151279691
Short name T178
Test name
Test status
Simulation time 7562161764 ps
CPU time 8.24 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 234312 kb
Host smart-0ac14d3f-8be9-42a7-b6a3-c542a4a98465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151279691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.151279691
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4134535926
Short name T54
Test name
Test status
Simulation time 15177754 ps
CPU time 0.77 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:02 PM PDT 24
Peak memory 205136 kb
Host smart-a4ca0c30-50d5-478c-ba6e-8ccd487ee4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134535926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4134535926
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2047871712
Short name T681
Test name
Test status
Simulation time 7265934853 ps
CPU time 11.58 seconds
Started Mar 28 01:37:05 PM PDT 24
Finished Mar 28 01:37:16 PM PDT 24
Peak memory 233828 kb
Host smart-fffdcae6-d45a-4202-85e5-b0dfa65e3ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047871712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2047871712
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3427422759
Short name T808
Test name
Test status
Simulation time 22390748 ps
CPU time 0.84 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:36:57 PM PDT 24
Peak memory 206492 kb
Host smart-ed503505-77e1-44f6-87a8-76c0ed5d3450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427422759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3427422759
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3244615489
Short name T159
Test name
Test status
Simulation time 32526245714 ps
CPU time 143.7 seconds
Started Mar 28 01:37:05 PM PDT 24
Finished Mar 28 01:39:29 PM PDT 24
Peak memory 249032 kb
Host smart-abcf64a7-917b-49a7-bac6-bfaf16b85a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244615489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3244615489
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2353403216
Short name T38
Test name
Test status
Simulation time 264371938936 ps
CPU time 276.41 seconds
Started Mar 28 01:37:06 PM PDT 24
Finished Mar 28 01:41:42 PM PDT 24
Peak memory 270516 kb
Host smart-da315abf-6784-4ced-a234-87fe43997f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353403216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2353403216
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3621240162
Short name T120
Test name
Test status
Simulation time 19861325384 ps
CPU time 25.91 seconds
Started Mar 28 01:36:59 PM PDT 24
Finished Mar 28 01:37:26 PM PDT 24
Peak memory 240776 kb
Host smart-6820259d-4610-4ec0-9e62-3aa6d776920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621240162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3621240162
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3127300812
Short name T502
Test name
Test status
Simulation time 259427333 ps
CPU time 2.98 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:06 PM PDT 24
Peak memory 218364 kb
Host smart-ad59faee-ae2f-45da-ad9f-6035143a5131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127300812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3127300812
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1880800827
Short name T699
Test name
Test status
Simulation time 3790129956 ps
CPU time 12.87 seconds
Started Mar 28 01:37:05 PM PDT 24
Finished Mar 28 01:37:18 PM PDT 24
Peak memory 237448 kb
Host smart-a2331567-9659-4233-a99f-497670f003b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880800827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1880800827
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2719595170
Short name T664
Test name
Test status
Simulation time 313691449 ps
CPU time 1.08 seconds
Started Mar 28 01:36:59 PM PDT 24
Finished Mar 28 01:37:00 PM PDT 24
Peak memory 216436 kb
Host smart-62ed76a9-7a5f-4af3-9257-f7661efda691
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719595170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2719595170
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4004071285
Short name T823
Test name
Test status
Simulation time 59236075277 ps
CPU time 42.4 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:43 PM PDT 24
Peak memory 237436 kb
Host smart-b3882aee-63fa-4418-86b2-8e6bbb507039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004071285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4004071285
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2779740509
Short name T445
Test name
Test status
Simulation time 1512137522 ps
CPU time 7.71 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:11 PM PDT 24
Peak memory 224360 kb
Host smart-e86af1ae-0996-41e6-9b62-51d4892d8329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779740509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2779740509
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.1801960406
Short name T539
Test name
Test status
Simulation time 17842442 ps
CPU time 0.76 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:36:58 PM PDT 24
Peak memory 215840 kb
Host smart-2b19d887-bd70-4b20-acd7-7a9af92f8d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801960406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.1801960406
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3733535542
Short name T786
Test name
Test status
Simulation time 275668174 ps
CPU time 3.49 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:03 PM PDT 24
Peak memory 222532 kb
Host smart-d32a7a4d-6e16-4949-953d-aa59ad25c7f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3733535542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3733535542
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2897668431
Short name T452
Test name
Test status
Simulation time 22764037604 ps
CPU time 16.45 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:20 PM PDT 24
Peak memory 216276 kb
Host smart-6a352b1b-8dda-496d-a946-1f8eb20b21f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897668431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2897668431
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3491676405
Short name T330
Test name
Test status
Simulation time 23831124320 ps
CPU time 19.16 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:16 PM PDT 24
Peak memory 216184 kb
Host smart-f7e543ed-2fd9-4ba6-a506-6cb9b6673c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491676405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3491676405
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4231589613
Short name T140
Test name
Test status
Simulation time 395746720 ps
CPU time 1.69 seconds
Started Mar 28 01:36:58 PM PDT 24
Finished Mar 28 01:37:00 PM PDT 24
Peak memory 216208 kb
Host smart-3cbd17dc-1e6a-491b-9fe7-826d3d4191a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231589613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4231589613
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1655276190
Short name T577
Test name
Test status
Simulation time 31884393 ps
CPU time 0.87 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:01 PM PDT 24
Peak memory 205584 kb
Host smart-b4be0cfc-9b19-4573-bf27-02d0e3550768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655276190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1655276190
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3298980491
Short name T561
Test name
Test status
Simulation time 4538843435 ps
CPU time 6.66 seconds
Started Mar 28 01:37:01 PM PDT 24
Finished Mar 28 01:37:08 PM PDT 24
Peak memory 218056 kb
Host smart-c98c1d4e-6254-493e-b9f5-42b0a7229883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298980491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3298980491
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.390190746
Short name T399
Test name
Test status
Simulation time 35310331 ps
CPU time 0.72 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:36:58 PM PDT 24
Peak memory 204584 kb
Host smart-af6fbc05-57aa-492a-8a31-4db18deab215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390190746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.390190746
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3373750762
Short name T639
Test name
Test status
Simulation time 1831333677 ps
CPU time 6.92 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:37:03 PM PDT 24
Peak memory 224520 kb
Host smart-16724e4d-b98c-4cc8-9162-127c1bf0a578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373750762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3373750762
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3010331829
Short name T361
Test name
Test status
Simulation time 44508044 ps
CPU time 0.84 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 205496 kb
Host smart-3a20fe79-0966-4639-be13-5147eed038db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010331829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3010331829
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2079458905
Short name T153
Test name
Test status
Simulation time 110615192750 ps
CPU time 254.06 seconds
Started Mar 28 01:36:52 PM PDT 24
Finished Mar 28 01:41:07 PM PDT 24
Peak memory 249364 kb
Host smart-cddbbb0d-693f-4020-9b58-4a1f4bec9c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079458905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2079458905
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1688247822
Short name T70
Test name
Test status
Simulation time 15423559726 ps
CPU time 104.59 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:38:40 PM PDT 24
Peak memory 257368 kb
Host smart-1151cb88-7703-4c7f-b891-0c0344fcbc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688247822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1688247822
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3451500296
Short name T123
Test name
Test status
Simulation time 238156591 ps
CPU time 7.19 seconds
Started Mar 28 01:36:54 PM PDT 24
Finished Mar 28 01:37:02 PM PDT 24
Peak memory 233544 kb
Host smart-64a1c604-b520-4c4a-bc88-f34a9200165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451500296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3451500296
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2981086055
Short name T911
Test name
Test status
Simulation time 10713441928 ps
CPU time 10.3 seconds
Started Mar 28 01:37:04 PM PDT 24
Finished Mar 28 01:37:15 PM PDT 24
Peak memory 224480 kb
Host smart-2ed29ba3-d40d-4979-9dc6-bfbefe4e1ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981086055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2981086055
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2924631708
Short name T656
Test name
Test status
Simulation time 134720925 ps
CPU time 3.81 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:37:00 PM PDT 24
Peak memory 232712 kb
Host smart-64de54ac-43fe-4a7c-9a34-c4427abc7e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924631708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2924631708
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3489351543
Short name T427
Test name
Test status
Simulation time 92477234 ps
CPU time 1.11 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:02 PM PDT 24
Peak memory 217748 kb
Host smart-f2626af6-fbeb-4508-bf0b-9c4fe91b1564
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489351543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3489351543
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4201786486
Short name T521
Test name
Test status
Simulation time 1973360147 ps
CPU time 9.46 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:11 PM PDT 24
Peak memory 218344 kb
Host smart-b3cd14d1-b4d3-4225-87ac-de878b28ffda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201786486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4201786486
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.533520950
Short name T219
Test name
Test status
Simulation time 28651843832 ps
CPU time 37.18 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 248756 kb
Host smart-75fa12a6-d21d-43b2-8597-8fcad16d2aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533520950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.533520950
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.1250526149
Short name T616
Test name
Test status
Simulation time 36890383 ps
CPU time 0.76 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 216048 kb
Host smart-8dd3f53f-14fa-41a6-a473-ae295dcda279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250526149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.1250526149
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1188716639
Short name T858
Test name
Test status
Simulation time 1739610644 ps
CPU time 7.49 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 222168 kb
Host smart-2a279a8d-1b04-407a-9516-b57786b3787b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1188716639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1188716639
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.14423174
Short name T700
Test name
Test status
Simulation time 80240939 ps
CPU time 1.24 seconds
Started Mar 28 01:36:50 PM PDT 24
Finished Mar 28 01:36:52 PM PDT 24
Peak memory 206856 kb
Host smart-750f6571-d702-481b-a1fa-37c2a1acb19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14423174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress
_all.14423174
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.578742664
Short name T569
Test name
Test status
Simulation time 1133762440 ps
CPU time 2.65 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:06 PM PDT 24
Peak memory 216088 kb
Host smart-ddfbee04-6fbd-4316-8b1a-e5e236b59a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578742664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.578742664
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2809383121
Short name T342
Test name
Test status
Simulation time 2658773850 ps
CPU time 5.12 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 216152 kb
Host smart-fe5287ee-7823-4edf-a8ae-857c3ee1b90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809383121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2809383121
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3227847253
Short name T913
Test name
Test status
Simulation time 1170089504 ps
CPU time 6.63 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:10 PM PDT 24
Peak memory 216272 kb
Host smart-fe8b2364-29b0-4ca3-9117-40eac3d4f76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227847253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3227847253
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1148334406
Short name T882
Test name
Test status
Simulation time 42392564 ps
CPU time 0.81 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 205536 kb
Host smart-941728f1-d909-4bc3-8663-ae6cf248461d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148334406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1148334406
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.749058846
Short name T538
Test name
Test status
Simulation time 2141433774 ps
CPU time 14.12 seconds
Started Mar 28 01:36:54 PM PDT 24
Finished Mar 28 01:37:08 PM PDT 24
Peak memory 232156 kb
Host smart-defc621d-b87d-4b49-8efc-cc3eb2b6da9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749058846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.749058846
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.671850037
Short name T942
Test name
Test status
Simulation time 32040486 ps
CPU time 0.76 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:36:02 PM PDT 24
Peak memory 204536 kb
Host smart-3bdb744d-dd8b-44d8-b6fe-51ea344f85b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671850037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.671850037
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.329801878
Short name T763
Test name
Test status
Simulation time 109649250 ps
CPU time 3.57 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 233352 kb
Host smart-bf8c853b-9806-4f4c-9aaf-771c26bf200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329801878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.329801878
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1407012196
Short name T796
Test name
Test status
Simulation time 29790426 ps
CPU time 0.81 seconds
Started Mar 28 01:36:07 PM PDT 24
Finished Mar 28 01:36:08 PM PDT 24
Peak memory 205088 kb
Host smart-febaf132-96d0-4c51-9ceb-cd92415476c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407012196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1407012196
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.462933706
Short name T444
Test name
Test status
Simulation time 14966110251 ps
CPU time 79.69 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:37:20 PM PDT 24
Peak memory 242384 kb
Host smart-711451a0-d872-4d8c-ac8b-65c9984bebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462933706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.462933706
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4229545427
Short name T916
Test name
Test status
Simulation time 101646229546 ps
CPU time 728.01 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:48:10 PM PDT 24
Peak memory 254804 kb
Host smart-e5b3f5a8-8872-4e67-8b2e-4a7dd897278b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229545427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4229545427
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2755761669
Short name T476
Test name
Test status
Simulation time 891274451 ps
CPU time 14.44 seconds
Started Mar 28 01:36:04 PM PDT 24
Finished Mar 28 01:36:18 PM PDT 24
Peak memory 237728 kb
Host smart-4aa6326a-6703-4a6f-96a0-f6d0b6323fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755761669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2755761669
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.678302582
Short name T666
Test name
Test status
Simulation time 840461107 ps
CPU time 5.41 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:15 PM PDT 24
Peak memory 235356 kb
Host smart-190e5e4e-2cdd-4342-a852-61018847803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678302582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.678302582
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.4208129191
Short name T908
Test name
Test status
Simulation time 465299446 ps
CPU time 7.76 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:36:09 PM PDT 24
Peak memory 237548 kb
Host smart-577f5256-4945-417b-9c04-d5565b616764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208129191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4208129191
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2371804994
Short name T415
Test name
Test status
Simulation time 27190087 ps
CPU time 1.1 seconds
Started Mar 28 01:36:02 PM PDT 24
Finished Mar 28 01:36:03 PM PDT 24
Peak memory 216524 kb
Host smart-7af47fd7-6bff-4cec-a9de-047098d90500
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371804994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2371804994
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.715471578
Short name T325
Test name
Test status
Simulation time 12610853556 ps
CPU time 20.17 seconds
Started Mar 28 01:35:56 PM PDT 24
Finished Mar 28 01:36:17 PM PDT 24
Peak memory 234140 kb
Host smart-e76af909-42a7-46c9-b161-59758d8667a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715471578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
715471578
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4084084503
Short name T881
Test name
Test status
Simulation time 620864940 ps
CPU time 4.35 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:11 PM PDT 24
Peak memory 234608 kb
Host smart-d7e4e4ec-b153-444f-87ce-a837e49a465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084084503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4084084503
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2722685485
Short name T390
Test name
Test status
Simulation time 46347398 ps
CPU time 0.77 seconds
Started Mar 28 01:36:02 PM PDT 24
Finished Mar 28 01:36:02 PM PDT 24
Peak memory 216060 kb
Host smart-11c5c50f-f93c-4deb-8cb7-0674e3ed80ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722685485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2722685485
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.819593619
Short name T386
Test name
Test status
Simulation time 373991014 ps
CPU time 3.52 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 219876 kb
Host smart-494bd2ff-83f1-4ac9-80a4-aa1c2264ad36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=819593619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.819593619
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1749523340
Short name T817
Test name
Test status
Simulation time 15519207155 ps
CPU time 205.22 seconds
Started Mar 28 01:36:04 PM PDT 24
Finished Mar 28 01:39:29 PM PDT 24
Peak memory 283064 kb
Host smart-21249ca0-4f79-4d5f-b717-00f5ed691bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749523340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1749523340
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1678360162
Short name T455
Test name
Test status
Simulation time 18450546802 ps
CPU time 23.41 seconds
Started Mar 28 01:36:00 PM PDT 24
Finished Mar 28 01:36:24 PM PDT 24
Peak memory 216140 kb
Host smart-fe74975f-0027-4366-ab64-caa546289584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678360162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1678360162
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2629795893
Short name T596
Test name
Test status
Simulation time 2153330865 ps
CPU time 8.33 seconds
Started Mar 28 01:35:58 PM PDT 24
Finished Mar 28 01:36:06 PM PDT 24
Peak memory 216244 kb
Host smart-271f1620-0cc2-4b6a-9038-c58feed05472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629795893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2629795893
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2657716020
Short name T835
Test name
Test status
Simulation time 955569271 ps
CPU time 3.7 seconds
Started Mar 28 01:36:04 PM PDT 24
Finished Mar 28 01:36:08 PM PDT 24
Peak memory 216176 kb
Host smart-7d954809-062a-4dd9-9235-6d4e8b255d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657716020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2657716020
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.179372696
Short name T263
Test name
Test status
Simulation time 147507697 ps
CPU time 0.89 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:36:02 PM PDT 24
Peak memory 206556 kb
Host smart-8b36734b-32e4-4d08-810f-b939ad683df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179372696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.179372696
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1664536400
Short name T865
Test name
Test status
Simulation time 5730529580 ps
CPU time 15.98 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:23 PM PDT 24
Peak memory 218740 kb
Host smart-64bc99fe-e026-4d0b-812b-dd1d57ffc91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664536400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1664536400
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.742629178
Short name T293
Test name
Test status
Simulation time 15139013 ps
CPU time 0.74 seconds
Started Mar 28 01:36:59 PM PDT 24
Finished Mar 28 01:37:00 PM PDT 24
Peak memory 205176 kb
Host smart-d1f4e542-becb-4558-89d7-805e99ad596d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742629178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.742629178
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2686119755
Short name T420
Test name
Test status
Simulation time 184791448 ps
CPU time 3.3 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:37:00 PM PDT 24
Peak memory 235128 kb
Host smart-a1ed773d-c155-4bde-a1a4-64bb2dd90c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686119755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2686119755
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2231110424
Short name T821
Test name
Test status
Simulation time 14047889 ps
CPU time 0.83 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:36:57 PM PDT 24
Peak memory 206112 kb
Host smart-bdc87c9a-124d-45df-8dd4-65350bdc46a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231110424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2231110424
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2783105604
Short name T934
Test name
Test status
Simulation time 25106209735 ps
CPU time 142.03 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:39:18 PM PDT 24
Peak memory 254920 kb
Host smart-21eb636f-6526-495e-ac91-805791f5d491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783105604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2783105604
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4213185434
Short name T834
Test name
Test status
Simulation time 5186414307 ps
CPU time 81.04 seconds
Started Mar 28 01:36:58 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 253716 kb
Host smart-0d95d581-155e-4375-88e2-b2bf7392048a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213185434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4213185434
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3844776417
Short name T42
Test name
Test status
Simulation time 361819684835 ps
CPU time 525.35 seconds
Started Mar 28 01:36:58 PM PDT 24
Finished Mar 28 01:45:44 PM PDT 24
Peak memory 264036 kb
Host smart-cc598436-fd12-43be-866a-329921363838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844776417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3844776417
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.433077004
Short name T394
Test name
Test status
Simulation time 1505968254 ps
CPU time 9.66 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 232564 kb
Host smart-b0c26e5f-922e-474f-a309-4e15a5682a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433077004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.433077004
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1023105209
Short name T836
Test name
Test status
Simulation time 3581254682 ps
CPU time 4.78 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:37:00 PM PDT 24
Peak memory 218436 kb
Host smart-3e20ffc1-568b-40c7-bc30-eef062861130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023105209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1023105209
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2202755581
Short name T297
Test name
Test status
Simulation time 575043766 ps
CPU time 7.81 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:08 PM PDT 24
Peak memory 244636 kb
Host smart-96d458f6-7b5d-4b78-b3b8-44be761a0131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202755581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2202755581
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1067819406
Short name T647
Test name
Test status
Simulation time 4573669766 ps
CPU time 7.42 seconds
Started Mar 28 01:36:57 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 246476 kb
Host smart-38f5ad26-5530-4097-bdfb-055941b80e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067819406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1067819406
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.456874003
Short name T605
Test name
Test status
Simulation time 10742481961 ps
CPU time 8.65 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 218376 kb
Host smart-243b6ce5-a4e9-47c7-8c44-6e7e0a24eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456874003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.456874003
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1173116530
Short name T703
Test name
Test status
Simulation time 2410220022 ps
CPU time 4.98 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:37:02 PM PDT 24
Peak memory 219956 kb
Host smart-47314801-2668-4745-947c-faa142845fe5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1173116530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1173116530
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1659761384
Short name T484
Test name
Test status
Simulation time 26664719799 ps
CPU time 42.79 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:37:37 PM PDT 24
Peak memory 216252 kb
Host smart-cc1f0318-0adc-44e2-94a0-a331887cabd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659761384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1659761384
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.28818755
Short name T570
Test name
Test status
Simulation time 27073941700 ps
CPU time 18.61 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:37:12 PM PDT 24
Peak memory 216172 kb
Host smart-a943a5a4-827d-4f84-8c18-564f43285ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28818755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.28818755
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1244049329
Short name T758
Test name
Test status
Simulation time 767395875 ps
CPU time 2.62 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:36:58 PM PDT 24
Peak memory 216148 kb
Host smart-f8fe140b-d7f2-4262-8345-459bd96556ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244049329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1244049329
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2583535531
Short name T968
Test name
Test status
Simulation time 79173412 ps
CPU time 0.85 seconds
Started Mar 28 01:36:54 PM PDT 24
Finished Mar 28 01:36:55 PM PDT 24
Peak memory 205544 kb
Host smart-941df08a-0981-4378-aebf-41ecd122a477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583535531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2583535531
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2534046843
Short name T895
Test name
Test status
Simulation time 840402816 ps
CPU time 4.83 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:37:01 PM PDT 24
Peak memory 217676 kb
Host smart-b87c626d-0f18-4110-89d0-1af9c51c4379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534046843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2534046843
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3838411790
Short name T278
Test name
Test status
Simulation time 36995929 ps
CPU time 0.73 seconds
Started Mar 28 01:37:05 PM PDT 24
Finished Mar 28 01:37:06 PM PDT 24
Peak memory 205196 kb
Host smart-7d20e264-bb01-4904-ae52-6c025821cd8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838411790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3838411790
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1000725460
Short name T364
Test name
Test status
Simulation time 1477452774 ps
CPU time 4.24 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:08 PM PDT 24
Peak memory 218376 kb
Host smart-817c7f4d-a313-4486-9da0-eb609491aba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000725460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1000725460
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2060790081
Short name T857
Test name
Test status
Simulation time 37279333 ps
CPU time 0.73 seconds
Started Mar 28 01:36:58 PM PDT 24
Finished Mar 28 01:36:59 PM PDT 24
Peak memory 205516 kb
Host smart-172b6884-7d9a-4ba3-99c2-126f69601d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060790081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2060790081
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3234040694
Short name T644
Test name
Test status
Simulation time 64887010245 ps
CPU time 165.25 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:39:49 PM PDT 24
Peak memory 250460 kb
Host smart-fe4dba7d-31c8-4762-8768-f318a848d0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234040694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3234040694
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3570588341
Short name T884
Test name
Test status
Simulation time 3276762625 ps
CPU time 29.01 seconds
Started Mar 28 01:37:05 PM PDT 24
Finished Mar 28 01:37:34 PM PDT 24
Peak memory 234984 kb
Host smart-4383681d-dc91-48ef-b5c5-7e479ad833ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570588341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3570588341
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.880787505
Short name T535
Test name
Test status
Simulation time 11296764316 ps
CPU time 15.39 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:19 PM PDT 24
Peak memory 233804 kb
Host smart-400fdbf0-e76b-484d-b6dc-23b67b792e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880787505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.880787505
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1505004347
Short name T428
Test name
Test status
Simulation time 93803848 ps
CPU time 2.98 seconds
Started Mar 28 01:36:59 PM PDT 24
Finished Mar 28 01:37:02 PM PDT 24
Peak memory 233572 kb
Host smart-44b13e52-03c3-4cdd-9a2e-b2452199b785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505004347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1505004347
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.401800587
Short name T82
Test name
Test status
Simulation time 3004278574 ps
CPU time 10.84 seconds
Started Mar 28 01:36:53 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 234040 kb
Host smart-ece05e76-0e43-4075-bb33-90a70faaa885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401800587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.401800587
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2655758050
Short name T614
Test name
Test status
Simulation time 1003014016 ps
CPU time 8.31 seconds
Started Mar 28 01:37:04 PM PDT 24
Finished Mar 28 01:37:12 PM PDT 24
Peak memory 233588 kb
Host smart-04693948-8414-4406-8a9b-ba567a8b27e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655758050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2655758050
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1848260370
Short name T948
Test name
Test status
Simulation time 3231647150 ps
CPU time 13.04 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:16 PM PDT 24
Peak memory 218496 kb
Host smart-424d0201-a63d-47ba-bc71-353742da2dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848260370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1848260370
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3224462837
Short name T493
Test name
Test status
Simulation time 1220874521 ps
CPU time 4.13 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:08 PM PDT 24
Peak memory 222660 kb
Host smart-02a73637-ef80-4612-bb7e-85785e0a8494
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3224462837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3224462837
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3621036858
Short name T254
Test name
Test status
Simulation time 60971468527 ps
CPU time 399.12 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:43:39 PM PDT 24
Peak memory 290012 kb
Host smart-dddeb5d3-ccf1-47ad-b33e-fb96420e3f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621036858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3621036858
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1537062104
Short name T756
Test name
Test status
Simulation time 2525054234 ps
CPU time 17.51 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:21 PM PDT 24
Peak memory 216176 kb
Host smart-0565cb4b-4ca7-4123-947d-c2bfe7070b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537062104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1537062104
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.92457116
Short name T523
Test name
Test status
Simulation time 2540308322 ps
CPU time 4.29 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 216232 kb
Host smart-a4abb8e8-0794-42fb-885d-12e115f50068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92457116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.92457116
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3079950065
Short name T707
Test name
Test status
Simulation time 126151987 ps
CPU time 2.54 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:06 PM PDT 24
Peak memory 216220 kb
Host smart-8a39f6c3-7660-4754-8218-8788cdb07e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079950065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3079950065
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3565067237
Short name T585
Test name
Test status
Simulation time 84665556 ps
CPU time 0.85 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 205524 kb
Host smart-91d21a53-926e-4942-bcb6-8e41c393c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565067237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3565067237
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.228451714
Short name T310
Test name
Test status
Simulation time 1815051406 ps
CPU time 7.95 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:11 PM PDT 24
Peak memory 223348 kb
Host smart-0e347272-ba17-4480-81c4-18d1667df2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228451714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.228451714
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2216564851
Short name T742
Test name
Test status
Simulation time 14637364 ps
CPU time 0.72 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:21 PM PDT 24
Peak memory 205188 kb
Host smart-88583486-5d00-4e5c-a7a3-3868317fb8d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216564851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2216564851
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2686585832
Short name T489
Test name
Test status
Simulation time 175188548 ps
CPU time 3.34 seconds
Started Mar 28 01:36:55 PM PDT 24
Finished Mar 28 01:36:59 PM PDT 24
Peak memory 235328 kb
Host smart-8b5128a2-d786-468c-9713-4b89cc596613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686585832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2686585832
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3650918624
Short name T424
Test name
Test status
Simulation time 40192884 ps
CPU time 0.8 seconds
Started Mar 28 01:37:05 PM PDT 24
Finished Mar 28 01:37:06 PM PDT 24
Peak memory 206552 kb
Host smart-1562cbf4-f7b0-45b2-9a57-205e7cf29fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650918624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3650918624
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2958359096
Short name T24
Test name
Test status
Simulation time 4911446171 ps
CPU time 24.12 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:46 PM PDT 24
Peak memory 234812 kb
Host smart-5070b4e6-0aaa-4655-9c30-8eaad5f661e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958359096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2958359096
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1897640169
Short name T588
Test name
Test status
Simulation time 17549393524 ps
CPU time 145.93 seconds
Started Mar 28 01:37:19 PM PDT 24
Finished Mar 28 01:39:45 PM PDT 24
Peak memory 249728 kb
Host smart-9f2966f0-0240-4178-88e9-a0d712b983c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897640169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1897640169
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4147753119
Short name T37
Test name
Test status
Simulation time 114199875719 ps
CPU time 259.85 seconds
Started Mar 28 01:37:19 PM PDT 24
Finished Mar 28 01:41:39 PM PDT 24
Peak memory 249320 kb
Host smart-c029200f-5080-42c4-8b3a-5d58d521e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147753119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4147753119
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3761947742
Short name T255
Test name
Test status
Simulation time 4847999463 ps
CPU time 13.8 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:36 PM PDT 24
Peak memory 233752 kb
Host smart-23e0df4f-5586-41ab-b4de-4af1a6db404a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761947742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3761947742
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1447514558
Short name T839
Test name
Test status
Simulation time 194468593 ps
CPU time 2.82 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:06 PM PDT 24
Peak memory 235292 kb
Host smart-3f977127-4646-48db-8621-c22df9b005b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447514558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1447514558
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2833879245
Short name T221
Test name
Test status
Simulation time 1037301308 ps
CPU time 5.71 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:07 PM PDT 24
Peak memory 218556 kb
Host smart-939a0b3a-cf8c-4c36-9bd6-68cfee3f5c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833879245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2833879245
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1981349435
Short name T69
Test name
Test status
Simulation time 22432750020 ps
CPU time 11.14 seconds
Started Mar 28 01:37:00 PM PDT 24
Finished Mar 28 01:37:12 PM PDT 24
Peak memory 239880 kb
Host smart-9b7c326a-8f48-4beb-ab93-0bcd71227f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981349435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1981349435
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.436192133
Short name T851
Test name
Test status
Simulation time 20489064120 ps
CPU time 8.58 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:12 PM PDT 24
Peak memory 232692 kb
Host smart-111fabbe-a44f-438f-8dce-a22a3c9704a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436192133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.436192133
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2187644415
Short name T764
Test name
Test status
Simulation time 1018331823 ps
CPU time 5.79 seconds
Started Mar 28 01:37:19 PM PDT 24
Finished Mar 28 01:37:25 PM PDT 24
Peak memory 222780 kb
Host smart-90dfe452-7d86-420f-b9b4-67dc9a4762b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2187644415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2187644415
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3866694590
Short name T862
Test name
Test status
Simulation time 5741585806 ps
CPU time 31.27 seconds
Started Mar 28 01:37:04 PM PDT 24
Finished Mar 28 01:37:36 PM PDT 24
Peak memory 216200 kb
Host smart-2ac389b1-8dff-4fd1-9e93-9ba30f82c1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866694590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3866694590
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2538908927
Short name T702
Test name
Test status
Simulation time 12432581574 ps
CPU time 8.98 seconds
Started Mar 28 01:37:06 PM PDT 24
Finished Mar 28 01:37:15 PM PDT 24
Peak memory 216228 kb
Host smart-1fe4bb55-352c-4509-a0a8-e37d8d2636af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538908927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2538908927
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2567728637
Short name T370
Test name
Test status
Simulation time 17820985 ps
CPU time 0.79 seconds
Started Mar 28 01:37:03 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 205512 kb
Host smart-9afba039-431a-4bd3-925f-154afcecd1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567728637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2567728637
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2024424168
Short name T799
Test name
Test status
Simulation time 201705656 ps
CPU time 1.07 seconds
Started Mar 28 01:37:02 PM PDT 24
Finished Mar 28 01:37:05 PM PDT 24
Peak memory 205420 kb
Host smart-be1ca38a-3db3-4aca-89b4-11097ca9e544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024424168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2024424168
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2441876073
Short name T905
Test name
Test status
Simulation time 387747335 ps
CPU time 7.18 seconds
Started Mar 28 01:36:56 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 238120 kb
Host smart-cb5f91ea-1ca9-4825-97f4-ce9cd88c8505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441876073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2441876073
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3279726874
Short name T55
Test name
Test status
Simulation time 10564424 ps
CPU time 0.73 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:23 PM PDT 24
Peak memory 205160 kb
Host smart-ea446766-dff0-4a2c-9b98-065a47d2dcbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279726874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3279726874
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2397462060
Short name T531
Test name
Test status
Simulation time 9101783182 ps
CPU time 9.94 seconds
Started Mar 28 01:37:26 PM PDT 24
Finished Mar 28 01:37:38 PM PDT 24
Peak memory 234692 kb
Host smart-a0b19ba0-0df0-4e4a-be72-f430f3092a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397462060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2397462060
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2640061553
Short name T541
Test name
Test status
Simulation time 47034424 ps
CPU time 0.81 seconds
Started Mar 28 01:37:25 PM PDT 24
Finished Mar 28 01:37:26 PM PDT 24
Peak memory 206224 kb
Host smart-2adcd621-42cf-4d79-b12b-4c156e4e9f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640061553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2640061553
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1197736497
Short name T350
Test name
Test status
Simulation time 32797042945 ps
CPU time 120.52 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:39:21 PM PDT 24
Peak memory 254332 kb
Host smart-974e0a1f-5053-4601-9abe-c8b0b8630728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197736497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1197736497
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2920386252
Short name T164
Test name
Test status
Simulation time 52908878955 ps
CPU time 303.85 seconds
Started Mar 28 01:37:24 PM PDT 24
Finished Mar 28 01:42:29 PM PDT 24
Peak memory 250340 kb
Host smart-cf3e6967-3c5b-4c6d-9144-4af583abbcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920386252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2920386252
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1461644997
Short name T630
Test name
Test status
Simulation time 11046171944 ps
CPU time 29.32 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:50 PM PDT 24
Peak memory 235432 kb
Host smart-d11051b0-c342-4355-b431-7bb6dee57bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461644997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1461644997
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3041919389
Short name T163
Test name
Test status
Simulation time 1715127486 ps
CPU time 3.51 seconds
Started Mar 28 01:37:12 PM PDT 24
Finished Mar 28 01:37:16 PM PDT 24
Peak memory 219616 kb
Host smart-5590dfb3-35a5-4d9e-bea7-c72169210e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041919389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3041919389
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1365153538
Short name T638
Test name
Test status
Simulation time 9208829915 ps
CPU time 26.97 seconds
Started Mar 28 01:37:19 PM PDT 24
Finished Mar 28 01:37:46 PM PDT 24
Peak memory 236836 kb
Host smart-43483930-ef2f-449e-940d-230cce5993b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365153538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1365153538
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2383025155
Short name T189
Test name
Test status
Simulation time 4110674571 ps
CPU time 15.41 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:35 PM PDT 24
Peak memory 233700 kb
Host smart-f2ade671-a563-41c5-857a-55b849d037ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383025155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2383025155
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1172028271
Short name T308
Test name
Test status
Simulation time 1278829520 ps
CPU time 4.68 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:25 PM PDT 24
Peak memory 219000 kb
Host smart-5b760595-e9bb-4dc4-ab7d-d74c1457acb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1172028271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1172028271
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3103138345
Short name T723
Test name
Test status
Simulation time 30705836065 ps
CPU time 217.74 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:40:59 PM PDT 24
Peak memory 237172 kb
Host smart-ff24fb66-b12a-47b4-ba83-781cb061222f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103138345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3103138345
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4140384329
Short name T780
Test name
Test status
Simulation time 2942235146 ps
CPU time 16.88 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:39 PM PDT 24
Peak memory 216228 kb
Host smart-8d0d4be3-a87c-4004-a44f-d94d79ede8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140384329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4140384329
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1213105104
Short name T411
Test name
Test status
Simulation time 546622121 ps
CPU time 1.86 seconds
Started Mar 28 01:37:26 PM PDT 24
Finished Mar 28 01:37:28 PM PDT 24
Peak memory 207604 kb
Host smart-7d4f1b4a-d25e-4d63-afc1-89091045671d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213105104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1213105104
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3118927299
Short name T422
Test name
Test status
Simulation time 348900408 ps
CPU time 3.45 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:25 PM PDT 24
Peak memory 215940 kb
Host smart-c384591a-c7f5-4f65-80ae-c4d1a7d99d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118927299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3118927299
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3959552521
Short name T847
Test name
Test status
Simulation time 39063262 ps
CPU time 0.84 seconds
Started Mar 28 01:37:24 PM PDT 24
Finished Mar 28 01:37:25 PM PDT 24
Peak memory 205512 kb
Host smart-48451e36-92ef-4129-8a22-a3d3c59438c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959552521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3959552521
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2918156094
Short name T135
Test name
Test status
Simulation time 5283435525 ps
CPU time 5.23 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:26 PM PDT 24
Peak memory 218676 kb
Host smart-5024c338-932e-46b7-bb50-a0cdf2bf6e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918156094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2918156094
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4219063987
Short name T594
Test name
Test status
Simulation time 25365229 ps
CPU time 0.71 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:22 PM PDT 24
Peak memory 204596 kb
Host smart-ee123fbf-884d-44c4-8c9a-f688aab52519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219063987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4219063987
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3153982013
Short name T442
Test name
Test status
Simulation time 3123696079 ps
CPU time 4.85 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:28 PM PDT 24
Peak memory 224408 kb
Host smart-530e05b3-d167-4c91-8627-3957f9c4b1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153982013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3153982013
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.4171262701
Short name T982
Test name
Test status
Simulation time 26707696 ps
CPU time 0.8 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:22 PM PDT 24
Peak memory 206012 kb
Host smart-0360874a-2c2b-49db-aacf-00945bde425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171262701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.4171262701
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3707345792
Short name T491
Test name
Test status
Simulation time 18495887909 ps
CPU time 54.99 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:38:16 PM PDT 24
Peak memory 249096 kb
Host smart-12f652db-79ab-4ea8-adfa-8626dfec4941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707345792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3707345792
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1119545574
Short name T485
Test name
Test status
Simulation time 672227282 ps
CPU time 9.95 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:31 PM PDT 24
Peak memory 232632 kb
Host smart-b3c72140-c725-41cf-9b8f-75995126cca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119545574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1119545574
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.447701099
Short name T549
Test name
Test status
Simulation time 930556533 ps
CPU time 6.31 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:27 PM PDT 24
Peak memory 237340 kb
Host smart-246d8f0b-9e62-4c05-aced-777b79cdc681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447701099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.447701099
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.24790986
Short name T173
Test name
Test status
Simulation time 11990744983 ps
CPU time 36.73 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:59 PM PDT 24
Peak memory 236864 kb
Host smart-8d95b984-625b-4d7d-8079-40862428e0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24790986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.24790986
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2977642929
Short name T336
Test name
Test status
Simulation time 3492004036 ps
CPU time 15.11 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:36 PM PDT 24
Peak memory 226564 kb
Host smart-e58122de-31c7-4b05-bd70-131a6efc01fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977642929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2977642929
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2050670013
Short name T743
Test name
Test status
Simulation time 6010563928 ps
CPU time 7.95 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:28 PM PDT 24
Peak memory 224508 kb
Host smart-3c188498-d111-465a-aa2c-3b1dd40a8eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050670013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2050670013
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2640525378
Short name T888
Test name
Test status
Simulation time 1446016277 ps
CPU time 6.73 seconds
Started Mar 28 01:37:24 PM PDT 24
Finished Mar 28 01:37:32 PM PDT 24
Peak memory 218976 kb
Host smart-4c85f6ca-3d1b-4fe1-9e79-a7e364dae96c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2640525378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2640525378
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1285518043
Short name T128
Test name
Test status
Simulation time 18563605287 ps
CPU time 136.9 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:39:38 PM PDT 24
Peak memory 268748 kb
Host smart-91b91498-620a-4fb7-bfa2-f8e328794047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285518043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1285518043
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.866448657
Short name T773
Test name
Test status
Simulation time 2662548395 ps
CPU time 20.09 seconds
Started Mar 28 01:37:19 PM PDT 24
Finished Mar 28 01:37:39 PM PDT 24
Peak memory 216244 kb
Host smart-de163103-577f-401d-a0d5-02d4de85839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866448657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.866448657
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2747094909
Short name T928
Test name
Test status
Simulation time 775446315 ps
CPU time 3.11 seconds
Started Mar 28 01:37:19 PM PDT 24
Finished Mar 28 01:37:23 PM PDT 24
Peak memory 215964 kb
Host smart-2d1a3210-0925-4faf-a018-8d0c4cb31191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747094909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2747094909
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1606910571
Short name T501
Test name
Test status
Simulation time 311631537 ps
CPU time 2.07 seconds
Started Mar 28 01:37:24 PM PDT 24
Finished Mar 28 01:37:26 PM PDT 24
Peak memory 216132 kb
Host smart-7604bf3e-ddab-4304-959b-3ee5169b0987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606910571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1606910571
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.516324889
Short name T826
Test name
Test status
Simulation time 969293165 ps
CPU time 1.04 seconds
Started Mar 28 01:37:25 PM PDT 24
Finished Mar 28 01:37:26 PM PDT 24
Peak memory 206520 kb
Host smart-8a691355-2d75-41e9-a837-5cb74c9c07a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516324889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.516324889
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.831183014
Short name T624
Test name
Test status
Simulation time 438212602 ps
CPU time 6.79 seconds
Started Mar 28 01:37:33 PM PDT 24
Finished Mar 28 01:37:40 PM PDT 24
Peak memory 240520 kb
Host smart-985d1d7a-49e7-424c-9756-07a7ce1404f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831183014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.831183014
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2081115961
Short name T266
Test name
Test status
Simulation time 49729875 ps
CPU time 0.72 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:20 PM PDT 24
Peak memory 205152 kb
Host smart-1379b0cf-50db-492b-92a2-e0af4320df2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081115961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2081115961
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2324030500
Short name T385
Test name
Test status
Simulation time 3316185629 ps
CPU time 8.34 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:29 PM PDT 24
Peak memory 220080 kb
Host smart-16925a8d-e857-4c77-bb57-d6f92dbe329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324030500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2324030500
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2791765861
Short name T709
Test name
Test status
Simulation time 21192133 ps
CPU time 0.81 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:22 PM PDT 24
Peak memory 205196 kb
Host smart-9a36c36c-c346-497f-a855-1e03d9a1ee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791765861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2791765861
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3132017691
Short name T537
Test name
Test status
Simulation time 19552690279 ps
CPU time 103.44 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:39:04 PM PDT 24
Peak memory 239788 kb
Host smart-ea9b6ec2-7533-4560-a4ef-46c357f6233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132017691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3132017691
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1506091980
Short name T208
Test name
Test status
Simulation time 5535411088 ps
CPU time 67.47 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:38:30 PM PDT 24
Peak memory 239412 kb
Host smart-12a527d8-6ca8-438b-9006-25a377b9807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506091980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1506091980
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3243714226
Short name T162
Test name
Test status
Simulation time 95205019517 ps
CPU time 695.32 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:48:56 PM PDT 24
Peak memory 249108 kb
Host smart-ec7dee97-206f-4eab-9665-5ba767b47138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243714226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3243714226
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3920027154
Short name T256
Test name
Test status
Simulation time 2911380729 ps
CPU time 21.4 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 232724 kb
Host smart-1884623f-ca92-4779-b539-364d0e3ac0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920027154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3920027154
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2191272286
Short name T918
Test name
Test status
Simulation time 506449411 ps
CPU time 5.1 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:27 PM PDT 24
Peak memory 233636 kb
Host smart-ef8fee09-b19c-4fdb-b589-eebd23e58ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191272286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2191272286
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3674792169
Short name T508
Test name
Test status
Simulation time 112788326 ps
CPU time 2.6 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:25 PM PDT 24
Peak memory 216448 kb
Host smart-7c9ec777-9ec1-4da8-8a3b-f4f327d85a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674792169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3674792169
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3446999518
Short name T11
Test name
Test status
Simulation time 692909601 ps
CPU time 7.37 seconds
Started Mar 28 01:37:24 PM PDT 24
Finished Mar 28 01:37:31 PM PDT 24
Peak memory 233544 kb
Host smart-d79a2b11-d632-4dfa-872d-f3caf4b0912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446999518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3446999518
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3253576917
Short name T785
Test name
Test status
Simulation time 126579326 ps
CPU time 3.17 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:26 PM PDT 24
Peak memory 232992 kb
Host smart-c6bece90-3169-4615-ab3c-4a49a682c00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253576917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3253576917
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1879675275
Short name T346
Test name
Test status
Simulation time 3171685780 ps
CPU time 6.63 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:28 PM PDT 24
Peak memory 219168 kb
Host smart-8d77f4e5-59aa-44a3-902c-f57cd5baa2bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1879675275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1879675275
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.785276619
Short name T869
Test name
Test status
Simulation time 364796714358 ps
CPU time 618.38 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:47:41 PM PDT 24
Peak memory 255480 kb
Host smart-e8facf8b-9b8f-4418-99b5-257ae656e6c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785276619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.785276619
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3469335242
Short name T690
Test name
Test status
Simulation time 33241249483 ps
CPU time 40.79 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:38:04 PM PDT 24
Peak memory 216248 kb
Host smart-d9b61a8c-9eae-4a59-8a94-72eebefeb9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469335242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3469335242
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.541063003
Short name T479
Test name
Test status
Simulation time 26887460302 ps
CPU time 13.27 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:35 PM PDT 24
Peak memory 216216 kb
Host smart-03cc0db7-6cdb-42d0-acdd-03579ce8ff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541063003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.541063003
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3018799988
Short name T498
Test name
Test status
Simulation time 54001810 ps
CPU time 1.71 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:23 PM PDT 24
Peak memory 216188 kb
Host smart-16c9c3b7-4483-4bd7-9033-18455be61dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018799988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3018799988
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2542088010
Short name T319
Test name
Test status
Simulation time 91290850 ps
CPU time 0.86 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:24 PM PDT 24
Peak memory 205440 kb
Host smart-bbb330b7-d056-463e-822b-26659a77ab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542088010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2542088010
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1081360044
Short name T338
Test name
Test status
Simulation time 17518959956 ps
CPU time 18.42 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:39 PM PDT 24
Peak memory 234064 kb
Host smart-35f98839-fe2b-44f4-a775-dcdc62819c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081360044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1081360044
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2934373814
Short name T602
Test name
Test status
Simulation time 20862917 ps
CPU time 0.75 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:24 PM PDT 24
Peak memory 204580 kb
Host smart-a394842f-e6c3-4bea-a805-a86226a56ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934373814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2934373814
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3810728740
Short name T540
Test name
Test status
Simulation time 299882886 ps
CPU time 2.83 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:26 PM PDT 24
Peak memory 233116 kb
Host smart-4205a515-9b1b-45f9-812e-0d5a570aaf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810728740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3810728740
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1348075128
Short name T431
Test name
Test status
Simulation time 29485991 ps
CPU time 0.85 seconds
Started Mar 28 01:37:26 PM PDT 24
Finished Mar 28 01:37:27 PM PDT 24
Peak memory 206268 kb
Host smart-84a0d22f-d94f-4752-83a9-58f6c24a2157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348075128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1348075128
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3268614233
Short name T807
Test name
Test status
Simulation time 38572488659 ps
CPU time 134.4 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:39:37 PM PDT 24
Peak memory 256760 kb
Host smart-866a8000-fd61-4cbb-9531-6cfd7cf4abdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268614233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3268614233
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.245025286
Short name T371
Test name
Test status
Simulation time 13339003398 ps
CPU time 62.37 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:38:23 PM PDT 24
Peak memory 240996 kb
Host smart-45903197-97be-49f4-b051-c0036279d737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245025286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.245025286
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3545221014
Short name T51
Test name
Test status
Simulation time 19886029667 ps
CPU time 184.43 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:40:27 PM PDT 24
Peak memory 259060 kb
Host smart-7456401e-a356-4063-9f22-49ca01a38144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545221014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3545221014
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2868158679
Short name T583
Test name
Test status
Simulation time 17281487784 ps
CPU time 39.52 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:59 PM PDT 24
Peak memory 234048 kb
Host smart-b8b8fd57-e217-41c4-83d8-4a21eeb345b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868158679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2868158679
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.54186148
Short name T511
Test name
Test status
Simulation time 576400905 ps
CPU time 4.84 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:25 PM PDT 24
Peak memory 224396 kb
Host smart-3d2a4f90-1cdf-43ef-b483-32499d56178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54186148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.54186148
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3722661136
Short name T10
Test name
Test status
Simulation time 3197560546 ps
CPU time 9.76 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:30 PM PDT 24
Peak memory 226880 kb
Host smart-fb9c7813-aea4-4979-9c1f-3bdb17958a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722661136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3722661136
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3666181809
Short name T678
Test name
Test status
Simulation time 269631792 ps
CPU time 4.04 seconds
Started Mar 28 01:37:26 PM PDT 24
Finished Mar 28 01:37:30 PM PDT 24
Peak memory 233612 kb
Host smart-c3ad91f9-cd07-4425-8383-30260f85fd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666181809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3666181809
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1336749950
Short name T626
Test name
Test status
Simulation time 24351874509 ps
CPU time 17.25 seconds
Started Mar 28 01:37:24 PM PDT 24
Finished Mar 28 01:37:42 PM PDT 24
Peak memory 224516 kb
Host smart-57627332-bc0d-45b5-9316-34eaa9ffded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336749950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1336749950
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2131586891
Short name T750
Test name
Test status
Simulation time 1333363701 ps
CPU time 5.54 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:28 PM PDT 24
Peak memory 219688 kb
Host smart-847a3141-1067-48ca-a988-ca24ff07cf0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131586891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2131586891
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1186497897
Short name T39
Test name
Test status
Simulation time 141807959222 ps
CPU time 193.4 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:40:34 PM PDT 24
Peak memory 240872 kb
Host smart-23d45ffb-dfc3-4723-ac26-12ea6f9234fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186497897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1186497897
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2981037599
Short name T646
Test name
Test status
Simulation time 7450501261 ps
CPU time 51.83 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:38:12 PM PDT 24
Peak memory 216164 kb
Host smart-ff7ac555-e301-4755-a163-15f704695ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981037599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2981037599
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3311580656
Short name T935
Test name
Test status
Simulation time 50740157495 ps
CPU time 36.69 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:56 PM PDT 24
Peak memory 216196 kb
Host smart-9e0215a1-2e11-441a-8451-c86265d30fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311580656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3311580656
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2670586499
Short name T267
Test name
Test status
Simulation time 57927437 ps
CPU time 1.61 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:24 PM PDT 24
Peak memory 207900 kb
Host smart-f13785cd-a6fe-4c6f-b6cb-6c3a3acc6abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670586499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2670586499
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.276059344
Short name T318
Test name
Test status
Simulation time 58822059 ps
CPU time 0.87 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:23 PM PDT 24
Peak memory 205504 kb
Host smart-1244c183-5bae-42b1-9e7e-7ced68f9288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276059344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.276059344
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4134663024
Short name T902
Test name
Test status
Simulation time 335756110 ps
CPU time 4.91 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:27 PM PDT 24
Peak memory 218708 kb
Host smart-c4094502-1d66-401e-b1f8-7dc3decaaca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134663024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4134663024
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1697538846
Short name T280
Test name
Test status
Simulation time 79551184 ps
CPU time 0.72 seconds
Started Mar 28 01:37:48 PM PDT 24
Finished Mar 28 01:37:49 PM PDT 24
Peak memory 205508 kb
Host smart-1f1c210c-a8bf-401d-9ea6-791e370e92fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697538846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1697538846
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.559104616
Short name T591
Test name
Test status
Simulation time 1013610781 ps
CPU time 3.88 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:27 PM PDT 24
Peak memory 219160 kb
Host smart-d49b4d15-8965-4fd6-a9dd-7b1456cf9800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559104616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.559104616
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1305955137
Short name T46
Test name
Test status
Simulation time 25692139 ps
CPU time 0.75 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:22 PM PDT 24
Peak memory 206216 kb
Host smart-dbedcc63-c2e9-441e-83f3-034f94842630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305955137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1305955137
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1602007585
Short name T232
Test name
Test status
Simulation time 100083116599 ps
CPU time 470.95 seconds
Started Mar 28 01:37:35 PM PDT 24
Finished Mar 28 01:45:26 PM PDT 24
Peak memory 265472 kb
Host smart-21e68927-d300-48a9-8a77-dd3e40249e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602007585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1602007585
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.977666509
Short name T824
Test name
Test status
Simulation time 3603879900 ps
CPU time 29.1 seconds
Started Mar 28 01:37:36 PM PDT 24
Finished Mar 28 01:38:05 PM PDT 24
Peak memory 221428 kb
Host smart-76f4b4ee-d1cb-43cd-b772-206ad08166b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977666509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.977666509
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2167721060
Short name T957
Test name
Test status
Simulation time 1969664284 ps
CPU time 11.12 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:34 PM PDT 24
Peak memory 240752 kb
Host smart-b0e93ccb-aedd-49d3-93c5-75c441e63ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167721060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2167721060
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1968295176
Short name T193
Test name
Test status
Simulation time 5194781447 ps
CPU time 5.76 seconds
Started Mar 28 01:37:23 PM PDT 24
Finished Mar 28 01:37:28 PM PDT 24
Peak memory 224444 kb
Host smart-da4f59d6-3326-49cf-b280-209abc83504e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968295176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1968295176
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1752262557
Short name T160
Test name
Test status
Simulation time 26839577874 ps
CPU time 24.57 seconds
Started Mar 28 01:37:25 PM PDT 24
Finished Mar 28 01:37:50 PM PDT 24
Peak memory 229824 kb
Host smart-fd259765-fa46-4107-ac6a-85b721720f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752262557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1752262557
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3551820169
Short name T972
Test name
Test status
Simulation time 9609405580 ps
CPU time 28.76 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:50 PM PDT 24
Peak memory 233200 kb
Host smart-e6218beb-1ba3-476c-82f7-a6f4a5a7e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551820169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3551820169
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4274155645
Short name T686
Test name
Test status
Simulation time 4205671797 ps
CPU time 12.07 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:33 PM PDT 24
Peak memory 233636 kb
Host smart-cfea73fd-4c10-4c96-b141-c2fc052c9e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274155645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4274155645
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3439429958
Short name T737
Test name
Test status
Simulation time 946189569734 ps
CPU time 403.29 seconds
Started Mar 28 01:37:35 PM PDT 24
Finished Mar 28 01:44:18 PM PDT 24
Peak memory 265520 kb
Host smart-a245a48f-db56-4aee-87db-d2058ea05be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439429958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3439429958
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3033639888
Short name T260
Test name
Test status
Simulation time 3907664004 ps
CPU time 40.01 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:38:01 PM PDT 24
Peak memory 216244 kb
Host smart-51507d67-5ab6-45e7-845b-af690aaaf203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033639888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3033639888
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1637304925
Short name T81
Test name
Test status
Simulation time 1751399083 ps
CPU time 6.15 seconds
Started Mar 28 01:37:20 PM PDT 24
Finished Mar 28 01:37:27 PM PDT 24
Peak memory 216084 kb
Host smart-7a8e8f93-095c-40f0-b135-db0dcf5f5372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637304925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1637304925
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2124671586
Short name T592
Test name
Test status
Simulation time 229098634 ps
CPU time 0.89 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:22 PM PDT 24
Peak memory 206068 kb
Host smart-6172671f-4766-4049-b470-6400f296f23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124671586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2124671586
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4106337677
Short name T621
Test name
Test status
Simulation time 183370340 ps
CPU time 1.22 seconds
Started Mar 28 01:37:22 PM PDT 24
Finished Mar 28 01:37:23 PM PDT 24
Peak memory 206584 kb
Host smart-30ad3d75-e5b6-4b52-b5b8-80a6856edb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106337677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4106337677
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2270984458
Short name T169
Test name
Test status
Simulation time 1146956242 ps
CPU time 9.4 seconds
Started Mar 28 01:37:21 PM PDT 24
Finished Mar 28 01:37:30 PM PDT 24
Peak memory 233932 kb
Host smart-6e51d57b-00d5-4572-9aac-d99d0ff97ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270984458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2270984458
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1115038125
Short name T524
Test name
Test status
Simulation time 14135597 ps
CPU time 0.74 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:38 PM PDT 24
Peak memory 205044 kb
Host smart-75d9a9a1-89fe-45b3-a7db-5589ab3b7eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115038125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1115038125
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3692468372
Short name T550
Test name
Test status
Simulation time 501869771 ps
CPU time 3.55 seconds
Started Mar 28 01:37:41 PM PDT 24
Finished Mar 28 01:37:45 PM PDT 24
Peak memory 234388 kb
Host smart-960e69a8-c0ab-4172-a3b8-8ccc73f8d0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692468372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3692468372
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1114317768
Short name T284
Test name
Test status
Simulation time 20220846 ps
CPU time 0.8 seconds
Started Mar 28 01:37:35 PM PDT 24
Finished Mar 28 01:37:36 PM PDT 24
Peak memory 206228 kb
Host smart-f7ae442f-75ca-416a-b8ca-537b584a7179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114317768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1114317768
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1820177973
Short name T790
Test name
Test status
Simulation time 174715058142 ps
CPU time 120.13 seconds
Started Mar 28 01:37:37 PM PDT 24
Finished Mar 28 01:39:38 PM PDT 24
Peak memory 266020 kb
Host smart-4d9655a8-3b89-4547-9e55-fea26f82b66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820177973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1820177973
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2313095825
Short name T384
Test name
Test status
Simulation time 73850165165 ps
CPU time 88.04 seconds
Started Mar 28 01:37:36 PM PDT 24
Finished Mar 28 01:39:04 PM PDT 24
Peak memory 256848 kb
Host smart-5238fef8-b860-4ad6-98a5-fc16c2fbc621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313095825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2313095825
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4048598056
Short name T717
Test name
Test status
Simulation time 32657790151 ps
CPU time 96.35 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:39:14 PM PDT 24
Peak memory 251556 kb
Host smart-160aa2b8-39e9-42b8-9654-0421ef415b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048598056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4048598056
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.412549092
Short name T590
Test name
Test status
Simulation time 56852059178 ps
CPU time 55.42 seconds
Started Mar 28 01:37:39 PM PDT 24
Finished Mar 28 01:38:35 PM PDT 24
Peak memory 238380 kb
Host smart-94e9b257-7c42-4c38-b922-4bc942011db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412549092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.412549092
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.45502417
Short name T584
Test name
Test status
Simulation time 2501262618 ps
CPU time 9 seconds
Started Mar 28 01:37:37 PM PDT 24
Finished Mar 28 01:37:46 PM PDT 24
Peak memory 219600 kb
Host smart-a2ecdd6c-221a-49eb-9083-e1617878bcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45502417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.45502417
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1402298129
Short name T187
Test name
Test status
Simulation time 9321239030 ps
CPU time 25.29 seconds
Started Mar 28 01:37:37 PM PDT 24
Finished Mar 28 01:38:02 PM PDT 24
Peak memory 231516 kb
Host smart-199bf864-15db-4d52-b8cb-c71ca66172f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402298129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1402298129
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3885575940
Short name T604
Test name
Test status
Simulation time 5363679240 ps
CPU time 15.66 seconds
Started Mar 28 01:37:36 PM PDT 24
Finished Mar 28 01:37:52 PM PDT 24
Peak memory 232876 kb
Host smart-5e68312f-da9f-48cf-b06a-42db5495f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885575940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3885575940
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.895578507
Short name T429
Test name
Test status
Simulation time 2469212805 ps
CPU time 9.69 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:50 PM PDT 24
Peak memory 233436 kb
Host smart-a53f120b-436d-46a9-a9ac-76932550c2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895578507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.895578507
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.353062353
Short name T470
Test name
Test status
Simulation time 995287571 ps
CPU time 5.01 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:45 PM PDT 24
Peak memory 222012 kb
Host smart-6ae1dc26-0b0f-4e7f-8ec9-73d1d111a3cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=353062353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.353062353
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.133587219
Short name T351
Test name
Test status
Simulation time 186746673 ps
CPU time 1.1 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 207592 kb
Host smart-3640fa3f-5e5c-4c10-99dc-151569288077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133587219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.133587219
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.187954821
Short name T897
Test name
Test status
Simulation time 7594042110 ps
CPU time 22.75 seconds
Started Mar 28 01:37:35 PM PDT 24
Finished Mar 28 01:37:58 PM PDT 24
Peak memory 216272 kb
Host smart-107ac5f4-9c71-4a47-b642-a50d78dec0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187954821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.187954821
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.807333791
Short name T49
Test name
Test status
Simulation time 2179388258 ps
CPU time 12.59 seconds
Started Mar 28 01:37:35 PM PDT 24
Finished Mar 28 01:37:48 PM PDT 24
Peak memory 216208 kb
Host smart-e4c8902d-a159-4864-bbcb-83f7c4f777f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807333791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.807333791
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2920736573
Short name T480
Test name
Test status
Simulation time 228475195 ps
CPU time 2.77 seconds
Started Mar 28 01:37:39 PM PDT 24
Finished Mar 28 01:37:43 PM PDT 24
Peak memory 216144 kb
Host smart-65813915-e31b-4cf4-8f4a-258840d7fa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920736573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2920736573
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3646981929
Short name T287
Test name
Test status
Simulation time 191871539 ps
CPU time 1.01 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:39 PM PDT 24
Peak memory 206604 kb
Host smart-641e0180-7aea-48ce-922d-5baef6dff76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646981929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3646981929
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2806380727
Short name T952
Test name
Test status
Simulation time 1568127076 ps
CPU time 6.34 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:44 PM PDT 24
Peak memory 237356 kb
Host smart-8fa9ca1d-190e-406f-a056-c068921730bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806380727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2806380727
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3892749413
Short name T388
Test name
Test status
Simulation time 14444394 ps
CPU time 0.68 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:39 PM PDT 24
Peak memory 204520 kb
Host smart-3d2b7a03-2473-4d80-9294-d580adbdd76d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892749413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3892749413
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.904557150
Short name T401
Test name
Test status
Simulation time 1353450365 ps
CPU time 4.55 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:45 PM PDT 24
Peak memory 235540 kb
Host smart-5fddaf76-a565-4b14-910f-f7dea21cf30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904557150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.904557150
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2168789050
Short name T334
Test name
Test status
Simulation time 13143516 ps
CPU time 0.72 seconds
Started Mar 28 01:37:33 PM PDT 24
Finished Mar 28 01:37:34 PM PDT 24
Peak memory 205496 kb
Host smart-1c97c824-05cf-453f-957e-c85e7ce8e223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168789050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2168789050
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3574147386
Short name T35
Test name
Test status
Simulation time 30081464708 ps
CPU time 83.71 seconds
Started Mar 28 01:37:40 PM PDT 24
Finished Mar 28 01:39:04 PM PDT 24
Peak memory 256960 kb
Host smart-231a9a27-dc85-4f0c-a4e7-d3c3ba5dd57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574147386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3574147386
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2370739242
Short name T340
Test name
Test status
Simulation time 26707181284 ps
CPU time 212.23 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:41:12 PM PDT 24
Peak memory 262308 kb
Host smart-fedff763-939e-4c17-9218-c856a897f6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370739242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2370739242
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.343453120
Short name T565
Test name
Test status
Simulation time 18469233892 ps
CPU time 29.05 seconds
Started Mar 28 01:37:37 PM PDT 24
Finished Mar 28 01:38:06 PM PDT 24
Peak memory 234620 kb
Host smart-212e9887-44e9-46f7-a818-64536290b81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343453120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.343453120
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4109776566
Short name T659
Test name
Test status
Simulation time 179238791 ps
CPU time 2.64 seconds
Started Mar 28 01:37:37 PM PDT 24
Finished Mar 28 01:37:40 PM PDT 24
Peak memory 232632 kb
Host smart-724c62fb-5e0f-4a0c-99aa-99ae892711da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109776566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4109776566
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2557804082
Short name T751
Test name
Test status
Simulation time 3852347462 ps
CPU time 6.49 seconds
Started Mar 28 01:37:39 PM PDT 24
Finished Mar 28 01:37:47 PM PDT 24
Peak memory 234120 kb
Host smart-a669aa0e-823f-4a8e-97a9-5ce1aeae7f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557804082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2557804082
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1029558624
Short name T788
Test name
Test status
Simulation time 158778771 ps
CPU time 2.44 seconds
Started Mar 28 01:37:36 PM PDT 24
Finished Mar 28 01:37:38 PM PDT 24
Peak memory 224276 kb
Host smart-5e4dcaac-a8b1-42a6-8853-c5ee08d3db7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029558624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1029558624
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.726919803
Short name T496
Test name
Test status
Simulation time 2105505468 ps
CPU time 6.89 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:47 PM PDT 24
Peak memory 224436 kb
Host smart-4dee113c-fb6c-40a4-aa13-2599cb9bd4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726919803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.726919803
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2925812565
Short name T904
Test name
Test status
Simulation time 715513737 ps
CPU time 5.72 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:46 PM PDT 24
Peak memory 222660 kb
Host smart-36f4dbc0-5ca7-4f45-88ee-cd0add0b94e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2925812565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2925812565
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3170381150
Short name T875
Test name
Test status
Simulation time 4993272211 ps
CPU time 7.81 seconds
Started Mar 28 01:37:36 PM PDT 24
Finished Mar 28 01:37:45 PM PDT 24
Peak memory 216168 kb
Host smart-31111bd0-6ea7-4d6c-9574-5c5fa325b803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170381150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3170381150
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4202412013
Short name T458
Test name
Test status
Simulation time 2512905039 ps
CPU time 6.71 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:44 PM PDT 24
Peak memory 216172 kb
Host smart-2088f0e3-e7bc-41ca-ae9f-85770dcccec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202412013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4202412013
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2800720568
Short name T871
Test name
Test status
Simulation time 51918613 ps
CPU time 0.85 seconds
Started Mar 28 01:37:36 PM PDT 24
Finished Mar 28 01:37:37 PM PDT 24
Peak memory 205524 kb
Host smart-212657e0-bd12-46d6-955f-9d7d5d74b624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800720568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2800720568
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3383309683
Short name T499
Test name
Test status
Simulation time 97470228 ps
CPU time 0.88 seconds
Started Mar 28 01:37:37 PM PDT 24
Finished Mar 28 01:37:38 PM PDT 24
Peak memory 205560 kb
Host smart-a5334084-d7c7-45fb-a283-3070f140eff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383309683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3383309683
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4065490059
Short name T769
Test name
Test status
Simulation time 846486392 ps
CPU time 4.73 seconds
Started Mar 28 01:37:36 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 218248 kb
Host smart-7c0bf9bc-68dd-400a-afc8-16b1d1ca5a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065490059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4065490059
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2741133223
Short name T856
Test name
Test status
Simulation time 20043781 ps
CPU time 0.74 seconds
Started Mar 28 01:36:00 PM PDT 24
Finished Mar 28 01:36:01 PM PDT 24
Peak memory 204560 kb
Host smart-08b329f6-fc53-4ab5-82c5-849863c49234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741133223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
741133223
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2993895656
Short name T958
Test name
Test status
Simulation time 1490841607 ps
CPU time 3.58 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:36:04 PM PDT 24
Peak memory 218528 kb
Host smart-3dfd2c3b-4898-4bbf-9822-2685a5a0f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993895656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2993895656
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.657982029
Short name T708
Test name
Test status
Simulation time 44342478 ps
CPU time 0.77 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:07 PM PDT 24
Peak memory 205156 kb
Host smart-be771ef7-a1b1-46dc-b408-c582a08d2e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657982029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.657982029
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2379904020
Short name T233
Test name
Test status
Simulation time 371023644357 ps
CPU time 208.45 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:39:29 PM PDT 24
Peak memory 265948 kb
Host smart-e4e87b4e-4198-4e96-99e0-890051f7ac6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379904020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2379904020
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3671669543
Short name T174
Test name
Test status
Simulation time 2543513653 ps
CPU time 36.56 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:36:38 PM PDT 24
Peak memory 252328 kb
Host smart-93635b2a-5f1f-4e2a-a541-42708c05092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671669543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3671669543
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2484363615
Short name T822
Test name
Test status
Simulation time 10515200962 ps
CPU time 37.51 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:36:39 PM PDT 24
Peak memory 232756 kb
Host smart-7b2d2282-6c54-4c21-bd0b-a57e745f3b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484363615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2484363615
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.112411567
Short name T369
Test name
Test status
Simulation time 7252206126 ps
CPU time 9.45 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:19 PM PDT 24
Peak memory 235104 kb
Host smart-dad2b386-b044-436c-b8c1-1eb17884dc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112411567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.112411567
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3962196067
Short name T339
Test name
Test status
Simulation time 3377650378 ps
CPU time 3.5 seconds
Started Mar 28 01:36:04 PM PDT 24
Finished Mar 28 01:36:08 PM PDT 24
Peak memory 233684 kb
Host smart-9f9dad33-d194-4489-b599-a9ce98f1e84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962196067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3962196067
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3773105288
Short name T482
Test name
Test status
Simulation time 13483307420 ps
CPU time 22.29 seconds
Started Mar 28 01:36:03 PM PDT 24
Finished Mar 28 01:36:25 PM PDT 24
Peak memory 238596 kb
Host smart-ac2d722b-bd50-477b-be19-9654e4ecaed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773105288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3773105288
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1610264222
Short name T622
Test name
Test status
Simulation time 26607834 ps
CPU time 1.07 seconds
Started Mar 28 01:36:03 PM PDT 24
Finished Mar 28 01:36:04 PM PDT 24
Peak memory 216508 kb
Host smart-890e055d-7399-4b2c-9e60-526e4a0c3f0b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610264222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1610264222
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.511385244
Short name T677
Test name
Test status
Simulation time 1031039835 ps
CPU time 3.33 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:09 PM PDT 24
Peak memory 218728 kb
Host smart-43e200d0-604b-44ff-8ca0-00c826c78018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511385244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
511385244
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.723842892
Short name T812
Test name
Test status
Simulation time 6578192734 ps
CPU time 10.69 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:16 PM PDT 24
Peak memory 224492 kb
Host smart-f840f887-dd74-4cbb-8d56-6f3c72873cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723842892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.723842892
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.2763012555
Short name T933
Test name
Test status
Simulation time 18482292 ps
CPU time 0.75 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:07 PM PDT 24
Peak memory 215984 kb
Host smart-fff16219-d024-41cb-b5b2-617f6a919185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763012555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.2763012555
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2553168344
Short name T696
Test name
Test status
Simulation time 534474711 ps
CPU time 3.34 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:13 PM PDT 24
Peak memory 218940 kb
Host smart-1910d98b-045e-49f5-ba39-96f5fedd6458
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2553168344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2553168344
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4292430109
Short name T61
Test name
Test status
Simulation time 339444584 ps
CPU time 1.06 seconds
Started Mar 28 01:36:08 PM PDT 24
Finished Mar 28 01:36:09 PM PDT 24
Peak memory 234516 kb
Host smart-9d32a3b2-df2e-417b-b8e3-fe270ee45454
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292430109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4292430109
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.325635294
Short name T130
Test name
Test status
Simulation time 14628588376 ps
CPU time 42.07 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:51 PM PDT 24
Peak memory 236780 kb
Host smart-778d89a1-d489-4cf1-9b33-8bcfc37ceae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325635294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.325635294
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1813919359
Short name T472
Test name
Test status
Simulation time 2347084833 ps
CPU time 33.17 seconds
Started Mar 28 01:35:58 PM PDT 24
Finished Mar 28 01:36:31 PM PDT 24
Peak memory 216208 kb
Host smart-feabae47-a296-41e5-a251-dd34983b4085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813919359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1813919359
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4079260222
Short name T890
Test name
Test status
Simulation time 1033669058 ps
CPU time 7.32 seconds
Started Mar 28 01:36:00 PM PDT 24
Finished Mar 28 01:36:08 PM PDT 24
Peak memory 216108 kb
Host smart-2e2e0575-b588-4b83-a417-5b53c2389275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079260222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4079260222
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.545654148
Short name T718
Test name
Test status
Simulation time 79200898 ps
CPU time 1.21 seconds
Started Mar 28 01:36:05 PM PDT 24
Finished Mar 28 01:36:06 PM PDT 24
Peak memory 216080 kb
Host smart-9871756f-88aa-428e-a003-7bcab415e26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545654148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.545654148
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3395155046
Short name T405
Test name
Test status
Simulation time 17842649 ps
CPU time 0.78 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:11 PM PDT 24
Peak memory 205520 kb
Host smart-1d28ff78-5a41-4bdb-a9a5-5e92ef76471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395155046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3395155046
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1020628116
Short name T543
Test name
Test status
Simulation time 835188586 ps
CPU time 3.49 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 218296 kb
Host smart-f48bd195-79fd-4965-8d95-523ddbe3374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020628116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1020628116
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1464236758
Short name T329
Test name
Test status
Simulation time 52769220 ps
CPU time 0.73 seconds
Started Mar 28 01:37:39 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 204592 kb
Host smart-f29160b3-3bc3-473f-b93f-cf701e6755d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464236758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1464236758
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1405443940
Short name T207
Test name
Test status
Simulation time 281446872 ps
CPU time 4.1 seconds
Started Mar 28 01:37:40 PM PDT 24
Finished Mar 28 01:37:45 PM PDT 24
Peak memory 236452 kb
Host smart-2d38c948-851a-474a-94f0-e3e32d221bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405443940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1405443940
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4018049569
Short name T853
Test name
Test status
Simulation time 75675679 ps
CPU time 0.83 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 206564 kb
Host smart-90b23f0a-3370-4c1f-a745-e4caccfa8da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018049569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4018049569
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.32823751
Short name T230
Test name
Test status
Simulation time 22600675482 ps
CPU time 28.94 seconds
Started Mar 28 01:37:48 PM PDT 24
Finished Mar 28 01:38:17 PM PDT 24
Peak memory 235004 kb
Host smart-14db3d2b-ae7e-4d60-a83f-fd055b06909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32823751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.32823751
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3393660375
Short name T253
Test name
Test status
Simulation time 9712648073 ps
CPU time 155.2 seconds
Started Mar 28 01:37:36 PM PDT 24
Finished Mar 28 01:40:12 PM PDT 24
Peak memory 260296 kb
Host smart-32a241a3-707e-4bf0-801d-ab364c8ae9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393660375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3393660375
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3862175895
Short name T722
Test name
Test status
Simulation time 128523241231 ps
CPU time 224.52 seconds
Started Mar 28 01:37:48 PM PDT 24
Finished Mar 28 01:41:33 PM PDT 24
Peak memory 267576 kb
Host smart-7416b028-42ed-44ca-a323-74ce5e52affe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862175895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3862175895
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2318389788
Short name T467
Test name
Test status
Simulation time 36639615707 ps
CPU time 24.69 seconds
Started Mar 28 01:37:40 PM PDT 24
Finished Mar 28 01:38:05 PM PDT 24
Peak memory 232620 kb
Host smart-dae51053-3a04-4417-80ae-2fc597838e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318389788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2318389788
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1050212217
Short name T167
Test name
Test status
Simulation time 1059846213 ps
CPU time 7.73 seconds
Started Mar 28 01:37:42 PM PDT 24
Finished Mar 28 01:37:50 PM PDT 24
Peak memory 233944 kb
Host smart-b49ddf2a-2ac3-4578-9e91-98c7ddb5882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050212217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1050212217
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3531865609
Short name T618
Test name
Test status
Simulation time 230063395 ps
CPU time 5.67 seconds
Started Mar 28 01:37:42 PM PDT 24
Finished Mar 28 01:37:47 PM PDT 24
Peak memory 232560 kb
Host smart-8fd6f6f8-5cf7-45aa-91b6-b7eba3b0c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531865609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3531865609
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1019072315
Short name T506
Test name
Test status
Simulation time 549584721 ps
CPU time 3.65 seconds
Started Mar 28 01:37:46 PM PDT 24
Finished Mar 28 01:37:51 PM PDT 24
Peak memory 233332 kb
Host smart-509a7050-be13-4353-ae91-40f1800ce531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019072315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1019072315
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3902949516
Short name T222
Test name
Test status
Simulation time 5987974013 ps
CPU time 9.78 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:50 PM PDT 24
Peak memory 218708 kb
Host smart-3bf37b5e-b411-405d-b721-4bbc6f33f8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902949516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3902949516
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3221715903
Short name T731
Test name
Test status
Simulation time 512359516 ps
CPU time 3.76 seconds
Started Mar 28 01:37:46 PM PDT 24
Finished Mar 28 01:37:51 PM PDT 24
Peak memory 221528 kb
Host smart-f51259e0-3535-4afa-8974-b56697bc61df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3221715903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3221715903
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.873034003
Short name T926
Test name
Test status
Simulation time 39228198 ps
CPU time 1.01 seconds
Started Mar 28 01:37:48 PM PDT 24
Finished Mar 28 01:37:49 PM PDT 24
Peak memory 206692 kb
Host smart-231e9853-61fc-4bdf-a782-6bcf9208e9a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873034003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.873034003
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3596372542
Short name T542
Test name
Test status
Simulation time 6402677295 ps
CPU time 24.06 seconds
Started Mar 28 01:37:34 PM PDT 24
Finished Mar 28 01:37:58 PM PDT 24
Peak memory 218416 kb
Host smart-c7e01c00-d5da-4603-96ee-33a9a54cbb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596372542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3596372542
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1805536286
Short name T734
Test name
Test status
Simulation time 14574275871 ps
CPU time 8.46 seconds
Started Mar 28 01:37:33 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 216268 kb
Host smart-1fd18533-8ebf-4721-b02c-6191706b9332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805536286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1805536286
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1517927959
Short name T273
Test name
Test status
Simulation time 210421568 ps
CPU time 2.94 seconds
Started Mar 28 01:37:41 PM PDT 24
Finished Mar 28 01:37:44 PM PDT 24
Peak memory 216140 kb
Host smart-e742a5fa-a61a-4a09-b6c0-a7ff3620decf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517927959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1517927959
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1865084617
Short name T374
Test name
Test status
Simulation time 174458223 ps
CPU time 0.83 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 205540 kb
Host smart-90f7c3d8-4684-4467-a822-e7345fa89b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865084617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1865084617
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3896456992
Short name T367
Test name
Test status
Simulation time 1453748591 ps
CPU time 11.2 seconds
Started Mar 28 01:37:42 PM PDT 24
Finished Mar 28 01:37:54 PM PDT 24
Peak memory 245884 kb
Host smart-72168fae-a0c7-4faa-9784-aac8468fc14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896456992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3896456992
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2018460099
Short name T848
Test name
Test status
Simulation time 56914750 ps
CPU time 0.77 seconds
Started Mar 28 01:37:44 PM PDT 24
Finished Mar 28 01:37:48 PM PDT 24
Peak memory 204512 kb
Host smart-dc4b5168-81c1-4031-b378-38cadef8bf90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018460099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2018460099
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3379901666
Short name T358
Test name
Test status
Simulation time 1604240770 ps
CPU time 4.44 seconds
Started Mar 28 01:37:43 PM PDT 24
Finished Mar 28 01:37:47 PM PDT 24
Peak memory 219516 kb
Host smart-54fd5426-bf04-47b3-a897-20cb571f3e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379901666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3379901666
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.933496578
Short name T556
Test name
Test status
Simulation time 43551021 ps
CPU time 0.8 seconds
Started Mar 28 01:37:48 PM PDT 24
Finished Mar 28 01:37:49 PM PDT 24
Peak memory 205200 kb
Host smart-401951ef-3a17-4251-81cc-84764c06013f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933496578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.933496578
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2468311823
Short name T450
Test name
Test status
Simulation time 399819048 ps
CPU time 4.34 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:37:54 PM PDT 24
Peak memory 227200 kb
Host smart-a2a7cb52-c09d-4f4e-aa92-524b9cf8dcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468311823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2468311823
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3987842518
Short name T366
Test name
Test status
Simulation time 4103529720 ps
CPU time 40.31 seconds
Started Mar 28 01:37:45 PM PDT 24
Finished Mar 28 01:38:28 PM PDT 24
Peak memory 222180 kb
Host smart-31ff5a0f-c3a1-4f33-ac2f-987cbf0ae6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987842518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3987842518
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.791557585
Short name T755
Test name
Test status
Simulation time 4842590521 ps
CPU time 14.36 seconds
Started Mar 28 01:37:37 PM PDT 24
Finished Mar 28 01:37:51 PM PDT 24
Peak memory 235680 kb
Host smart-a3eb0420-9d99-46d5-8ad1-45fa428a650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791557585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.791557585
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.186778830
Short name T3
Test name
Test status
Simulation time 441382034 ps
CPU time 3.82 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:37:53 PM PDT 24
Peak memory 219332 kb
Host smart-89392342-b019-4a1d-a8e1-0abec44f3321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186778830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.186778830
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1690613966
Short name T226
Test name
Test status
Simulation time 3778403741 ps
CPU time 25.03 seconds
Started Mar 28 01:37:41 PM PDT 24
Finished Mar 28 01:38:06 PM PDT 24
Peak memory 244900 kb
Host smart-cfae653e-7975-46a4-bf5d-d283ceed0646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690613966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1690613966
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2673013791
Short name T753
Test name
Test status
Simulation time 10667747531 ps
CPU time 11.86 seconds
Started Mar 28 01:37:42 PM PDT 24
Finished Mar 28 01:37:54 PM PDT 24
Peak memory 224508 kb
Host smart-d8f77a3b-d3ac-4f76-ac96-ab208fbe4def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673013791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2673013791
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1337009499
Short name T846
Test name
Test status
Simulation time 43620871249 ps
CPU time 21.67 seconds
Started Mar 28 01:37:43 PM PDT 24
Finished Mar 28 01:38:04 PM PDT 24
Peak memory 224444 kb
Host smart-ef5275e9-53ad-4829-9686-dbda7e6d5e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337009499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1337009499
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3371764684
Short name T298
Test name
Test status
Simulation time 975385329 ps
CPU time 5.26 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:37:55 PM PDT 24
Peak memory 220040 kb
Host smart-088e2904-8d8a-4062-a4d4-72b8fcbd9ff8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3371764684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3371764684
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3592762598
Short name T727
Test name
Test status
Simulation time 83728674 ps
CPU time 1.11 seconds
Started Mar 28 01:37:44 PM PDT 24
Finished Mar 28 01:37:48 PM PDT 24
Peak memory 206616 kb
Host smart-4be3c4e4-a93e-4960-b121-6ddcf991bc3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592762598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3592762598
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3435689993
Short name T468
Test name
Test status
Simulation time 9565245339 ps
CPU time 36.25 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:38:16 PM PDT 24
Peak memory 216264 kb
Host smart-fb7c44e6-3232-4641-84f5-4b92624671f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435689993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3435689993
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3191772277
Short name T381
Test name
Test status
Simulation time 1902105260 ps
CPU time 9.68 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:37:59 PM PDT 24
Peak memory 216188 kb
Host smart-7538fdd0-6453-46aa-bbe3-53f3a768eafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191772277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3191772277
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1916917166
Short name T272
Test name
Test status
Simulation time 23991082 ps
CPU time 0.76 seconds
Started Mar 28 01:37:37 PM PDT 24
Finished Mar 28 01:37:38 PM PDT 24
Peak memory 205580 kb
Host smart-0159f109-7054-4fbc-8b96-d4680771954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916917166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1916917166
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.136049020
Short name T917
Test name
Test status
Simulation time 80952482 ps
CPU time 1.05 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:37:51 PM PDT 24
Peak memory 206492 kb
Host smart-9a39328c-58fb-4cff-a220-620f1465e345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136049020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.136049020
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3299133960
Short name T652
Test name
Test status
Simulation time 1260226779 ps
CPU time 12 seconds
Started Mar 28 01:37:42 PM PDT 24
Finished Mar 28 01:37:54 PM PDT 24
Peak memory 230680 kb
Host smart-4153579f-aa5b-4d01-830b-cda385a14a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299133960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3299133960
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3032509528
Short name T774
Test name
Test status
Simulation time 34381053 ps
CPU time 0.7 seconds
Started Mar 28 01:37:46 PM PDT 24
Finished Mar 28 01:37:48 PM PDT 24
Peak memory 205164 kb
Host smart-40a12167-c599-4f0e-a1d8-cb0c89696fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032509528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3032509528
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.734584189
Short name T787
Test name
Test status
Simulation time 5916754823 ps
CPU time 5.68 seconds
Started Mar 28 01:37:40 PM PDT 24
Finished Mar 28 01:37:46 PM PDT 24
Peak memory 233688 kb
Host smart-652cbc5f-5cf3-48d4-a83d-132daaff7f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734584189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.734584189
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1861536173
Short name T921
Test name
Test status
Simulation time 19236029 ps
CPU time 0.79 seconds
Started Mar 28 01:37:44 PM PDT 24
Finished Mar 28 01:37:45 PM PDT 24
Peak memory 206520 kb
Host smart-558b982c-c46e-4db3-b0e1-cffa732acbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861536173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1861536173
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.953891744
Short name T156
Test name
Test status
Simulation time 183939907665 ps
CPU time 236.46 seconds
Started Mar 28 01:37:45 PM PDT 24
Finished Mar 28 01:41:44 PM PDT 24
Peak memory 255672 kb
Host smart-bc7993c5-bee0-4773-b228-327d6d5324b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953891744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.953891744
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.77630320
Short name T185
Test name
Test status
Simulation time 44026088509 ps
CPU time 290.52 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:42:40 PM PDT 24
Peak memory 249140 kb
Host smart-050608cf-24f0-48c6-8668-117542217c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77630320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.77630320
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3883185154
Short name T430
Test name
Test status
Simulation time 286511851687 ps
CPU time 524.48 seconds
Started Mar 28 01:37:36 PM PDT 24
Finished Mar 28 01:46:20 PM PDT 24
Peak memory 265496 kb
Host smart-9b031049-b78f-4762-8aa6-7dcb5710b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883185154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3883185154
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3505610176
Short name T816
Test name
Test status
Simulation time 1767336962 ps
CPU time 18.3 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:38:08 PM PDT 24
Peak memory 234768 kb
Host smart-d4a3999e-b620-4625-9eca-769a0058d0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505610176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3505610176
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.654922447
Short name T827
Test name
Test status
Simulation time 3909785648 ps
CPU time 6.92 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:47 PM PDT 24
Peak memory 235092 kb
Host smart-ddc9a932-6c50-4125-b1f3-1292252ea610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654922447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.654922447
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.986898903
Short name T220
Test name
Test status
Simulation time 18486414425 ps
CPU time 19.05 seconds
Started Mar 28 01:37:45 PM PDT 24
Finished Mar 28 01:38:06 PM PDT 24
Peak memory 232436 kb
Host smart-5d2b503a-ea14-4d8a-a339-d634f61e45a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986898903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.986898903
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2663125325
Short name T321
Test name
Test status
Simulation time 10358914381 ps
CPU time 9.75 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:50 PM PDT 24
Peak memory 233604 kb
Host smart-a1c49d93-8024-4310-a7d7-d1c5042fc98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663125325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2663125325
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2676493756
Short name T872
Test name
Test status
Simulation time 374857791 ps
CPU time 6.73 seconds
Started Mar 28 01:37:39 PM PDT 24
Finished Mar 28 01:37:47 PM PDT 24
Peak memory 228392 kb
Host smart-39a0cf00-b33e-4b7d-ad11-b2a244991c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676493756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2676493756
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3531741034
Short name T697
Test name
Test status
Simulation time 5093114443 ps
CPU time 6.39 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:37:56 PM PDT 24
Peak memory 222820 kb
Host smart-cd9d0719-ce49-4ef1-8582-2efaf6d0900a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3531741034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3531741034
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1000416174
Short name T2
Test name
Test status
Simulation time 16831983584 ps
CPU time 41.67 seconds
Started Mar 28 01:37:41 PM PDT 24
Finished Mar 28 01:38:22 PM PDT 24
Peak memory 216244 kb
Host smart-39fcb89a-2bba-4949-898c-219961e58be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000416174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1000416174
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3852829626
Short name T721
Test name
Test status
Simulation time 314781147 ps
CPU time 2.33 seconds
Started Mar 28 01:37:54 PM PDT 24
Finished Mar 28 01:37:56 PM PDT 24
Peak memory 215968 kb
Host smart-712e1f34-2151-4423-8443-db2999340551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852829626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3852829626
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1321603653
Short name T555
Test name
Test status
Simulation time 575181534 ps
CPU time 3.7 seconds
Started Mar 28 01:37:44 PM PDT 24
Finished Mar 28 01:37:47 PM PDT 24
Peak memory 216356 kb
Host smart-139589b5-5f89-4de2-8368-1804e8502d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321603653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1321603653
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3366613874
Short name T355
Test name
Test status
Simulation time 274393421 ps
CPU time 1.14 seconds
Started Mar 28 01:37:39 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 206568 kb
Host smart-4d7d3927-944a-4802-bb49-29504b911c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366613874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3366613874
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2011864108
Short name T665
Test name
Test status
Simulation time 27093871719 ps
CPU time 24.33 seconds
Started Mar 28 01:37:36 PM PDT 24
Finished Mar 28 01:38:00 PM PDT 24
Peak memory 240948 kb
Host smart-1284c314-5bd7-43fa-8660-b0b11b64d450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011864108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2011864108
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3564724177
Short name T425
Test name
Test status
Simulation time 36776548 ps
CPU time 0.74 seconds
Started Mar 28 01:37:51 PM PDT 24
Finished Mar 28 01:37:52 PM PDT 24
Peak memory 205220 kb
Host smart-f0727e6e-b8f9-497c-97c8-74358655a91f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564724177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3564724177
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3710478193
Short name T204
Test name
Test status
Simulation time 204887070 ps
CPU time 3.26 seconds
Started Mar 28 01:37:48 PM PDT 24
Finished Mar 28 01:37:51 PM PDT 24
Peak memory 233188 kb
Host smart-c8bb96f6-7007-40ca-ae8a-aebfe3119785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710478193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3710478193
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1005046472
Short name T314
Test name
Test status
Simulation time 61273920 ps
CPU time 0.77 seconds
Started Mar 28 01:37:40 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 205244 kb
Host smart-9c104eb3-0ee5-4882-9b25-b523345a23c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005046472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1005046472
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1098372118
Short name T240
Test name
Test status
Simulation time 45247995524 ps
CPU time 109.88 seconds
Started Mar 28 01:37:50 PM PDT 24
Finished Mar 28 01:39:40 PM PDT 24
Peak memory 249856 kb
Host smart-2e5580ca-402e-4b0e-ad18-04c88192e79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098372118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1098372118
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3516670710
Short name T4
Test name
Test status
Simulation time 53676173560 ps
CPU time 67.08 seconds
Started Mar 28 01:37:51 PM PDT 24
Finished Mar 28 01:38:58 PM PDT 24
Peak memory 222408 kb
Host smart-b0223f4a-a6a4-4b80-a54c-c8f93a22c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516670710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3516670710
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.14942326
Short name T459
Test name
Test status
Simulation time 8110083625 ps
CPU time 22.93 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:38:01 PM PDT 24
Peak memory 232684 kb
Host smart-3d3d63fc-df73-4667-aa9d-d5d952b65a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14942326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.14942326
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3757588616
Short name T177
Test name
Test status
Simulation time 223003475 ps
CPU time 4.07 seconds
Started Mar 28 01:37:46 PM PDT 24
Finished Mar 28 01:37:51 PM PDT 24
Peak memory 217860 kb
Host smart-61f1047b-606e-4f2e-98af-0eb335bc323b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757588616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3757588616
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1891310251
Short name T587
Test name
Test status
Simulation time 185752982 ps
CPU time 3.14 seconds
Started Mar 28 01:37:40 PM PDT 24
Finished Mar 28 01:37:43 PM PDT 24
Peak memory 235900 kb
Host smart-2070cf36-3cc6-4dd3-8f68-cf649814c048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891310251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1891310251
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.573930518
Short name T929
Test name
Test status
Simulation time 5646204481 ps
CPU time 17.44 seconds
Started Mar 28 01:37:41 PM PDT 24
Finished Mar 28 01:37:59 PM PDT 24
Peak memory 234308 kb
Host smart-16d22c9f-3735-4e3f-9230-8356093798f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573930518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.573930518
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2670478492
Short name T770
Test name
Test status
Simulation time 120398930 ps
CPU time 2.96 seconds
Started Mar 28 01:37:46 PM PDT 24
Finished Mar 28 01:37:50 PM PDT 24
Peak memory 234836 kb
Host smart-17b09966-7cc6-47a9-9d63-8d9b83651823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670478492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2670478492
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2354931851
Short name T426
Test name
Test status
Simulation time 79160568 ps
CPU time 3.06 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:43 PM PDT 24
Peak memory 218560 kb
Host smart-736bfa97-6c79-4d0f-86d9-25f673826ed7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2354931851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2354931851
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2160819703
Short name T863
Test name
Test status
Simulation time 10512550868 ps
CPU time 32.17 seconds
Started Mar 28 01:37:42 PM PDT 24
Finished Mar 28 01:38:15 PM PDT 24
Peak memory 216128 kb
Host smart-7d1f055b-88b1-4488-a3f0-f96fa2020c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160819703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2160819703
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.181842490
Short name T679
Test name
Test status
Simulation time 2092545657 ps
CPU time 7.79 seconds
Started Mar 28 01:37:38 PM PDT 24
Finished Mar 28 01:37:48 PM PDT 24
Peak memory 216164 kb
Host smart-16b4dce9-b5a6-48c0-892d-3024ebc49222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181842490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.181842490
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.501537371
Short name T64
Test name
Test status
Simulation time 59581508 ps
CPU time 1.88 seconds
Started Mar 28 01:37:46 PM PDT 24
Finished Mar 28 01:37:49 PM PDT 24
Peak memory 216124 kb
Host smart-001579f4-13a1-4983-ace7-a9cd92dfc839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501537371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.501537371
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.45313950
Short name T396
Test name
Test status
Simulation time 185462449 ps
CPU time 0.94 seconds
Started Mar 28 01:37:46 PM PDT 24
Finished Mar 28 01:37:48 PM PDT 24
Peak memory 205536 kb
Host smart-64489bd9-e62c-4b91-a6a2-e3ac68783062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45313950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.45313950
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4164047015
Short name T551
Test name
Test status
Simulation time 542547792 ps
CPU time 6.06 seconds
Started Mar 28 01:37:48 PM PDT 24
Finished Mar 28 01:37:54 PM PDT 24
Peak memory 230684 kb
Host smart-c85fb791-6fda-4bf1-b1cf-e6252baf5740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164047015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4164047015
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3136710272
Short name T486
Test name
Test status
Simulation time 13820744 ps
CPU time 0.72 seconds
Started Mar 28 01:37:51 PM PDT 24
Finished Mar 28 01:37:52 PM PDT 24
Peak memory 204604 kb
Host smart-ef034685-f0b5-4d62-af32-7dee7a2ede8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136710272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3136710272
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3545476861
Short name T209
Test name
Test status
Simulation time 146248997 ps
CPU time 2.62 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:37:52 PM PDT 24
Peak memory 233672 kb
Host smart-75f9c115-b1c3-4ef5-97c1-43dee036cea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545476861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3545476861
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1340904722
Short name T548
Test name
Test status
Simulation time 16617567 ps
CPU time 0.78 seconds
Started Mar 28 01:37:58 PM PDT 24
Finished Mar 28 01:37:59 PM PDT 24
Peak memory 205528 kb
Host smart-37f6badc-137c-438d-94c1-f0ba2721be24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340904722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1340904722
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3596522510
Short name T175
Test name
Test status
Simulation time 92184037584 ps
CPU time 410.58 seconds
Started Mar 28 01:37:52 PM PDT 24
Finished Mar 28 01:44:43 PM PDT 24
Peak memory 249764 kb
Host smart-f8832468-6aff-4cec-9a8c-0cc709c4a027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596522510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3596522510
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1323111500
Short name T441
Test name
Test status
Simulation time 16549354435 ps
CPU time 161.16 seconds
Started Mar 28 01:37:52 PM PDT 24
Finished Mar 28 01:40:33 PM PDT 24
Peak memory 257388 kb
Host smart-f6741069-bcdc-4354-be38-a9a21f89e54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323111500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1323111500
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.510834348
Short name T248
Test name
Test status
Simulation time 48330044474 ps
CPU time 229.71 seconds
Started Mar 28 01:37:52 PM PDT 24
Finished Mar 28 01:41:42 PM PDT 24
Peak memory 265948 kb
Host smart-94cfea18-5d39-4032-82d8-01c91f84ce0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510834348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.510834348
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3955041905
Short name T354
Test name
Test status
Simulation time 5118429696 ps
CPU time 19.5 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:38:09 PM PDT 24
Peak memory 234612 kb
Host smart-4bb3d0df-4e5f-47ab-b1f2-52901bfa8d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955041905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3955041905
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1909290939
Short name T966
Test name
Test status
Simulation time 388890588 ps
CPU time 3.59 seconds
Started Mar 28 01:37:50 PM PDT 24
Finished Mar 28 01:37:54 PM PDT 24
Peak memory 218336 kb
Host smart-3eb1fa78-2f2f-44fa-9470-0222891bf96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909290939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1909290939
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2025657194
Short name T513
Test name
Test status
Simulation time 28692592009 ps
CPU time 28.53 seconds
Started Mar 28 01:37:59 PM PDT 24
Finished Mar 28 01:38:28 PM PDT 24
Peak memory 245912 kb
Host smart-12589552-32de-436d-a030-9dd3eb8db9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025657194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2025657194
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2110979725
Short name T191
Test name
Test status
Simulation time 889104586 ps
CPU time 6.53 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:38:03 PM PDT 24
Peak memory 218012 kb
Host smart-a2045a3e-2f41-42ca-89d9-42f515eca4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110979725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2110979725
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.378477457
Short name T359
Test name
Test status
Simulation time 3031648061 ps
CPU time 6.88 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:38:03 PM PDT 24
Peak memory 224484 kb
Host smart-1e64e932-96a8-4766-b665-9ff4b978c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378477457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.378477457
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3638958903
Short name T693
Test name
Test status
Simulation time 342726570 ps
CPU time 3.87 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:38:00 PM PDT 24
Peak memory 222192 kb
Host smart-08d41c7f-b1b5-47a6-b8fa-3985727fad38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3638958903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3638958903
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4176734797
Short name T522
Test name
Test status
Simulation time 123815835 ps
CPU time 1.02 seconds
Started Mar 28 01:37:52 PM PDT 24
Finished Mar 28 01:37:53 PM PDT 24
Peak memory 206428 kb
Host smart-7677c862-0584-4b0a-b960-eb7e1ae61e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176734797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4176734797
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1812366076
Short name T855
Test name
Test status
Simulation time 7813682049 ps
CPU time 25.73 seconds
Started Mar 28 01:37:53 PM PDT 24
Finished Mar 28 01:38:19 PM PDT 24
Peak memory 216260 kb
Host smart-80734dc5-2b30-4742-8615-470d4e16f935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812366076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1812366076
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3363207059
Short name T514
Test name
Test status
Simulation time 3406057909 ps
CPU time 7.36 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:38:03 PM PDT 24
Peak memory 216196 kb
Host smart-ddb4554a-8f04-432a-b163-2b6ea508191a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363207059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3363207059
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2245221839
Short name T631
Test name
Test status
Simulation time 431845286 ps
CPU time 3.57 seconds
Started Mar 28 01:37:53 PM PDT 24
Finished Mar 28 01:37:57 PM PDT 24
Peak memory 216124 kb
Host smart-4391fb4e-9ddc-42f3-8d02-c9b09d728cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245221839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2245221839
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3885731818
Short name T311
Test name
Test status
Simulation time 95042122 ps
CPU time 0.84 seconds
Started Mar 28 01:37:57 PM PDT 24
Finished Mar 28 01:37:58 PM PDT 24
Peak memory 205532 kb
Host smart-267b0cc0-947b-4bb8-894e-73f5aba2ff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885731818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3885731818
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.223090100
Short name T352
Test name
Test status
Simulation time 9698381769 ps
CPU time 16.41 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:38:12 PM PDT 24
Peak memory 223932 kb
Host smart-d259d4e7-780f-42fe-9dc9-fb3637bc44ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223090100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.223090100
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.757835277
Short name T776
Test name
Test status
Simulation time 54933683 ps
CPU time 0.68 seconds
Started Mar 28 01:37:54 PM PDT 24
Finished Mar 28 01:37:54 PM PDT 24
Peak memory 205092 kb
Host smart-c84937b3-8ad7-45ef-9ee4-97903d56eb99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757835277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.757835277
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.874649323
Short name T843
Test name
Test status
Simulation time 390381189 ps
CPU time 3.15 seconds
Started Mar 28 01:37:54 PM PDT 24
Finished Mar 28 01:37:58 PM PDT 24
Peak memory 218292 kb
Host smart-f6d2ecae-fb05-4c59-8e57-a999bccd5163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874649323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.874649323
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2566863779
Short name T749
Test name
Test status
Simulation time 38630129 ps
CPU time 0.81 seconds
Started Mar 28 01:37:50 PM PDT 24
Finished Mar 28 01:37:51 PM PDT 24
Peak memory 206248 kb
Host smart-4872eec5-e8d4-4ee3-86f3-cb2fb770df54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566863779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2566863779
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.541483958
Short name T68
Test name
Test status
Simulation time 32161074274 ps
CPU time 39.36 seconds
Started Mar 28 01:37:51 PM PDT 24
Finished Mar 28 01:38:30 PM PDT 24
Peak memory 232536 kb
Host smart-52b14d12-fb62-4c24-86ac-5ffe1a592d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541483958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.541483958
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.308497203
Short name T680
Test name
Test status
Simulation time 5183827469 ps
CPU time 65.76 seconds
Started Mar 28 01:37:52 PM PDT 24
Finished Mar 28 01:38:58 PM PDT 24
Peak memory 249964 kb
Host smart-56ea69d6-a74d-4041-9778-d1a1572265a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308497203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.308497203
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2004279855
Short name T283
Test name
Test status
Simulation time 3115686826 ps
CPU time 34.69 seconds
Started Mar 28 01:37:54 PM PDT 24
Finished Mar 28 01:38:29 PM PDT 24
Peak memory 234352 kb
Host smart-1d3a0445-226a-44ea-af33-7960a1a2d86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004279855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2004279855
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3264035178
Short name T376
Test name
Test status
Simulation time 4080797672 ps
CPU time 25.07 seconds
Started Mar 28 01:37:52 PM PDT 24
Finished Mar 28 01:38:17 PM PDT 24
Peak memory 231760 kb
Host smart-9383f9de-a12c-4e9b-871c-87f4e4d06cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264035178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3264035178
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2764719144
Short name T198
Test name
Test status
Simulation time 6276151249 ps
CPU time 5.46 seconds
Started Mar 28 01:37:54 PM PDT 24
Finished Mar 28 01:38:00 PM PDT 24
Peak memory 224452 kb
Host smart-97a2da37-b839-4c81-b9a5-8e89d459a8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764719144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2764719144
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2443172443
Short name T578
Test name
Test status
Simulation time 11030206827 ps
CPU time 12.95 seconds
Started Mar 28 01:37:53 PM PDT 24
Finished Mar 28 01:38:06 PM PDT 24
Peak memory 233700 kb
Host smart-52bf21b0-0edc-4ee8-8c9c-cf8589eb3c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443172443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2443172443
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2682877565
Short name T612
Test name
Test status
Simulation time 149802115 ps
CPU time 3.98 seconds
Started Mar 28 01:37:52 PM PDT 24
Finished Mar 28 01:37:56 PM PDT 24
Peak memory 235912 kb
Host smart-35a60529-a605-4a92-8dc0-3ef769b4500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682877565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2682877565
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1858701479
Short name T640
Test name
Test status
Simulation time 9400039882 ps
CPU time 8.22 seconds
Started Mar 28 01:37:52 PM PDT 24
Finished Mar 28 01:38:01 PM PDT 24
Peak memory 233664 kb
Host smart-e9944056-7d02-48ca-b832-7139a3843d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858701479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1858701479
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2504803090
Short name T303
Test name
Test status
Simulation time 1381644490 ps
CPU time 6.63 seconds
Started Mar 28 01:37:54 PM PDT 24
Finished Mar 28 01:38:00 PM PDT 24
Peak memory 222140 kb
Host smart-4d5124f9-2547-4938-9b75-612cb45c3b50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2504803090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2504803090
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2670359243
Short name T250
Test name
Test status
Simulation time 47826066140 ps
CPU time 158.68 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:40:35 PM PDT 24
Peak memory 257044 kb
Host smart-c240937e-da44-4658-85a8-0a854c9b9151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670359243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2670359243
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2498084791
Short name T798
Test name
Test status
Simulation time 1985231291 ps
CPU time 10.1 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:38:00 PM PDT 24
Peak memory 216156 kb
Host smart-5c8c3ef1-9ce8-4335-9aae-528eed3116b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498084791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2498084791
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.904834086
Short name T301
Test name
Test status
Simulation time 4318904012 ps
CPU time 17.38 seconds
Started Mar 28 01:37:50 PM PDT 24
Finished Mar 28 01:38:08 PM PDT 24
Peak memory 216300 kb
Host smart-6282f0c8-73a4-46ea-843b-765ae4741485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904834086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.904834086
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4115748085
Short name T922
Test name
Test status
Simulation time 16977446 ps
CPU time 0.84 seconds
Started Mar 28 01:37:53 PM PDT 24
Finished Mar 28 01:37:54 PM PDT 24
Peak memory 205064 kb
Host smart-e8e1e757-3fd0-4da9-b3c3-06ca204e9733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115748085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4115748085
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.274501128
Short name T487
Test name
Test status
Simulation time 238010456 ps
CPU time 1.02 seconds
Started Mar 28 01:37:50 PM PDT 24
Finished Mar 28 01:37:52 PM PDT 24
Peak memory 206560 kb
Host smart-82d6e710-d307-4370-b070-6478692b5ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274501128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.274501128
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1040942277
Short name T956
Test name
Test status
Simulation time 275961705 ps
CPU time 4.73 seconds
Started Mar 28 01:37:49 PM PDT 24
Finished Mar 28 01:37:54 PM PDT 24
Peak memory 217640 kb
Host smart-15dd7db6-544d-46d2-b869-ecf6513c12e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040942277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1040942277
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3043243380
Short name T552
Test name
Test status
Simulation time 10405362 ps
CPU time 0.72 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:37:57 PM PDT 24
Peak memory 205208 kb
Host smart-71046b9d-3fdb-407d-aa16-df383eaea08d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043243380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3043243380
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.4148280202
Short name T192
Test name
Test status
Simulation time 155346782 ps
CPU time 2.63 seconds
Started Mar 28 01:38:06 PM PDT 24
Finished Mar 28 01:38:09 PM PDT 24
Peak memory 218288 kb
Host smart-8984aa83-da4d-43fd-9477-e502a68d821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148280202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4148280202
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.717908628
Short name T451
Test name
Test status
Simulation time 50256862 ps
CPU time 0.73 seconds
Started Mar 28 01:37:48 PM PDT 24
Finished Mar 28 01:37:49 PM PDT 24
Peak memory 206592 kb
Host smart-d72c2e85-8bf0-4cfb-a487-86688399a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717908628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.717908628
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3883900490
Short name T739
Test name
Test status
Simulation time 98390275627 ps
CPU time 120.95 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:39:57 PM PDT 24
Peak memory 240856 kb
Host smart-b47465a6-5b41-4fe1-aa9c-d8e6cadfa940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883900490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3883900490
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1517796781
Short name T387
Test name
Test status
Simulation time 124870552341 ps
CPU time 194.82 seconds
Started Mar 28 01:38:02 PM PDT 24
Finished Mar 28 01:41:17 PM PDT 24
Peak memory 249156 kb
Host smart-27769666-5fa8-4e0f-add3-2cf1dc41ad62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517796781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1517796781
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2312160604
Short name T16
Test name
Test status
Simulation time 3066811304 ps
CPU time 54.9 seconds
Started Mar 28 01:38:03 PM PDT 24
Finished Mar 28 01:38:58 PM PDT 24
Peak memory 240540 kb
Host smart-6d48e233-f1dc-4518-a79d-9994c316aa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312160604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2312160604
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2314382540
Short name T271
Test name
Test status
Simulation time 38063800106 ps
CPU time 50.6 seconds
Started Mar 28 01:37:53 PM PDT 24
Finished Mar 28 01:38:43 PM PDT 24
Peak memory 255380 kb
Host smart-e79baf36-b914-406d-86a6-2322f5685218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314382540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2314382540
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3412974458
Short name T981
Test name
Test status
Simulation time 820132655 ps
CPU time 5.02 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:38:02 PM PDT 24
Peak memory 233252 kb
Host smart-b065c10f-698c-40f4-841b-54c7e043863f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412974458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3412974458
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.733155420
Short name T265
Test name
Test status
Simulation time 5605627815 ps
CPU time 6.06 seconds
Started Mar 28 01:37:54 PM PDT 24
Finished Mar 28 01:38:00 PM PDT 24
Peak memory 240824 kb
Host smart-ab0a1e34-28a9-49d1-ab3e-82f9cddd75a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733155420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.733155420
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2855638166
Short name T27
Test name
Test status
Simulation time 91497628 ps
CPU time 3.28 seconds
Started Mar 28 01:37:57 PM PDT 24
Finished Mar 28 01:38:01 PM PDT 24
Peak memory 233696 kb
Host smart-779f2113-5e83-4bb2-b3e6-4a7b70da36d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855638166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2855638166
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1101465075
Short name T766
Test name
Test status
Simulation time 13254960854 ps
CPU time 33.31 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:38:29 PM PDT 24
Peak memory 229100 kb
Host smart-0c4ce13e-eae9-4c94-a876-24f28e370cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101465075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1101465075
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.661943489
Short name T357
Test name
Test status
Simulation time 1949099062 ps
CPU time 3.45 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:37:59 PM PDT 24
Peak memory 218428 kb
Host smart-c54e9078-64cb-43e8-834d-c2ddbf80e8bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=661943489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.661943489
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2150033988
Short name T870
Test name
Test status
Simulation time 41721925829 ps
CPU time 326.19 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:43:23 PM PDT 24
Peak memory 272552 kb
Host smart-0975b24b-5cce-4bee-a5fb-67c7e37b131b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150033988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2150033988
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.334203434
Short name T536
Test name
Test status
Simulation time 307075503 ps
CPU time 3.97 seconds
Started Mar 28 01:37:53 PM PDT 24
Finished Mar 28 01:37:58 PM PDT 24
Peak memory 216384 kb
Host smart-62a0557a-7794-4e55-9e23-7417936e696e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334203434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.334203434
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2704374686
Short name T789
Test name
Test status
Simulation time 886163826 ps
CPU time 8.26 seconds
Started Mar 28 01:37:53 PM PDT 24
Finished Mar 28 01:38:02 PM PDT 24
Peak memory 216096 kb
Host smart-a6d191f9-9efd-4a3e-9f19-0d5f8dba7089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704374686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2704374686
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3842014954
Short name T307
Test name
Test status
Simulation time 27548644 ps
CPU time 1 seconds
Started Mar 28 01:37:50 PM PDT 24
Finished Mar 28 01:37:51 PM PDT 24
Peak memory 206556 kb
Host smart-f82de963-2363-4b31-a3cd-6b1318c0a9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842014954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3842014954
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1228151310
Short name T894
Test name
Test status
Simulation time 395022542 ps
CPU time 1.02 seconds
Started Mar 28 01:37:54 PM PDT 24
Finished Mar 28 01:37:56 PM PDT 24
Peak memory 205804 kb
Host smart-e07fc10d-3764-4dcb-a1f8-bb2e1d14fe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228151310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1228151310
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1567183752
Short name T172
Test name
Test status
Simulation time 2382335103 ps
CPU time 9.5 seconds
Started Mar 28 01:37:52 PM PDT 24
Finished Mar 28 01:38:02 PM PDT 24
Peak memory 218764 kb
Host smart-42b290eb-5c04-4a50-a8cd-d84ff913832d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567183752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1567183752
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1859081397
Short name T519
Test name
Test status
Simulation time 11862218 ps
CPU time 0.76 seconds
Started Mar 28 01:37:59 PM PDT 24
Finished Mar 28 01:38:00 PM PDT 24
Peak memory 205168 kb
Host smart-ff80b8ce-7d1a-4e97-b498-a5866e998197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859081397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1859081397
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1416929014
Short name T914
Test name
Test status
Simulation time 2960490115 ps
CPU time 6.47 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:38:02 PM PDT 24
Peak memory 233716 kb
Host smart-691e53a9-abf9-4f95-8205-0db957566a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416929014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1416929014
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.944742309
Short name T828
Test name
Test status
Simulation time 68502894 ps
CPU time 0.8 seconds
Started Mar 28 01:37:54 PM PDT 24
Finished Mar 28 01:37:55 PM PDT 24
Peak memory 206184 kb
Host smart-7c189813-b300-4081-863d-44fc3eb1324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944742309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.944742309
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1777015792
Short name T246
Test name
Test status
Simulation time 359276896568 ps
CPU time 363.17 seconds
Started Mar 28 01:37:57 PM PDT 24
Finished Mar 28 01:44:01 PM PDT 24
Peak memory 265164 kb
Host smart-df8c3d0a-46c7-4150-a8cb-bc4bbd4f260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777015792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1777015792
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.82107723
Short name T244
Test name
Test status
Simulation time 34919914979 ps
CPU time 211.75 seconds
Started Mar 28 01:37:50 PM PDT 24
Finished Mar 28 01:41:22 PM PDT 24
Peak memory 266832 kb
Host smart-75503ff1-2ec0-4340-81f9-8fdfadd17fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82107723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.82107723
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3798120518
Short name T474
Test name
Test status
Simulation time 10694281528 ps
CPU time 41.43 seconds
Started Mar 28 01:37:50 PM PDT 24
Finished Mar 28 01:38:32 PM PDT 24
Peak memory 249120 kb
Host smart-26864f78-5d56-467a-96e7-4d869fd2485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798120518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3798120518
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.477893727
Short name T532
Test name
Test status
Simulation time 1452691827 ps
CPU time 11.4 seconds
Started Mar 28 01:37:50 PM PDT 24
Finished Mar 28 01:38:02 PM PDT 24
Peak memory 240736 kb
Host smart-e6ecc775-2082-437a-bf9b-8c7eb3cdd355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477893727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.477893727
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.767331938
Short name T910
Test name
Test status
Simulation time 7563030985 ps
CPU time 11.7 seconds
Started Mar 28 01:37:57 PM PDT 24
Finished Mar 28 01:38:09 PM PDT 24
Peak memory 219800 kb
Host smart-7ed0b0ab-882f-40c4-a0b4-854cf64e4e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767331938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.767331938
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4141068154
Short name T212
Test name
Test status
Simulation time 22838885418 ps
CPU time 16.87 seconds
Started Mar 28 01:37:55 PM PDT 24
Finished Mar 28 01:38:12 PM PDT 24
Peak memory 237416 kb
Host smart-af6212db-8e00-4fdc-938a-e7a91ce8e166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141068154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4141068154
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2660960585
Short name T533
Test name
Test status
Simulation time 7473813780 ps
CPU time 20.78 seconds
Started Mar 28 01:37:54 PM PDT 24
Finished Mar 28 01:38:16 PM PDT 24
Peak memory 232628 kb
Host smart-6ca9b38e-0e97-4fa4-9b85-a0dbfe329cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660960585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2660960585
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3268645918
Short name T765
Test name
Test status
Simulation time 377904961 ps
CPU time 3.75 seconds
Started Mar 28 01:38:02 PM PDT 24
Finished Mar 28 01:38:06 PM PDT 24
Peak memory 219388 kb
Host smart-19e72713-8934-4e61-b0ea-372baef7504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268645918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3268645918
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.691922074
Short name T950
Test name
Test status
Simulation time 726435189 ps
CPU time 5.23 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:38:01 PM PDT 24
Peak memory 221456 kb
Host smart-d575f69e-d40f-4c39-b1fe-9b8cf4d4c9de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=691922074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.691922074
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3531448776
Short name T529
Test name
Test status
Simulation time 2332666243 ps
CPU time 36.14 seconds
Started Mar 28 01:37:53 PM PDT 24
Finished Mar 28 01:38:29 PM PDT 24
Peak memory 215832 kb
Host smart-dfe53376-7462-48be-9f66-942ecd4c640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531448776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3531448776
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3585702943
Short name T669
Test name
Test status
Simulation time 2245787632 ps
CPU time 4.65 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:38:00 PM PDT 24
Peak memory 216292 kb
Host smart-f2955608-8dff-4dda-b8bf-3e7a13c5e29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585702943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3585702943
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3327504909
Short name T668
Test name
Test status
Simulation time 439773174 ps
CPU time 7.24 seconds
Started Mar 28 01:37:55 PM PDT 24
Finished Mar 28 01:38:02 PM PDT 24
Peak memory 216200 kb
Host smart-033494c0-4876-4ca4-839b-1868707e6092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327504909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3327504909
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2463412926
Short name T464
Test name
Test status
Simulation time 64091349 ps
CPU time 0.88 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:37:57 PM PDT 24
Peak memory 205600 kb
Host smart-055188bf-45ee-471c-a079-0ce57daa09a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463412926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2463412926
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.4084710083
Short name T210
Test name
Test status
Simulation time 263790226 ps
CPU time 2.59 seconds
Started Mar 28 01:37:56 PM PDT 24
Finished Mar 28 01:37:58 PM PDT 24
Peak memory 233248 kb
Host smart-25cc3fbf-192e-4b69-8bac-16685a941918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084710083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.4084710083
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.969555121
Short name T290
Test name
Test status
Simulation time 42247826 ps
CPU time 0.7 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:18 PM PDT 24
Peak memory 205404 kb
Host smart-d220f042-fd68-488f-9b45-dc008c1c5b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969555121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.969555121
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.462175747
Short name T264
Test name
Test status
Simulation time 798523546 ps
CPU time 3.07 seconds
Started Mar 28 01:38:14 PM PDT 24
Finished Mar 28 01:38:17 PM PDT 24
Peak memory 224416 kb
Host smart-3da99717-7ff5-43f8-a0d8-b64589e34876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462175747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.462175747
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2441888138
Short name T274
Test name
Test status
Simulation time 16720017 ps
CPU time 0.79 seconds
Started Mar 28 01:38:15 PM PDT 24
Finished Mar 28 01:38:16 PM PDT 24
Peak memory 205176 kb
Host smart-0ddf09fc-4376-4cba-9946-affdf084163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441888138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2441888138
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2947655258
Short name T672
Test name
Test status
Simulation time 41084429410 ps
CPU time 93.78 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:39:50 PM PDT 24
Peak memory 240852 kb
Host smart-5d9f7eba-37ee-4e52-87d3-e08eade8b033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947655258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2947655258
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1340402723
Short name T762
Test name
Test status
Simulation time 506972778078 ps
CPU time 208.12 seconds
Started Mar 28 01:38:14 PM PDT 24
Finished Mar 28 01:41:42 PM PDT 24
Peak memory 249132 kb
Host smart-5f3416cf-0b7b-4c7e-ae85-5c0c45524926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340402723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1340402723
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1868261464
Short name T227
Test name
Test status
Simulation time 13195511269 ps
CPU time 92.51 seconds
Started Mar 28 01:38:15 PM PDT 24
Finished Mar 28 01:39:48 PM PDT 24
Peak memory 235848 kb
Host smart-1df8dfa6-6a60-49d5-b7f5-1348030692a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868261464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1868261464
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4142389758
Short name T643
Test name
Test status
Simulation time 3392186029 ps
CPU time 17.97 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:35 PM PDT 24
Peak memory 234872 kb
Host smart-db8ff608-9ba0-4abe-9931-182c1cd6f577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142389758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4142389758
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3772254494
Short name T850
Test name
Test status
Simulation time 151889096 ps
CPU time 3.43 seconds
Started Mar 28 01:38:13 PM PDT 24
Finished Mar 28 01:38:17 PM PDT 24
Peak memory 233644 kb
Host smart-dc67bd78-275c-4551-ba8c-292e3bbc6595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772254494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3772254494
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1140370953
Short name T206
Test name
Test status
Simulation time 5130202062 ps
CPU time 15.06 seconds
Started Mar 28 01:38:12 PM PDT 24
Finished Mar 28 01:38:27 PM PDT 24
Peak memory 222224 kb
Host smart-25dac789-a8d0-478c-b4c4-aab5b3cbae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140370953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1140370953
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2590981857
Short name T215
Test name
Test status
Simulation time 54873610995 ps
CPU time 39.83 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:57 PM PDT 24
Peak memory 247236 kb
Host smart-6e3fa50e-c03a-47e5-a85b-ab1260a4af0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590981857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2590981857
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.690764000
Short name T582
Test name
Test status
Simulation time 1353544671 ps
CPU time 5.2 seconds
Started Mar 28 01:38:11 PM PDT 24
Finished Mar 28 01:38:17 PM PDT 24
Peak memory 224444 kb
Host smart-b2367a70-275e-49e6-88be-7da9684ecd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690764000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.690764000
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1449943488
Short name T9
Test name
Test status
Simulation time 1404258828 ps
CPU time 6.75 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:25 PM PDT 24
Peak memory 222604 kb
Host smart-78775e78-d6f7-4652-a525-27aa5d2f9b49
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449943488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1449943488
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4031239285
Short name T313
Test name
Test status
Simulation time 2240212741 ps
CPU time 23.91 seconds
Started Mar 28 01:38:13 PM PDT 24
Finished Mar 28 01:38:37 PM PDT 24
Peak memory 216228 kb
Host smart-9562f5c2-b658-4df3-a230-528fc2bb0fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031239285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4031239285
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.257445335
Short name T560
Test name
Test status
Simulation time 4973522591 ps
CPU time 6.97 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:38:23 PM PDT 24
Peak memory 216292 kb
Host smart-f7408336-33b2-4383-8362-2fb4595bdc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257445335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.257445335
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2027844536
Short name T579
Test name
Test status
Simulation time 472175795 ps
CPU time 1.86 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 216196 kb
Host smart-b4d7b6c4-4780-49aa-87e2-2a1b858d551b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027844536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2027844536
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2020055620
Short name T406
Test name
Test status
Simulation time 15265344 ps
CPU time 0.72 seconds
Started Mar 28 01:38:12 PM PDT 24
Finished Mar 28 01:38:13 PM PDT 24
Peak memory 205536 kb
Host smart-5c6b6d66-18d4-4756-98ff-3608f0179ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020055620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2020055620
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3672724200
Short name T67
Test name
Test status
Simulation time 16568686100 ps
CPU time 15.72 seconds
Started Mar 28 01:38:12 PM PDT 24
Finished Mar 28 01:38:28 PM PDT 24
Peak memory 218712 kb
Host smart-f65a79a2-473a-4b5a-a451-54e99a6ed6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672724200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3672724200
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3167919530
Short name T887
Test name
Test status
Simulation time 101268551 ps
CPU time 0.71 seconds
Started Mar 28 01:38:20 PM PDT 24
Finished Mar 28 01:38:21 PM PDT 24
Peak memory 204720 kb
Host smart-b308808b-e535-4600-9f4a-0a8fc2aed1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167919530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3167919530
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3420532430
Short name T211
Test name
Test status
Simulation time 56523403 ps
CPU time 2.29 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 233024 kb
Host smart-0f0aa11f-c59b-44c9-b0d3-6c32a08769e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420532430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3420532430
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2964307694
Short name T279
Test name
Test status
Simulation time 14527353 ps
CPU time 0.82 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:18 PM PDT 24
Peak memory 206516 kb
Host smart-af4ab5a7-f819-4407-8c2d-0e74c44de08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964307694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2964307694
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1293669382
Short name T841
Test name
Test status
Simulation time 8064183286 ps
CPU time 14.3 seconds
Started Mar 28 01:38:21 PM PDT 24
Finished Mar 28 01:38:35 PM PDT 24
Peak memory 236928 kb
Host smart-270618e9-cceb-4847-ba3c-89696ff17f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293669382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1293669382
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.250990681
Short name T684
Test name
Test status
Simulation time 1538399053 ps
CPU time 17.74 seconds
Started Mar 28 01:38:20 PM PDT 24
Finished Mar 28 01:38:38 PM PDT 24
Peak memory 237516 kb
Host smart-a8de8ac8-1c9d-4f08-9e0e-f31dfb853bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250990681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.250990681
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.585221948
Short name T795
Test name
Test status
Simulation time 48053735225 ps
CPU time 56.49 seconds
Started Mar 28 01:38:20 PM PDT 24
Finished Mar 28 01:39:17 PM PDT 24
Peak memory 252600 kb
Host smart-0f79a76e-d841-4ee9-a94e-400463408432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585221948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.585221948
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2368976384
Short name T257
Test name
Test status
Simulation time 36386023367 ps
CPU time 42.04 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:59 PM PDT 24
Peak memory 240844 kb
Host smart-981dbb3f-0012-44e3-ba47-4b74a476b031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368976384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2368976384
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4019310304
Short name T650
Test name
Test status
Simulation time 284134788 ps
CPU time 2.97 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:38:22 PM PDT 24
Peak memory 232564 kb
Host smart-9fcbd1c8-cc13-4c39-b15d-c9326f1a35a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019310304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4019310304
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1606106456
Short name T961
Test name
Test status
Simulation time 11270480633 ps
CPU time 36.81 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:55 PM PDT 24
Peak memory 226872 kb
Host smart-3a27eea9-4003-4e32-87ca-9aa35812b677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606106456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1606106456
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3537119954
Short name T567
Test name
Test status
Simulation time 1947238414 ps
CPU time 4.82 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:23 PM PDT 24
Peak memory 240696 kb
Host smart-95f29d3b-3100-4886-89cb-b7c99c6140c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537119954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3537119954
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.536171380
Short name T324
Test name
Test status
Simulation time 6544215553 ps
CPU time 18.52 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:36 PM PDT 24
Peak memory 248808 kb
Host smart-f1351a25-8aff-4394-9c73-a8fc2a93e822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536171380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.536171380
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2115527282
Short name T805
Test name
Test status
Simulation time 169903638 ps
CPU time 3.3 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 220220 kb
Host smart-260b0c65-a9d7-49c3-9745-f04f98cbc27d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2115527282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2115527282
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1302308299
Short name T52
Test name
Test status
Simulation time 215417933 ps
CPU time 0.95 seconds
Started Mar 28 01:38:20 PM PDT 24
Finished Mar 28 01:38:21 PM PDT 24
Peak memory 206288 kb
Host smart-42e53531-3b6f-4002-ade8-a4c927b79b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302308299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1302308299
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2963693575
Short name T530
Test name
Test status
Simulation time 10359956584 ps
CPU time 55.48 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:39:13 PM PDT 24
Peak memory 216252 kb
Host smart-6fc49683-48d0-4e7b-a9ac-427ed02451f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963693575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2963693575
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1400302925
Short name T375
Test name
Test status
Simulation time 873505998 ps
CPU time 3.37 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:22 PM PDT 24
Peak memory 207748 kb
Host smart-089eb7d3-60ba-403e-b9bd-69b3a462314d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400302925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1400302925
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3382433776
Short name T633
Test name
Test status
Simulation time 315605737 ps
CPU time 4.5 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:22 PM PDT 24
Peak memory 216260 kb
Host smart-acd6f67f-c203-4e34-87ce-d0990d81250d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382433776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3382433776
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3282539540
Short name T937
Test name
Test status
Simulation time 1177618170 ps
CPU time 0.97 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 205512 kb
Host smart-60f58428-5f45-4a1b-aaa3-1ecf68765072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282539540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3282539540
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4007177339
Short name T460
Test name
Test status
Simulation time 8129497655 ps
CPU time 24.75 seconds
Started Mar 28 01:38:13 PM PDT 24
Finished Mar 28 01:38:38 PM PDT 24
Peak memory 218488 kb
Host smart-4dd95d1f-fbb8-474a-9901-aa71c97fe71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007177339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4007177339
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1296375167
Short name T970
Test name
Test status
Simulation time 34019272 ps
CPU time 0.73 seconds
Started Mar 28 01:36:00 PM PDT 24
Finished Mar 28 01:36:01 PM PDT 24
Peak memory 205220 kb
Host smart-53c0eb9f-c81d-4742-9886-7aadd26c85d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296375167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
296375167
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1073055282
Short name T262
Test name
Test status
Simulation time 1397914894 ps
CPU time 2.96 seconds
Started Mar 28 01:36:07 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 233856 kb
Host smart-80a87ba2-3c36-4c6f-a146-31865c5675d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073055282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1073055282
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1048987890
Short name T744
Test name
Test status
Simulation time 19632978 ps
CPU time 0.81 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:11 PM PDT 24
Peak memory 206552 kb
Host smart-be47968c-e1d8-4d80-9be2-5b213bee6561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048987890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1048987890
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1676400804
Short name T180
Test name
Test status
Simulation time 53892720109 ps
CPU time 93.58 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:37:43 PM PDT 24
Peak memory 256024 kb
Host smart-31ecf8a4-0419-467f-8cec-f499e5ac6393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676400804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1676400804
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4062423074
Short name T754
Test name
Test status
Simulation time 4381771078 ps
CPU time 86.41 seconds
Started Mar 28 01:36:00 PM PDT 24
Finished Mar 28 01:37:27 PM PDT 24
Peak memory 264564 kb
Host smart-4e343489-5fa5-4eba-9a8e-b08ff66d7557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062423074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4062423074
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3677025557
Short name T229
Test name
Test status
Simulation time 184506494122 ps
CPU time 247.29 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:40:17 PM PDT 24
Peak memory 249044 kb
Host smart-8710882b-7974-493a-a2a3-f84e40beee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677025557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3677025557
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.482952800
Short name T705
Test name
Test status
Simulation time 5294599973 ps
CPU time 29.29 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:36 PM PDT 24
Peak memory 233764 kb
Host smart-a54a5276-24a2-42be-863c-8260202a6f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482952800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.482952800
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2335811551
Short name T182
Test name
Test status
Simulation time 789571990 ps
CPU time 3.17 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:12 PM PDT 24
Peak memory 233076 kb
Host smart-412823e6-9fcf-4acb-9b63-32330d960d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335811551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2335811551
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1899518650
Short name T810
Test name
Test status
Simulation time 8443436439 ps
CPU time 27.54 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:34 PM PDT 24
Peak memory 226676 kb
Host smart-3e850067-478b-47df-b42d-755b4c0ee29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899518650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1899518650
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2420811845
Short name T494
Test name
Test status
Simulation time 119117913 ps
CPU time 1.04 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 216508 kb
Host smart-6c4dec4d-19ec-4698-b909-2b1f9f096e24
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420811845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2420811845
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3590958129
Short name T791
Test name
Test status
Simulation time 40253163493 ps
CPU time 29.12 seconds
Started Mar 28 01:36:04 PM PDT 24
Finished Mar 28 01:36:33 PM PDT 24
Peak memory 233156 kb
Host smart-ef82669c-8043-491a-9e12-870dc0d86489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590958129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3590958129
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3297455330
Short name T137
Test name
Test status
Simulation time 1347995042 ps
CPU time 6.38 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:36:08 PM PDT 24
Peak memory 233504 kb
Host smart-ce80b285-4188-45c2-9a6d-692a10c9d0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297455330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3297455330
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.4232277256
Short name T377
Test name
Test status
Simulation time 84948191 ps
CPU time 0.74 seconds
Started Mar 28 01:36:08 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 216076 kb
Host smart-50f1f734-9908-485b-b059-01aeb4e552fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232277256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.4232277256
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2208282095
Short name T840
Test name
Test status
Simulation time 301154922 ps
CPU time 4.52 seconds
Started Mar 28 01:36:11 PM PDT 24
Finished Mar 28 01:36:16 PM PDT 24
Peak memory 222612 kb
Host smart-ae2647f8-a6cf-4c75-a671-a4623c03083b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2208282095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2208282095
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1786559614
Short name T58
Test name
Test status
Simulation time 329660000 ps
CPU time 1.24 seconds
Started Mar 28 01:36:07 PM PDT 24
Finished Mar 28 01:36:08 PM PDT 24
Peak memory 235228 kb
Host smart-2fa86641-360e-4823-a2d5-2705aa0862d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786559614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1786559614
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2938551525
Short name T820
Test name
Test status
Simulation time 23109606764 ps
CPU time 142.47 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:38:33 PM PDT 24
Peak memory 249324 kb
Host smart-d0ec7c23-90ac-44b2-9d3d-4ef83d90769d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938551525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2938551525
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2676822242
Short name T759
Test name
Test status
Simulation time 2586337723 ps
CPU time 4.67 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:14 PM PDT 24
Peak memory 216168 kb
Host smart-9704f410-5228-48c9-a226-38484c25461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676822242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2676822242
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3845502736
Short name T15
Test name
Test status
Simulation time 9258574930 ps
CPU time 25.34 seconds
Started Mar 28 01:36:03 PM PDT 24
Finished Mar 28 01:36:29 PM PDT 24
Peak memory 216220 kb
Host smart-2d0f2c78-8d69-41b9-bfc7-89fa03102993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845502736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3845502736
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2881755561
Short name T337
Test name
Test status
Simulation time 650334518 ps
CPU time 3.8 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 216328 kb
Host smart-4b686910-bc5e-47a5-8657-d8630973a613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881755561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2881755561
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2037578122
Short name T885
Test name
Test status
Simulation time 213543112 ps
CPU time 1.12 seconds
Started Mar 28 01:36:00 PM PDT 24
Finished Mar 28 01:36:01 PM PDT 24
Peak memory 205752 kb
Host smart-66b6494e-f5eb-4a9a-86fd-8b7f8d4c6ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037578122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2037578122
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2179360551
Short name T628
Test name
Test status
Simulation time 237558374 ps
CPU time 3.28 seconds
Started Mar 28 01:36:04 PM PDT 24
Finished Mar 28 01:36:07 PM PDT 24
Peak memory 232624 kb
Host smart-ba12c883-3d8a-43d5-92bc-04ce99284e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179360551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2179360551
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3609786008
Short name T692
Test name
Test status
Simulation time 34122385 ps
CPU time 0.7 seconds
Started Mar 28 01:38:14 PM PDT 24
Finished Mar 28 01:38:15 PM PDT 24
Peak memory 204592 kb
Host smart-7344313e-565c-4b33-9b68-c03491bde4e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609786008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3609786008
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3946965781
Short name T733
Test name
Test status
Simulation time 142332785 ps
CPU time 3.02 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:38:19 PM PDT 24
Peak memory 233716 kb
Host smart-f204a496-38a6-49b0-af17-ce04875fbfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946965781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3946965781
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3330748752
Short name T797
Test name
Test status
Simulation time 34609987 ps
CPU time 0.8 seconds
Started Mar 28 01:38:21 PM PDT 24
Finished Mar 28 01:38:22 PM PDT 24
Peak memory 206620 kb
Host smart-5eaef856-7692-46cd-b4be-f66201b67708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330748752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3330748752
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3981778863
Short name T218
Test name
Test status
Simulation time 6315370050 ps
CPU time 39.56 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:58 PM PDT 24
Peak memory 253492 kb
Host smart-52c50966-12f1-43d0-ad7d-6d6d95bfa79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981778863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3981778863
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2581311702
Short name T76
Test name
Test status
Simulation time 43422897709 ps
CPU time 95.12 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:39:52 PM PDT 24
Peak memory 251156 kb
Host smart-6faa85e6-0def-4c2a-acdc-e08bf593567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581311702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2581311702
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1217957157
Short name T615
Test name
Test status
Simulation time 2916099052 ps
CPU time 20.25 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:38:36 PM PDT 24
Peak memory 249148 kb
Host smart-968c84b2-cb4a-4eda-8b3c-42cf1b72d94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217957157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1217957157
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2383047919
Short name T32
Test name
Test status
Simulation time 11233378687 ps
CPU time 26.88 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:46 PM PDT 24
Peak memory 232488 kb
Host smart-88e88dfd-9012-4c41-b199-a9e4dfc657d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383047919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2383047919
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2173544010
Short name T726
Test name
Test status
Simulation time 537022424 ps
CPU time 5.72 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:38:25 PM PDT 24
Peak memory 233888 kb
Host smart-832f160f-602c-4692-9fda-4d889e0a5917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173544010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2173544010
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3656838270
Short name T658
Test name
Test status
Simulation time 1486639485 ps
CPU time 17.39 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:36 PM PDT 24
Peak memory 247592 kb
Host smart-d1949ae2-1c2f-4742-a4dd-6e1d545d849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656838270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3656838270
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2784803688
Short name T225
Test name
Test status
Simulation time 7474648059 ps
CPU time 16.52 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:38:36 PM PDT 24
Peak memory 236556 kb
Host smart-af1acbee-9ec3-413d-9207-7f613cbc318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784803688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2784803688
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1434265178
Short name T849
Test name
Test status
Simulation time 39479337 ps
CPU time 2.35 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:21 PM PDT 24
Peak memory 233072 kb
Host smart-e0668075-0c59-46dd-b489-33bf2b68548d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434265178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1434265178
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4290686403
Short name T778
Test name
Test status
Simulation time 1746996707 ps
CPU time 5.6 seconds
Started Mar 28 01:38:21 PM PDT 24
Finished Mar 28 01:38:27 PM PDT 24
Peak memory 222836 kb
Host smart-f7c6b688-a489-4e93-87c2-00614aab5540
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4290686403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4290686403
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1578555893
Short name T944
Test name
Test status
Simulation time 29154653586 ps
CPU time 237.47 seconds
Started Mar 28 01:38:12 PM PDT 24
Finished Mar 28 01:42:10 PM PDT 24
Peak memory 251880 kb
Host smart-23eb122d-6721-4300-9d3b-02b265000e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578555893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1578555893
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3428775810
Short name T586
Test name
Test status
Simulation time 1111954140 ps
CPU time 5.25 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:38:25 PM PDT 24
Peak memory 216116 kb
Host smart-85a68a86-7966-4b12-b04c-1f6af4a2bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428775810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3428775810
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1344128057
Short name T837
Test name
Test status
Simulation time 410317508 ps
CPU time 3.39 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:22 PM PDT 24
Peak memory 216208 kb
Host smart-6e20c8d4-a60c-4999-b0f2-d20cd94e4abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344128057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1344128057
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1091704144
Short name T395
Test name
Test status
Simulation time 322108247 ps
CPU time 4.08 seconds
Started Mar 28 01:38:15 PM PDT 24
Finished Mar 28 01:38:19 PM PDT 24
Peak memory 216184 kb
Host smart-34aa2aab-e716-4e04-a793-c558534db086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091704144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1091704144
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.82391852
Short name T730
Test name
Test status
Simulation time 62806093 ps
CPU time 0.79 seconds
Started Mar 28 01:38:14 PM PDT 24
Finished Mar 28 01:38:15 PM PDT 24
Peak memory 205536 kb
Host smart-b93570fe-0073-4ea1-a7a3-01fd95d91d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82391852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.82391852
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.557823696
Short name T134
Test name
Test status
Simulation time 55872379622 ps
CPU time 45.45 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:39:05 PM PDT 24
Peak memory 235016 kb
Host smart-a23f2a42-83c7-49ed-89ae-4d381aa83a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557823696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.557823696
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.475094890
Short name T465
Test name
Test status
Simulation time 13162835 ps
CPU time 0.73 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:38:17 PM PDT 24
Peak memory 205192 kb
Host smart-7906ed3f-055f-43f8-9063-064072108b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475094890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.475094890
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3645511121
Short name T896
Test name
Test status
Simulation time 251686340 ps
CPU time 3.16 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:38:19 PM PDT 24
Peak memory 218428 kb
Host smart-09860c99-396f-46a6-8394-294e1f17a28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645511121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3645511121
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1116771550
Short name T806
Test name
Test status
Simulation time 274871439 ps
CPU time 0.77 seconds
Started Mar 28 01:38:14 PM PDT 24
Finished Mar 28 01:38:15 PM PDT 24
Peak memory 206260 kb
Host smart-ceb56bb1-0dcc-4f59-a182-6d162c75ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116771550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1116771550
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3114292419
Short name T245
Test name
Test status
Simulation time 19729250395 ps
CPU time 49.66 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:39:08 PM PDT 24
Peak memory 224388 kb
Host smart-91eff20c-d60f-40b3-8d4b-cfadec59c1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114292419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3114292419
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4199129947
Short name T30
Test name
Test status
Simulation time 43403102390 ps
CPU time 254.27 seconds
Started Mar 28 01:38:20 PM PDT 24
Finished Mar 28 01:42:35 PM PDT 24
Peak memory 252396 kb
Host smart-fa6dbc3a-f366-4584-a149-93cc8a5052c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199129947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4199129947
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3062920608
Short name T694
Test name
Test status
Simulation time 7013121380 ps
CPU time 28.8 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:38:45 PM PDT 24
Peak memory 222564 kb
Host smart-d5f8d345-f649-475d-83a5-a764239c4d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062920608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3062920608
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1694487928
Short name T125
Test name
Test status
Simulation time 3323268088 ps
CPU time 24.45 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:38:41 PM PDT 24
Peak memory 235344 kb
Host smart-4526de8a-fd2e-4847-b3fe-1e50787ad0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694487928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1694487928
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.635852076
Short name T976
Test name
Test status
Simulation time 885450179 ps
CPU time 7.52 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:25 PM PDT 24
Peak memory 218256 kb
Host smart-41d1331e-7651-4f04-8054-fe86e05e539c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635852076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.635852076
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3393354764
Short name T466
Test name
Test status
Simulation time 15492782375 ps
CPU time 25.83 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:38:42 PM PDT 24
Peak memory 228020 kb
Host smart-e2db9c6f-789f-4096-bef8-a6079331e27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393354764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3393354764
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.186499578
Short name T595
Test name
Test status
Simulation time 8897651602 ps
CPU time 13.32 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:32 PM PDT 24
Peak memory 224372 kb
Host smart-21338cae-f01a-401c-ab07-1644340986e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186499578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.186499578
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1597986808
Short name T517
Test name
Test status
Simulation time 938432324 ps
CPU time 2.8 seconds
Started Mar 28 01:38:11 PM PDT 24
Finished Mar 28 01:38:14 PM PDT 24
Peak memory 218284 kb
Host smart-d9a2b2b9-bb52-47be-ab3b-8730832465dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597986808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1597986808
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2545070368
Short name T940
Test name
Test status
Simulation time 5767307237 ps
CPU time 7.06 seconds
Started Mar 28 01:38:13 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 222756 kb
Host smart-68f5e526-1db3-4659-a2ec-ffd8103f7793
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2545070368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2545070368
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1252339685
Short name T939
Test name
Test status
Simulation time 10534476263 ps
CPU time 114.96 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:40:12 PM PDT 24
Peak memory 255636 kb
Host smart-b1be1c4f-864f-47f6-acae-656f38ee33bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252339685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1252339685
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2968644573
Short name T258
Test name
Test status
Simulation time 14139340885 ps
CPU time 81.42 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:39:38 PM PDT 24
Peak memory 216100 kb
Host smart-f7fc2f57-7452-403e-87a3-147c2a3c74db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968644573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2968644573
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1721063158
Short name T691
Test name
Test status
Simulation time 13707184998 ps
CPU time 19.43 seconds
Started Mar 28 01:38:15 PM PDT 24
Finished Mar 28 01:38:35 PM PDT 24
Peak memory 216156 kb
Host smart-23c89fe3-90e5-493d-95b9-1d436a92d782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721063158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1721063158
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3915490161
Short name T281
Test name
Test status
Simulation time 565784140 ps
CPU time 3.19 seconds
Started Mar 28 01:38:15 PM PDT 24
Finished Mar 28 01:38:19 PM PDT 24
Peak memory 216084 kb
Host smart-f74be529-d4b2-4361-9d49-0e0c35264e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915490161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3915490161
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1727026069
Short name T322
Test name
Test status
Simulation time 171587692 ps
CPU time 1.17 seconds
Started Mar 28 01:38:14 PM PDT 24
Finished Mar 28 01:38:15 PM PDT 24
Peak memory 206568 kb
Host smart-fc14079e-9fdd-4592-95de-01c1b9bcd233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727026069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1727026069
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1668236456
Short name T147
Test name
Test status
Simulation time 941198970 ps
CPU time 6.68 seconds
Started Mar 28 01:38:56 PM PDT 24
Finished Mar 28 01:39:03 PM PDT 24
Peak memory 224388 kb
Host smart-456ee9e5-8cf3-4f28-9077-cfb0896d4bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668236456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1668236456
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.730377468
Short name T268
Test name
Test status
Simulation time 26659798 ps
CPU time 0.74 seconds
Started Mar 28 01:38:23 PM PDT 24
Finished Mar 28 01:38:24 PM PDT 24
Peak memory 204580 kb
Host smart-3b1fec6f-8291-4358-89ff-5197e9efab2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730377468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.730377468
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2340520283
Short name T627
Test name
Test status
Simulation time 92363646 ps
CPU time 2.67 seconds
Started Mar 28 01:38:20 PM PDT 24
Finished Mar 28 01:38:22 PM PDT 24
Peak memory 234272 kb
Host smart-193ecb99-7ea6-4a94-9c76-ac35c0001462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340520283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2340520283
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3740982804
Short name T328
Test name
Test status
Simulation time 70650494 ps
CPU time 0.79 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:18 PM PDT 24
Peak memory 206520 kb
Host smart-c513920e-3d0c-4473-87fe-72d7e1ea4707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740982804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3740982804
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3956660631
Short name T392
Test name
Test status
Simulation time 97640408215 ps
CPU time 96.57 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:39:55 PM PDT 24
Peak memory 253296 kb
Host smart-c2ff1de2-7881-451d-8c3d-f16110d75e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956660631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3956660631
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1961505423
Short name T642
Test name
Test status
Simulation time 23521135017 ps
CPU time 202.45 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:41:42 PM PDT 24
Peak memory 249176 kb
Host smart-6c69946b-f3fc-4f5c-bb91-57eaf40baaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961505423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1961505423
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1390921546
Short name T598
Test name
Test status
Simulation time 54736221937 ps
CPU time 56.59 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:39:16 PM PDT 24
Peak memory 237796 kb
Host smart-5ef469ac-07fc-4b9f-b8b2-5b08455366b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390921546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1390921546
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3711736825
Short name T719
Test name
Test status
Simulation time 12299146038 ps
CPU time 5.11 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:38:25 PM PDT 24
Peak memory 224424 kb
Host smart-37fac312-e0ac-409a-8b8d-e7f40ed54bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711736825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3711736825
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2128374853
Short name T148
Test name
Test status
Simulation time 3469766331 ps
CPU time 7.04 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:25 PM PDT 24
Peak memory 240476 kb
Host smart-c32fa581-2ab1-4420-808e-614e875b51de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128374853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2128374853
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.635675465
Short name T600
Test name
Test status
Simulation time 5077532619 ps
CPU time 5.97 seconds
Started Mar 28 01:38:20 PM PDT 24
Finished Mar 28 01:38:26 PM PDT 24
Peak memory 217684 kb
Host smart-2c4bf4b3-5a4d-48fe-bd29-18245c6790c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635675465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.635675465
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1602864349
Short name T745
Test name
Test status
Simulation time 2730911584 ps
CPU time 11.37 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:30 PM PDT 24
Peak memory 233396 kb
Host smart-b8ced7b3-119c-4eea-a63e-b9f891cb4c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602864349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1602864349
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1170517420
Short name T557
Test name
Test status
Simulation time 110720443 ps
CPU time 3.6 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:38:23 PM PDT 24
Peak memory 222832 kb
Host smart-3ba089be-ab09-46ce-abbe-858bba5edf8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1170517420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1170517420
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.99801654
Short name T252
Test name
Test status
Simulation time 9296931426 ps
CPU time 83.95 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:39:43 PM PDT 24
Peak memory 250424 kb
Host smart-13c3655c-ee1a-4a54-99ae-bf7d262a70c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99801654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress
_all.99801654
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.75848955
Short name T299
Test name
Test status
Simulation time 24268605440 ps
CPU time 71.98 seconds
Started Mar 28 01:38:16 PM PDT 24
Finished Mar 28 01:39:28 PM PDT 24
Peak memory 216268 kb
Host smart-89970629-efe3-488d-b1d5-dd1f7586a7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75848955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.75848955
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.242962369
Short name T43
Test name
Test status
Simulation time 2920968402 ps
CPU time 9.03 seconds
Started Mar 28 01:38:17 PM PDT 24
Finished Mar 28 01:38:27 PM PDT 24
Peak memory 216220 kb
Host smart-cbfcf3a6-de19-4343-abd9-35350ea24c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242962369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.242962369
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2047510908
Short name T454
Test name
Test status
Simulation time 156029973 ps
CPU time 1.37 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 207800 kb
Host smart-775635e4-9482-48e7-b8e5-ea7addc9aace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047510908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2047510908
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1716379193
Short name T382
Test name
Test status
Simulation time 139288630 ps
CPU time 1.06 seconds
Started Mar 28 01:38:12 PM PDT 24
Finished Mar 28 01:38:14 PM PDT 24
Peak memory 206004 kb
Host smart-57cbcc3a-7e66-4c66-b3de-593337030164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716379193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1716379193
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2722415346
Short name T544
Test name
Test status
Simulation time 199938044 ps
CPU time 3.27 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:21 PM PDT 24
Peak memory 234076 kb
Host smart-2c4fdb5e-aee5-4ad8-a64d-3258d71eea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722415346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2722415346
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3553807999
Short name T977
Test name
Test status
Simulation time 63555863 ps
CPU time 0.73 seconds
Started Mar 28 01:38:33 PM PDT 24
Finished Mar 28 01:38:34 PM PDT 24
Peak memory 205132 kb
Host smart-986a7d90-a890-4874-a269-d53c795965a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553807999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3553807999
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1057741846
Short name T729
Test name
Test status
Simulation time 172307235 ps
CPU time 3.18 seconds
Started Mar 28 01:38:30 PM PDT 24
Finished Mar 28 01:38:34 PM PDT 24
Peak memory 233328 kb
Host smart-d1343741-b14c-4793-bcae-f39ba1e41b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057741846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1057741846
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2803562228
Short name T553
Test name
Test status
Simulation time 92194906 ps
CPU time 0.76 seconds
Started Mar 28 01:38:19 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 206240 kb
Host smart-aaff0586-6903-4372-ba16-5740c4b3ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803562228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2803562228
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2194497576
Short name T231
Test name
Test status
Simulation time 192254862540 ps
CPU time 206.46 seconds
Started Mar 28 01:38:36 PM PDT 24
Finished Mar 28 01:42:02 PM PDT 24
Peak memory 254512 kb
Host smart-8cbec16c-cb91-4646-8a38-f5c8ed1e2be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194497576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2194497576
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1719058741
Short name T296
Test name
Test status
Simulation time 379287926066 ps
CPU time 191.5 seconds
Started Mar 28 01:38:36 PM PDT 24
Finished Mar 28 01:41:48 PM PDT 24
Peak memory 254920 kb
Host smart-df2b20bc-d0a9-413b-8468-56f3464054b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719058741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1719058741
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.874515274
Short name T802
Test name
Test status
Simulation time 1426511186 ps
CPU time 8.6 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:38:40 PM PDT 24
Peak memory 237896 kb
Host smart-c351e6bc-9c3c-4766-ab3b-55e34a3bf5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874515274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.874515274
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3302392010
Short name T688
Test name
Test status
Simulation time 2115039220 ps
CPU time 5.7 seconds
Started Mar 28 01:38:31 PM PDT 24
Finished Mar 28 01:38:37 PM PDT 24
Peak memory 218236 kb
Host smart-15dff466-811b-4e3e-8f60-0c08f2017a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302392010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3302392010
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1763594152
Short name T559
Test name
Test status
Simulation time 37076818905 ps
CPU time 32.1 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:39:04 PM PDT 24
Peak memory 250300 kb
Host smart-8c091fa2-64ec-4257-a574-109d561abe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763594152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1763594152
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.50060375
Short name T623
Test name
Test status
Simulation time 28029036606 ps
CPU time 18.67 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:38:51 PM PDT 24
Peak memory 240456 kb
Host smart-742785eb-9753-4c92-b68b-a6f3ce8d83e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50060375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.50060375
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3990932859
Short name T158
Test name
Test status
Simulation time 1245323295 ps
CPU time 4.82 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:38:39 PM PDT 24
Peak memory 216928 kb
Host smart-d60618b0-ed5c-456f-98c7-c85f9f9d1b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990932859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3990932859
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4234636083
Short name T475
Test name
Test status
Simulation time 2625127456 ps
CPU time 6.99 seconds
Started Mar 28 01:38:31 PM PDT 24
Finished Mar 28 01:38:38 PM PDT 24
Peak memory 222752 kb
Host smart-409c0dfd-c17e-42f0-9e5e-e843fcd7dfc4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4234636083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4234636083
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4108897781
Short name T813
Test name
Test status
Simulation time 3365123331 ps
CPU time 26.19 seconds
Started Mar 28 01:38:27 PM PDT 24
Finished Mar 28 01:38:54 PM PDT 24
Peak memory 216188 kb
Host smart-1759ebf4-0bde-4f0f-94d0-c1cdd1f52c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108897781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4108897781
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3771382220
Short name T332
Test name
Test status
Simulation time 147086336 ps
CPU time 1.34 seconds
Started Mar 28 01:38:18 PM PDT 24
Finished Mar 28 01:38:19 PM PDT 24
Peak memory 207764 kb
Host smart-5326bff8-5568-4584-b5bc-ab311bdfdc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771382220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3771382220
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2222025750
Short name T419
Test name
Test status
Simulation time 1597148492 ps
CPU time 2.56 seconds
Started Mar 28 01:38:31 PM PDT 24
Finished Mar 28 01:38:34 PM PDT 24
Peak memory 216020 kb
Host smart-5b0b7db4-b8bb-4810-908c-35c8c3f0d6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222025750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2222025750
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2199515722
Short name T432
Test name
Test status
Simulation time 47138580 ps
CPU time 0.7 seconds
Started Mar 28 01:38:30 PM PDT 24
Finished Mar 28 01:38:30 PM PDT 24
Peak memory 205556 kb
Host smart-314ae1ab-e7ae-4e9b-8174-a4d78a8c76f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199515722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2199515722
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1775030786
Short name T893
Test name
Test status
Simulation time 14052765860 ps
CPU time 22.49 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:38:55 PM PDT 24
Peak memory 234004 kb
Host smart-192daeac-9b5a-486d-af19-06ea74af5f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775030786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1775030786
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1309069104
Short name T53
Test name
Test status
Simulation time 107514529 ps
CPU time 0.76 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:38:36 PM PDT 24
Peak memory 204600 kb
Host smart-fe1cb9c8-83de-4a67-bc36-f97815e55448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309069104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1309069104
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1256685832
Short name T196
Test name
Test status
Simulation time 170816358 ps
CPU time 2.66 seconds
Started Mar 28 01:38:35 PM PDT 24
Finished Mar 28 01:38:38 PM PDT 24
Peak memory 218340 kb
Host smart-5c3b403f-8c70-4e3d-a181-7ca9cbd1ab63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256685832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1256685832
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.36427608
Short name T829
Test name
Test status
Simulation time 16194590 ps
CPU time 0.77 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:38:36 PM PDT 24
Peak memory 205148 kb
Host smart-8642c6aa-6aa5-4c03-8037-30fe3a8aba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36427608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.36427608
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.593319319
Short name T877
Test name
Test status
Simulation time 3028165032 ps
CPU time 11.75 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:38:46 PM PDT 24
Peak memory 234820 kb
Host smart-004c5c31-46c3-4a56-91ce-d3ccc077b93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593319319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.593319319
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1066206290
Short name T77
Test name
Test status
Simulation time 53753532553 ps
CPU time 223.11 seconds
Started Mar 28 01:38:35 PM PDT 24
Finished Mar 28 01:42:19 PM PDT 24
Peak memory 257224 kb
Host smart-042906e5-5d01-4474-b67d-27f66cdbfb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066206290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1066206290
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1070129221
Short name T516
Test name
Test status
Simulation time 8071715427 ps
CPU time 71.42 seconds
Started Mar 28 01:38:36 PM PDT 24
Finished Mar 28 01:39:48 PM PDT 24
Peak memory 265504 kb
Host smart-707f467c-3727-4b15-b60f-8302c73758fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070129221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1070129221
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3137942329
Short name T879
Test name
Test status
Simulation time 5535430514 ps
CPU time 33.89 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:39:08 PM PDT 24
Peak memory 240280 kb
Host smart-e5aebdc0-5bdf-4e31-a011-bcf74ad70865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137942329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3137942329
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2463883113
Short name T629
Test name
Test status
Simulation time 699657616 ps
CPU time 3.15 seconds
Started Mar 28 01:38:35 PM PDT 24
Finished Mar 28 01:38:39 PM PDT 24
Peak memory 216540 kb
Host smart-a181cb70-35a1-40ef-993c-d51cbc91e37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463883113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2463883113
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1619099389
Short name T504
Test name
Test status
Simulation time 26860277120 ps
CPU time 23.09 seconds
Started Mar 28 01:38:36 PM PDT 24
Finished Mar 28 01:39:00 PM PDT 24
Peak memory 233688 kb
Host smart-d405a6fe-8aee-4543-bdfc-0b316000e374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619099389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1619099389
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.233859349
Short name T495
Test name
Test status
Simulation time 8518223822 ps
CPU time 14.23 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:38:46 PM PDT 24
Peak memory 224292 kb
Host smart-a3a67c17-00ec-4abe-8b40-2f32b8302307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233859349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.233859349
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3389157684
Short name T832
Test name
Test status
Simulation time 807044461 ps
CPU time 3.85 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:38:38 PM PDT 24
Peak memory 221160 kb
Host smart-a1a421ff-b1cc-4be6-83bc-e8b98e4bfcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389157684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3389157684
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2814007938
Short name T518
Test name
Test status
Simulation time 612568809 ps
CPU time 4.74 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:38:42 PM PDT 24
Peak memory 222820 kb
Host smart-91bb7056-f5e6-4770-8d16-59a9a4b638da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2814007938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2814007938
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2769162460
Short name T243
Test name
Test status
Simulation time 14223377086 ps
CPU time 115.54 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:40:30 PM PDT 24
Peak memory 249840 kb
Host smart-cc1e7c66-9e97-4433-b039-98d0f790b7b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769162460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2769162460
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4105262255
Short name T963
Test name
Test status
Simulation time 36881960720 ps
CPU time 47.91 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:39:22 PM PDT 24
Peak memory 216244 kb
Host smart-ebe26d5a-c1e8-4dce-9526-1fa9feb2577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105262255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4105262255
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2792518671
Short name T746
Test name
Test status
Simulation time 3621300588 ps
CPU time 16.6 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:38:54 PM PDT 24
Peak memory 216220 kb
Host smart-e9e2c6fd-2e57-4f74-ab3e-09c3ea0d44cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792518671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2792518671
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3909577725
Short name T767
Test name
Test status
Simulation time 158222469 ps
CPU time 8.09 seconds
Started Mar 28 01:38:41 PM PDT 24
Finished Mar 28 01:38:49 PM PDT 24
Peak memory 216136 kb
Host smart-33a4acb9-ef05-4773-b921-207b41385ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909577725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3909577725
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2242473624
Short name T687
Test name
Test status
Simulation time 685805968 ps
CPU time 1.14 seconds
Started Mar 28 01:38:35 PM PDT 24
Finished Mar 28 01:38:37 PM PDT 24
Peak memory 206552 kb
Host smart-21c46fe2-d0e8-4de3-bf2c-e5d626b77b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242473624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2242473624
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3087389686
Short name T889
Test name
Test status
Simulation time 2958714544 ps
CPU time 13.69 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:52 PM PDT 24
Peak memory 235736 kb
Host smart-43555ee2-f825-4312-89ea-e6fb74c812ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087389686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3087389686
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4214554160
Short name T469
Test name
Test status
Simulation time 34179330 ps
CPU time 0.72 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:38:33 PM PDT 24
Peak memory 204580 kb
Host smart-79bebff2-3e91-485b-9d85-9c862409f7f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214554160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4214554160
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3147309610
Short name T903
Test name
Test status
Simulation time 708146666 ps
CPU time 5.04 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:43 PM PDT 24
Peak memory 224388 kb
Host smart-3dca93a5-78e2-479b-a4bb-08b352803bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147309610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3147309610
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.847117473
Short name T286
Test name
Test status
Simulation time 20872088 ps
CPU time 0.81 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:38:35 PM PDT 24
Peak memory 205228 kb
Host smart-12c1e079-e4cc-4130-b8d4-29c831158c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847117473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.847117473
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2048428878
Short name T380
Test name
Test status
Simulation time 289457935 ps
CPU time 4.86 seconds
Started Mar 28 01:38:40 PM PDT 24
Finished Mar 28 01:38:45 PM PDT 24
Peak memory 235772 kb
Host smart-ee9c86de-7cec-423c-ac19-953cf897f65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048428878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2048428878
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.752551414
Short name T955
Test name
Test status
Simulation time 78270602929 ps
CPU time 63.93 seconds
Started Mar 28 01:38:40 PM PDT 24
Finished Mar 28 01:39:44 PM PDT 24
Peak memory 253472 kb
Host smart-e23ab18a-e324-4006-bd1f-83a22d3b00b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752551414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.752551414
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.317571532
Short name T40
Test name
Test status
Simulation time 15284590412 ps
CPU time 107.84 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:40:26 PM PDT 24
Peak memory 253700 kb
Host smart-a6144c81-f1ff-434a-930f-3c8eb9e9a98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317571532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.317571532
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2673026931
Short name T397
Test name
Test status
Simulation time 1621776369 ps
CPU time 11.41 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:50 PM PDT 24
Peak memory 235068 kb
Host smart-f6d69e47-1599-485a-a63e-94e98dea2be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673026931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2673026931
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4223540095
Short name T503
Test name
Test status
Simulation time 2354372645 ps
CPU time 5.6 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:43 PM PDT 24
Peak memory 224428 kb
Host smart-e5af881d-2176-4768-afde-ac964a610373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223540095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4223540095
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4221836259
Short name T779
Test name
Test status
Simulation time 6886994621 ps
CPU time 23.84 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:39:01 PM PDT 24
Peak memory 235444 kb
Host smart-f7f7f235-076b-480e-a286-067618de1110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221836259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4221836259
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2593934752
Short name T900
Test name
Test status
Simulation time 65557244 ps
CPU time 3.07 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:42 PM PDT 24
Peak memory 234180 kb
Host smart-e8ba99d5-82cd-4fe1-bfad-73578e4399a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593934752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2593934752
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1929607328
Short name T747
Test name
Test status
Simulation time 542257022 ps
CPU time 7.52 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:46 PM PDT 24
Peak memory 219916 kb
Host smart-3c7379d0-dfc6-4c1a-b7f0-980ad4ef6da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929607328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1929607328
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1084600207
Short name T122
Test name
Test status
Simulation time 3617884321 ps
CPU time 5.29 seconds
Started Mar 28 01:38:36 PM PDT 24
Finished Mar 28 01:38:42 PM PDT 24
Peak memory 222756 kb
Host smart-2fd352cf-e6a4-4203-a599-2b8fde112bfd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1084600207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1084600207
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3540956966
Short name T133
Test name
Test status
Simulation time 1043186921 ps
CPU time 15.1 seconds
Started Mar 28 01:38:30 PM PDT 24
Finished Mar 28 01:38:46 PM PDT 24
Peak memory 223348 kb
Host smart-538fb367-4564-4c4b-8e61-2d21415060ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540956966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3540956966
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4141695884
Short name T771
Test name
Test status
Simulation time 11996605071 ps
CPU time 59.12 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:39:37 PM PDT 24
Peak memory 216156 kb
Host smart-929fb01c-72f9-4290-b75b-c86e51bffe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141695884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4141695884
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2052630439
Short name T852
Test name
Test status
Simulation time 6714942189 ps
CPU time 21.47 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:38:59 PM PDT 24
Peak memory 216236 kb
Host smart-cd223ada-db94-4826-8371-dfc4eebe26cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052630439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2052630439
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3070559613
Short name T675
Test name
Test status
Simulation time 20096210 ps
CPU time 0.82 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:38:38 PM PDT 24
Peak memory 205544 kb
Host smart-98b872b4-d390-47e6-93de-0ab534a85d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070559613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3070559613
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2840934707
Short name T819
Test name
Test status
Simulation time 65024596 ps
CPU time 0.78 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:38:38 PM PDT 24
Peak memory 205500 kb
Host smart-ad07a5e1-fb0c-49a5-93c9-6730f0eeb094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840934707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2840934707
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.327722631
Short name T833
Test name
Test status
Simulation time 4966256702 ps
CPU time 8.77 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:47 PM PDT 24
Peak memory 233736 kb
Host smart-083e47d2-5622-47cd-a5c6-61d0752c79b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327722631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.327722631
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3184525462
Short name T641
Test name
Test status
Simulation time 15027977 ps
CPU time 0.78 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:38:33 PM PDT 24
Peak memory 205412 kb
Host smart-e63d8853-8195-4a9d-9604-39da7cd6bf85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184525462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3184525462
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.741144584
Short name T500
Test name
Test status
Simulation time 766958831 ps
CPU time 5.28 seconds
Started Mar 28 01:38:35 PM PDT 24
Finished Mar 28 01:38:40 PM PDT 24
Peak memory 219420 kb
Host smart-e462d326-f511-4136-af05-ce2a4db00843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741144584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.741144584
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1693002563
Short name T809
Test name
Test status
Simulation time 83397084 ps
CPU time 0.77 seconds
Started Mar 28 01:38:30 PM PDT 24
Finished Mar 28 01:38:31 PM PDT 24
Peak memory 206172 kb
Host smart-5b1c63a3-4226-446f-b6bb-0cac794036e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693002563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1693002563
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1266762838
Short name T671
Test name
Test status
Simulation time 3469906761 ps
CPU time 23.85 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:38:56 PM PDT 24
Peak memory 237436 kb
Host smart-86f04838-1c67-4ad2-a98f-6055cd7cc5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266762838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1266762838
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3150036767
Short name T171
Test name
Test status
Simulation time 17884127931 ps
CPU time 71.63 seconds
Started Mar 28 01:38:33 PM PDT 24
Finished Mar 28 01:39:45 PM PDT 24
Peak memory 256728 kb
Host smart-1df4ab64-315d-43d0-bcfd-41f4eabe82a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150036767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3150036767
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.230841142
Short name T155
Test name
Test status
Simulation time 2701390577 ps
CPU time 41.62 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:39:14 PM PDT 24
Peak memory 248312 kb
Host smart-a76cc02e-916c-4da1-ba3e-d0e80e360c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230841142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.230841142
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2530072754
Short name T317
Test name
Test status
Simulation time 9775497863 ps
CPU time 28.54 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:39:02 PM PDT 24
Peak memory 240808 kb
Host smart-df393fb8-f658-4e7c-b4e2-30d86691210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530072754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2530072754
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1329642860
Short name T151
Test name
Test status
Simulation time 1239103005 ps
CPU time 4.67 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:38:36 PM PDT 24
Peak memory 217696 kb
Host smart-f2a28caa-dd9f-4b13-8b97-ecbe8a89a6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329642860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1329642860
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.738694160
Short name T526
Test name
Test status
Simulation time 15056488964 ps
CPU time 12.78 seconds
Started Mar 28 01:38:33 PM PDT 24
Finished Mar 28 01:38:46 PM PDT 24
Peak memory 218464 kb
Host smart-9d4683e6-0827-4f52-ba08-3ef2c152ca13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738694160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.738694160
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3910727666
Short name T619
Test name
Test status
Simulation time 658049314 ps
CPU time 5.31 seconds
Started Mar 28 01:38:36 PM PDT 24
Finished Mar 28 01:38:42 PM PDT 24
Peak memory 224312 kb
Host smart-cbcc6d49-7d9c-4239-bc93-4e25db344df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910727666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3910727666
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1526435877
Short name T186
Test name
Test status
Simulation time 47369500014 ps
CPU time 31.59 seconds
Started Mar 28 01:38:30 PM PDT 24
Finished Mar 28 01:39:01 PM PDT 24
Peak memory 217576 kb
Host smart-0d50cd26-93c8-4e25-aa79-f6ebcf4581fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526435877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1526435877
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3487293977
Short name T546
Test name
Test status
Simulation time 4306893363 ps
CPU time 4.32 seconds
Started Mar 28 01:38:31 PM PDT 24
Finished Mar 28 01:38:36 PM PDT 24
Peak memory 222608 kb
Host smart-c346f01e-c951-4f96-90ec-aa9748a0bc2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3487293977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3487293977
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3489755784
Short name T391
Test name
Test status
Simulation time 94364963684 ps
CPU time 360.17 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:44:33 PM PDT 24
Peak memory 257380 kb
Host smart-e0765cac-871c-4e4a-b736-9fb91dbf2809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489755784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3489755784
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.41552480
Short name T437
Test name
Test status
Simulation time 16262742767 ps
CPU time 14.64 seconds
Started Mar 28 01:38:33 PM PDT 24
Finished Mar 28 01:38:48 PM PDT 24
Peak memory 216280 kb
Host smart-20892f12-db59-49b3-a473-957628c78849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41552480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.41552480
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2761888275
Short name T667
Test name
Test status
Simulation time 2342175224 ps
CPU time 5.4 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:38:37 PM PDT 24
Peak memory 216224 kb
Host smart-67077426-74c4-439f-89f9-98e3820ff68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761888275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2761888275
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1481092116
Short name T558
Test name
Test status
Simulation time 5229925430 ps
CPU time 8.36 seconds
Started Mar 28 01:38:30 PM PDT 24
Finished Mar 28 01:38:39 PM PDT 24
Peak memory 216304 kb
Host smart-0aaa22ec-f2b0-45d7-a69b-7a8f5fa723e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481092116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1481092116
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1011154487
Short name T920
Test name
Test status
Simulation time 28525484 ps
CPU time 0.73 seconds
Started Mar 28 01:38:31 PM PDT 24
Finished Mar 28 01:38:32 PM PDT 24
Peak memory 205536 kb
Host smart-fe46d5c3-097b-4782-b18d-f527121f2df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011154487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1011154487
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4271939692
Short name T581
Test name
Test status
Simulation time 2595765552 ps
CPU time 10.45 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:38:45 PM PDT 24
Peak memory 219300 kb
Host smart-fc34704f-26a5-46f9-8df0-1a3c504d6296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271939692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4271939692
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2715718687
Short name T291
Test name
Test status
Simulation time 36771712 ps
CPU time 0.7 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:38:38 PM PDT 24
Peak memory 204592 kb
Host smart-0cf94b8a-7fd9-42f2-a3fe-703d12964af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715718687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2715718687
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.4151332868
Short name T861
Test name
Test status
Simulation time 185228923 ps
CPU time 3.38 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:38:41 PM PDT 24
Peak memory 219648 kb
Host smart-c1095417-ba27-4491-bea8-ff4131d501b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151332868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.4151332868
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4211456248
Short name T825
Test name
Test status
Simulation time 15600306 ps
CPU time 0.75 seconds
Started Mar 28 01:38:33 PM PDT 24
Finished Mar 28 01:38:33 PM PDT 24
Peak memory 205552 kb
Host smart-b82851b1-5d53-4c39-aae3-5efdbe8e61aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211456248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4211456248
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.665089551
Short name T969
Test name
Test status
Simulation time 5081765236 ps
CPU time 12.66 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:38:50 PM PDT 24
Peak memory 239112 kb
Host smart-808d4042-6b08-4e19-a4f3-0a9e15557aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665089551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.665089551
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2441563239
Short name T800
Test name
Test status
Simulation time 4320383592 ps
CPU time 51.79 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:39:29 PM PDT 24
Peak memory 237532 kb
Host smart-c2220468-f594-4c1c-9973-5a3e99704f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441563239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2441563239
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3232712609
Short name T5
Test name
Test status
Simulation time 17899380627 ps
CPU time 99.33 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:40:17 PM PDT 24
Peak memory 255332 kb
Host smart-2569d762-8009-4fe1-8928-9e51fb55cdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232712609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3232712609
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.700898088
Short name T525
Test name
Test status
Simulation time 24605825940 ps
CPU time 28.75 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:39:06 PM PDT 24
Peak memory 244512 kb
Host smart-9f78dd19-c42e-4065-ba1c-43b3753dd677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700898088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.700898088
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1192046787
Short name T898
Test name
Test status
Simulation time 289847089 ps
CPU time 2.97 seconds
Started Mar 28 01:38:33 PM PDT 24
Finished Mar 28 01:38:36 PM PDT 24
Peak memory 224428 kb
Host smart-a6063c0c-c2b8-4a13-937c-d8c24d0dd9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192046787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1192046787
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3679145862
Short name T783
Test name
Test status
Simulation time 1434184945 ps
CPU time 7.13 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:38:41 PM PDT 24
Peak memory 234696 kb
Host smart-657d2fcf-a258-49f5-8955-95370721e071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679145862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3679145862
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4143080631
Short name T936
Test name
Test status
Simulation time 466430222 ps
CPU time 2.25 seconds
Started Mar 28 01:38:39 PM PDT 24
Finished Mar 28 01:38:41 PM PDT 24
Peak memory 224360 kb
Host smart-00a6cf4d-e1b9-4738-93de-861d47312d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143080631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4143080631
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.91544944
Short name T201
Test name
Test status
Simulation time 8829153531 ps
CPU time 9.2 seconds
Started Mar 28 01:38:34 PM PDT 24
Finished Mar 28 01:38:43 PM PDT 24
Peak memory 224516 kb
Host smart-9a767c36-0ac8-4280-b214-fcda82d22ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91544944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.91544944
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3966720768
Short name T404
Test name
Test status
Simulation time 1222338862 ps
CPU time 6.41 seconds
Started Mar 28 01:38:36 PM PDT 24
Finished Mar 28 01:38:42 PM PDT 24
Peak memory 221976 kb
Host smart-5ce398df-3d10-4b71-9e8a-6cd4cd410961
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3966720768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3966720768
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3901145611
Short name T18
Test name
Test status
Simulation time 305229896247 ps
CPU time 956.11 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:54:34 PM PDT 24
Peak memory 298360 kb
Host smart-47bf6df2-e506-4047-ae5c-0b2c93fb53be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901145611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3901145611
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3502849222
Short name T978
Test name
Test status
Simulation time 5948198279 ps
CPU time 30.77 seconds
Started Mar 28 01:38:36 PM PDT 24
Finished Mar 28 01:39:07 PM PDT 24
Peak memory 216188 kb
Host smart-b62a21e9-6db3-405d-9580-588c19f5961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502849222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3502849222
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1515917134
Short name T457
Test name
Test status
Simulation time 6833390121 ps
CPU time 19.97 seconds
Started Mar 28 01:38:36 PM PDT 24
Finished Mar 28 01:38:56 PM PDT 24
Peak memory 216232 kb
Host smart-bf1897a2-71d2-476a-8e7a-b3cc376af6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515917134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1515917134
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2092025091
Short name T326
Test name
Test status
Simulation time 242651010 ps
CPU time 1.74 seconds
Started Mar 28 01:38:35 PM PDT 24
Finished Mar 28 01:38:37 PM PDT 24
Peak memory 216212 kb
Host smart-e1902f0c-bfe6-4a19-ac89-a4a390716543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092025091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2092025091
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4264691018
Short name T512
Test name
Test status
Simulation time 129943849 ps
CPU time 0.87 seconds
Started Mar 28 01:38:41 PM PDT 24
Finished Mar 28 01:38:42 PM PDT 24
Peak memory 205540 kb
Host smart-3127a507-60a0-43d9-b0a8-6f626420a00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264691018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4264691018
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3836022565
Short name T574
Test name
Test status
Simulation time 24235507125 ps
CPU time 24.23 seconds
Started Mar 28 01:38:33 PM PDT 24
Finished Mar 28 01:38:58 PM PDT 24
Peak memory 238196 kb
Host smart-7cccb83e-e05f-40b1-a6d5-25b38beb51e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836022565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3836022565
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1473929573
Short name T312
Test name
Test status
Simulation time 64670419 ps
CPU time 0.71 seconds
Started Mar 28 01:38:53 PM PDT 24
Finished Mar 28 01:38:54 PM PDT 24
Peak memory 204576 kb
Host smart-b5e21e24-609c-4497-99ed-8bbef2e1bb52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473929573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1473929573
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3778853919
Short name T661
Test name
Test status
Simulation time 188134057 ps
CPU time 2.5 seconds
Started Mar 28 01:38:35 PM PDT 24
Finished Mar 28 01:38:38 PM PDT 24
Peak memory 233064 kb
Host smart-236463a2-06d3-48a9-a961-80e9c46b43c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778853919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3778853919
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4089408517
Short name T478
Test name
Test status
Simulation time 66590210 ps
CPU time 0.81 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:38:38 PM PDT 24
Peak memory 206240 kb
Host smart-05659157-5b95-4102-8407-e77aebd7fc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089408517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4089408517
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1594012090
Short name T505
Test name
Test status
Simulation time 16759974176 ps
CPU time 33.44 seconds
Started Mar 28 01:38:35 PM PDT 24
Finished Mar 28 01:39:08 PM PDT 24
Peak memory 249084 kb
Host smart-05dd96a9-5f42-4eb5-a9c4-515844b4e58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594012090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1594012090
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3951990396
Short name T238
Test name
Test status
Simulation time 27769038894 ps
CPU time 117.75 seconds
Started Mar 28 01:38:33 PM PDT 24
Finished Mar 28 01:40:31 PM PDT 24
Peak memory 273580 kb
Host smart-2c21d60b-32d9-4611-a1b0-5af4d97229b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951990396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3951990396
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1371317824
Short name T118
Test name
Test status
Simulation time 12851786186 ps
CPU time 34.74 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:39:13 PM PDT 24
Peak memory 240480 kb
Host smart-a859f10d-bcc6-4d2d-bdd0-d1d70d0e13ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371317824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1371317824
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3932488029
Short name T793
Test name
Test status
Simulation time 4740734157 ps
CPU time 4.55 seconds
Started Mar 28 01:38:39 PM PDT 24
Finished Mar 28 01:38:44 PM PDT 24
Peak memory 218396 kb
Host smart-4cbed634-4931-4d69-82d4-30188d1c639d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932488029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3932488029
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2098565503
Short name T277
Test name
Test status
Simulation time 3086970418 ps
CPU time 9.83 seconds
Started Mar 28 01:38:40 PM PDT 24
Finished Mar 28 01:38:50 PM PDT 24
Peak memory 239072 kb
Host smart-57b4b000-1a95-41df-8c77-e2b8a4ae349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098565503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2098565503
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1486118299
Short name T609
Test name
Test status
Simulation time 205836996 ps
CPU time 3.07 seconds
Started Mar 28 01:38:40 PM PDT 24
Finished Mar 28 01:38:43 PM PDT 24
Peak memory 233280 kb
Host smart-ce43893b-fbbc-436a-b1b7-1aff7f02be3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486118299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1486118299
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4269552675
Short name T289
Test name
Test status
Simulation time 112298686 ps
CPU time 2.08 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:40 PM PDT 24
Peak memory 224412 kb
Host smart-342031fd-0f61-4e80-9542-d3ecf64a4717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269552675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4269552675
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3536675825
Short name T33
Test name
Test status
Simulation time 1976598721 ps
CPU time 4.62 seconds
Started Mar 28 01:38:36 PM PDT 24
Finished Mar 28 01:38:41 PM PDT 24
Peak memory 221504 kb
Host smart-c14653f6-917a-4079-af6a-0fff4041cb5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3536675825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3536675825
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2956595352
Short name T876
Test name
Test status
Simulation time 95177507603 ps
CPU time 357.61 seconds
Started Mar 28 01:38:49 PM PDT 24
Finished Mar 28 01:44:47 PM PDT 24
Peak memory 283164 kb
Host smart-85d6333d-9401-4653-b869-447251430ed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956595352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2956595352
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1448446759
Short name T891
Test name
Test status
Simulation time 258305827 ps
CPU time 3.93 seconds
Started Mar 28 01:38:37 PM PDT 24
Finished Mar 28 01:38:41 PM PDT 24
Peak memory 216428 kb
Host smart-7bfa5ba8-4766-417e-b49f-ec0eb81f1cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448446759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1448446759
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2447242197
Short name T368
Test name
Test status
Simulation time 23834710483 ps
CPU time 13.24 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:51 PM PDT 24
Peak memory 216256 kb
Host smart-b7ff3877-e6fb-4f0f-a584-c6751efdd549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447242197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2447242197
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.4234327876
Short name T547
Test name
Test status
Simulation time 173485991 ps
CPU time 2.98 seconds
Started Mar 28 01:38:32 PM PDT 24
Finished Mar 28 01:38:35 PM PDT 24
Peak memory 216180 kb
Host smart-b16dd9ad-218b-43c3-a20f-5ee8afbe92ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234327876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.4234327876
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2523206280
Short name T907
Test name
Test status
Simulation time 43095216 ps
CPU time 0.84 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:39 PM PDT 24
Peak memory 205548 kb
Host smart-eca758a4-f1bd-417a-b544-944a42857016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523206280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2523206280
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.343535829
Short name T636
Test name
Test status
Simulation time 1411790338 ps
CPU time 5.89 seconds
Started Mar 28 01:38:38 PM PDT 24
Finished Mar 28 01:38:44 PM PDT 24
Peak memory 229640 kb
Host smart-9225eefa-ae28-46ac-88e0-a336b115567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343535829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.343535829
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4186162465
Short name T365
Test name
Test status
Simulation time 108803434 ps
CPU time 0.76 seconds
Started Mar 28 01:38:47 PM PDT 24
Finished Mar 28 01:38:48 PM PDT 24
Peak memory 204572 kb
Host smart-55f13cd1-3dc3-464b-a755-02f788385ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186162465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4186162465
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1559895322
Short name T909
Test name
Test status
Simulation time 153525791 ps
CPU time 2.35 seconds
Started Mar 28 01:38:48 PM PDT 24
Finished Mar 28 01:38:50 PM PDT 24
Peak memory 218312 kb
Host smart-fc65d277-45a6-4477-ac63-6501d63bce82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559895322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1559895322
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.55218265
Short name T710
Test name
Test status
Simulation time 40070652 ps
CPU time 0.75 seconds
Started Mar 28 01:38:48 PM PDT 24
Finished Mar 28 01:38:49 PM PDT 24
Peak memory 205196 kb
Host smart-940eea1b-8b47-4009-b88e-11a228465ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55218265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.55218265
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4127158467
Short name T735
Test name
Test status
Simulation time 63093524648 ps
CPU time 151.17 seconds
Started Mar 28 01:38:49 PM PDT 24
Finished Mar 28 01:41:21 PM PDT 24
Peak memory 252004 kb
Host smart-ec3fd82c-055e-4187-8ba5-fbd0689918ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127158467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4127158467
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3580070897
Short name T237
Test name
Test status
Simulation time 156509772536 ps
CPU time 578.32 seconds
Started Mar 28 01:38:46 PM PDT 24
Finished Mar 28 01:48:25 PM PDT 24
Peak memory 255968 kb
Host smart-c31a6526-328a-4163-a8f7-b28aee5669dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580070897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3580070897
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.254438650
Short name T412
Test name
Test status
Simulation time 6575718712 ps
CPU time 13.9 seconds
Started Mar 28 01:38:53 PM PDT 24
Finished Mar 28 01:39:07 PM PDT 24
Peak memory 245820 kb
Host smart-b4154aa7-dd62-464d-83d4-2677cb865a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254438650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.254438650
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1496967722
Short name T165
Test name
Test status
Simulation time 11438690214 ps
CPU time 9.88 seconds
Started Mar 28 01:38:48 PM PDT 24
Finished Mar 28 01:38:58 PM PDT 24
Peak memory 224452 kb
Host smart-242c4948-2613-4a1d-98fe-24c65fd166de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496967722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1496967722
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.397143670
Short name T414
Test name
Test status
Simulation time 3260874831 ps
CPU time 17.64 seconds
Started Mar 28 01:38:47 PM PDT 24
Finished Mar 28 01:39:05 PM PDT 24
Peak memory 232556 kb
Host smart-c093e344-8849-4725-8856-e4ee065c3178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397143670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.397143670
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1862256934
Short name T249
Test name
Test status
Simulation time 1839303399 ps
CPU time 12.77 seconds
Started Mar 28 01:38:49 PM PDT 24
Finished Mar 28 01:39:02 PM PDT 24
Peak memory 229224 kb
Host smart-7b3355a3-fc2b-4da1-a1bd-21dd174f4c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862256934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1862256934
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3869542134
Short name T946
Test name
Test status
Simulation time 11516381352 ps
CPU time 10.5 seconds
Started Mar 28 01:38:49 PM PDT 24
Finished Mar 28 01:39:00 PM PDT 24
Peak memory 224484 kb
Host smart-65c52194-3aed-4fcc-93d2-eac477fd7a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869542134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3869542134
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2652847525
Short name T119
Test name
Test status
Simulation time 7036224323 ps
CPU time 7.41 seconds
Started Mar 28 01:38:47 PM PDT 24
Finished Mar 28 01:38:54 PM PDT 24
Peak memory 218772 kb
Host smart-41cff546-a91a-4f13-bd56-2cecec86e4f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2652847525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2652847525
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.590294006
Short name T202
Test name
Test status
Simulation time 306088826366 ps
CPU time 599.72 seconds
Started Mar 28 01:38:47 PM PDT 24
Finished Mar 28 01:48:47 PM PDT 24
Peak memory 270876 kb
Host smart-bfa1bff0-8119-422f-b1d0-85ac10a100b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590294006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.590294006
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.676089586
Short name T348
Test name
Test status
Simulation time 24284514350 ps
CPU time 40.65 seconds
Started Mar 28 01:38:46 PM PDT 24
Finished Mar 28 01:39:27 PM PDT 24
Peak memory 216152 kb
Host smart-15b5529a-ae0f-4aae-b59b-c3c29a49b92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676089586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.676089586
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.379556834
Short name T276
Test name
Test status
Simulation time 2648115711 ps
CPU time 8.69 seconds
Started Mar 28 01:38:52 PM PDT 24
Finished Mar 28 01:39:01 PM PDT 24
Peak memory 216692 kb
Host smart-a04cc24d-8fd9-4773-851d-5f12dd769d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379556834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.379556834
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3976002039
Short name T410
Test name
Test status
Simulation time 369053755 ps
CPU time 5.26 seconds
Started Mar 28 01:38:49 PM PDT 24
Finished Mar 28 01:38:54 PM PDT 24
Peak memory 216160 kb
Host smart-896be3f3-f5b7-47f5-8096-48a5dee9fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976002039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3976002039
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3760452530
Short name T714
Test name
Test status
Simulation time 80297429 ps
CPU time 0.79 seconds
Started Mar 28 01:38:50 PM PDT 24
Finished Mar 28 01:38:51 PM PDT 24
Peak memory 205544 kb
Host smart-6cff3104-8b20-4152-a4b4-0500ca743955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760452530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3760452530
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3056311118
Short name T670
Test name
Test status
Simulation time 7347796269 ps
CPU time 8.76 seconds
Started Mar 28 01:38:48 PM PDT 24
Finished Mar 28 01:38:57 PM PDT 24
Peak memory 217308 kb
Host smart-4c0d0588-80b2-4205-b082-383ca3b55d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056311118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3056311118
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2971144668
Short name T398
Test name
Test status
Simulation time 43380875 ps
CPU time 0.8 seconds
Started Mar 28 01:36:07 PM PDT 24
Finished Mar 28 01:36:08 PM PDT 24
Peak memory 205168 kb
Host smart-99f67e24-8ba1-4499-96a5-4eb7878d9eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971144668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
971144668
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2440335856
Short name T320
Test name
Test status
Simulation time 390794546 ps
CPU time 2.51 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:12 PM PDT 24
Peak memory 224348 kb
Host smart-adfd2a4e-5b11-4d2d-bdb9-af63bb0cafa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440335856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2440335856
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4254885594
Short name T353
Test name
Test status
Simulation time 20039918 ps
CPU time 0.81 seconds
Started Mar 28 01:36:02 PM PDT 24
Finished Mar 28 01:36:03 PM PDT 24
Peak memory 206320 kb
Host smart-a079022c-dc48-449c-918f-cb876a4ccdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254885594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4254885594
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.317586425
Short name T179
Test name
Test status
Simulation time 67627822973 ps
CPU time 121.93 seconds
Started Mar 28 01:36:08 PM PDT 24
Finished Mar 28 01:38:10 PM PDT 24
Peak memory 252448 kb
Host smart-3393da7a-a09e-4578-9d66-5d5eb7476514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317586425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.317586425
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2803533194
Short name T235
Test name
Test status
Simulation time 21380372703 ps
CPU time 91.87 seconds
Started Mar 28 01:36:08 PM PDT 24
Finished Mar 28 01:37:40 PM PDT 24
Peak memory 250152 kb
Host smart-5e7ac112-5a56-48af-92f7-112a1daef636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803533194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2803533194
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.964579370
Short name T247
Test name
Test status
Simulation time 11273958669 ps
CPU time 112.15 seconds
Started Mar 28 01:36:07 PM PDT 24
Finished Mar 28 01:38:00 PM PDT 24
Peak memory 250172 kb
Host smart-fc7c968b-23f0-44d2-9390-77bd0000de70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964579370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
964579370
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1678203927
Short name T657
Test name
Test status
Simulation time 2435198416 ps
CPU time 8.96 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:19 PM PDT 24
Peak memory 232704 kb
Host smart-8ac9c478-8f50-45e2-b5f8-27e84ded1520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678203927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1678203927
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.161496109
Short name T711
Test name
Test status
Simulation time 658447590 ps
CPU time 6.44 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:16 PM PDT 24
Peak memory 236460 kb
Host smart-a4d8b0d8-47d7-4882-bb5c-b885d6777ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161496109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.161496109
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3872770514
Short name T413
Test name
Test status
Simulation time 8927399237 ps
CPU time 19.15 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:29 PM PDT 24
Peak memory 228760 kb
Host smart-1af028e6-cf49-4455-9e4a-5538144e281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872770514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3872770514
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.65593272
Short name T22
Test name
Test status
Simulation time 35856537 ps
CPU time 1.03 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 217740 kb
Host smart-05741911-93d2-499f-86a3-59aabe0f17ea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65593272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.65593272
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2709262971
Short name T373
Test name
Test status
Simulation time 1975183830 ps
CPU time 8.26 seconds
Started Mar 28 01:36:08 PM PDT 24
Finished Mar 28 01:36:16 PM PDT 24
Peak memory 224428 kb
Host smart-81377321-5708-4d57-afba-b7c1a5de16ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709262971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2709262971
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3232080130
Short name T712
Test name
Test status
Simulation time 5608580198 ps
CPU time 8.58 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:19 PM PDT 24
Peak memory 219140 kb
Host smart-eeeb6727-e4a9-4805-b437-8cf0be1d82b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232080130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3232080130
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.2834103164
Short name T607
Test name
Test status
Simulation time 22718553 ps
CPU time 0.78 seconds
Started Mar 28 01:36:01 PM PDT 24
Finished Mar 28 01:36:02 PM PDT 24
Peak memory 216100 kb
Host smart-922858aa-2300-47c1-8506-4df142142b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834103164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.2834103164
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2847672003
Short name T383
Test name
Test status
Simulation time 4125967545 ps
CPU time 5.96 seconds
Started Mar 28 01:36:08 PM PDT 24
Finished Mar 28 01:36:14 PM PDT 24
Peak memory 222588 kb
Host smart-52a175c6-47d2-4986-aba5-f5805021337d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2847672003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2847672003
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.925549514
Short name T804
Test name
Test status
Simulation time 75286847030 ps
CPU time 399.65 seconds
Started Mar 28 01:36:08 PM PDT 24
Finished Mar 28 01:42:49 PM PDT 24
Peak memory 272248 kb
Host smart-10392023-1692-4318-a720-899097dd3664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925549514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.925549514
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3411778531
Short name T433
Test name
Test status
Simulation time 7627158323 ps
CPU time 12.84 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:23 PM PDT 24
Peak memory 219448 kb
Host smart-e980e6f1-0865-4acf-9b1b-7cecb2c0d9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411778531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3411778531
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.640353646
Short name T637
Test name
Test status
Simulation time 5003051338 ps
CPU time 12.62 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:22 PM PDT 24
Peak memory 216284 kb
Host smart-7422e994-3450-4468-8515-b94cb2ef0e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640353646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.640353646
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2373249596
Short name T965
Test name
Test status
Simulation time 214703635 ps
CPU time 3.99 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:15 PM PDT 24
Peak memory 216128 kb
Host smart-df2a4f5f-c4e0-468b-ad8a-d029d7e52656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373249596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2373249596
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.999314087
Short name T915
Test name
Test status
Simulation time 92114959 ps
CPU time 0.88 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:11 PM PDT 24
Peak memory 205540 kb
Host smart-8df29926-3bde-4308-99fb-0087388bfe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999314087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.999314087
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2415153575
Short name T315
Test name
Test status
Simulation time 581938330 ps
CPU time 3.62 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:13 PM PDT 24
Peak memory 218584 kb
Host smart-26ac05ef-32f5-4813-a4e0-40aa79eebc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415153575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2415153575
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1388282996
Short name T868
Test name
Test status
Simulation time 39160896 ps
CPU time 0.74 seconds
Started Mar 28 01:36:17 PM PDT 24
Finished Mar 28 01:36:18 PM PDT 24
Peak memory 205144 kb
Host smart-73317de2-3942-4a32-a8a7-650d8c750a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388282996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
388282996
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.113301514
Short name T224
Test name
Test status
Simulation time 123955721 ps
CPU time 2.12 seconds
Started Mar 28 01:36:11 PM PDT 24
Finished Mar 28 01:36:13 PM PDT 24
Peak memory 218360 kb
Host smart-f4d4644a-697a-453a-9254-cbf1b668466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113301514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.113301514
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.722662212
Short name T960
Test name
Test status
Simulation time 46273257 ps
CPU time 0.77 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 206252 kb
Host smart-e1a3f6ba-b930-4b67-8afb-936620ee4d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722662212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.722662212
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3562724265
Short name T927
Test name
Test status
Simulation time 73286044985 ps
CPU time 168.49 seconds
Started Mar 28 01:36:15 PM PDT 24
Finished Mar 28 01:39:04 PM PDT 24
Peak memory 252452 kb
Host smart-5fbc4535-f48b-4e78-8e89-20c49fb8eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562724265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3562724265
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4195821095
Short name T19
Test name
Test status
Simulation time 100143777802 ps
CPU time 682.46 seconds
Started Mar 28 01:36:17 PM PDT 24
Finished Mar 28 01:47:40 PM PDT 24
Peak memory 269236 kb
Host smart-032bed91-b6a0-4324-9fe2-9bc9b684bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195821095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4195821095
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.932607525
Short name T124
Test name
Test status
Simulation time 618484539 ps
CPU time 13.24 seconds
Started Mar 28 01:36:11 PM PDT 24
Finished Mar 28 01:36:24 PM PDT 24
Peak memory 235912 kb
Host smart-3600daba-3d8c-4524-a91a-1f725f4c0548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932607525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.932607525
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.637935627
Short name T199
Test name
Test status
Simulation time 2169178130 ps
CPU time 8.04 seconds
Started Mar 28 01:36:18 PM PDT 24
Finished Mar 28 01:36:26 PM PDT 24
Peak memory 224404 kb
Host smart-566f723a-c351-4319-b3a7-8d7e3972d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637935627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.637935627
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3607639474
Short name T168
Test name
Test status
Simulation time 15056014698 ps
CPU time 44.32 seconds
Started Mar 28 01:36:12 PM PDT 24
Finished Mar 28 01:36:57 PM PDT 24
Peak memory 240356 kb
Host smart-c0bb486e-4f97-4979-9543-fd7e53b86c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607639474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3607639474
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2607537616
Short name T347
Test name
Test status
Simulation time 14792810 ps
CPU time 1 seconds
Started Mar 28 01:36:09 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 217736 kb
Host smart-22649657-8983-4fbe-a56d-8f707b17df1c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607537616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2607537616
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2757378940
Short name T188
Test name
Test status
Simulation time 3957686610 ps
CPU time 4.59 seconds
Started Mar 28 01:36:29 PM PDT 24
Finished Mar 28 01:36:33 PM PDT 24
Peak memory 233656 kb
Host smart-f41b025a-75d9-4bbe-b94b-2dab38188780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757378940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2757378940
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3399705566
Short name T715
Test name
Test status
Simulation time 27739666608 ps
CPU time 13.52 seconds
Started Mar 28 01:36:07 PM PDT 24
Finished Mar 28 01:36:21 PM PDT 24
Peak memory 241936 kb
Host smart-ae799af1-1a31-4ca6-bf54-d8374b1d5a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399705566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3399705566
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.4016364382
Short name T528
Test name
Test status
Simulation time 25012694 ps
CPU time 0.72 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:07 PM PDT 24
Peak memory 216140 kb
Host smart-ca780e54-699f-420f-9021-447a4fa81bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016364382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.4016364382
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1637629673
Short name T292
Test name
Test status
Simulation time 6794504831 ps
CPU time 6.4 seconds
Started Mar 28 01:36:15 PM PDT 24
Finished Mar 28 01:36:22 PM PDT 24
Peak memory 219880 kb
Host smart-f250c9de-8fd7-4cb4-b46b-492b65f55f30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1637629673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1637629673
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.504420578
Short name T127
Test name
Test status
Simulation time 216138845824 ps
CPU time 102.57 seconds
Started Mar 28 01:36:13 PM PDT 24
Finished Mar 28 01:37:56 PM PDT 24
Peak memory 254824 kb
Host smart-7b19ab5d-6fe9-443b-99cc-c3880793b4cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504420578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.504420578
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2536142198
Short name T564
Test name
Test status
Simulation time 1372329220 ps
CPU time 5.23 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:11 PM PDT 24
Peak memory 216168 kb
Host smart-84b53ea7-c09a-43c6-8c8c-a10caa5b2fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536142198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2536142198
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3992223214
Short name T509
Test name
Test status
Simulation time 8062783511 ps
CPU time 23.13 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:29 PM PDT 24
Peak memory 216232 kb
Host smart-7f9eefa3-b422-44a7-b549-31d4f175c15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992223214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3992223214
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2979749810
Short name T400
Test name
Test status
Simulation time 105830677 ps
CPU time 1.37 seconds
Started Mar 28 01:36:10 PM PDT 24
Finished Mar 28 01:36:11 PM PDT 24
Peak memory 216160 kb
Host smart-9a9a78ad-307f-4873-b2f3-662ce8b34157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979749810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2979749810
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1134063517
Short name T923
Test name
Test status
Simulation time 177214948 ps
CPU time 0.91 seconds
Started Mar 28 01:36:06 PM PDT 24
Finished Mar 28 01:36:07 PM PDT 24
Peak memory 206608 kb
Host smart-c10ef50b-087a-49ef-a775-8a26e4b2fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134063517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1134063517
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2467202762
Short name T752
Test name
Test status
Simulation time 10268619805 ps
CPU time 31.96 seconds
Started Mar 28 01:36:15 PM PDT 24
Finished Mar 28 01:36:48 PM PDT 24
Peak memory 238496 kb
Host smart-f4f0b5e0-c098-4564-b4c1-ffcd3b054b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467202762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2467202762
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.211253541
Short name T792
Test name
Test status
Simulation time 17155798 ps
CPU time 0.69 seconds
Started Mar 28 01:36:18 PM PDT 24
Finished Mar 28 01:36:19 PM PDT 24
Peak memory 204572 kb
Host smart-c77c4f40-8e39-473e-b668-0309b71407fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211253541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.211253541
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.592324148
Short name T194
Test name
Test status
Simulation time 439787612 ps
CPU time 3.7 seconds
Started Mar 28 01:36:24 PM PDT 24
Finished Mar 28 01:36:29 PM PDT 24
Peak memory 233412 kb
Host smart-2b80cff1-db96-459b-908e-5e7a202db133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592324148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.592324148
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2342732813
Short name T490
Test name
Test status
Simulation time 17082981 ps
CPU time 0.83 seconds
Started Mar 28 01:36:14 PM PDT 24
Finished Mar 28 01:36:16 PM PDT 24
Peak memory 206192 kb
Host smart-f13c1695-3eb5-4169-a698-7e64c31b5c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342732813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2342732813
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1477060036
Short name T234
Test name
Test status
Simulation time 109735018371 ps
CPU time 560.46 seconds
Started Mar 28 01:36:18 PM PDT 24
Finished Mar 28 01:45:38 PM PDT 24
Peak memory 273588 kb
Host smart-4f7e9a87-76ff-416b-b30e-7c1c4012bf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477060036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1477060036
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.929741385
Short name T803
Test name
Test status
Simulation time 15660657168 ps
CPU time 52.62 seconds
Started Mar 28 01:36:17 PM PDT 24
Finished Mar 28 01:37:10 PM PDT 24
Peak memory 235972 kb
Host smart-39dfa691-6de6-4e5c-8e4a-48016ae6a623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929741385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.929741385
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.225801547
Short name T439
Test name
Test status
Simulation time 39804103035 ps
CPU time 129.16 seconds
Started Mar 28 01:36:25 PM PDT 24
Finished Mar 28 01:38:34 PM PDT 24
Peak memory 240120 kb
Host smart-6edbc6e9-02a1-4626-949d-623314c3366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225801547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
225801547
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1344299987
Short name T481
Test name
Test status
Simulation time 674255603 ps
CPU time 8.99 seconds
Started Mar 28 01:36:19 PM PDT 24
Finished Mar 28 01:36:28 PM PDT 24
Peak memory 240556 kb
Host smart-aea4796c-2466-4fc8-bc2d-cfa2bc4022aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344299987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1344299987
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1304264570
Short name T190
Test name
Test status
Simulation time 8700633762 ps
CPU time 8.15 seconds
Started Mar 28 01:36:17 PM PDT 24
Finished Mar 28 01:36:25 PM PDT 24
Peak memory 224432 kb
Host smart-b5719b4a-925f-4a32-a7d4-eb2dd83c8f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304264570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1304264570
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1692531608
Short name T149
Test name
Test status
Simulation time 5196642646 ps
CPU time 14.79 seconds
Started Mar 28 01:36:30 PM PDT 24
Finished Mar 28 01:36:45 PM PDT 24
Peak memory 249104 kb
Host smart-ac78b028-14cc-4cac-af9d-8b1bf0f175c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692531608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1692531608
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3789275233
Short name T760
Test name
Test status
Simulation time 27093342 ps
CPU time 1.14 seconds
Started Mar 28 01:36:17 PM PDT 24
Finished Mar 28 01:36:18 PM PDT 24
Peak memory 216520 kb
Host smart-f1c3cb8e-d560-4673-8271-9b6b0bf0e2ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789275233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3789275233
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.279464872
Short name T7
Test name
Test status
Simulation time 11713721851 ps
CPU time 30.75 seconds
Started Mar 28 01:36:17 PM PDT 24
Finished Mar 28 01:36:48 PM PDT 24
Peak memory 238360 kb
Host smart-772148de-baa0-4113-8fca-d7a6e27b24a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279464872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
279464872
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3701110422
Short name T655
Test name
Test status
Simulation time 1879498947 ps
CPU time 8.23 seconds
Started Mar 28 01:36:15 PM PDT 24
Finished Mar 28 01:36:24 PM PDT 24
Peak memory 233776 kb
Host smart-0d245d0d-f7e7-46dd-9a93-fbcc2ae0a629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701110422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3701110422
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.3053185986
Short name T964
Test name
Test status
Simulation time 20136471 ps
CPU time 0.77 seconds
Started Mar 28 01:36:13 PM PDT 24
Finished Mar 28 01:36:14 PM PDT 24
Peak memory 216080 kb
Host smart-facda3f6-9f44-4acc-927d-3454012b0ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053185986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.3053185986
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1421793472
Short name T520
Test name
Test status
Simulation time 493416413 ps
CPU time 3.84 seconds
Started Mar 28 01:36:21 PM PDT 24
Finished Mar 28 01:36:25 PM PDT 24
Peak memory 221468 kb
Host smart-9502ebcf-a28d-4ef3-8c5c-d67f115c255c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1421793472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1421793472
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3725727120
Short name T943
Test name
Test status
Simulation time 6973404569 ps
CPU time 85.63 seconds
Started Mar 28 01:36:33 PM PDT 24
Finished Mar 28 01:37:59 PM PDT 24
Peak memory 253640 kb
Host smart-67c5f8ef-a308-4c7b-8ed2-bc119c8bf09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725727120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3725727120
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4241922221
Short name T568
Test name
Test status
Simulation time 7899379402 ps
CPU time 16.16 seconds
Started Mar 28 01:36:26 PM PDT 24
Finished Mar 28 01:36:42 PM PDT 24
Peak memory 216204 kb
Host smart-5063b843-322f-4438-8754-387c6d8b9094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241922221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4241922221
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1521253614
Short name T864
Test name
Test status
Simulation time 3511345454 ps
CPU time 11.4 seconds
Started Mar 28 01:36:26 PM PDT 24
Finished Mar 28 01:36:37 PM PDT 24
Peak memory 216196 kb
Host smart-8856f5f7-b289-4958-a991-b0208d64f986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521253614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1521253614
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.803130359
Short name T845
Test name
Test status
Simulation time 290651729 ps
CPU time 2.26 seconds
Started Mar 28 01:36:21 PM PDT 24
Finished Mar 28 01:36:24 PM PDT 24
Peak memory 216252 kb
Host smart-85ae81e0-f0f6-4afe-9eda-2abc8900dc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803130359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.803130359
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3853314100
Short name T477
Test name
Test status
Simulation time 78642378 ps
CPU time 0.86 seconds
Started Mar 28 01:36:12 PM PDT 24
Finished Mar 28 01:36:13 PM PDT 24
Peak memory 205536 kb
Host smart-0833e2f3-a0e5-453c-9b3f-8a9e3c4114d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853314100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3853314100
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3928064698
Short name T673
Test name
Test status
Simulation time 117401663 ps
CPU time 2.87 seconds
Started Mar 28 01:36:18 PM PDT 24
Finished Mar 28 01:36:21 PM PDT 24
Peak memory 224352 kb
Host smart-dfa54b9b-34d6-435b-aedf-760821a7e6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928064698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3928064698
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.98412143
Short name T269
Test name
Test status
Simulation time 29571432 ps
CPU time 0.7 seconds
Started Mar 28 01:36:26 PM PDT 24
Finished Mar 28 01:36:27 PM PDT 24
Peak memory 204580 kb
Host smart-8dbc7901-25b9-48db-9233-3a1773708b47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98412143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.98412143
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1636565653
Short name T706
Test name
Test status
Simulation time 1614251279 ps
CPU time 5.44 seconds
Started Mar 28 01:36:26 PM PDT 24
Finished Mar 28 01:36:31 PM PDT 24
Peak memory 219700 kb
Host smart-c1cbc364-3340-4676-bc96-c8b65221b73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636565653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1636565653
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.677100170
Short name T683
Test name
Test status
Simulation time 14459382 ps
CPU time 0.79 seconds
Started Mar 28 01:36:12 PM PDT 24
Finished Mar 28 01:36:12 PM PDT 24
Peak memory 206176 kb
Host smart-4d7d6620-2895-4994-a26e-3dd1402e4191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677100170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.677100170
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.887707568
Short name T154
Test name
Test status
Simulation time 24282960165 ps
CPU time 62.63 seconds
Started Mar 28 01:36:17 PM PDT 24
Finished Mar 28 01:37:20 PM PDT 24
Peak memory 253448 kb
Host smart-aacbb8cb-77ce-494e-9196-73d5c4033a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887707568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.887707568
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1038822318
Short name T854
Test name
Test status
Simulation time 19622905524 ps
CPU time 199.02 seconds
Started Mar 28 01:36:14 PM PDT 24
Finished Mar 28 01:39:33 PM PDT 24
Peak memory 256780 kb
Host smart-c1f0348f-fb28-4595-8997-d498c1a2c6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038822318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1038822318
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3898491494
Short name T65
Test name
Test status
Simulation time 43139234716 ps
CPU time 321.99 seconds
Started Mar 28 01:36:16 PM PDT 24
Finished Mar 28 01:41:38 PM PDT 24
Peak memory 253680 kb
Host smart-196a266d-127a-4f98-bd77-3c11874535ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898491494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3898491494
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3693074526
Short name T610
Test name
Test status
Simulation time 1785873730 ps
CPU time 17.27 seconds
Started Mar 28 01:36:15 PM PDT 24
Finished Mar 28 01:36:33 PM PDT 24
Peak memory 231036 kb
Host smart-d7396c12-ac64-4eab-98c9-90e352785870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693074526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3693074526
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.724064407
Short name T534
Test name
Test status
Simulation time 1162884175 ps
CPU time 3.3 seconds
Started Mar 28 01:36:15 PM PDT 24
Finished Mar 28 01:36:19 PM PDT 24
Peak memory 233532 kb
Host smart-2c079cef-c08d-48de-a2fe-b9dd87e6e941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724064407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.724064407
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1719765374
Short name T951
Test name
Test status
Simulation time 3202567807 ps
CPU time 9.29 seconds
Started Mar 28 01:36:15 PM PDT 24
Finished Mar 28 01:36:25 PM PDT 24
Peak memory 217800 kb
Host smart-e1049151-6b05-4820-9976-840efa88f099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719765374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1719765374
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1888141308
Short name T648
Test name
Test status
Simulation time 66277017 ps
CPU time 1.15 seconds
Started Mar 28 01:36:26 PM PDT 24
Finished Mar 28 01:36:27 PM PDT 24
Peak memory 216520 kb
Host smart-47fd8200-0330-46d4-90ea-257fa9167f0b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888141308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1888141308
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.90337291
Short name T389
Test name
Test status
Simulation time 7248283563 ps
CPU time 23.6 seconds
Started Mar 28 01:36:32 PM PDT 24
Finished Mar 28 01:36:57 PM PDT 24
Peak memory 239176 kb
Host smart-2eb8063e-7a18-40a3-a7b3-2587c0ef1867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90337291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.90337291
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3989056338
Short name T139
Test name
Test status
Simulation time 1098012863 ps
CPU time 8.14 seconds
Started Mar 28 01:36:16 PM PDT 24
Finished Mar 28 01:36:25 PM PDT 24
Peak memory 228516 kb
Host smart-a1be8f9f-29a9-4dc6-aded-9d6a6aeef25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989056338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3989056338
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.249688823
Short name T724
Test name
Test status
Simulation time 15475699 ps
CPU time 0.75 seconds
Started Mar 28 01:36:13 PM PDT 24
Finished Mar 28 01:36:14 PM PDT 24
Peak memory 216132 kb
Host smart-206313a3-f067-4a26-805d-872d32c07a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249688823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.249688823
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4049474300
Short name T757
Test name
Test status
Simulation time 552507182 ps
CPU time 2.98 seconds
Started Mar 28 01:36:13 PM PDT 24
Finished Mar 28 01:36:16 PM PDT 24
Peak memory 218572 kb
Host smart-f7c89132-479e-4e34-8118-145cd76ef8ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4049474300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4049474300
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1598105757
Short name T14
Test name
Test status
Simulation time 2004684540 ps
CPU time 29.5 seconds
Started Mar 28 01:36:17 PM PDT 24
Finished Mar 28 01:36:47 PM PDT 24
Peak memory 216256 kb
Host smart-cae75ba7-1718-40fb-bc05-87a088f59ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598105757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1598105757
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3765444428
Short name T874
Test name
Test status
Simulation time 2302943467 ps
CPU time 7 seconds
Started Mar 28 01:36:17 PM PDT 24
Finished Mar 28 01:36:25 PM PDT 24
Peak memory 216112 kb
Host smart-46bdb32d-8c94-42f9-9419-af82191e4743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765444428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3765444428
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3830975684
Short name T461
Test name
Test status
Simulation time 270827468 ps
CPU time 5.66 seconds
Started Mar 28 01:36:16 PM PDT 24
Finished Mar 28 01:36:22 PM PDT 24
Peak memory 216140 kb
Host smart-06381b5d-ef05-47fb-a718-7bef283f27d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830975684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3830975684
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3919763070
Short name T649
Test name
Test status
Simulation time 145108253 ps
CPU time 0.77 seconds
Started Mar 28 01:36:14 PM PDT 24
Finished Mar 28 01:36:14 PM PDT 24
Peak memory 205504 kb
Host smart-3cea2c20-7e2b-4695-a56a-1ab756d301db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919763070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3919763070
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2999392907
Short name T689
Test name
Test status
Simulation time 17110093583 ps
CPU time 16.32 seconds
Started Mar 28 01:36:21 PM PDT 24
Finished Mar 28 01:36:38 PM PDT 24
Peak memory 227620 kb
Host smart-7cc6ac3d-e72e-4d56-a960-88e7fcc68ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999392907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2999392907
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.684209395
Short name T620
Test name
Test status
Simulation time 15435720 ps
CPU time 0.71 seconds
Started Mar 28 01:36:35 PM PDT 24
Finished Mar 28 01:36:36 PM PDT 24
Peak memory 205160 kb
Host smart-b42cdf2c-8a92-4c4b-bb23-2b03f475d151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684209395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.684209395
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1622836424
Short name T63
Test name
Test status
Simulation time 324207561 ps
CPU time 2.95 seconds
Started Mar 28 01:36:12 PM PDT 24
Finished Mar 28 01:36:15 PM PDT 24
Peak memory 219680 kb
Host smart-00c4401f-c92e-4939-9f7b-75233287b78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622836424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1622836424
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1959842820
Short name T304
Test name
Test status
Simulation time 19838426 ps
CPU time 0.8 seconds
Started Mar 28 01:36:26 PM PDT 24
Finished Mar 28 01:36:27 PM PDT 24
Peak memory 206240 kb
Host smart-5ec50b1b-7058-4af1-9ae9-27fefa96e099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959842820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1959842820
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1960784452
Short name T945
Test name
Test status
Simulation time 67389546726 ps
CPU time 94.05 seconds
Started Mar 28 01:36:21 PM PDT 24
Finished Mar 28 01:37:55 PM PDT 24
Peak memory 249008 kb
Host smart-0dd74d2b-3376-434a-9337-57bcef29345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960784452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1960784452
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2529846399
Short name T949
Test name
Test status
Simulation time 9909625533 ps
CPU time 67.92 seconds
Started Mar 28 01:36:33 PM PDT 24
Finished Mar 28 01:37:41 PM PDT 24
Peak memory 249096 kb
Host smart-ce381d43-e519-4651-bba5-9a3a062e5a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529846399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2529846399
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.362724499
Short name T492
Test name
Test status
Simulation time 3259942035 ps
CPU time 21.53 seconds
Started Mar 28 01:36:22 PM PDT 24
Finished Mar 28 01:36:44 PM PDT 24
Peak memory 240796 kb
Host smart-8ba6e7d9-d1b0-4b33-a275-12db6b55b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362724499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.362724499
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.641418336
Short name T184
Test name
Test status
Simulation time 1323243678 ps
CPU time 5.87 seconds
Started Mar 28 01:36:22 PM PDT 24
Finished Mar 28 01:36:29 PM PDT 24
Peak memory 218560 kb
Host smart-44b1ff38-32fe-4263-9644-ed530f5fab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641418336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.641418336
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3626887232
Short name T912
Test name
Test status
Simulation time 31421238977 ps
CPU time 37.44 seconds
Started Mar 28 01:36:12 PM PDT 24
Finished Mar 28 01:36:50 PM PDT 24
Peak memory 237360 kb
Host smart-80dd8201-f5f3-462e-be8d-77377459ece1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626887232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3626887232
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3989074277
Short name T23
Test name
Test status
Simulation time 40510140 ps
CPU time 1.13 seconds
Started Mar 28 01:36:21 PM PDT 24
Finished Mar 28 01:36:23 PM PDT 24
Peak memory 216172 kb
Host smart-01c391b4-d695-4771-b584-ca34a0e12f37
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989074277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3989074277
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2041793876
Short name T632
Test name
Test status
Simulation time 2921718439 ps
CPU time 4.44 seconds
Started Mar 28 01:36:17 PM PDT 24
Finished Mar 28 01:36:22 PM PDT 24
Peak memory 232680 kb
Host smart-961b9fd5-22f4-440f-b1df-09270cabddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041793876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2041793876
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1943128079
Short name T740
Test name
Test status
Simulation time 665241074 ps
CPU time 3.26 seconds
Started Mar 28 01:36:22 PM PDT 24
Finished Mar 28 01:36:26 PM PDT 24
Peak memory 216644 kb
Host smart-8f19643e-1427-4d4b-9a0c-da2924b865bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943128079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1943128079
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.1802542173
Short name T815
Test name
Test status
Simulation time 16530152 ps
CPU time 0.76 seconds
Started Mar 28 01:36:18 PM PDT 24
Finished Mar 28 01:36:19 PM PDT 24
Peak memory 216100 kb
Host smart-a1a8aa0d-280d-457e-823a-d0533397c538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802542173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1802542173
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1667096057
Short name T483
Test name
Test status
Simulation time 198356911 ps
CPU time 4.21 seconds
Started Mar 28 01:36:16 PM PDT 24
Finished Mar 28 01:36:21 PM PDT 24
Peak memory 221976 kb
Host smart-6547ac1b-a840-4dc9-b0b8-87f014093ab4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1667096057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1667096057
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2906445941
Short name T488
Test name
Test status
Simulation time 5762829093 ps
CPU time 19.53 seconds
Started Mar 28 01:36:32 PM PDT 24
Finished Mar 28 01:36:53 PM PDT 24
Peak memory 215952 kb
Host smart-3032ec8a-13a9-4f5e-b19a-9eb9bfc33311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906445941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2906445941
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.92971531
Short name T794
Test name
Test status
Simulation time 1110925541 ps
CPU time 8.89 seconds
Started Mar 28 01:36:18 PM PDT 24
Finished Mar 28 01:36:27 PM PDT 24
Peak memory 216112 kb
Host smart-b12a9f69-c154-4d8a-9bfe-3249e184d64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92971531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.92971531
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3101596636
Short name T901
Test name
Test status
Simulation time 86252000 ps
CPU time 1.91 seconds
Started Mar 28 01:36:33 PM PDT 24
Finished Mar 28 01:36:35 PM PDT 24
Peak memory 216400 kb
Host smart-7fb45bca-4a9f-43c1-80e9-062ee58ecf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101596636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3101596636
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.835268302
Short name T438
Test name
Test status
Simulation time 51025939 ps
CPU time 0.78 seconds
Started Mar 28 01:36:22 PM PDT 24
Finished Mar 28 01:36:23 PM PDT 24
Peak memory 205556 kb
Host smart-4c0fcfb3-40db-4d1f-9c99-56639c5a18c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835268302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.835268302
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2202250740
Short name T651
Test name
Test status
Simulation time 2672173178 ps
CPU time 9.62 seconds
Started Mar 28 01:36:23 PM PDT 24
Finished Mar 28 01:36:33 PM PDT 24
Peak memory 226992 kb
Host smart-48796277-b0e1-4262-bd6a-bb49d3757917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202250740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2202250740
Directory /workspace/9.spi_device_upload/latest
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