Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1318573	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1506366

1

T1

979

T2

29871

T3

109

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2164041	1			T1	139		T2	57887		T3	101
values[0x0]	329806	1			T1	450		T2	473		T3	47
values[0x1]	331092	1			T1	459		T2	471		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1000368	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1824571

1

T1

992

T2

35635

T3

159

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10671	1			T1	6		T2	298		T4	2
valid_sources[0x01]	9329	1			T1	5		T2	237		T3	3
valid_sources[0x02]	9515	1			T1	2		T2	181		T4	2
valid_sources[0x03]	10739	1			T1	6		T2	292		T3	2
valid_sources[0x04]	8825	1			T1	3		T2	206		T4	4
valid_sources[0x05]	8939	1			T1	1		T2	281		T4	5
valid_sources[0x06]	9803	1			T1	2		T2	279		T4	7
valid_sources[0x07]	12197	1			T1	1		T2	247		T4	5
valid_sources[0x08]	14401	1			T1	5		T2	183		T4	4
valid_sources[0x09]	48745	1			T1	2		T2	253		T4	2
valid_sources[0x0a]	11969	1			T1	2		T2	226		T4	2
valid_sources[0x0b]	10811	1			T1	9		T2	228		T4	6
valid_sources[0x0c]	10676	1			T2	224		T4	2		T5	13
valid_sources[0x0d]	11112	1			T2	205		T3	3		T4	3
valid_sources[0x0e]	10313	1			T1	4		T2	268		T4	4
valid_sources[0x0f]	10210	1			T1	8		T2	165		T3	1
valid_sources[0x10]	17183	1			T1	7		T2	271		T4	5
valid_sources[0x11]	9115	1			T1	10		T2	219		T3	1
valid_sources[0x12]	8848	1			T1	1		T2	196		T4	5
valid_sources[0x13]	9290	1			T1	2		T2	305		T3	1
valid_sources[0x14]	18217	1			T1	4		T2	176		T4	1
valid_sources[0x15]	12433	1			T1	7		T2	217		T3	1
valid_sources[0x16]	11316	1			T2	238		T4	3		T5	13
valid_sources[0x17]	9482	1			T1	6		T2	214		T4	3
valid_sources[0x18]	8768	1			T1	1		T2	202		T4	3
valid_sources[0x19]	10895	1			T1	5		T2	224		T4	4
valid_sources[0x1a]	9375	1			T1	3		T2	215		T3	2
valid_sources[0x1b]	11190	1			T1	2		T2	226		T4	3
valid_sources[0x1c]	10214	1			T1	5		T2	268		T4	4
valid_sources[0x1d]	9802	1			T1	8		T2	282		T3	7
valid_sources[0x1e]	8764	1			T1	3		T2	290		T3	3
valid_sources[0x1f]	9983	1			T1	1		T2	161		T4	4
valid_sources[0x20]	12068	1			T1	2		T2	248		T4	3
valid_sources[0x21]	9682	1			T2	256		T3	4		T4	4
valid_sources[0x22]	9788	1			T1	8		T2	238		T4	5
valid_sources[0x23]	8648	1			T1	4		T2	193		T4	4
valid_sources[0x24]	8776	1			T2	193		T4	4		T5	14
valid_sources[0x25]	9786	1			T1	5		T2	219		T4	4
valid_sources[0x26]	10250	1			T1	9		T2	240		T4	2
valid_sources[0x27]	10501	1			T1	8		T2	176		T5	13
valid_sources[0x28]	11262	1			T1	4		T2	238		T3	2
valid_sources[0x29]	9074	1			T1	7		T2	190		T4	3
valid_sources[0x2a]	8334	1			T1	1		T2	234		T4	2
valid_sources[0x2b]	9276	1			T1	6		T2	223		T4	5
valid_sources[0x2c]	13083	1			T1	9		T2	209		T4	3
valid_sources[0x2d]	10089	1			T1	5		T2	279		T4	3
valid_sources[0x2e]	10021	1			T1	7		T2	295		T4	3
valid_sources[0x2f]	11578	1			T1	4		T2	250		T4	11
valid_sources[0x30]	9769	1			T1	8		T2	187		T3	4
valid_sources[0x31]	8814	1			T1	5		T2	266		T4	3
valid_sources[0x32]	9212	1			T1	4		T2	196		T3	1
valid_sources[0x33]	8326	1			T1	5		T2	219		T3	6
valid_sources[0x34]	9040	1			T1	2		T2	245		T3	3
valid_sources[0x35]	13345	1			T1	2		T2	267		T3	5
valid_sources[0x36]	8860	1			T1	1		T2	240		T4	8
valid_sources[0x37]	10266	1			T1	8		T2	156		T5	17
valid_sources[0x38]	15716	1			T1	1		T2	235		T4	8
valid_sources[0x39]	8426	1			T1	1		T2	209		T4	3
valid_sources[0x3a]	8935	1			T1	2		T2	213		T4	1
valid_sources[0x3b]	9053	1			T1	1		T2	197		T4	4
valid_sources[0x3c]	9022	1			T1	4		T2	321		T3	3
valid_sources[0x3d]	8371	1			T1	4		T2	266		T4	4
valid_sources[0x3e]	10376	1			T1	3		T2	208		T5	14
valid_sources[0x3f]	9329	1			T1	6		T2	223		T4	2
valid_sources[0x40]	9785	1			T2	254		T3	7		T4	1
valid_sources[0x41]	10191	1			T2	294		T4	4		T5	15
valid_sources[0x42]	8875	1			T1	2		T2	213		T4	3
valid_sources[0x43]	11012	1			T2	143		T3	1		T4	3
valid_sources[0x44]	9510	1			T1	6		T2	241		T3	2
valid_sources[0x45]	8785	1			T1	4		T2	188		T4	4
valid_sources[0x46]	13821	1			T1	5		T2	178		T3	1
valid_sources[0x47]	19392	1			T2	219		T3	2		T4	1
valid_sources[0x48]	11940	1			T1	1		T2	212		T4	5
valid_sources[0x49]	8400	1			T1	3		T2	200		T4	2
valid_sources[0x4a]	10363	1			T1	3		T2	199		T4	6
valid_sources[0x4b]	11439	1			T1	10		T2	210		T4	3
valid_sources[0x4c]	10701	1			T1	5		T2	239		T4	3
valid_sources[0x4d]	13731	1			T1	6		T2	249		T4	4
valid_sources[0x4e]	18127	1			T1	6		T2	181		T4	5
valid_sources[0x4f]	9154	1			T2	286		T4	4		T5	12
valid_sources[0x50]	9838	1			T2	250		T3	1		T4	5
valid_sources[0x51]	8176	1			T1	1		T2	215		T4	5
valid_sources[0x52]	11426	1			T1	6		T2	185		T4	4
valid_sources[0x53]	9025	1			T1	6		T2	226		T4	2
valid_sources[0x54]	12336	1			T1	6		T2	269		T4	7
valid_sources[0x55]	16851	1			T1	5		T2	211		T3	1
valid_sources[0x56]	15646	1			T1	2		T2	211		T4	7
valid_sources[0x57]	11113	1			T1	11		T2	205		T4	2
valid_sources[0x58]	13149	1			T1	10		T2	208		T4	7
valid_sources[0x59]	8280	1			T1	5		T2	205		T4	3
valid_sources[0x5a]	9175	1			T1	1		T2	259		T4	5
valid_sources[0x5b]	9576	1			T1	8		T2	322		T4	5
valid_sources[0x5c]	10157	1			T1	5		T2	216		T4	3
valid_sources[0x5d]	8691	1			T1	1		T2	241		T4	4
valid_sources[0x5e]	25180	1			T1	7		T2	279		T4	6
valid_sources[0x5f]	8744	1			T1	5		T2	252		T3	4
valid_sources[0x60]	9540	1			T2	262		T3	3		T4	3
valid_sources[0x61]	8387	1			T1	5		T2	174		T4	3
valid_sources[0x62]	10985	1			T1	7		T2	292		T4	2
valid_sources[0x63]	8904	1			T1	4		T2	258		T4	1
valid_sources[0x64]	16189	1			T1	2		T2	201		T4	3
valid_sources[0x65]	9252	1			T1	9		T2	269		T4	7
valid_sources[0x66]	9506	1			T1	6		T2	336		T4	4
valid_sources[0x67]	11230	1			T1	3		T2	253		T4	1
valid_sources[0x68]	8555	1			T1	1		T2	236		T3	1
valid_sources[0x69]	9528	1			T1	3		T2	152		T3	1
valid_sources[0x6a]	9297	1			T1	1		T2	301		T4	6
valid_sources[0x6b]	8893	1			T1	2		T2	259		T4	5
valid_sources[0x6c]	9999	1			T1	2		T2	193		T4	2
valid_sources[0x6d]	8346	1			T2	213		T4	4		T5	9
valid_sources[0x6e]	10205	1			T1	3		T2	213		T4	1
valid_sources[0x6f]	14631	1			T2	200		T3	5		T4	7
valid_sources[0x70]	15755	1			T1	3		T2	171		T4	2
valid_sources[0x71]	9038	1			T1	1		T2	213		T3	6
valid_sources[0x72]	8558	1			T1	16		T2	289		T4	3
valid_sources[0x73]	8441	1			T1	1		T2	220		T4	3
valid_sources[0x74]	9880	1			T1	2		T2	210		T4	2
valid_sources[0x75]	14841	1			T1	2		T2	237		T4	3
valid_sources[0x76]	9119	1			T1	5		T2	222		T4	8
valid_sources[0x77]	9695	1			T1	2		T2	258		T3	2
valid_sources[0x78]	8903	1			T1	5		T2	207		T4	2
valid_sources[0x79]	14439	1			T1	5		T2	250		T4	2
valid_sources[0x7a]	9609	1			T1	6		T2	226		T3	3
valid_sources[0x7b]	9393	1			T1	3		T2	292		T3	1
valid_sources[0x7c]	10215	1			T1	3		T2	206		T4	4
valid_sources[0x7d]	12333	1			T1	3		T2	222		T4	1
valid_sources[0x7e]	8761	1			T1	1		T2	197		T4	6
valid_sources[0x7f]	8993	1			T1	5		T2	202		T4	4
valid_sources[0x80]	21675	1			T2	240		T4	2		T5	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

909172

1

T1

73

T2

28936

T3

9

values[0x0]

all_enables

biggest_size

301466

1

T1

450

T2

471

T3

47

values[0x1]

all_enables

biggest_size

295728

1

T1

456

T2

464

T3

53