Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1335339

1

T1

69

T2

28960

T4

5

full_word

1505298

1

T1

979

T2

29871

T4

878

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2840277	1			T1	1048		T2	58831		T4	883
auto[TlIntgErrCmd]	103	1			T41	5		T101	3		T103	4
auto[TlIntgErrData]	121	1			T41	7		T101	3		T103	3
auto[TlIntgErrBoth]	136	1			T41	8		T101	4		T103	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2165335

1

T1

139

T2

57887

T4

4

auto[1]

675302

1

T1

909

T2

944

T4

879

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1255957	1			T1	66		T2	28951		T4	3
auto[TlIntgErrNone]	partial	auto[1]	79061	1			T1	3		T2	9		T4	2
auto[TlIntgErrNone]	full_word	auto[0]	909205	1			T1	73		T2	28936		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	596054	1			T1	906		T2	935		T4	877
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T41	2		T103	3		T108	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T41	3		T101	3		T103	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T364	1		T365	1		T366	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T125	1		T367	1		T363	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T41	6		T101	3		T103	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T41	1		T103	2		T108	3
auto[TlIntgErrData]	full_word	auto[0]	9	1			T361	2		T367	1		T368	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T361	1		T149	1		T362	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T41	1		T101	1		T108	2
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T41	7		T101	2		T103	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T101	1		T149	1		T362	2
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T103	1		T108	1		T361	1