Unified Coverage Report :: Module :: prim_ram_2p_async_adv

Module : prim_ram_2p_async_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	75.00			100.00		u_spid_dpram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_2p_async_adv

	Line No.	Total	Covered	Percent
TOTAL		51	51	100.00
ALWAYS	136	3	3	100.00
ALWAYS	143	3	3	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	233	15	15	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	355	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv' or '../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
150	1	1
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
233	1	1
234	1	1
235	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
247	1	1
248	1	1
249	1	1
250	1	1
252	1	1
253	1	1
267	1	1
268	1	1
307	1	1
308	1	1
309	1	1
310	1	1
311	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
347	1	1
348	1	1
350	1	1
352	1	1
353	1	1
355	1	1

---

Cond Coverage for Module : prim_ram_2p_async_adv

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (a_req_q & ((~a_write_q)))
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T13,T14

 LINE       146
 EXPRESSION (b_req_q & ((~b_write_q)))
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T4,T5

---

Branch Coverage for Module : prim_ram_2p_async_adv

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	136	2	2	100.00
IF	143	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv' or '../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	136	if ((!rst_a_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if ((!rst_b_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

---

Assert Coverage for Module : prim_ram_2p_async_adv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CannotHaveEccAndParity_A	679	679	0	0
gen_byte_parity.ParityNeedsByteWriteMask_A	679	679	0	0
gen_byte_parity.WidthNeedsToBeByteAligned_A	679	679	0	0

CannotHaveEccAndParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679	679	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

gen_byte_parity.ParityNeedsByteWriteMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679	679	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

gen_byte_parity.WidthNeedsToBeByteAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679	679	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0