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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.99 97.56 92.93 98.61 80.85 95.95 90.92 87.09


Total test records in report: 854
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T362 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2216535474 Apr 16 02:50:34 PM PDT 24 Apr 16 02:50:57 PM PDT 24 1587362034 ps
T770 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.776851205 Apr 16 02:50:38 PM PDT 24 Apr 16 02:50:41 PM PDT 24 240863389 ps
T771 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1808486014 Apr 16 02:50:53 PM PDT 24 Apr 16 02:50:55 PM PDT 24 16376476 ps
T133 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2463917963 Apr 16 02:50:51 PM PDT 24 Apr 16 02:50:55 PM PDT 24 249082998 ps
T772 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3338998867 Apr 16 02:50:55 PM PDT 24 Apr 16 02:50:56 PM PDT 24 12255781 ps
T773 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1136829185 Apr 16 02:50:50 PM PDT 24 Apr 16 02:50:55 PM PDT 24 66993447 ps
T115 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2578134262 Apr 16 02:50:41 PM PDT 24 Apr 16 02:50:45 PM PDT 24 102425870 ps
T774 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.280879720 Apr 16 02:50:52 PM PDT 24 Apr 16 02:50:53 PM PDT 24 14894356 ps
T116 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3013126358 Apr 16 02:51:01 PM PDT 24 Apr 16 02:51:05 PM PDT 24 251118242 ps
T134 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3590740125 Apr 16 02:50:48 PM PDT 24 Apr 16 02:50:52 PM PDT 24 40432014 ps
T775 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.517154162 Apr 16 02:50:41 PM PDT 24 Apr 16 02:50:44 PM PDT 24 270831362 ps
T776 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.401726984 Apr 16 02:50:35 PM PDT 24 Apr 16 02:50:37 PM PDT 24 38971348 ps
T777 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2774763215 Apr 16 02:50:30 PM PDT 24 Apr 16 02:50:32 PM PDT 24 85621064 ps
T135 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.499481363 Apr 16 02:50:44 PM PDT 24 Apr 16 02:50:47 PM PDT 24 255452831 ps
T122 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.228397839 Apr 16 02:50:51 PM PDT 24 Apr 16 02:50:54 PM PDT 24 96436005 ps
T778 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1465671937 Apr 16 02:50:50 PM PDT 24 Apr 16 02:50:52 PM PDT 24 24612941 ps
T364 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2838923467 Apr 16 02:50:39 PM PDT 24 Apr 16 02:50:52 PM PDT 24 209472494 ps
T779 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2302193332 Apr 16 02:50:35 PM PDT 24 Apr 16 02:50:39 PM PDT 24 138306156 ps
T780 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4101472506 Apr 16 02:50:53 PM PDT 24 Apr 16 02:50:55 PM PDT 24 25431003 ps
T136 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1757568756 Apr 16 02:50:43 PM PDT 24 Apr 16 02:50:46 PM PDT 24 69046621 ps
T781 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.409312665 Apr 16 02:50:46 PM PDT 24 Apr 16 02:50:47 PM PDT 24 33105287 ps
T782 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.331219689 Apr 16 02:51:00 PM PDT 24 Apr 16 02:51:02 PM PDT 24 54875781 ps
T783 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3712801668 Apr 16 02:50:56 PM PDT 24 Apr 16 02:50:57 PM PDT 24 86173247 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2302981730 Apr 16 02:50:36 PM PDT 24 Apr 16 02:50:39 PM PDT 24 211345831 ps
T784 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1677443338 Apr 16 02:50:46 PM PDT 24 Apr 16 02:50:48 PM PDT 24 20793191 ps
T785 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2804293268 Apr 16 02:50:31 PM PDT 24 Apr 16 02:50:39 PM PDT 24 439075945 ps
T786 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3911843994 Apr 16 02:50:51 PM PDT 24 Apr 16 02:50:53 PM PDT 24 16979348 ps
T137 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1086986014 Apr 16 02:50:47 PM PDT 24 Apr 16 02:50:51 PM PDT 24 110700376 ps
T363 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3175489811 Apr 16 02:50:47 PM PDT 24 Apr 16 02:50:55 PM PDT 24 584780526 ps
T787 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.29196569 Apr 16 02:50:54 PM PDT 24 Apr 16 02:50:56 PM PDT 24 43186703 ps
T788 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1125434030 Apr 16 02:50:51 PM PDT 24 Apr 16 02:50:55 PM PDT 24 134900791 ps
T789 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2039078198 Apr 16 02:50:30 PM PDT 24 Apr 16 02:50:33 PM PDT 24 74417979 ps
T790 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1886869591 Apr 16 02:50:35 PM PDT 24 Apr 16 02:51:16 PM PDT 24 2795408483 ps
T123 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3924740461 Apr 16 02:50:47 PM PDT 24 Apr 16 02:50:51 PM PDT 24 815491573 ps
T791 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3476289833 Apr 16 02:50:29 PM PDT 24 Apr 16 02:50:42 PM PDT 24 3149157125 ps
T792 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.886557710 Apr 16 02:50:37 PM PDT 24 Apr 16 02:50:41 PM PDT 24 68587703 ps
T793 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3898069999 Apr 16 02:50:49 PM PDT 24 Apr 16 02:50:51 PM PDT 24 19719587 ps
T98 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1644893767 Apr 16 02:50:33 PM PDT 24 Apr 16 02:50:36 PM PDT 24 530346748 ps
T794 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1229444997 Apr 16 02:50:51 PM PDT 24 Apr 16 02:50:53 PM PDT 24 15498732 ps
T795 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2586292979 Apr 16 02:50:50 PM PDT 24 Apr 16 02:50:54 PM PDT 24 400279612 ps
T796 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3948762021 Apr 16 02:50:43 PM PDT 24 Apr 16 02:50:45 PM PDT 24 37959477 ps
T797 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3082136695 Apr 16 02:50:47 PM PDT 24 Apr 16 02:50:50 PM PDT 24 33115528 ps
T798 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3703967558 Apr 16 02:50:57 PM PDT 24 Apr 16 02:50:58 PM PDT 24 47793797 ps
T365 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2764512755 Apr 16 02:50:38 PM PDT 24 Apr 16 02:51:01 PM PDT 24 1674430719 ps
T799 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2622488941 Apr 16 02:50:45 PM PDT 24 Apr 16 02:50:47 PM PDT 24 14606725 ps
T800 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4004885295 Apr 16 02:50:36 PM PDT 24 Apr 16 02:50:40 PM PDT 24 442387158 ps
T801 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1646158248 Apr 16 02:50:50 PM PDT 24 Apr 16 02:50:53 PM PDT 24 24554621 ps
T802 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3073179534 Apr 16 02:50:45 PM PDT 24 Apr 16 02:50:49 PM PDT 24 101300658 ps
T803 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2535527490 Apr 16 02:50:44 PM PDT 24 Apr 16 02:50:48 PM PDT 24 480653313 ps
T804 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.342097564 Apr 16 02:50:51 PM PDT 24 Apr 16 02:50:59 PM PDT 24 277144438 ps
T805 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3640681923 Apr 16 02:50:39 PM PDT 24 Apr 16 02:50:42 PM PDT 24 184658383 ps
T124 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4068625107 Apr 16 02:50:51 PM PDT 24 Apr 16 02:50:55 PM PDT 24 34866406 ps
T806 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1990987513 Apr 16 02:50:34 PM PDT 24 Apr 16 02:50:37 PM PDT 24 99284946 ps
T807 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.534285929 Apr 16 02:50:33 PM PDT 24 Apr 16 02:50:35 PM PDT 24 55561678 ps
T808 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1084776695 Apr 16 02:50:53 PM PDT 24 Apr 16 02:50:55 PM PDT 24 11934886 ps
T809 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2688645085 Apr 16 02:50:40 PM PDT 24 Apr 16 02:50:43 PM PDT 24 111787776 ps
T810 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.889179156 Apr 16 02:50:48 PM PDT 24 Apr 16 02:50:50 PM PDT 24 14638776 ps
T120 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1272807927 Apr 16 02:50:51 PM PDT 24 Apr 16 02:50:58 PM PDT 24 210737284 ps
T811 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1367685413 Apr 16 02:50:53 PM PDT 24 Apr 16 02:50:55 PM PDT 24 19813253 ps
T812 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3956107833 Apr 16 02:50:52 PM PDT 24 Apr 16 02:50:54 PM PDT 24 41149575 ps
T813 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.722568746 Apr 16 02:50:32 PM PDT 24 Apr 16 02:50:44 PM PDT 24 187600888 ps
T814 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4226947207 Apr 16 02:50:31 PM PDT 24 Apr 16 02:50:55 PM PDT 24 8973153269 ps
T815 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.411493394 Apr 16 02:50:57 PM PDT 24 Apr 16 02:50:59 PM PDT 24 14119251 ps
T816 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1903689804 Apr 16 02:50:34 PM PDT 24 Apr 16 02:50:39 PM PDT 24 81623515 ps
T817 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1809246331 Apr 16 02:50:50 PM PDT 24 Apr 16 02:50:54 PM PDT 24 99506260 ps
T818 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2719864565 Apr 16 02:50:24 PM PDT 24 Apr 16 02:50:50 PM PDT 24 1233434377 ps
T819 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1436457495 Apr 16 02:50:36 PM PDT 24 Apr 16 02:50:38 PM PDT 24 12241091 ps
T820 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4223912286 Apr 16 02:50:39 PM PDT 24 Apr 16 02:50:47 PM PDT 24 210783056 ps
T821 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.93515699 Apr 16 02:50:33 PM PDT 24 Apr 16 02:50:35 PM PDT 24 16688875 ps
T822 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3531901211 Apr 16 02:50:34 PM PDT 24 Apr 16 02:50:37 PM PDT 24 25911852 ps
T366 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.115314253 Apr 16 02:50:33 PM PDT 24 Apr 16 02:50:57 PM PDT 24 3347485503 ps
T823 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1898498435 Apr 16 02:50:31 PM PDT 24 Apr 16 02:50:34 PM PDT 24 91847635 ps
T824 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1180467270 Apr 16 02:50:52 PM PDT 24 Apr 16 02:50:54 PM PDT 24 43687135 ps
T825 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.836012836 Apr 16 02:50:43 PM PDT 24 Apr 16 02:50:47 PM PDT 24 44582845 ps
T826 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2230471651 Apr 16 02:50:44 PM PDT 24 Apr 16 02:50:49 PM PDT 24 606968892 ps
T827 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3740032059 Apr 16 02:50:30 PM PDT 24 Apr 16 02:50:32 PM PDT 24 41505106 ps
T828 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.970285486 Apr 16 02:50:31 PM PDT 24 Apr 16 02:50:34 PM PDT 24 22507373 ps
T829 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.315850289 Apr 16 02:50:41 PM PDT 24 Apr 16 02:50:43 PM PDT 24 51293853 ps
T830 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1829516663 Apr 16 02:50:36 PM PDT 24 Apr 16 02:50:40 PM PDT 24 552657586 ps
T831 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2569620760 Apr 16 02:50:30 PM PDT 24 Apr 16 02:50:32 PM PDT 24 127729845 ps
T832 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3505839144 Apr 16 02:50:39 PM PDT 24 Apr 16 02:50:42 PM PDT 24 45478249 ps
T833 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2348003110 Apr 16 02:50:32 PM PDT 24 Apr 16 02:50:34 PM PDT 24 41214937 ps
T834 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3184446535 Apr 16 02:50:38 PM PDT 24 Apr 16 02:50:52 PM PDT 24 198540930 ps
T835 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3624086369 Apr 16 02:50:36 PM PDT 24 Apr 16 02:50:40 PM PDT 24 97701293 ps
T836 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3854292427 Apr 16 02:50:42 PM PDT 24 Apr 16 02:50:45 PM PDT 24 41163362 ps
T837 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3718610891 Apr 16 02:50:44 PM PDT 24 Apr 16 02:50:47 PM PDT 24 101459083 ps
T838 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3420654941 Apr 16 02:50:37 PM PDT 24 Apr 16 02:50:41 PM PDT 24 39525786 ps
T839 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1963914636 Apr 16 02:50:45 PM PDT 24 Apr 16 02:50:49 PM PDT 24 427708743 ps
T840 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4056732783 Apr 16 02:50:26 PM PDT 24 Apr 16 02:50:29 PM PDT 24 1114910905 ps
T841 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.202339222 Apr 16 02:50:38 PM PDT 24 Apr 16 02:50:43 PM PDT 24 442968271 ps
T842 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2618490809 Apr 16 02:50:48 PM PDT 24 Apr 16 02:50:51 PM PDT 24 30744926 ps
T843 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3474232128 Apr 16 02:50:52 PM PDT 24 Apr 16 02:50:55 PM PDT 24 39071685 ps
T844 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2420099040 Apr 16 02:50:39 PM PDT 24 Apr 16 02:50:41 PM PDT 24 30471919 ps
T845 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.399621627 Apr 16 02:50:51 PM PDT 24 Apr 16 02:50:52 PM PDT 24 11813430 ps
T846 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1431583291 Apr 16 02:51:02 PM PDT 24 Apr 16 02:51:04 PM PDT 24 64757765 ps
T847 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4160160036 Apr 16 02:50:37 PM PDT 24 Apr 16 02:50:52 PM PDT 24 1737730200 ps
T848 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2552387643 Apr 16 02:50:50 PM PDT 24 Apr 16 02:50:52 PM PDT 24 48419221 ps
T360 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.490264803 Apr 16 02:50:27 PM PDT 24 Apr 16 02:50:31 PM PDT 24 253416589 ps
T849 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.422835116 Apr 16 02:50:37 PM PDT 24 Apr 16 02:50:39 PM PDT 24 14461769 ps
T850 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2880911049 Apr 16 02:50:46 PM PDT 24 Apr 16 02:51:01 PM PDT 24 1026468574 ps
T851 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3245774773 Apr 16 02:50:47 PM PDT 24 Apr 16 02:50:49 PM PDT 24 23350888 ps
T852 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2952771736 Apr 16 02:50:28 PM PDT 24 Apr 16 02:50:30 PM PDT 24 68188752 ps
T853 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.595821153 Apr 16 02:50:58 PM PDT 24 Apr 16 02:50:59 PM PDT 24 12626501 ps
T854 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2246707599 Apr 16 02:50:47 PM PDT 24 Apr 16 02:50:49 PM PDT 24 29225280 ps

Test location /workspace/coverage/default/6.spi_device_intercept.3877263387
Short name T7
Test name
Test status
Simulation time 1761343753 ps
CPU time 5.85 seconds
Started Apr 16 02:52:24 PM PDT 24
Finished Apr 16 02:52:32 PM PDT 24
Peak memory 216972 kb
Host smart-75483a50-939e-470d-b41d-ae0e5cc73aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877263387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3877263387
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2228405437
Short name T15
Test name
Test status
Simulation time 19983747366 ps
CPU time 57.15 seconds
Started Apr 16 02:53:53 PM PDT 24
Finished Apr 16 02:54:51 PM PDT 24
Peak memory 216644 kb
Host smart-fae923d8-1faf-47d3-9e71-523b727c3cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228405437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2228405437
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_upload.3323075693
Short name T1
Test name
Test status
Simulation time 796583424 ps
CPU time 11.3 seconds
Started Apr 16 02:53:47 PM PDT 24
Finished Apr 16 02:54:00 PM PDT 24
Peak memory 232892 kb
Host smart-86918beb-ee33-4c43-b715-faacdca8759d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323075693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3323075693
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.401170848
Short name T108
Test name
Test status
Simulation time 1406277384 ps
CPU time 15.08 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:51:03 PM PDT 24
Peak memory 215560 kb
Host smart-390e04f8-47e0-4bd8-a240-ea7515997a93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401170848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.401170848
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1508701960
Short name T68
Test name
Test status
Simulation time 8203421073 ps
CPU time 39.66 seconds
Started Apr 16 02:52:53 PM PDT 24
Finished Apr 16 02:53:34 PM PDT 24
Peak memory 216648 kb
Host smart-ef8c0bd5-f319-4e68-9226-8ff7ae105f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508701960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1508701960
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1106965912
Short name T23
Test name
Test status
Simulation time 44047727 ps
CPU time 0.94 seconds
Started Apr 16 02:54:09 PM PDT 24
Finished Apr 16 02:54:11 PM PDT 24
Peak memory 207036 kb
Host smart-f76b95ba-8fae-4587-b407-1ca548fda6e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106965912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1106965912
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1048746807
Short name T220
Test name
Test status
Simulation time 10372333325 ps
CPU time 28.33 seconds
Started Apr 16 02:53:11 PM PDT 24
Finished Apr 16 02:53:41 PM PDT 24
Peak memory 218676 kb
Host smart-e620cd18-c99e-49ac-9786-12b38eddd212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048746807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1048746807
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2453912229
Short name T27
Test name
Test status
Simulation time 8842694888 ps
CPU time 19.36 seconds
Started Apr 16 02:52:55 PM PDT 24
Finished Apr 16 02:53:16 PM PDT 24
Peak memory 218908 kb
Host smart-4115e7e4-2191-4292-8bec-1bdb666e14b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453912229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2453912229
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3585571875
Short name T71
Test name
Test status
Simulation time 11116525683 ps
CPU time 27.23 seconds
Started Apr 16 02:52:26 PM PDT 24
Finished Apr 16 02:52:55 PM PDT 24
Peak memory 224768 kb
Host smart-60ede618-f9f8-4dfc-b403-187b8accd450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585571875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3585571875
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_intercept.741120212
Short name T47
Test name
Test status
Simulation time 2050945253 ps
CPU time 18.28 seconds
Started Apr 16 02:54:33 PM PDT 24
Finished Apr 16 02:54:53 PM PDT 24
Peak memory 232960 kb
Host smart-d8101a53-29bd-4261-a4e3-9904fe32c827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741120212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.741120212
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3213403812
Short name T44
Test name
Test status
Simulation time 17587083 ps
CPU time 0.74 seconds
Started Apr 16 02:52:18 PM PDT 24
Finished Apr 16 02:52:20 PM PDT 24
Peak memory 216372 kb
Host smart-4f82d3ed-a091-4b24-a7d8-89733e161876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213403812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3213403812
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3456433753
Short name T6
Test name
Test status
Simulation time 2380048177 ps
CPU time 31.8 seconds
Started Apr 16 02:53:03 PM PDT 24
Finished Apr 16 02:53:36 PM PDT 24
Peak memory 241236 kb
Host smart-cc6e3498-c87d-4559-ab8d-fdace6790d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456433753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3456433753
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4206199902
Short name T386
Test name
Test status
Simulation time 31493274863 ps
CPU time 36.27 seconds
Started Apr 16 02:53:24 PM PDT 24
Finished Apr 16 02:54:02 PM PDT 24
Peak memory 216608 kb
Host smart-ed548a57-f68e-4669-913a-0606410d8d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206199902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4206199902
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1583458863
Short name T376
Test name
Test status
Simulation time 2512915249 ps
CPU time 32.34 seconds
Started Apr 16 02:52:38 PM PDT 24
Finished Apr 16 02:53:11 PM PDT 24
Peak memory 216468 kb
Host smart-6c4c22ca-5168-4fb6-b069-d0bfd733d82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583458863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1583458863
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3735253869
Short name T110
Test name
Test status
Simulation time 569098132 ps
CPU time 3.67 seconds
Started Apr 16 02:50:36 PM PDT 24
Finished Apr 16 02:50:42 PM PDT 24
Peak memory 215484 kb
Host smart-499ce1c4-b7e6-4e48-8144-d9491ebbcc72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735253869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
735253869
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2256722008
Short name T49
Test name
Test status
Simulation time 132879501 ps
CPU time 0.99 seconds
Started Apr 16 02:52:14 PM PDT 24
Finished Apr 16 02:52:16 PM PDT 24
Peak memory 235404 kb
Host smart-8066efed-1013-45eb-801d-f32ade4d0053
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256722008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2256722008
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2814064957
Short name T245
Test name
Test status
Simulation time 18345307393 ps
CPU time 15.31 seconds
Started Apr 16 02:54:08 PM PDT 24
Finished Apr 16 02:54:24 PM PDT 24
Peak memory 235124 kb
Host smart-05407253-fa3f-49f2-917d-d586cb5cf447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814064957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2814064957
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.787082164
Short name T2
Test name
Test status
Simulation time 58938368721 ps
CPU time 121.38 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:54:27 PM PDT 24
Peak memory 234984 kb
Host smart-9066979e-f968-4181-8955-f32a030e18c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787082164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.787082164
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_upload.2409294006
Short name T76
Test name
Test status
Simulation time 145511079430 ps
CPU time 26.52 seconds
Started Apr 16 02:52:41 PM PDT 24
Finished Apr 16 02:53:08 PM PDT 24
Peak memory 218964 kb
Host smart-829328b7-c397-45c2-aab7-fe66c3124d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409294006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2409294006
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2896285543
Short name T86
Test name
Test status
Simulation time 5934018879 ps
CPU time 35.8 seconds
Started Apr 16 02:54:13 PM PDT 24
Finished Apr 16 02:54:50 PM PDT 24
Peak memory 224816 kb
Host smart-03bb913a-a796-4d10-9fef-05d4f09a314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896285543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2896285543
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2155724031
Short name T42
Test name
Test status
Simulation time 389733589 ps
CPU time 2.25 seconds
Started Apr 16 02:50:45 PM PDT 24
Finished Apr 16 02:50:48 PM PDT 24
Peak memory 207092 kb
Host smart-edd7e0d9-f4d9-4f75-ad64-e2df3bd2a543
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155724031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2155724031
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1298947475
Short name T249
Test name
Test status
Simulation time 10265296729 ps
CPU time 46.29 seconds
Started Apr 16 02:53:27 PM PDT 24
Finished Apr 16 02:54:15 PM PDT 24
Peak memory 234984 kb
Host smart-c1efb7e7-3cd5-4ff8-b8b9-b608b67852e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298947475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1298947475
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.636830396
Short name T277
Test name
Test status
Simulation time 19524989531 ps
CPU time 26.9 seconds
Started Apr 16 02:53:42 PM PDT 24
Finished Apr 16 02:54:11 PM PDT 24
Peak memory 233124 kb
Host smart-e2a63a41-5ade-4fdf-a49a-7ac7b69e02c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636830396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.636830396
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.454376266
Short name T177
Test name
Test status
Simulation time 2559951235 ps
CPU time 8.23 seconds
Started Apr 16 02:53:07 PM PDT 24
Finished Apr 16 02:53:17 PM PDT 24
Peak memory 239528 kb
Host smart-57494fab-e18c-492a-96b3-7ee8ddfd1b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454376266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.454376266
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1898317733
Short name T64
Test name
Test status
Simulation time 2341096137 ps
CPU time 34.86 seconds
Started Apr 16 02:53:26 PM PDT 24
Finished Apr 16 02:54:02 PM PDT 24
Peak memory 216608 kb
Host smart-f402f22d-844a-4e1d-a949-e453b7aa5b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898317733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1898317733
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.434611870
Short name T255
Test name
Test status
Simulation time 13325688371 ps
CPU time 55.6 seconds
Started Apr 16 02:52:32 PM PDT 24
Finished Apr 16 02:53:29 PM PDT 24
Peak memory 235068 kb
Host smart-9c50a5fa-5a75-4d7b-a30c-1191db288717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434611870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.434611870
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.91875679
Short name T336
Test name
Test status
Simulation time 41037412546 ps
CPU time 31.33 seconds
Started Apr 16 02:53:13 PM PDT 24
Finished Apr 16 02:53:45 PM PDT 24
Peak memory 235868 kb
Host smart-a511c09e-5e3f-47bd-8262-f90103fee567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91875679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.91875679
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3239785577
Short name T80
Test name
Test status
Simulation time 43470451389 ps
CPU time 21 seconds
Started Apr 16 02:52:37 PM PDT 24
Finished Apr 16 02:52:59 PM PDT 24
Peak memory 234872 kb
Host smart-2969a6d6-81c0-4a16-949a-0452b5e924dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239785577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3239785577
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.728461380
Short name T422
Test name
Test status
Simulation time 45865937 ps
CPU time 1.04 seconds
Started Apr 16 02:52:13 PM PDT 24
Finished Apr 16 02:52:16 PM PDT 24
Peak memory 216988 kb
Host smart-2334fce5-39b2-46f3-a2fe-6cff72250f1b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728461380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.728461380
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1272821454
Short name T77
Test name
Test status
Simulation time 42378850765 ps
CPU time 28.34 seconds
Started Apr 16 02:52:34 PM PDT 24
Finished Apr 16 02:53:03 PM PDT 24
Peak memory 222992 kb
Host smart-eb55c03e-3681-4628-9ba9-34eec9f3d321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272821454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1272821454
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_upload.454689070
Short name T184
Test name
Test status
Simulation time 173847035 ps
CPU time 3.32 seconds
Started Apr 16 02:53:00 PM PDT 24
Finished Apr 16 02:53:05 PM PDT 24
Peak memory 216512 kb
Host smart-b41213c6-58b4-4e1a-b3c8-d586866c92d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454689070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.454689070
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2419586560
Short name T227
Test name
Test status
Simulation time 434777226 ps
CPU time 3.75 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:27 PM PDT 24
Peak memory 221256 kb
Host smart-ec8b0fb1-4f08-4418-a1e9-05917d530992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419586560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2419586560
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1466598709
Short name T10
Test name
Test status
Simulation time 67225207363 ps
CPU time 55.67 seconds
Started Apr 16 02:53:41 PM PDT 24
Finished Apr 16 02:54:38 PM PDT 24
Peak memory 240620 kb
Host smart-7d650a91-b64d-4feb-8434-a8fb9c5aaad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466598709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1466598709
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3622173334
Short name T372
Test name
Test status
Simulation time 90547464033 ps
CPU time 19.05 seconds
Started Apr 16 02:52:59 PM PDT 24
Finished Apr 16 02:53:19 PM PDT 24
Peak memory 223080 kb
Host smart-e468bb90-9fe7-4ee6-92bf-0bad520aa4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622173334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3622173334
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3438863204
Short name T214
Test name
Test status
Simulation time 760836513 ps
CPU time 5.01 seconds
Started Apr 16 02:52:38 PM PDT 24
Finished Apr 16 02:52:44 PM PDT 24
Peak memory 223168 kb
Host smart-a1febfe9-83fa-4078-8906-9273462fca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438863204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3438863204
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_intercept.501159286
Short name T205
Test name
Test status
Simulation time 2712190563 ps
CPU time 6.07 seconds
Started Apr 16 02:52:56 PM PDT 24
Finished Apr 16 02:53:03 PM PDT 24
Peak memory 224540 kb
Host smart-d2f326cb-abc1-4f1d-b472-8f3d90520da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501159286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.501159286
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1663638500
Short name T716
Test name
Test status
Simulation time 4664890443 ps
CPU time 8.88 seconds
Started Apr 16 02:52:12 PM PDT 24
Finished Apr 16 02:52:22 PM PDT 24
Peak memory 224660 kb
Host smart-0f7ea5c3-1d22-483b-91be-e4268027a40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663638500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1663638500
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2504904227
Short name T394
Test name
Test status
Simulation time 6365818750 ps
CPU time 33.26 seconds
Started Apr 16 02:52:22 PM PDT 24
Finished Apr 16 02:52:58 PM PDT 24
Peak memory 216632 kb
Host smart-64b8b235-4e79-4532-80ae-acac87d073b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504904227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2504904227
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3396737642
Short name T266
Test name
Test status
Simulation time 16961868033 ps
CPU time 27.87 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:40 PM PDT 24
Peak memory 223500 kb
Host smart-12e91db5-300b-433a-a5c4-10cfbdb1f655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396737642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3396737642
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.995942224
Short name T89
Test name
Test status
Simulation time 7223536244 ps
CPU time 39.79 seconds
Started Apr 16 02:53:16 PM PDT 24
Finished Apr 16 02:53:57 PM PDT 24
Peak memory 239196 kb
Host smart-0d183a78-e2ba-4390-af9d-14f88b3fbad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995942224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.995942224
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1473113124
Short name T85
Test name
Test status
Simulation time 12062568466 ps
CPU time 25.95 seconds
Started Apr 16 02:53:43 PM PDT 24
Finished Apr 16 02:54:11 PM PDT 24
Peak memory 226972 kb
Host smart-25defff9-64f4-4836-abfb-f0160393e93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473113124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1473113124
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1432725697
Short name T209
Test name
Test status
Simulation time 1861331844 ps
CPU time 7.03 seconds
Started Apr 16 02:54:09 PM PDT 24
Finished Apr 16 02:54:17 PM PDT 24
Peak memory 232892 kb
Host smart-9f40a3be-02fb-4b48-9de9-65a85fe575c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432725697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1432725697
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.115314253
Short name T366
Test name
Test status
Simulation time 3347485503 ps
CPU time 22.91 seconds
Started Apr 16 02:50:33 PM PDT 24
Finished Apr 16 02:50:57 PM PDT 24
Peak memory 215548 kb
Host smart-b199b6e6-7aba-4a7e-9e51-3f6db3eec7d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115314253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.115314253
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_upload.1963304137
Short name T242
Test name
Test status
Simulation time 1207223711 ps
CPU time 5.72 seconds
Started Apr 16 02:52:55 PM PDT 24
Finished Apr 16 02:53:02 PM PDT 24
Peak memory 218748 kb
Host smart-5302525d-227b-4365-b79c-6d3a423227b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963304137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1963304137
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4243835084
Short name T343
Test name
Test status
Simulation time 543490089 ps
CPU time 12.37 seconds
Started Apr 16 02:53:08 PM PDT 24
Finished Apr 16 02:53:21 PM PDT 24
Peak memory 224712 kb
Host smart-cc1f9452-ace6-4d64-9d3e-010c7331d99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243835084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4243835084
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.985213330
Short name T290
Test name
Test status
Simulation time 4196903185 ps
CPU time 57 seconds
Started Apr 16 02:53:14 PM PDT 24
Finished Apr 16 02:54:12 PM PDT 24
Peak memory 234412 kb
Host smart-de62bb9c-4a26-47b2-92ca-ace61f6ea4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985213330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.985213330
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.37909203
Short name T294
Test name
Test status
Simulation time 777299911 ps
CPU time 18.19 seconds
Started Apr 16 02:54:03 PM PDT 24
Finished Apr 16 02:54:22 PM PDT 24
Peak memory 237432 kb
Host smart-52c31625-60cd-4833-9570-5edbd4358210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37909203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.37909203
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3106589084
Short name T402
Test name
Test status
Simulation time 14826562 ps
CPU time 0.75 seconds
Started Apr 16 02:52:35 PM PDT 24
Finished Apr 16 02:52:37 PM PDT 24
Peak memory 205424 kb
Host smart-c9467c94-65e0-4e00-bb31-48ed549ad81a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106589084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3106589084
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3123331366
Short name T276
Test name
Test status
Simulation time 11022136132 ps
CPU time 23.93 seconds
Started Apr 16 02:52:43 PM PDT 24
Finished Apr 16 02:53:08 PM PDT 24
Peak memory 235584 kb
Host smart-05b8e43b-4d0d-4420-a4aa-0cec507a61b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123331366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3123331366
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1794649852
Short name T665
Test name
Test status
Simulation time 39566964798 ps
CPU time 52.21 seconds
Started Apr 16 02:52:14 PM PDT 24
Finished Apr 16 02:53:08 PM PDT 24
Peak memory 216544 kb
Host smart-7c77f1cb-4fa2-4e5d-a9c0-7379ae1cca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794649852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1794649852
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3391852906
Short name T75
Test name
Test status
Simulation time 9267897142 ps
CPU time 27.96 seconds
Started Apr 16 02:53:12 PM PDT 24
Finished Apr 16 02:53:41 PM PDT 24
Peak memory 238628 kb
Host smart-f8727bff-8814-42dd-a801-9fa17ac1183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391852906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3391852906
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4160956874
Short name T215
Test name
Test status
Simulation time 4570274771 ps
CPU time 8.87 seconds
Started Apr 16 02:54:04 PM PDT 24
Finished Apr 16 02:54:14 PM PDT 24
Peak memory 217132 kb
Host smart-65860517-94e6-4917-8f94-db282dd2ee6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160956874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4160956874
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.206948510
Short name T344
Test name
Test status
Simulation time 357209076 ps
CPU time 7.85 seconds
Started Apr 16 02:54:08 PM PDT 24
Finished Apr 16 02:54:17 PM PDT 24
Peak memory 220208 kb
Host smart-511a7621-3efb-4d36-b727-23de821f49c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206948510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.206948510
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_upload.3743937304
Short name T241
Test name
Test status
Simulation time 1709605769 ps
CPU time 10.01 seconds
Started Apr 16 02:54:14 PM PDT 24
Finished Apr 16 02:54:25 PM PDT 24
Peak memory 248728 kb
Host smart-6c49362b-2a3d-4371-b5c4-1f4b0ef7a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743937304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3743937304
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1272807927
Short name T120
Test name
Test status
Simulation time 210737284 ps
CPU time 6.11 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:58 PM PDT 24
Peak memory 215376 kb
Host smart-887658c7-0050-4be1-8a14-f908aad9d234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272807927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1272807927
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.720728712
Short name T310
Test name
Test status
Simulation time 35783716512 ps
CPU time 23.34 seconds
Started Apr 16 02:52:34 PM PDT 24
Finished Apr 16 02:52:59 PM PDT 24
Peak memory 223576 kb
Host smart-a2dab5e1-58c4-4c35-af11-34a80395a2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720728712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.720728712
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.803386788
Short name T216
Test name
Test status
Simulation time 1555612432 ps
CPU time 4.66 seconds
Started Apr 16 02:52:24 PM PDT 24
Finished Apr 16 02:52:31 PM PDT 24
Peak memory 218592 kb
Host smart-362bc2a7-4d67-49b7-95a1-3693165a317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803386788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.803386788
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2196553386
Short name T210
Test name
Test status
Simulation time 7873359014 ps
CPU time 7.26 seconds
Started Apr 16 02:53:08 PM PDT 24
Finished Apr 16 02:53:16 PM PDT 24
Peak memory 218940 kb
Host smart-47c2b0df-f60f-4b60-a2f9-170c68d0324f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196553386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2196553386
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_intercept.872793367
Short name T92
Test name
Test status
Simulation time 1299371273 ps
CPU time 16.22 seconds
Started Apr 16 02:53:19 PM PDT 24
Finished Apr 16 02:53:36 PM PDT 24
Peak memory 232576 kb
Host smart-56066c26-5ff8-4b52-a1d9-8d9b5d06ac8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872793367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.872793367
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_upload.2478757541
Short name T244
Test name
Test status
Simulation time 1058602124 ps
CPU time 5.13 seconds
Started Apr 16 02:53:28 PM PDT 24
Finished Apr 16 02:53:35 PM PDT 24
Peak memory 224736 kb
Host smart-5c5a591f-b1eb-4960-b01d-f692ec24926f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478757541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2478757541
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_upload.3447070211
Short name T173
Test name
Test status
Simulation time 2181829535 ps
CPU time 14.88 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:54:11 PM PDT 24
Peak memory 238204 kb
Host smart-3dd189f6-d013-4f46-ae33-5397e49f455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447070211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3447070211
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.432624463
Short name T218
Test name
Test status
Simulation time 6618797531 ps
CPU time 9.98 seconds
Started Apr 16 02:54:03 PM PDT 24
Finished Apr 16 02:54:13 PM PDT 24
Peak memory 221236 kb
Host smart-a6f055bd-2142-4213-a479-fc26395ab9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432624463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.432624463
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_upload.199913439
Short name T299
Test name
Test status
Simulation time 486479233 ps
CPU time 3.25 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:23 PM PDT 24
Peak memory 220572 kb
Host smart-4a613992-82bf-4f26-bfc8-b6c13c3b13fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199913439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.199913439
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2097156470
Short name T262
Test name
Test status
Simulation time 10265720813 ps
CPU time 100.4 seconds
Started Apr 16 02:52:20 PM PDT 24
Finished Apr 16 02:54:03 PM PDT 24
Peak memory 234536 kb
Host smart-42656cae-24d5-4c8e-a7ff-7d608398c6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097156470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2097156470
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3734086248
Short name T401
Test name
Test status
Simulation time 17656703713 ps
CPU time 20.74 seconds
Started Apr 16 02:52:14 PM PDT 24
Finished Apr 16 02:52:37 PM PDT 24
Peak memory 216596 kb
Host smart-7939a3af-53f9-460e-a02e-0713ea768a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734086248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3734086248
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3991284368
Short name T357
Test name
Test status
Simulation time 48928964 ps
CPU time 1.12 seconds
Started Apr 16 02:52:54 PM PDT 24
Finished Apr 16 02:52:57 PM PDT 24
Peak memory 207384 kb
Host smart-fd9692ac-a291-4b4c-bf6c-12d959f67c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991284368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3991284368
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2674417542
Short name T292
Test name
Test status
Simulation time 493827705 ps
CPU time 14.23 seconds
Started Apr 16 02:53:13 PM PDT 24
Finished Apr 16 02:53:28 PM PDT 24
Peak memory 224760 kb
Host smart-30d0341e-1415-4683-bf85-c9f9e6cd6f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674417542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2674417542
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.844879248
Short name T193
Test name
Test status
Simulation time 13972758636 ps
CPU time 63.13 seconds
Started Apr 16 02:53:33 PM PDT 24
Finished Apr 16 02:54:38 PM PDT 24
Peak memory 224512 kb
Host smart-bc19e3ef-ba1d-4f93-b264-5a5df48f83f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844879248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.844879248
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1183354581
Short name T272
Test name
Test status
Simulation time 1464499335 ps
CPU time 8.36 seconds
Started Apr 16 02:53:50 PM PDT 24
Finished Apr 16 02:53:59 PM PDT 24
Peak memory 224696 kb
Host smart-2588318a-de50-4d29-91c0-32297f2c249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183354581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1183354581
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.812941700
Short name T84
Test name
Test status
Simulation time 3288515494 ps
CPU time 15.76 seconds
Started Apr 16 02:53:51 PM PDT 24
Finished Apr 16 02:54:08 PM PDT 24
Peak memory 235396 kb
Host smart-62310d69-878c-4ba6-aaf5-2181efdf5843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812941700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.812941700
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.692072133
Short name T306
Test name
Test status
Simulation time 5337445411 ps
CPU time 56.7 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:54:53 PM PDT 24
Peak memory 233008 kb
Host smart-f0b60aa1-f724-4343-991a-3b08c1a50b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692072133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.692072133
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.918176743
Short name T82
Test name
Test status
Simulation time 27108677765 ps
CPU time 27.2 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:54:24 PM PDT 24
Peak memory 239324 kb
Host smart-cb3f9515-c2b6-4a44-a89b-fc05db631ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918176743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.918176743
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.777326190
Short name T275
Test name
Test status
Simulation time 6203021756 ps
CPU time 20.74 seconds
Started Apr 16 02:54:08 PM PDT 24
Finished Apr 16 02:54:30 PM PDT 24
Peak memory 232896 kb
Host smart-8343cf69-051e-47d7-b5bb-ac493920fa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777326190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.777326190
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_upload.2177854831
Short name T269
Test name
Test status
Simulation time 4818781077 ps
CPU time 4.8 seconds
Started Apr 16 02:54:13 PM PDT 24
Finished Apr 16 02:54:19 PM PDT 24
Peak memory 216540 kb
Host smart-94367bd4-247d-4351-bba8-e4f2d49cbea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177854831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2177854831
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_intercept.143766523
Short name T168
Test name
Test status
Simulation time 140826724 ps
CPU time 5.59 seconds
Started Apr 16 02:54:14 PM PDT 24
Finished Apr 16 02:54:21 PM PDT 24
Peak memory 222948 kb
Host smart-a94ff15e-7391-4338-b387-971168d9c31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143766523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.143766523
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2859931332
Short name T335
Test name
Test status
Simulation time 1772364705 ps
CPU time 7.43 seconds
Started Apr 16 02:54:49 PM PDT 24
Finished Apr 16 02:54:58 PM PDT 24
Peak memory 239660 kb
Host smart-305e46f8-8e04-43af-b1c9-4e848c7e9007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859931332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2859931332
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1880609847
Short name T28
Test name
Test status
Simulation time 2845308335 ps
CPU time 23.69 seconds
Started Apr 16 02:52:37 PM PDT 24
Finished Apr 16 02:53:02 PM PDT 24
Peak memory 232948 kb
Host smart-0d725696-e733-41bc-b2a5-58d67d3d0d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880609847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1880609847
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4263303793
Short name T320
Test name
Test status
Simulation time 2280091108 ps
CPU time 7.96 seconds
Started Apr 16 02:52:39 PM PDT 24
Finished Apr 16 02:52:47 PM PDT 24
Peak memory 224612 kb
Host smart-577dd5ad-9c30-4392-9888-2e0832f67a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263303793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4263303793
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3861032209
Short name T192
Test name
Test status
Simulation time 423962933 ps
CPU time 5 seconds
Started Apr 16 02:52:54 PM PDT 24
Finished Apr 16 02:53:01 PM PDT 24
Peak memory 223596 kb
Host smart-31ac1a5e-83bf-4992-a76d-df33b573e74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861032209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3861032209
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3554781812
Short name T70
Test name
Test status
Simulation time 183125638 ps
CPU time 2.59 seconds
Started Apr 16 02:52:53 PM PDT 24
Finished Apr 16 02:52:57 PM PDT 24
Peak memory 223408 kb
Host smart-2bef20da-ef0c-4920-a0c7-9b99a467b715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554781812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3554781812
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4260328181
Short name T301
Test name
Test status
Simulation time 1127274065 ps
CPU time 4.79 seconds
Started Apr 16 02:53:03 PM PDT 24
Finished Apr 16 02:53:09 PM PDT 24
Peak memory 221656 kb
Host smart-c3cc1a19-2be1-4637-addf-eb993e5873c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260328181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4260328181
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2529540608
Short name T342
Test name
Test status
Simulation time 552730534 ps
CPU time 11.86 seconds
Started Apr 16 02:53:08 PM PDT 24
Finished Apr 16 02:53:20 PM PDT 24
Peak memory 237084 kb
Host smart-2fc3c2d9-ee6d-490f-803c-f5f7c6895cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529540608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2529540608
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_upload.2255398301
Short name T281
Test name
Test status
Simulation time 140829775 ps
CPU time 2.59 seconds
Started Apr 16 02:53:22 PM PDT 24
Finished Apr 16 02:53:25 PM PDT 24
Peak memory 222108 kb
Host smart-4655e082-dd3b-4730-8956-6f8dee67b7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255398301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2255398301
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.635803568
Short name T221
Test name
Test status
Simulation time 1091775535 ps
CPU time 4.98 seconds
Started Apr 16 02:53:28 PM PDT 24
Finished Apr 16 02:53:34 PM PDT 24
Peak memory 223480 kb
Host smart-7258d09e-7a5f-47ac-8ce4-6a6fce470cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635803568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.635803568
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_upload.2150741039
Short name T179
Test name
Test status
Simulation time 1804228702 ps
CPU time 12.84 seconds
Started Apr 16 02:52:24 PM PDT 24
Finished Apr 16 02:52:39 PM PDT 24
Peak memory 224464 kb
Host smart-493fc5e9-1d8e-487b-b9de-22188adb030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150741039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2150741039
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3962067403
Short name T61
Test name
Test status
Simulation time 601702041 ps
CPU time 2.65 seconds
Started Apr 16 02:53:36 PM PDT 24
Finished Apr 16 02:53:41 PM PDT 24
Peak memory 220168 kb
Host smart-86283730-2473-42ea-a1c7-37555f6d42bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962067403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3962067403
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3486300980
Short name T228
Test name
Test status
Simulation time 1423388669 ps
CPU time 5.53 seconds
Started Apr 16 02:53:31 PM PDT 24
Finished Apr 16 02:53:38 PM PDT 24
Peak memory 232868 kb
Host smart-61ffb515-cf2c-45f2-ae4e-ff44257a1024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486300980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3486300980
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_upload.224828741
Short name T274
Test name
Test status
Simulation time 471366717 ps
CPU time 7.09 seconds
Started Apr 16 02:53:43 PM PDT 24
Finished Apr 16 02:53:51 PM PDT 24
Peak memory 224760 kb
Host smart-0c7b7ef6-ac63-46a4-986c-955dfe9b2280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224828741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.224828741
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4127785713
Short name T351
Test name
Test status
Simulation time 3147199998 ps
CPU time 16.43 seconds
Started Apr 16 02:53:47 PM PDT 24
Finished Apr 16 02:54:05 PM PDT 24
Peak memory 232988 kb
Host smart-22e1598a-7a74-4c77-84c0-dba08d5d27a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127785713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4127785713
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2644245994
Short name T195
Test name
Test status
Simulation time 282527247 ps
CPU time 2.71 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:53:58 PM PDT 24
Peak memory 218092 kb
Host smart-a95fc718-4df0-44bc-ae9c-cadb5c30e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644245994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2644245994
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1877323472
Short name T185
Test name
Test status
Simulation time 1223857717 ps
CPU time 4.76 seconds
Started Apr 16 02:54:14 PM PDT 24
Finished Apr 16 02:54:20 PM PDT 24
Peak memory 216776 kb
Host smart-deb4d191-fcb2-45c6-a187-59e41e71d3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877323472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1877323472
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1230509468
Short name T163
Test name
Test status
Simulation time 3671185872 ps
CPU time 15.07 seconds
Started Apr 16 02:54:14 PM PDT 24
Finished Apr 16 02:54:30 PM PDT 24
Peak memory 223128 kb
Host smart-704ccb11-1d10-4416-9bed-a14855e30c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230509468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1230509468
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3275508298
Short name T187
Test name
Test status
Simulation time 1005333059 ps
CPU time 3.39 seconds
Started Apr 16 02:54:39 PM PDT 24
Finished Apr 16 02:54:43 PM PDT 24
Peak memory 221436 kb
Host smart-6ffbf282-da46-4d8d-8681-41c670822b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275508298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3275508298
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3300092840
Short name T198
Test name
Test status
Simulation time 4324528584 ps
CPU time 33.29 seconds
Started Apr 16 02:52:47 PM PDT 24
Finished Apr 16 02:53:22 PM PDT 24
Peak memory 237108 kb
Host smart-402f7aa6-fdb4-40b5-b852-e9fbdd96d044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300092840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3300092840
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2299624294
Short name T105
Test name
Test status
Simulation time 25996504 ps
CPU time 1.9 seconds
Started Apr 16 02:50:38 PM PDT 24
Finished Apr 16 02:50:42 PM PDT 24
Peak memory 216428 kb
Host smart-5327da68-2ee5-4bbf-b7fe-a17ebdf6adc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299624294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
299624294
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.199300226
Short name T29
Test name
Test status
Simulation time 742192386 ps
CPU time 6.86 seconds
Started Apr 16 02:52:17 PM PDT 24
Finished Apr 16 02:52:26 PM PDT 24
Peak memory 224496 kb
Host smart-36de2f3d-745a-4550-9ca7-3cccb0c68261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199300226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.199300226
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.315459250
Short name T285
Test name
Test status
Simulation time 21299943351 ps
CPU time 55.97 seconds
Started Apr 16 02:52:14 PM PDT 24
Finished Apr 16 02:53:11 PM PDT 24
Peak memory 250428 kb
Host smart-735ac4a2-4608-41b3-8301-1548cac07a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315459250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.315459250
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2185176163
Short name T182
Test name
Test status
Simulation time 424076944 ps
CPU time 4.27 seconds
Started Apr 16 02:52:25 PM PDT 24
Finished Apr 16 02:52:31 PM PDT 24
Peak memory 216972 kb
Host smart-b5ce3a9b-b6a0-4611-9eca-76b969bd48e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185176163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2185176163
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2576821211
Short name T355
Test name
Test status
Simulation time 199659125 ps
CPU time 7.69 seconds
Started Apr 16 02:52:13 PM PDT 24
Finished Apr 16 02:52:22 PM PDT 24
Peak memory 233908 kb
Host smart-165a9eb8-e343-41ad-aadf-581e8ebc38d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576821211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2576821211
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1295121103
Short name T169
Test name
Test status
Simulation time 203661720 ps
CPU time 2.43 seconds
Started Apr 16 02:52:25 PM PDT 24
Finished Apr 16 02:52:29 PM PDT 24
Peak memory 218692 kb
Host smart-2fae3b98-2e8b-459d-a515-5994b618fe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295121103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1295121103
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3047112829
Short name T380
Test name
Test status
Simulation time 21695823628 ps
CPU time 37.42 seconds
Started Apr 16 02:52:14 PM PDT 24
Finished Apr 16 02:52:53 PM PDT 24
Peak memory 216608 kb
Host smart-5a007ba1-cab4-4b76-b096-ba2b3d2a744e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047112829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3047112829
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_upload.4254508797
Short name T316
Test name
Test status
Simulation time 2980829788 ps
CPU time 12.83 seconds
Started Apr 16 02:52:16 PM PDT 24
Finished Apr 16 02:52:30 PM PDT 24
Peak memory 234904 kb
Host smart-08b400ae-6fcc-44a1-b8ca-d5bdb000f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254508797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4254508797
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3524841644
Short name T219
Test name
Test status
Simulation time 2163021144 ps
CPU time 4.25 seconds
Started Apr 16 02:52:37 PM PDT 24
Finished Apr 16 02:52:42 PM PDT 24
Peak memory 217104 kb
Host smart-ace0da5d-2671-4944-92bb-c60e0ed1ce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524841644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3524841644
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.785961547
Short name T339
Test name
Test status
Simulation time 654210030 ps
CPU time 2.28 seconds
Started Apr 16 02:52:41 PM PDT 24
Finished Apr 16 02:52:43 PM PDT 24
Peak memory 222896 kb
Host smart-6c7d068b-405a-4ad6-8b8f-20a492413796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785961547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.785961547
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.135715960
Short name T237
Test name
Test status
Simulation time 5176202599 ps
CPU time 14.95 seconds
Started Apr 16 02:52:47 PM PDT 24
Finished Apr 16 02:53:03 PM PDT 24
Peak memory 219260 kb
Host smart-c98b5dbe-513f-4a7f-af52-67d64ab1f45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135715960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.135715960
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_upload.483825901
Short name T330
Test name
Test status
Simulation time 3944741336 ps
CPU time 6.37 seconds
Started Apr 16 02:52:45 PM PDT 24
Finished Apr 16 02:52:53 PM PDT 24
Peak memory 220440 kb
Host smart-0933b22c-8e26-4887-a4e6-f3d04220b59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483825901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.483825901
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.765119156
Short name T4
Test name
Test status
Simulation time 239224604 ps
CPU time 2.88 seconds
Started Apr 16 02:52:57 PM PDT 24
Finished Apr 16 02:53:00 PM PDT 24
Peak memory 222936 kb
Host smart-a9f73242-391e-4472-ab5b-96f1298cb582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765119156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.765119156
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1476071436
Short name T653
Test name
Test status
Simulation time 972410138 ps
CPU time 5.34 seconds
Started Apr 16 02:52:51 PM PDT 24
Finished Apr 16 02:52:57 PM PDT 24
Peak memory 224152 kb
Host smart-c7356e0b-1a6e-4217-9295-c4031ccce886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476071436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1476071436
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3290719950
Short name T83
Test name
Test status
Simulation time 2105270642 ps
CPU time 3.51 seconds
Started Apr 16 02:52:51 PM PDT 24
Finished Apr 16 02:52:55 PM PDT 24
Peak memory 221236 kb
Host smart-d5eb2ecc-eaa2-4c4b-aa7d-3d797b537359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290719950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3290719950
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3409982593
Short name T337
Test name
Test status
Simulation time 904651053 ps
CPU time 8.46 seconds
Started Apr 16 02:52:58 PM PDT 24
Finished Apr 16 02:53:08 PM PDT 24
Peak memory 232908 kb
Host smart-96b04c4d-5862-471d-bfea-55b7fb9eb6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409982593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3409982593
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3271111248
Short name T11
Test name
Test status
Simulation time 102658174 ps
CPU time 3.27 seconds
Started Apr 16 02:52:53 PM PDT 24
Finished Apr 16 02:52:58 PM PDT 24
Peak memory 222192 kb
Host smart-79e8e37d-cbed-4756-a6f3-6fb643144bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271111248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3271111248
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2418578807
Short name T263
Test name
Test status
Simulation time 116062929 ps
CPU time 4.09 seconds
Started Apr 16 02:52:58 PM PDT 24
Finished Apr 16 02:53:04 PM PDT 24
Peak memory 217316 kb
Host smart-9526e234-3619-429c-991d-9f6de50609a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418578807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2418578807
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_upload.2379142068
Short name T300
Test name
Test status
Simulation time 411811932 ps
CPU time 2.19 seconds
Started Apr 16 02:52:55 PM PDT 24
Finished Apr 16 02:52:58 PM PDT 24
Peak memory 219752 kb
Host smart-887793a7-d55e-4a64-b06a-6ddcc5b45c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379142068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2379142068
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.101259233
Short name T239
Test name
Test status
Simulation time 30409524915 ps
CPU time 21.64 seconds
Started Apr 16 02:52:58 PM PDT 24
Finished Apr 16 02:53:21 PM PDT 24
Peak memory 222312 kb
Host smart-24904798-2ed4-4177-a275-77a8742a3ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101259233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.101259233
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.996704321
Short name T189
Test name
Test status
Simulation time 34088034392 ps
CPU time 22.04 seconds
Started Apr 16 02:52:59 PM PDT 24
Finished Apr 16 02:53:22 PM PDT 24
Peak memory 222868 kb
Host smart-b31769c8-3aae-4946-be3f-c4c98fb99b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996704321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.996704321
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_upload.2237616940
Short name T211
Test name
Test status
Simulation time 2259523084 ps
CPU time 9.06 seconds
Started Apr 16 02:53:00 PM PDT 24
Finished Apr 16 02:53:11 PM PDT 24
Peak memory 224800 kb
Host smart-4185ef8b-15ae-4246-8ccc-c4f12228e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237616940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2237616940
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2252018315
Short name T297
Test name
Test status
Simulation time 3174893744 ps
CPU time 36.14 seconds
Started Apr 16 02:52:16 PM PDT 24
Finished Apr 16 02:52:54 PM PDT 24
Peak memory 240320 kb
Host smart-1d965102-05e3-4548-94b9-2d34a5b6d19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252018315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2252018315
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1529091178
Short name T81
Test name
Test status
Simulation time 800674892 ps
CPU time 7.35 seconds
Started Apr 16 02:53:08 PM PDT 24
Finished Apr 16 02:53:17 PM PDT 24
Peak memory 218924 kb
Host smart-f04bc695-e9b9-468c-a444-3eb189437c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529091178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1529091178
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3216407072
Short name T250
Test name
Test status
Simulation time 10106149331 ps
CPU time 10.27 seconds
Started Apr 16 02:53:17 PM PDT 24
Finished Apr 16 02:53:28 PM PDT 24
Peak memory 233896 kb
Host smart-b9bbd419-d7ca-4d7c-8447-4cabf501e489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216407072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3216407072
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1621511062
Short name T260
Test name
Test status
Simulation time 2583704335 ps
CPU time 13.12 seconds
Started Apr 16 02:53:23 PM PDT 24
Finished Apr 16 02:53:37 PM PDT 24
Peak memory 218712 kb
Host smart-b6b5d5f0-d459-4c9f-a321-74324bce2677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621511062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1621511062
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2990652574
Short name T270
Test name
Test status
Simulation time 4542623438 ps
CPU time 9.68 seconds
Started Apr 16 02:53:24 PM PDT 24
Finished Apr 16 02:53:35 PM PDT 24
Peak memory 216936 kb
Host smart-21ceda4d-8b55-4e69-a2f9-24a3490e88f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990652574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2990652574
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3575325389
Short name T341
Test name
Test status
Simulation time 2882860170 ps
CPU time 11.96 seconds
Started Apr 16 02:53:21 PM PDT 24
Finished Apr 16 02:53:34 PM PDT 24
Peak memory 217124 kb
Host smart-95c87415-af35-404c-99d8-ec17b2fbb97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575325389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3575325389
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4087282822
Short name T238
Test name
Test status
Simulation time 3471901646 ps
CPU time 8.59 seconds
Started Apr 16 02:53:27 PM PDT 24
Finished Apr 16 02:53:37 PM PDT 24
Peak memory 224808 kb
Host smart-b2002994-b1b2-481e-bae2-a326d78aaefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087282822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4087282822
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4178748216
Short name T298
Test name
Test status
Simulation time 8545882786 ps
CPU time 42.03 seconds
Started Apr 16 02:53:31 PM PDT 24
Finished Apr 16 02:54:14 PM PDT 24
Peak memory 232968 kb
Host smart-4ab5960b-e200-48db-82a8-ee4111076e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178748216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4178748216
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1729060557
Short name T333
Test name
Test status
Simulation time 1994070845 ps
CPU time 3.28 seconds
Started Apr 16 02:53:34 PM PDT 24
Finished Apr 16 02:53:39 PM PDT 24
Peak memory 223120 kb
Host smart-225c5274-35cb-4a2d-9895-c579cb355607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729060557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1729060557
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.115499842
Short name T230
Test name
Test status
Simulation time 3776019554 ps
CPU time 9.57 seconds
Started Apr 16 02:53:31 PM PDT 24
Finished Apr 16 02:53:42 PM PDT 24
Peak memory 224776 kb
Host smart-12c66ede-32ab-47f4-bb2b-aa761c8c6d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115499842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.115499842
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3677175926
Short name T206
Test name
Test status
Simulation time 1859809144 ps
CPU time 12.78 seconds
Started Apr 16 02:53:43 PM PDT 24
Finished Apr 16 02:53:57 PM PDT 24
Peak memory 222416 kb
Host smart-14bc326e-dfec-4e85-a17d-d5607c8d239b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677175926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3677175926
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.387385235
Short name T181
Test name
Test status
Simulation time 5995027094 ps
CPU time 15.25 seconds
Started Apr 16 02:53:49 PM PDT 24
Finished Apr 16 02:54:05 PM PDT 24
Peak memory 223996 kb
Host smart-0a07ac10-627e-4012-bae7-b1f11fdb79bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387385235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.387385235
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_upload.376514786
Short name T212
Test name
Test status
Simulation time 314664207 ps
CPU time 4.76 seconds
Started Apr 16 02:53:51 PM PDT 24
Finished Apr 16 02:53:57 PM PDT 24
Peak memory 220872 kb
Host smart-b9ad4878-0ba8-49af-b035-224a0fe97730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376514786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.376514786
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1163395514
Short name T252
Test name
Test status
Simulation time 13550843408 ps
CPU time 12.09 seconds
Started Apr 16 02:53:59 PM PDT 24
Finished Apr 16 02:54:12 PM PDT 24
Peak memory 219980 kb
Host smart-86a2c44b-3883-4e48-8364-f2140dc80615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163395514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1163395514
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3520693575
Short name T191
Test name
Test status
Simulation time 33230460733 ps
CPU time 25.31 seconds
Started Apr 16 02:53:58 PM PDT 24
Finished Apr 16 02:54:24 PM PDT 24
Peak memory 238328 kb
Host smart-caa6bca1-17fa-4559-9bcc-df663946a601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520693575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3520693575
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1840566069
Short name T226
Test name
Test status
Simulation time 794802626 ps
CPU time 4.24 seconds
Started Apr 16 02:54:04 PM PDT 24
Finished Apr 16 02:54:09 PM PDT 24
Peak memory 220420 kb
Host smart-83e0019b-af29-4b92-8661-399cf6df70ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840566069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1840566069
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3917378119
Short name T224
Test name
Test status
Simulation time 3120409373 ps
CPU time 11.57 seconds
Started Apr 16 02:54:11 PM PDT 24
Finished Apr 16 02:54:23 PM PDT 24
Peak memory 224532 kb
Host smart-39aa694a-5ede-4f19-9650-0ea75d56ab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917378119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3917378119
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3913498849
Short name T203
Test name
Test status
Simulation time 2086206366 ps
CPU time 3.2 seconds
Started Apr 16 02:54:08 PM PDT 24
Finished Apr 16 02:54:12 PM PDT 24
Peak memory 218608 kb
Host smart-d23b9636-9dc4-4a52-84fc-47eede9d369f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913498849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3913498849
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3500665934
Short name T170
Test name
Test status
Simulation time 1208975897 ps
CPU time 3.44 seconds
Started Apr 16 02:54:20 PM PDT 24
Finished Apr 16 02:54:25 PM PDT 24
Peak memory 218904 kb
Host smart-4f69eac0-f500-4da5-8b04-ef23ccd98199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500665934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3500665934
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2528928253
Short name T72
Test name
Test status
Simulation time 1786501035 ps
CPU time 36.13 seconds
Started Apr 16 02:54:20 PM PDT 24
Finished Apr 16 02:54:58 PM PDT 24
Peak memory 239940 kb
Host smart-09ca1d5b-2e1d-409b-a4e0-c301b7d1f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528928253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2528928253
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4099186847
Short name T46
Test name
Test status
Simulation time 3770572346 ps
CPU time 11.21 seconds
Started Apr 16 02:54:24 PM PDT 24
Finished Apr 16 02:54:37 PM PDT 24
Peak memory 217160 kb
Host smart-1be474c3-39f0-4b9a-9b2a-6f52c2e95589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099186847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4099186847
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3243136664
Short name T251
Test name
Test status
Simulation time 33699355491 ps
CPU time 22.03 seconds
Started Apr 16 02:54:22 PM PDT 24
Finished Apr 16 02:54:46 PM PDT 24
Peak memory 235740 kb
Host smart-53c935a9-203f-4d52-a354-d4d8108facfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243136664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3243136664
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_upload.4154102084
Short name T278
Test name
Test status
Simulation time 4325458718 ps
CPU time 10.58 seconds
Started Apr 16 02:54:25 PM PDT 24
Finished Apr 16 02:54:37 PM PDT 24
Peak memory 223732 kb
Host smart-55a49f6e-a7a3-44f7-b5f5-24d774ee3689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154102084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4154102084
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1037599495
Short name T304
Test name
Test status
Simulation time 4213420904 ps
CPU time 4.42 seconds
Started Apr 16 02:54:29 PM PDT 24
Finished Apr 16 02:54:36 PM PDT 24
Peak memory 223372 kb
Host smart-3197b833-7461-4383-8c36-d37ba22bf653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037599495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1037599495
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3926908552
Short name T236
Test name
Test status
Simulation time 7159129544 ps
CPU time 17.19 seconds
Started Apr 16 02:54:34 PM PDT 24
Finished Apr 16 02:54:53 PM PDT 24
Peak memory 240344 kb
Host smart-12870b56-c780-4efa-925d-bb3cfd5a5485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926908552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3926908552
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1805771868
Short name T334
Test name
Test status
Simulation time 63090360612 ps
CPU time 32.96 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:53 PM PDT 24
Peak memory 218980 kb
Host smart-7929e6bf-8d16-4308-967a-584f17a939f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805771868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1805771868
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3562712739
Short name T53
Test name
Test status
Simulation time 606215570 ps
CPU time 19.37 seconds
Started Apr 16 02:52:26 PM PDT 24
Finished Apr 16 02:52:47 PM PDT 24
Peak memory 236844 kb
Host smart-3761244b-b8f2-455d-a9b8-14dabee10da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562712739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3562712739
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3682511900
Short name T259
Test name
Test status
Simulation time 367796388 ps
CPU time 5.13 seconds
Started Apr 16 02:52:29 PM PDT 24
Finished Apr 16 02:52:35 PM PDT 24
Peak memory 219932 kb
Host smart-cb1c72e8-b4c3-40c1-96b5-04e3baa97ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682511900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3682511900
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.680986541
Short name T96
Test name
Test status
Simulation time 284112925 ps
CPU time 1.44 seconds
Started Apr 16 02:50:35 PM PDT 24
Finished Apr 16 02:50:38 PM PDT 24
Peak memory 207052 kb
Host smart-b76bb04e-af9f-4ae1-bf2c-543cf898705c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680986541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.680986541
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.490264803
Short name T360
Test name
Test status
Simulation time 253416589 ps
CPU time 3.72 seconds
Started Apr 16 02:50:27 PM PDT 24
Finished Apr 16 02:50:31 PM PDT 24
Peak memory 215572 kb
Host smart-2e9ed03d-76a9-46bb-8d26-1d436a74b466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490264803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.490264803
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.317305483
Short name T5
Test name
Test status
Simulation time 1775041475 ps
CPU time 11.03 seconds
Started Apr 16 02:52:14 PM PDT 24
Finished Apr 16 02:52:26 PM PDT 24
Peak memory 222004 kb
Host smart-3617c9c3-1b02-4bfb-ad1b-94323b6bfbb0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=317305483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.317305483
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2719864565
Short name T818
Test name
Test status
Simulation time 1233434377 ps
CPU time 25.31 seconds
Started Apr 16 02:50:24 PM PDT 24
Finished Apr 16 02:50:50 PM PDT 24
Peak memory 207156 kb
Host smart-94a0fd95-f588-4847-a967-35b9377abbf4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719864565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2719864565
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.384203647
Short name T130
Test name
Test status
Simulation time 189854911 ps
CPU time 12.48 seconds
Started Apr 16 02:50:31 PM PDT 24
Finished Apr 16 02:50:44 PM PDT 24
Peak memory 207180 kb
Host smart-224e1d78-a6ef-47d0-ab95-96f9663893db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384203647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.384203647
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3740032059
Short name T827
Test name
Test status
Simulation time 41505106 ps
CPU time 1.48 seconds
Started Apr 16 02:50:30 PM PDT 24
Finished Apr 16 02:50:32 PM PDT 24
Peak memory 207172 kb
Host smart-9a82b263-ef3f-46e7-abc0-d59936d95a2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740032059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3740032059
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2774763215
Short name T777
Test name
Test status
Simulation time 85621064 ps
CPU time 1.75 seconds
Started Apr 16 02:50:30 PM PDT 24
Finished Apr 16 02:50:32 PM PDT 24
Peak memory 215368 kb
Host smart-742dac8f-1597-4207-b0a4-ef9170599083
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774763215 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2774763215
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4056732783
Short name T840
Test name
Test status
Simulation time 1114910905 ps
CPU time 2 seconds
Started Apr 16 02:50:26 PM PDT 24
Finished Apr 16 02:50:29 PM PDT 24
Peak memory 207180 kb
Host smart-a45a4b5e-8b29-49ea-b4a7-ab80178ccaa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056732783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
056732783
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.85096269
Short name T156
Test name
Test status
Simulation time 42632015 ps
CPU time 0.71 seconds
Started Apr 16 02:50:27 PM PDT 24
Finished Apr 16 02:50:28 PM PDT 24
Peak memory 203404 kb
Host smart-21a116ee-5218-4347-8115-54d32579a9c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85096269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.85096269
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2952771736
Short name T852
Test name
Test status
Simulation time 68188752 ps
CPU time 1.23 seconds
Started Apr 16 02:50:28 PM PDT 24
Finished Apr 16 02:50:30 PM PDT 24
Peak memory 215332 kb
Host smart-85e36e2a-a650-44aa-9293-75cb09e4c21f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952771736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2952771736
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3203813968
Short name T768
Test name
Test status
Simulation time 33439247 ps
CPU time 0.67 seconds
Started Apr 16 02:50:30 PM PDT 24
Finished Apr 16 02:50:31 PM PDT 24
Peak memory 203432 kb
Host smart-a9a4865d-e05c-44d5-b92d-b7e9c0520588
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203813968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3203813968
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2572091563
Short name T140
Test name
Test status
Simulation time 652895193 ps
CPU time 3.19 seconds
Started Apr 16 02:50:27 PM PDT 24
Finished Apr 16 02:50:30 PM PDT 24
Peak memory 215316 kb
Host smart-42a01ded-53ae-43d7-9bb0-0780fa4ded56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572091563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2572091563
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2804293268
Short name T785
Test name
Test status
Simulation time 439075945 ps
CPU time 6.73 seconds
Started Apr 16 02:50:31 PM PDT 24
Finished Apr 16 02:50:39 PM PDT 24
Peak memory 207092 kb
Host smart-068deca6-bc44-4d72-8168-8691fe492f29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804293268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2804293268
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3476289833
Short name T791
Test name
Test status
Simulation time 3149157125 ps
CPU time 12.96 seconds
Started Apr 16 02:50:29 PM PDT 24
Finished Apr 16 02:50:42 PM PDT 24
Peak memory 207216 kb
Host smart-e82c349c-bd1a-4d71-bf57-1dd2db90679e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476289833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3476289833
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3956177311
Short name T40
Test name
Test status
Simulation time 166481993 ps
CPU time 0.96 seconds
Started Apr 16 02:50:29 PM PDT 24
Finished Apr 16 02:50:30 PM PDT 24
Peak memory 206924 kb
Host smart-c39887af-63ec-4e3e-8aa0-138482fdac1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956177311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3956177311
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2849957916
Short name T152
Test name
Test status
Simulation time 490747666 ps
CPU time 4.07 seconds
Started Apr 16 02:50:35 PM PDT 24
Finished Apr 16 02:50:40 PM PDT 24
Peak memory 217896 kb
Host smart-f71beb3c-7915-4477-8f1e-15755f2a6ff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849957916 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2849957916
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1898498435
Short name T823
Test name
Test status
Simulation time 91847635 ps
CPU time 2.22 seconds
Started Apr 16 02:50:31 PM PDT 24
Finished Apr 16 02:50:34 PM PDT 24
Peak memory 215268 kb
Host smart-2542077f-92b8-4a98-aa79-d74a802def55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898498435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
898498435
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1296732851
Short name T745
Test name
Test status
Simulation time 15036109 ps
CPU time 0.75 seconds
Started Apr 16 02:50:30 PM PDT 24
Finished Apr 16 02:50:31 PM PDT 24
Peak memory 203412 kb
Host smart-c289d472-7499-4fab-88b5-1ba813f5fd97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296732851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
296732851
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2569620760
Short name T831
Test name
Test status
Simulation time 127729845 ps
CPU time 1.28 seconds
Started Apr 16 02:50:30 PM PDT 24
Finished Apr 16 02:50:32 PM PDT 24
Peak memory 215332 kb
Host smart-6bb605cb-7174-4ee7-83ce-c2933575b087
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569620760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2569620760
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4231964292
Short name T743
Test name
Test status
Simulation time 14292146 ps
CPU time 0.7 seconds
Started Apr 16 02:50:33 PM PDT 24
Finished Apr 16 02:50:35 PM PDT 24
Peak memory 203372 kb
Host smart-df02efed-6618-4f00-af59-19d179f7b60f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231964292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4231964292
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.534285929
Short name T807
Test name
Test status
Simulation time 55561678 ps
CPU time 1.81 seconds
Started Apr 16 02:50:33 PM PDT 24
Finished Apr 16 02:50:35 PM PDT 24
Peak memory 215420 kb
Host smart-c719c285-2452-4a58-b446-bb41b5bc8804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534285929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.534285929
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3737121560
Short name T111
Test name
Test status
Simulation time 61879795 ps
CPU time 2.09 seconds
Started Apr 16 02:50:33 PM PDT 24
Finished Apr 16 02:50:36 PM PDT 24
Peak memory 215416 kb
Host smart-b1071146-ac35-43e6-8e8d-4a5aba35b2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737121560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
737121560
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3378663133
Short name T41
Test name
Test status
Simulation time 390485835 ps
CPU time 11.72 seconds
Started Apr 16 02:50:28 PM PDT 24
Finished Apr 16 02:50:40 PM PDT 24
Peak memory 215404 kb
Host smart-ce6ba9f1-e360-462c-b474-c06bcbc11501
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378663133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3378663133
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3854292427
Short name T836
Test name
Test status
Simulation time 41163362 ps
CPU time 2.77 seconds
Started Apr 16 02:50:42 PM PDT 24
Finished Apr 16 02:50:45 PM PDT 24
Peak memory 217664 kb
Host smart-b6431926-43ce-45f2-8dda-759845c315d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854292427 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3854292427
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3640681923
Short name T805
Test name
Test status
Simulation time 184658383 ps
CPU time 1.43 seconds
Started Apr 16 02:50:39 PM PDT 24
Finished Apr 16 02:50:42 PM PDT 24
Peak memory 207108 kb
Host smart-b4ed171a-e8ff-4e7e-aef6-2623395027a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640681923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3640681923
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3948762021
Short name T796
Test name
Test status
Simulation time 37959477 ps
CPU time 0.74 seconds
Started Apr 16 02:50:43 PM PDT 24
Finished Apr 16 02:50:45 PM PDT 24
Peak memory 203436 kb
Host smart-ff42db4f-4da3-4a6c-9725-f3f2b24eea74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948762021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3948762021
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1963914636
Short name T839
Test name
Test status
Simulation time 427708743 ps
CPU time 2.91 seconds
Started Apr 16 02:50:45 PM PDT 24
Finished Apr 16 02:50:49 PM PDT 24
Peak memory 215244 kb
Host smart-56f9c3d7-2c31-42ae-9207-2d138e465f71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963914636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1963914636
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2578134262
Short name T115
Test name
Test status
Simulation time 102425870 ps
CPU time 2.87 seconds
Started Apr 16 02:50:41 PM PDT 24
Finished Apr 16 02:50:45 PM PDT 24
Peak memory 215492 kb
Host smart-492c3977-747d-4345-8f48-8141cb65a684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578134262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2578134262
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2838923467
Short name T364
Test name
Test status
Simulation time 209472494 ps
CPU time 12.16 seconds
Started Apr 16 02:50:39 PM PDT 24
Finished Apr 16 02:50:52 PM PDT 24
Peak memory 215404 kb
Host smart-9c9a5b2c-4fdc-4867-8e16-90f55deb109b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838923467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2838923467
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3603551148
Short name T762
Test name
Test status
Simulation time 92403023 ps
CPU time 1.69 seconds
Started Apr 16 02:50:46 PM PDT 24
Finished Apr 16 02:50:48 PM PDT 24
Peak memory 215356 kb
Host smart-6ae6b98c-e81a-4c2b-b199-b36f2e95005f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603551148 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3603551148
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4172120135
Short name T157
Test name
Test status
Simulation time 16606215 ps
CPU time 0.74 seconds
Started Apr 16 02:50:44 PM PDT 24
Finished Apr 16 02:50:45 PM PDT 24
Peak memory 203508 kb
Host smart-38414363-e665-417d-ba16-b80882b5d5a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172120135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4172120135
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3073179534
Short name T802
Test name
Test status
Simulation time 101300658 ps
CPU time 2.81 seconds
Started Apr 16 02:50:45 PM PDT 24
Finished Apr 16 02:50:49 PM PDT 24
Peak memory 215268 kb
Host smart-b0ff0e7e-4e25-4f0c-8c9e-c9185b1579c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073179534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3073179534
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3245774773
Short name T851
Test name
Test status
Simulation time 23350888 ps
CPU time 1.46 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:50:49 PM PDT 24
Peak memory 215428 kb
Host smart-06a2935e-c1c9-4276-a92e-b88d14892bba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245774773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3245774773
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4268089577
Short name T101
Test name
Test status
Simulation time 438330397 ps
CPU time 6.92 seconds
Started Apr 16 02:50:46 PM PDT 24
Finished Apr 16 02:50:54 PM PDT 24
Peak memory 215412 kb
Host smart-ac2a8640-ff17-4c9b-905a-27041794e591
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268089577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4268089577
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4183072946
Short name T749
Test name
Test status
Simulation time 28911184 ps
CPU time 2.02 seconds
Started Apr 16 02:50:46 PM PDT 24
Finished Apr 16 02:50:49 PM PDT 24
Peak memory 216292 kb
Host smart-048bed92-0546-49a9-8b7c-fa54309792a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183072946 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4183072946
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.839811593
Short name T129
Test name
Test status
Simulation time 138945893 ps
CPU time 1.2 seconds
Started Apr 16 02:50:44 PM PDT 24
Finished Apr 16 02:50:46 PM PDT 24
Peak memory 215388 kb
Host smart-70161ee9-448c-4c0b-83e1-915d2e743c26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839811593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.839811593
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2622488941
Short name T799
Test name
Test status
Simulation time 14606725 ps
CPU time 0.78 seconds
Started Apr 16 02:50:45 PM PDT 24
Finished Apr 16 02:50:47 PM PDT 24
Peak memory 203368 kb
Host smart-4955e348-504f-4761-800e-ef2e1d4b77f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622488941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2622488941
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2230471651
Short name T826
Test name
Test status
Simulation time 606968892 ps
CPU time 4.11 seconds
Started Apr 16 02:50:44 PM PDT 24
Finished Apr 16 02:50:49 PM PDT 24
Peak memory 215264 kb
Host smart-4d452f7d-befc-44bc-81af-aa7c3763522d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230471651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2230471651
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3718610891
Short name T837
Test name
Test status
Simulation time 101459083 ps
CPU time 1.87 seconds
Started Apr 16 02:50:44 PM PDT 24
Finished Apr 16 02:50:47 PM PDT 24
Peak memory 215408 kb
Host smart-64f95656-3982-4f37-9b2a-38c67d286186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718610891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3718610891
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1479178330
Short name T367
Test name
Test status
Simulation time 2397816037 ps
CPU time 15.69 seconds
Started Apr 16 02:50:45 PM PDT 24
Finished Apr 16 02:51:01 PM PDT 24
Peak memory 215564 kb
Host smart-5cfd3997-5224-4f36-8882-6a91e7a24297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479178330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1479178330
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2830458109
Short name T126
Test name
Test status
Simulation time 84552597 ps
CPU time 1.87 seconds
Started Apr 16 02:50:43 PM PDT 24
Finished Apr 16 02:50:45 PM PDT 24
Peak memory 215392 kb
Host smart-150c1d86-cce4-4cee-b5bf-e89ca3dc8822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830458109 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2830458109
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1677443338
Short name T784
Test name
Test status
Simulation time 20793191 ps
CPU time 1.24 seconds
Started Apr 16 02:50:46 PM PDT 24
Finished Apr 16 02:50:48 PM PDT 24
Peak memory 215248 kb
Host smart-1a7a4835-d3ff-49c5-a2be-b4baf3cc0a1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677443338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1677443338
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2552387643
Short name T848
Test name
Test status
Simulation time 48419221 ps
CPU time 0.71 seconds
Started Apr 16 02:50:50 PM PDT 24
Finished Apr 16 02:50:52 PM PDT 24
Peak memory 203396 kb
Host smart-90f9fa2b-2217-4c56-aa51-93d8dffa5db1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552387643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2552387643
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3451691732
Short name T150
Test name
Test status
Simulation time 300856857 ps
CPU time 1.96 seconds
Started Apr 16 02:50:48 PM PDT 24
Finished Apr 16 02:50:51 PM PDT 24
Peak memory 207192 kb
Host smart-bed32f2b-0e00-43c0-a956-ed1460a4c69a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451691732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3451691732
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3013126358
Short name T116
Test name
Test status
Simulation time 251118242 ps
CPU time 3.6 seconds
Started Apr 16 02:51:01 PM PDT 24
Finished Apr 16 02:51:05 PM PDT 24
Peak memory 216384 kb
Host smart-73781290-ef6c-4d0a-9e33-0f10a1a843f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013126358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3013126358
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3175489811
Short name T363
Test name
Test status
Simulation time 584780526 ps
CPU time 6.54 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 215304 kb
Host smart-3fdfdcda-40e7-4a1f-b021-c3862441b12a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175489811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3175489811
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4222514196
Short name T102
Test name
Test status
Simulation time 24796505 ps
CPU time 1.78 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:50:49 PM PDT 24
Peak memory 215376 kb
Host smart-9bbf6d67-16b8-414a-9387-8699f2495374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222514196 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4222514196
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3082136695
Short name T797
Test name
Test status
Simulation time 33115528 ps
CPU time 2.08 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:50:50 PM PDT 24
Peak memory 207232 kb
Host smart-029182b0-5df5-4d18-a442-256ef378c430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082136695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3082136695
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.409312665
Short name T781
Test name
Test status
Simulation time 33105287 ps
CPU time 0.73 seconds
Started Apr 16 02:50:46 PM PDT 24
Finished Apr 16 02:50:47 PM PDT 24
Peak memory 203744 kb
Host smart-a947d624-f63c-47e5-8428-2faa2f435250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409312665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.409312665
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.677684086
Short name T144
Test name
Test status
Simulation time 166208899 ps
CPU time 4.13 seconds
Started Apr 16 02:50:45 PM PDT 24
Finished Apr 16 02:50:50 PM PDT 24
Peak memory 215352 kb
Host smart-8b09b689-470e-4618-b391-e7f279cb4d71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677684086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.677684086
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3924740461
Short name T123
Test name
Test status
Simulation time 815491573 ps
CPU time 3.9 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:50:51 PM PDT 24
Peak memory 215500 kb
Host smart-4084de1b-3f0d-4b31-8cc1-ae15387cbf49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924740461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3924740461
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2611211276
Short name T368
Test name
Test status
Simulation time 288176273 ps
CPU time 7.8 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:50:56 PM PDT 24
Peak memory 215316 kb
Host smart-5c2c59a5-2fd9-49cc-881b-06a238688fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611211276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2611211276
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1136829185
Short name T773
Test name
Test status
Simulation time 66993447 ps
CPU time 3.98 seconds
Started Apr 16 02:50:50 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 218072 kb
Host smart-b09da3a5-fffb-4de7-b08d-894fcc6a82da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136829185 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1136829185
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1086986014
Short name T137
Test name
Test status
Simulation time 110700376 ps
CPU time 2.53 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:50:51 PM PDT 24
Peak memory 207040 kb
Host smart-d09ad475-3111-4210-9c5a-2446e013b6f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086986014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1086986014
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3898069999
Short name T793
Test name
Test status
Simulation time 19719587 ps
CPU time 0.69 seconds
Started Apr 16 02:50:49 PM PDT 24
Finished Apr 16 02:50:51 PM PDT 24
Peak memory 203352 kb
Host smart-959250ea-4ff9-4fa2-a6bf-d4a8f068ab9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898069999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3898069999
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3631342207
Short name T142
Test name
Test status
Simulation time 893191154 ps
CPU time 3.91 seconds
Started Apr 16 02:50:48 PM PDT 24
Finished Apr 16 02:50:54 PM PDT 24
Peak memory 215260 kb
Host smart-d600ad4f-e875-4b41-a2a2-fbf8e419c7fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631342207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3631342207
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.228397839
Short name T122
Test name
Test status
Simulation time 96436005 ps
CPU time 1.77 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:54 PM PDT 24
Peak memory 215548 kb
Host smart-43cfb893-0235-41f1-a02e-d92a2640eb8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228397839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.228397839
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1646158248
Short name T801
Test name
Test status
Simulation time 24554621 ps
CPU time 1.74 seconds
Started Apr 16 02:50:50 PM PDT 24
Finished Apr 16 02:50:53 PM PDT 24
Peak memory 215404 kb
Host smart-7c4c1735-01a4-40c0-9370-94f8d82eb373
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646158248 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1646158248
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1464226994
Short name T131
Test name
Test status
Simulation time 113707283 ps
CPU time 2.49 seconds
Started Apr 16 02:50:48 PM PDT 24
Finished Apr 16 02:50:51 PM PDT 24
Peak memory 215272 kb
Host smart-b0326f6b-2f1d-4850-bac5-74d9d8515d32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464226994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1464226994
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.889179156
Short name T810
Test name
Test status
Simulation time 14638776 ps
CPU time 0.75 seconds
Started Apr 16 02:50:48 PM PDT 24
Finished Apr 16 02:50:50 PM PDT 24
Peak memory 203396 kb
Host smart-5b6b5db8-ab94-4dc5-ba52-412f61b40c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889179156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.889179156
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.136102437
Short name T145
Test name
Test status
Simulation time 29612944 ps
CPU time 1.82 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:50:50 PM PDT 24
Peak memory 207136 kb
Host smart-76c845cd-88b9-414f-ad1c-c1f29b1b8d5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136102437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.136102437
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1809246331
Short name T817
Test name
Test status
Simulation time 99506260 ps
CPU time 2.75 seconds
Started Apr 16 02:50:50 PM PDT 24
Finished Apr 16 02:50:54 PM PDT 24
Peak memory 215500 kb
Host smart-04e98260-d879-4d7f-8f6a-03ed0730435f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809246331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1809246331
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3540168657
Short name T125
Test name
Test status
Simulation time 298767622 ps
CPU time 6.72 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 215336 kb
Host smart-ff96df8b-bac8-46bb-ae6d-28ae184eac35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540168657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3540168657
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2586292979
Short name T795
Test name
Test status
Simulation time 400279612 ps
CPU time 2.74 seconds
Started Apr 16 02:50:50 PM PDT 24
Finished Apr 16 02:50:54 PM PDT 24
Peak memory 216452 kb
Host smart-dec5e7ec-624c-495b-8a12-8e5e7c6b6c03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586292979 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2586292979
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3474232128
Short name T843
Test name
Test status
Simulation time 39071685 ps
CPU time 1.27 seconds
Started Apr 16 02:50:52 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 207196 kb
Host smart-0d600c1f-34fe-4130-877c-5cdab1a53a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474232128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3474232128
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2618490809
Short name T842
Test name
Test status
Simulation time 30744926 ps
CPU time 0.78 seconds
Started Apr 16 02:50:48 PM PDT 24
Finished Apr 16 02:50:51 PM PDT 24
Peak memory 203504 kb
Host smart-11bf1a86-77f1-4db4-986d-0d320f4b59a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618490809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2618490809
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2246707599
Short name T854
Test name
Test status
Simulation time 29225280 ps
CPU time 1.69 seconds
Started Apr 16 02:50:47 PM PDT 24
Finished Apr 16 02:50:49 PM PDT 24
Peak memory 215376 kb
Host smart-0d0054fd-da47-4ad3-88ee-acf29e6bdfb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246707599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2246707599
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.342097564
Short name T804
Test name
Test status
Simulation time 277144438 ps
CPU time 6.89 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:59 PM PDT 24
Peak memory 215412 kb
Host smart-e9da5ddd-9b98-426f-b8f1-5ca877336487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342097564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.342097564
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1125434030
Short name T788
Test name
Test status
Simulation time 134900791 ps
CPU time 2.56 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 215560 kb
Host smart-f2765eb1-4525-4c9a-ab6c-389dc0ea5217
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125434030 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1125434030
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2463917963
Short name T133
Test name
Test status
Simulation time 249082998 ps
CPU time 2.95 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 215312 kb
Host smart-20f35485-e37a-4d5e-ab8e-8393494de9d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463917963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2463917963
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1442571695
Short name T746
Test name
Test status
Simulation time 18545075 ps
CPU time 0.69 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:52 PM PDT 24
Peak memory 203748 kb
Host smart-50eb8993-a7a3-4016-aa2c-e87e83233b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442571695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1442571695
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3913741525
Short name T139
Test name
Test status
Simulation time 135098069 ps
CPU time 2.9 seconds
Started Apr 16 02:50:48 PM PDT 24
Finished Apr 16 02:50:52 PM PDT 24
Peak memory 215352 kb
Host smart-265fed73-f2dc-46ff-b7ae-9936de445c85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913741525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3913741525
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.352415528
Short name T117
Test name
Test status
Simulation time 199416714 ps
CPU time 4.83 seconds
Started Apr 16 02:50:49 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 215520 kb
Host smart-9bdd1d9a-569f-4af0-9647-0a6c3c121a4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352415528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.352415528
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1259607455
Short name T103
Test name
Test status
Simulation time 606859780 ps
CPU time 7.4 seconds
Started Apr 16 02:50:50 PM PDT 24
Finished Apr 16 02:50:58 PM PDT 24
Peak memory 215336 kb
Host smart-05a6a068-4eef-4ac4-9013-1b57ef96074c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259607455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1259607455
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1632417383
Short name T104
Test name
Test status
Simulation time 206159752 ps
CPU time 1.63 seconds
Started Apr 16 02:50:50 PM PDT 24
Finished Apr 16 02:50:53 PM PDT 24
Peak memory 215240 kb
Host smart-b03cab3b-0718-4782-88c1-077cbfc4d412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632417383 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1632417383
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3590740125
Short name T134
Test name
Test status
Simulation time 40432014 ps
CPU time 2.31 seconds
Started Apr 16 02:50:48 PM PDT 24
Finished Apr 16 02:50:52 PM PDT 24
Peak memory 215408 kb
Host smart-400f8757-89fa-4be2-9c48-63f33aed05b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590740125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3590740125
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.399621627
Short name T845
Test name
Test status
Simulation time 11813430 ps
CPU time 0.74 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:52 PM PDT 24
Peak memory 203748 kb
Host smart-72504afa-b52e-4014-b6c7-b96a2b26b1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399621627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.399621627
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4176232790
Short name T752
Test name
Test status
Simulation time 108409861 ps
CPU time 2.83 seconds
Started Apr 16 02:50:49 PM PDT 24
Finished Apr 16 02:50:53 PM PDT 24
Peak memory 215384 kb
Host smart-cdb9eeaf-c176-44b5-97f2-00639c2b034f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176232790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4176232790
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4068625107
Short name T124
Test name
Test status
Simulation time 34866406 ps
CPU time 2.78 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 215444 kb
Host smart-8ec763cf-827f-4ccf-980b-f7e6b260b4d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068625107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4068625107
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2322300130
Short name T149
Test name
Test status
Simulation time 659332671 ps
CPU time 14.79 seconds
Started Apr 16 02:50:48 PM PDT 24
Finished Apr 16 02:51:05 PM PDT 24
Peak memory 215416 kb
Host smart-0ec30b0e-4024-47c2-896c-443bc9869ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322300130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2322300130
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4226947207
Short name T814
Test name
Test status
Simulation time 8973153269 ps
CPU time 22.84 seconds
Started Apr 16 02:50:31 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 215392 kb
Host smart-1643e770-00dc-4f0b-88d2-90814eff7be3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226947207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4226947207
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4023347162
Short name T128
Test name
Test status
Simulation time 526189447 ps
CPU time 35.73 seconds
Started Apr 16 02:50:32 PM PDT 24
Finished Apr 16 02:51:09 PM PDT 24
Peak memory 207188 kb
Host smart-ff2b8ad3-77aa-4b30-aef4-598dc60e86cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023347162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4023347162
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1829516663
Short name T830
Test name
Test status
Simulation time 552657586 ps
CPU time 2.49 seconds
Started Apr 16 02:50:36 PM PDT 24
Finished Apr 16 02:50:40 PM PDT 24
Peak memory 216500 kb
Host smart-03b72142-e426-4e05-9354-97c5c745282a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829516663 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1829516663
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3624086369
Short name T835
Test name
Test status
Simulation time 97701293 ps
CPU time 1.92 seconds
Started Apr 16 02:50:36 PM PDT 24
Finished Apr 16 02:50:40 PM PDT 24
Peak memory 215380 kb
Host smart-ac332adf-3434-42c4-be76-ec4114eff44c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624086369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
624086369
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2348003110
Short name T833
Test name
Test status
Simulation time 41214937 ps
CPU time 0.69 seconds
Started Apr 16 02:50:32 PM PDT 24
Finished Apr 16 02:50:34 PM PDT 24
Peak memory 203756 kb
Host smart-cbf6ba0b-893d-4932-8bd1-0519ecd5e6ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348003110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
348003110
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3521143476
Short name T127
Test name
Test status
Simulation time 37983383 ps
CPU time 1.39 seconds
Started Apr 16 02:50:32 PM PDT 24
Finished Apr 16 02:50:35 PM PDT 24
Peak memory 215392 kb
Host smart-f432eb20-69c0-4b21-914a-3eeced0dbdce
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521143476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3521143476
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2218503362
Short name T747
Test name
Test status
Simulation time 17413595 ps
CPU time 0.62 seconds
Started Apr 16 02:50:31 PM PDT 24
Finished Apr 16 02:50:32 PM PDT 24
Peak memory 203392 kb
Host smart-5e42d0bb-c7bb-44d7-a364-b1a32bc4f332
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218503362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2218503362
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2302193332
Short name T779
Test name
Test status
Simulation time 138306156 ps
CPU time 3.09 seconds
Started Apr 16 02:50:35 PM PDT 24
Finished Apr 16 02:50:39 PM PDT 24
Peak memory 215280 kb
Host smart-18208fe1-b7d3-4605-b0fd-49851bb0151e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302193332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2302193332
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2039078198
Short name T789
Test name
Test status
Simulation time 74417979 ps
CPU time 1.59 seconds
Started Apr 16 02:50:30 PM PDT 24
Finished Apr 16 02:50:33 PM PDT 24
Peak memory 216660 kb
Host smart-e9a06b69-5e3e-4d10-b6d5-fb25f516d15f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039078198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
039078198
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.722568746
Short name T813
Test name
Test status
Simulation time 187600888 ps
CPU time 11.16 seconds
Started Apr 16 02:50:32 PM PDT 24
Finished Apr 16 02:50:44 PM PDT 24
Peak memory 215384 kb
Host smart-d01e4bba-17ef-47da-94f1-f483045b5a34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722568746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.722568746
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1690376669
Short name T761
Test name
Test status
Simulation time 45597886 ps
CPU time 0.68 seconds
Started Apr 16 02:50:48 PM PDT 24
Finished Apr 16 02:50:50 PM PDT 24
Peak memory 203432 kb
Host smart-0730f286-a7d3-4ca0-911c-d87fe04bb7de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690376669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1690376669
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1354950430
Short name T764
Test name
Test status
Simulation time 12935508 ps
CPU time 0.74 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:53 PM PDT 24
Peak memory 203712 kb
Host smart-a57fc03c-1549-44a6-a0ff-5ff81d59a9fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354950430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1354950430
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.460568591
Short name T758
Test name
Test status
Simulation time 15231175 ps
CPU time 0.72 seconds
Started Apr 16 02:50:52 PM PDT 24
Finished Apr 16 02:50:54 PM PDT 24
Peak memory 203416 kb
Host smart-464487f0-b8fd-4f1f-96a2-9bd117fd318c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460568591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.460568591
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2786070697
Short name T750
Test name
Test status
Simulation time 15392992 ps
CPU time 0.78 seconds
Started Apr 16 02:50:56 PM PDT 24
Finished Apr 16 02:50:57 PM PDT 24
Peak memory 203452 kb
Host smart-a46d2ed5-8015-4b43-8c7d-e853a8bb4527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786070697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2786070697
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1367685413
Short name T811
Test name
Test status
Simulation time 19813253 ps
CPU time 0.75 seconds
Started Apr 16 02:50:53 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 203472 kb
Host smart-d8ee8eae-58cc-4585-8c36-b4ecc053f56b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367685413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1367685413
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.329060617
Short name T744
Test name
Test status
Simulation time 28787028 ps
CPU time 0.74 seconds
Started Apr 16 02:50:52 PM PDT 24
Finished Apr 16 02:50:54 PM PDT 24
Peak memory 203716 kb
Host smart-47a6a950-0ee5-429f-a78e-f80ccfe1e9f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329060617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.329060617
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3338998867
Short name T772
Test name
Test status
Simulation time 12255781 ps
CPU time 0.82 seconds
Started Apr 16 02:50:55 PM PDT 24
Finished Apr 16 02:50:56 PM PDT 24
Peak memory 203500 kb
Host smart-1ce600cc-96cc-4e54-a9e0-0c1d121d86d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338998867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3338998867
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.943405193
Short name T766
Test name
Test status
Simulation time 14773921 ps
CPU time 0.7 seconds
Started Apr 16 02:50:54 PM PDT 24
Finished Apr 16 02:50:56 PM PDT 24
Peak memory 203744 kb
Host smart-66cb89c5-34d6-438d-ad02-92fe5cc1b5b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943405193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.943405193
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1084776695
Short name T808
Test name
Test status
Simulation time 11934886 ps
CPU time 0.69 seconds
Started Apr 16 02:50:53 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 203420 kb
Host smart-67b7cb98-45a7-426e-8f6c-68d3f9f8a335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084776695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1084776695
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2475534967
Short name T763
Test name
Test status
Simulation time 23492879 ps
CPU time 0.7 seconds
Started Apr 16 02:50:52 PM PDT 24
Finished Apr 16 02:50:54 PM PDT 24
Peak memory 203408 kb
Host smart-e42a63b2-4724-4a6b-9903-0aa36615326e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475534967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2475534967
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.26629677
Short name T753
Test name
Test status
Simulation time 112768542 ps
CPU time 7.65 seconds
Started Apr 16 02:50:36 PM PDT 24
Finished Apr 16 02:50:45 PM PDT 24
Peak memory 215316 kb
Host smart-47141b5e-f0fa-4414-a046-fa8417a60293
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26629677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
aliasing.26629677
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.148711842
Short name T755
Test name
Test status
Simulation time 7212131877 ps
CPU time 34.97 seconds
Started Apr 16 02:50:36 PM PDT 24
Finished Apr 16 02:51:13 PM PDT 24
Peak memory 207332 kb
Host smart-fa862195-eebf-4464-a211-fddc2c92abb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148711842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.148711842
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1644893767
Short name T98
Test name
Test status
Simulation time 530346748 ps
CPU time 1.39 seconds
Started Apr 16 02:50:33 PM PDT 24
Finished Apr 16 02:50:36 PM PDT 24
Peak memory 216308 kb
Host smart-809ad145-f16b-44dd-92aa-d8b9ee107a45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644893767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1644893767
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4004885295
Short name T800
Test name
Test status
Simulation time 442387158 ps
CPU time 2.82 seconds
Started Apr 16 02:50:36 PM PDT 24
Finished Apr 16 02:50:40 PM PDT 24
Peak memory 216696 kb
Host smart-a08be210-d9ce-451f-bbc1-cdcc3c7e6731
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004885295 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4004885295
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2947385955
Short name T760
Test name
Test status
Simulation time 148711083 ps
CPU time 2.46 seconds
Started Apr 16 02:50:32 PM PDT 24
Finished Apr 16 02:50:36 PM PDT 24
Peak memory 215388 kb
Host smart-608d1029-f233-417d-9b87-807e02ba1cd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947385955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
947385955
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.401726984
Short name T776
Test name
Test status
Simulation time 38971348 ps
CPU time 0.74 seconds
Started Apr 16 02:50:35 PM PDT 24
Finished Apr 16 02:50:37 PM PDT 24
Peak memory 203504 kb
Host smart-868e2cdc-54ba-4196-8796-b7f0cfd0baf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401726984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.401726984
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.970285486
Short name T828
Test name
Test status
Simulation time 22507373 ps
CPU time 1.72 seconds
Started Apr 16 02:50:31 PM PDT 24
Finished Apr 16 02:50:34 PM PDT 24
Peak memory 215252 kb
Host smart-1767a6e2-59e4-4386-9471-cbc893f0e098
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970285486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.970285486
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.93515699
Short name T821
Test name
Test status
Simulation time 16688875 ps
CPU time 0.64 seconds
Started Apr 16 02:50:33 PM PDT 24
Finished Apr 16 02:50:35 PM PDT 24
Peak memory 203408 kb
Host smart-f9cb4a43-41cb-4348-880d-a3a3155e64b2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93515699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_
walk.93515699
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4273934243
Short name T138
Test name
Test status
Simulation time 113125752 ps
CPU time 3.57 seconds
Started Apr 16 02:50:35 PM PDT 24
Finished Apr 16 02:50:40 PM PDT 24
Peak memory 215276 kb
Host smart-431266d8-1063-4ad8-b2b1-f35da77d918c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273934243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4273934243
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1990987513
Short name T806
Test name
Test status
Simulation time 99284946 ps
CPU time 2.76 seconds
Started Apr 16 02:50:34 PM PDT 24
Finished Apr 16 02:50:37 PM PDT 24
Peak memory 215592 kb
Host smart-a18f6983-0563-4c79-873a-d14200f05997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990987513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
990987513
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2216535474
Short name T362
Test name
Test status
Simulation time 1587362034 ps
CPU time 21.36 seconds
Started Apr 16 02:50:34 PM PDT 24
Finished Apr 16 02:50:57 PM PDT 24
Peak memory 215688 kb
Host smart-6a9ef0f2-3727-4036-8560-cdd4e4bf17b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216535474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2216535474
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4101472506
Short name T780
Test name
Test status
Simulation time 25431003 ps
CPU time 0.73 seconds
Started Apr 16 02:50:53 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 203728 kb
Host smart-57c92004-002e-42b9-8420-f93de57ff5cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101472506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4101472506
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.411493394
Short name T815
Test name
Test status
Simulation time 14119251 ps
CPU time 0.78 seconds
Started Apr 16 02:50:57 PM PDT 24
Finished Apr 16 02:50:59 PM PDT 24
Peak memory 203484 kb
Host smart-e3617d48-626c-43b8-97b7-9bf13009dceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411493394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.411493394
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3712801668
Short name T783
Test name
Test status
Simulation time 86173247 ps
CPU time 0.73 seconds
Started Apr 16 02:50:56 PM PDT 24
Finished Apr 16 02:50:57 PM PDT 24
Peak memory 203708 kb
Host smart-7534c9d4-d1df-4f5f-ad89-cbcb3ca734bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712801668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3712801668
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1180467270
Short name T824
Test name
Test status
Simulation time 43687135 ps
CPU time 0.71 seconds
Started Apr 16 02:50:52 PM PDT 24
Finished Apr 16 02:50:54 PM PDT 24
Peak memory 203352 kb
Host smart-37d4cebc-cc8d-4dc7-930b-5a8f8410bca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180467270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1180467270
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.595821153
Short name T853
Test name
Test status
Simulation time 12626501 ps
CPU time 0.71 seconds
Started Apr 16 02:50:58 PM PDT 24
Finished Apr 16 02:50:59 PM PDT 24
Peak memory 203744 kb
Host smart-90cff1b5-318d-4979-a607-3989c9be130d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595821153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.595821153
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1465671937
Short name T778
Test name
Test status
Simulation time 24612941 ps
CPU time 0.66 seconds
Started Apr 16 02:50:50 PM PDT 24
Finished Apr 16 02:50:52 PM PDT 24
Peak memory 203696 kb
Host smart-8af66752-789d-4edb-8f71-22a595c76e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465671937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1465671937
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2490578420
Short name T751
Test name
Test status
Simulation time 45748719 ps
CPU time 0.73 seconds
Started Apr 16 02:50:53 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 203744 kb
Host smart-d16466ec-6d7e-442d-93cf-bb1b97d080bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490578420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2490578420
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3376330309
Short name T765
Test name
Test status
Simulation time 12309033 ps
CPU time 0.76 seconds
Started Apr 16 02:50:57 PM PDT 24
Finished Apr 16 02:50:59 PM PDT 24
Peak memory 203488 kb
Host smart-06683b7e-74e1-448d-845b-39a3ba74417e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376330309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3376330309
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4236547037
Short name T748
Test name
Test status
Simulation time 31725845 ps
CPU time 0.74 seconds
Started Apr 16 02:50:57 PM PDT 24
Finished Apr 16 02:50:59 PM PDT 24
Peak memory 203744 kb
Host smart-72086125-e8a8-4e83-9632-d8a5a095fbc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236547037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4236547037
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1229444997
Short name T794
Test name
Test status
Simulation time 15498732 ps
CPU time 0.71 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:53 PM PDT 24
Peak memory 203744 kb
Host smart-0d4fae32-59dd-4600-a338-0a8019c163eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229444997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1229444997
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.268498438
Short name T132
Test name
Test status
Simulation time 392092829 ps
CPU time 8.58 seconds
Started Apr 16 02:50:35 PM PDT 24
Finished Apr 16 02:50:45 PM PDT 24
Peak memory 207216 kb
Host smart-2e660e65-5026-48df-b8ab-99f992884e3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268498438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.268498438
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1886869591
Short name T790
Test name
Test status
Simulation time 2795408483 ps
CPU time 39.1 seconds
Started Apr 16 02:50:35 PM PDT 24
Finished Apr 16 02:51:16 PM PDT 24
Peak memory 207272 kb
Host smart-f39b37d5-c4df-4b77-812f-18b014a7de87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886869591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1886869591
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.274983658
Short name T97
Test name
Test status
Simulation time 55948805 ps
CPU time 0.96 seconds
Started Apr 16 02:50:36 PM PDT 24
Finished Apr 16 02:50:39 PM PDT 24
Peak memory 206652 kb
Host smart-b7312317-51cd-4134-9291-ad71247a13f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274983658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.274983658
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1903689804
Short name T816
Test name
Test status
Simulation time 81623515 ps
CPU time 2.93 seconds
Started Apr 16 02:50:34 PM PDT 24
Finished Apr 16 02:50:39 PM PDT 24
Peak memory 217448 kb
Host smart-a603256c-fffa-4445-9c74-2b838042d020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903689804 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1903689804
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3505839144
Short name T832
Test name
Test status
Simulation time 45478249 ps
CPU time 1.38 seconds
Started Apr 16 02:50:39 PM PDT 24
Finished Apr 16 02:50:42 PM PDT 24
Peak memory 207180 kb
Host smart-328452f8-613d-4ca7-82dc-beb6e94fff8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505839144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
505839144
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.422835116
Short name T849
Test name
Test status
Simulation time 14461769 ps
CPU time 0.77 seconds
Started Apr 16 02:50:37 PM PDT 24
Finished Apr 16 02:50:39 PM PDT 24
Peak memory 203504 kb
Host smart-2417b2df-0d84-4fb5-8cf3-b0c9b9d69d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422835116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.422835116
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3531901211
Short name T822
Test name
Test status
Simulation time 25911852 ps
CPU time 1.47 seconds
Started Apr 16 02:50:34 PM PDT 24
Finished Apr 16 02:50:37 PM PDT 24
Peak memory 215376 kb
Host smart-f11be9ae-9ce5-4212-9ade-f522a15776c9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531901211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3531901211
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.47340215
Short name T759
Test name
Test status
Simulation time 13439744 ps
CPU time 0.67 seconds
Started Apr 16 02:50:37 PM PDT 24
Finished Apr 16 02:50:40 PM PDT 24
Peak memory 203428 kb
Host smart-64e2c965-16ad-4710-b693-66b4e0ffcb53
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47340215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_
walk.47340215
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2535527490
Short name T803
Test name
Test status
Simulation time 480653313 ps
CPU time 3.46 seconds
Started Apr 16 02:50:44 PM PDT 24
Finished Apr 16 02:50:48 PM PDT 24
Peak memory 216508 kb
Host smart-a22e578f-07dc-46f1-849c-f8c358efa9ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535527490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2535527490
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2302981730
Short name T119
Test name
Test status
Simulation time 211345831 ps
CPU time 1.74 seconds
Started Apr 16 02:50:36 PM PDT 24
Finished Apr 16 02:50:39 PM PDT 24
Peak memory 215464 kb
Host smart-d824e1e8-ab42-43b7-803f-cfef4125b3c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302981730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
302981730
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4160160036
Short name T847
Test name
Test status
Simulation time 1737730200 ps
CPU time 12.65 seconds
Started Apr 16 02:50:37 PM PDT 24
Finished Apr 16 02:50:52 PM PDT 24
Peak memory 215704 kb
Host smart-120de1f0-9485-498e-a64e-692c84ef28ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160160036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4160160036
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1703395033
Short name T756
Test name
Test status
Simulation time 37195184 ps
CPU time 0.67 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:52 PM PDT 24
Peak memory 203376 kb
Host smart-2d2f8b96-29fe-4d44-91e3-d491c72ba878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703395033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1703395033
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3956107833
Short name T812
Test name
Test status
Simulation time 41149575 ps
CPU time 0.77 seconds
Started Apr 16 02:50:52 PM PDT 24
Finished Apr 16 02:50:54 PM PDT 24
Peak memory 203728 kb
Host smart-a3d5f4d4-3e51-4490-b235-970ee27d43a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956107833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3956107833
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2110291203
Short name T757
Test name
Test status
Simulation time 31628104 ps
CPU time 0.69 seconds
Started Apr 16 02:51:00 PM PDT 24
Finished Apr 16 02:51:02 PM PDT 24
Peak memory 203344 kb
Host smart-ecd9de15-2c83-4a39-a39b-a5d291c0621d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110291203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2110291203
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1808486014
Short name T771
Test name
Test status
Simulation time 16376476 ps
CPU time 0.77 seconds
Started Apr 16 02:50:53 PM PDT 24
Finished Apr 16 02:50:55 PM PDT 24
Peak memory 203720 kb
Host smart-15c603ef-5f7d-4db4-9443-d9b5394393d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808486014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1808486014
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.29196569
Short name T787
Test name
Test status
Simulation time 43186703 ps
CPU time 0.74 seconds
Started Apr 16 02:50:54 PM PDT 24
Finished Apr 16 02:50:56 PM PDT 24
Peak memory 203424 kb
Host smart-e1649dbd-54c7-4bd9-8500-3b09a0aa6dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29196569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.29196569
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3911843994
Short name T786
Test name
Test status
Simulation time 16979348 ps
CPU time 0.67 seconds
Started Apr 16 02:50:51 PM PDT 24
Finished Apr 16 02:50:53 PM PDT 24
Peak memory 203352 kb
Host smart-65ee2ed2-e2e2-4d17-8a09-c16ab2b88ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911843994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3911843994
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.331219689
Short name T782
Test name
Test status
Simulation time 54875781 ps
CPU time 0.75 seconds
Started Apr 16 02:51:00 PM PDT 24
Finished Apr 16 02:51:02 PM PDT 24
Peak memory 203412 kb
Host smart-37ade111-ff1d-416d-af87-5aeffb0a1e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331219689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.331219689
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.280879720
Short name T774
Test name
Test status
Simulation time 14894356 ps
CPU time 0.72 seconds
Started Apr 16 02:50:52 PM PDT 24
Finished Apr 16 02:50:53 PM PDT 24
Peak memory 203464 kb
Host smart-585fc11d-533e-4e1d-bae9-9e95ec7d841e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280879720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.280879720
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3703967558
Short name T798
Test name
Test status
Simulation time 47793797 ps
CPU time 0.74 seconds
Started Apr 16 02:50:57 PM PDT 24
Finished Apr 16 02:50:58 PM PDT 24
Peak memory 203376 kb
Host smart-394da835-8e3e-4ddc-8384-79be265e5056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703967558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3703967558
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1431583291
Short name T846
Test name
Test status
Simulation time 64757765 ps
CPU time 0.73 seconds
Started Apr 16 02:51:02 PM PDT 24
Finished Apr 16 02:51:04 PM PDT 24
Peak memory 203344 kb
Host smart-4b20c97e-6745-4d9e-aa0e-b3f07e589b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431583291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1431583291
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.776851205
Short name T770
Test name
Test status
Simulation time 240863389 ps
CPU time 1.82 seconds
Started Apr 16 02:50:38 PM PDT 24
Finished Apr 16 02:50:41 PM PDT 24
Peak memory 215512 kb
Host smart-7321fa90-3d96-49a0-9ced-7a9e3216e112
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776851205 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.776851205
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3420654941
Short name T838
Test name
Test status
Simulation time 39525786 ps
CPU time 2.41 seconds
Started Apr 16 02:50:37 PM PDT 24
Finished Apr 16 02:50:41 PM PDT 24
Peak memory 215388 kb
Host smart-6d4b13c8-6b4a-447f-9f3a-abff10d7afd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420654941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
420654941
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3599125040
Short name T155
Test name
Test status
Simulation time 14353752 ps
CPU time 0.7 seconds
Started Apr 16 02:50:39 PM PDT 24
Finished Apr 16 02:50:41 PM PDT 24
Peak memory 203384 kb
Host smart-56610a0e-6940-4e5e-a05f-017eabc0d2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599125040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
599125040
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4142217047
Short name T143
Test name
Test status
Simulation time 59079971 ps
CPU time 3.42 seconds
Started Apr 16 02:50:34 PM PDT 24
Finished Apr 16 02:50:39 PM PDT 24
Peak memory 215312 kb
Host smart-11ff4ab7-2426-431c-a7f6-f4376021d06b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142217047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4142217047
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2520058909
Short name T361
Test name
Test status
Simulation time 575720206 ps
CPU time 14.62 seconds
Started Apr 16 02:50:41 PM PDT 24
Finished Apr 16 02:50:56 PM PDT 24
Peak memory 215704 kb
Host smart-54a360de-2f74-4ad5-b2fe-dac20bb6337a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520058909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2520058909
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1256989044
Short name T121
Test name
Test status
Simulation time 87311285 ps
CPU time 1.77 seconds
Started Apr 16 02:50:44 PM PDT 24
Finished Apr 16 02:50:47 PM PDT 24
Peak memory 215376 kb
Host smart-03355949-fea1-47fb-afef-2328c08b3f5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256989044 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1256989044
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.202339222
Short name T841
Test name
Test status
Simulation time 442968271 ps
CPU time 2.72 seconds
Started Apr 16 02:50:38 PM PDT 24
Finished Apr 16 02:50:43 PM PDT 24
Peak memory 215316 kb
Host smart-4ac12f1d-2b5b-4181-8ad0-797aac74ff68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202339222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.202339222
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1436457495
Short name T819
Test name
Test status
Simulation time 12241091 ps
CPU time 0.7 seconds
Started Apr 16 02:50:36 PM PDT 24
Finished Apr 16 02:50:38 PM PDT 24
Peak memory 203356 kb
Host smart-bb4d2614-ecbc-4ef9-abb3-2c865db25748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436457495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
436457495
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4162573452
Short name T769
Test name
Test status
Simulation time 159269797 ps
CPU time 2.02 seconds
Started Apr 16 02:50:38 PM PDT 24
Finished Apr 16 02:50:42 PM PDT 24
Peak memory 215212 kb
Host smart-cc4b514b-101a-436f-92b1-db4788abd622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162573452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4162573452
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3291803226
Short name T114
Test name
Test status
Simulation time 70772678 ps
CPU time 2.63 seconds
Started Apr 16 02:50:35 PM PDT 24
Finished Apr 16 02:50:39 PM PDT 24
Peak memory 215408 kb
Host smart-a0faf7da-a70c-41cf-80ae-ba8b6c9eb1dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291803226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
291803226
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4223912286
Short name T820
Test name
Test status
Simulation time 210783056 ps
CPU time 6.53 seconds
Started Apr 16 02:50:39 PM PDT 24
Finished Apr 16 02:50:47 PM PDT 24
Peak memory 215348 kb
Host smart-f8fafd7f-c28b-449c-ba87-2ebe0eea2315
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223912286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.4223912286
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1365917741
Short name T151
Test name
Test status
Simulation time 59476445 ps
CPU time 1.8 seconds
Started Apr 16 02:50:41 PM PDT 24
Finished Apr 16 02:50:44 PM PDT 24
Peak memory 215408 kb
Host smart-c94350b3-8761-4909-a628-7220d69c0dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365917741 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1365917741
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.886557710
Short name T792
Test name
Test status
Simulation time 68587703 ps
CPU time 2 seconds
Started Apr 16 02:50:37 PM PDT 24
Finished Apr 16 02:50:41 PM PDT 24
Peak memory 215332 kb
Host smart-79875ee6-21d2-40ad-874f-82adf568c1be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886557710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.886557710
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2420099040
Short name T844
Test name
Test status
Simulation time 30471919 ps
CPU time 0.79 seconds
Started Apr 16 02:50:39 PM PDT 24
Finished Apr 16 02:50:41 PM PDT 24
Peak memory 203492 kb
Host smart-af5b0bf1-2160-4330-a326-0e0fbf08c656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420099040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
420099040
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.517154162
Short name T775
Test name
Test status
Simulation time 270831362 ps
CPU time 1.7 seconds
Started Apr 16 02:50:41 PM PDT 24
Finished Apr 16 02:50:44 PM PDT 24
Peak memory 215340 kb
Host smart-a07af464-bead-4546-bd81-bed65a3dc137
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517154162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.517154162
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2764512755
Short name T365
Test name
Test status
Simulation time 1674430719 ps
CPU time 20.94 seconds
Started Apr 16 02:50:38 PM PDT 24
Finished Apr 16 02:51:01 PM PDT 24
Peak memory 216604 kb
Host smart-07595f26-4517-409d-9e22-350563ef070b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764512755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2764512755
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4128898609
Short name T767
Test name
Test status
Simulation time 27366630 ps
CPU time 1.88 seconds
Started Apr 16 02:50:42 PM PDT 24
Finished Apr 16 02:50:44 PM PDT 24
Peak memory 215680 kb
Host smart-ea1d2da9-22d2-47bc-9fb2-928474822421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128898609 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4128898609
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.499481363
Short name T135
Test name
Test status
Simulation time 255452831 ps
CPU time 1.77 seconds
Started Apr 16 02:50:44 PM PDT 24
Finished Apr 16 02:50:47 PM PDT 24
Peak memory 215360 kb
Host smart-4c280bf5-f852-4602-8e62-c4a452e4a744
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499481363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.499481363
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.315850289
Short name T829
Test name
Test status
Simulation time 51293853 ps
CPU time 0.79 seconds
Started Apr 16 02:50:41 PM PDT 24
Finished Apr 16 02:50:43 PM PDT 24
Peak memory 203744 kb
Host smart-9e1d388e-1adf-42e8-9974-19697057071a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315850289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.315850289
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3933197137
Short name T141
Test name
Test status
Simulation time 124931595 ps
CPU time 1.95 seconds
Started Apr 16 02:50:38 PM PDT 24
Finished Apr 16 02:50:41 PM PDT 24
Peak memory 215256 kb
Host smart-54f89231-8b18-4e6c-884e-0b5a81b27263
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933197137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3933197137
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2688645085
Short name T809
Test name
Test status
Simulation time 111787776 ps
CPU time 1.96 seconds
Started Apr 16 02:50:40 PM PDT 24
Finished Apr 16 02:50:43 PM PDT 24
Peak memory 215568 kb
Host smart-037c3027-8f80-4f23-ac9d-4b5594e8525f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688645085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
688645085
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3184446535
Short name T834
Test name
Test status
Simulation time 198540930 ps
CPU time 12.81 seconds
Started Apr 16 02:50:38 PM PDT 24
Finished Apr 16 02:50:52 PM PDT 24
Peak memory 215384 kb
Host smart-11cd91c9-2bdb-41f7-bbc5-b0daf905e690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184446535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3184446535
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1707229228
Short name T118
Test name
Test status
Simulation time 213704576 ps
CPU time 4.01 seconds
Started Apr 16 02:50:43 PM PDT 24
Finished Apr 16 02:50:48 PM PDT 24
Peak memory 217860 kb
Host smart-e9acd78a-63d6-4f6c-ac1c-04cc3889b0cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707229228 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1707229228
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1757568756
Short name T136
Test name
Test status
Simulation time 69046621 ps
CPU time 2.01 seconds
Started Apr 16 02:50:43 PM PDT 24
Finished Apr 16 02:50:46 PM PDT 24
Peak memory 215380 kb
Host smart-5827a822-3e24-4dea-81f7-ec942e944b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757568756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
757568756
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3361452080
Short name T754
Test name
Test status
Simulation time 33533355 ps
CPU time 0.7 seconds
Started Apr 16 02:50:37 PM PDT 24
Finished Apr 16 02:50:39 PM PDT 24
Peak memory 203600 kb
Host smart-92773918-ffc3-4ca2-9ce3-d512bd697076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361452080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
361452080
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.836012836
Short name T825
Test name
Test status
Simulation time 44582845 ps
CPU time 2.88 seconds
Started Apr 16 02:50:43 PM PDT 24
Finished Apr 16 02:50:47 PM PDT 24
Peak memory 215184 kb
Host smart-6f9f7c11-35c5-48a3-967d-8c8371fbab21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836012836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.836012836
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3303545574
Short name T109
Test name
Test status
Simulation time 768135433 ps
CPU time 5 seconds
Started Apr 16 02:50:44 PM PDT 24
Finished Apr 16 02:50:49 PM PDT 24
Peak memory 216472 kb
Host smart-082cb93f-9de7-485d-89ae-1c6bb4769238
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303545574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
303545574
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2880911049
Short name T850
Test name
Test status
Simulation time 1026468574 ps
CPU time 14.11 seconds
Started Apr 16 02:50:46 PM PDT 24
Finished Apr 16 02:51:01 PM PDT 24
Peak memory 215612 kb
Host smart-23acd045-2e16-4a5f-9ab9-0d0436ac9e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880911049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2880911049
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.991554332
Short name T536
Test name
Test status
Simulation time 20144421 ps
CPU time 0.7 seconds
Started Apr 16 02:52:18 PM PDT 24
Finished Apr 16 02:52:20 PM PDT 24
Peak memory 205776 kb
Host smart-26879bef-bef2-4fa1-923c-b90a9f9543d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991554332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.991554332
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3727712041
Short name T489
Test name
Test status
Simulation time 19514099 ps
CPU time 0.77 seconds
Started Apr 16 02:52:12 PM PDT 24
Finished Apr 16 02:52:14 PM PDT 24
Peak memory 205568 kb
Host smart-1640153a-7eb2-43ac-a483-58f8954e30e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727712041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3727712041
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4106358115
Short name T405
Test name
Test status
Simulation time 306286524 ps
CPU time 4.79 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:28 PM PDT 24
Peak memory 223452 kb
Host smart-c44af722-3fd0-4b5e-b871-33168932bae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106358115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4106358115
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3184405204
Short name T197
Test name
Test status
Simulation time 7172852381 ps
CPU time 23.9 seconds
Started Apr 16 02:52:17 PM PDT 24
Finished Apr 16 02:52:42 PM PDT 24
Peak memory 240976 kb
Host smart-8e0d5da2-d611-4669-ade6-febd4f467dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184405204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3184405204
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3392514967
Short name T659
Test name
Test status
Simulation time 101693289 ps
CPU time 1 seconds
Started Apr 16 02:52:13 PM PDT 24
Finished Apr 16 02:52:16 PM PDT 24
Peak memory 218188 kb
Host smart-8db31888-5625-41e5-8606-429d569aee14
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392514967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3392514967
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.482494430
Short name T371
Test name
Test status
Simulation time 1957589662 ps
CPU time 7.73 seconds
Started Apr 16 02:52:16 PM PDT 24
Finished Apr 16 02:52:25 PM PDT 24
Peak memory 221112 kb
Host smart-e81cbbb2-d678-493c-a276-92bb20303e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482494430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.482494430
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2838457033
Short name T693
Test name
Test status
Simulation time 1339917581 ps
CPU time 5.62 seconds
Started Apr 16 02:52:16 PM PDT 24
Finished Apr 16 02:52:23 PM PDT 24
Peak memory 222948 kb
Host smart-1358f12e-c90a-485f-bc3b-b1999fb599ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2838457033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2838457033
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.857496960
Short name T736
Test name
Test status
Simulation time 837754460 ps
CPU time 5.33 seconds
Started Apr 16 02:52:12 PM PDT 24
Finished Apr 16 02:52:19 PM PDT 24
Peak memory 216460 kb
Host smart-1cde07fb-30a7-4ce4-9fe8-3ee6404362d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857496960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.857496960
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2136543609
Short name T436
Test name
Test status
Simulation time 7312976628 ps
CPU time 7.75 seconds
Started Apr 16 02:52:18 PM PDT 24
Finished Apr 16 02:52:27 PM PDT 24
Peak memory 216576 kb
Host smart-ede80090-3363-4bf2-95ae-a18722abe566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136543609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2136543609
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3046507337
Short name T572
Test name
Test status
Simulation time 247175365 ps
CPU time 1.47 seconds
Started Apr 16 02:52:14 PM PDT 24
Finished Apr 16 02:52:17 PM PDT 24
Peak memory 216552 kb
Host smart-8b0a69b7-f48d-42ba-9533-699ca4195baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046507337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3046507337
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.693972480
Short name T451
Test name
Test status
Simulation time 43473254 ps
CPU time 0.82 seconds
Started Apr 16 02:52:10 PM PDT 24
Finished Apr 16 02:52:12 PM PDT 24
Peak memory 205768 kb
Host smart-ccf3617a-48e0-4ab7-aad4-2aed7955b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693972480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.693972480
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1030028970
Short name T464
Test name
Test status
Simulation time 192143129 ps
CPU time 2.72 seconds
Started Apr 16 02:52:16 PM PDT 24
Finished Apr 16 02:52:20 PM PDT 24
Peak memory 222316 kb
Host smart-7063718b-8fd0-41f0-9c6a-c7bde74fb30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030028970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1030028970
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2777746289
Short name T162
Test name
Test status
Simulation time 10529508 ps
CPU time 0.67 seconds
Started Apr 16 02:52:20 PM PDT 24
Finished Apr 16 02:52:22 PM PDT 24
Peak memory 205324 kb
Host smart-20c3a479-5f0f-44ce-90ff-dbba91acf765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777746289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
777746289
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3102370048
Short name T303
Test name
Test status
Simulation time 632928699 ps
CPU time 4.3 seconds
Started Apr 16 02:52:17 PM PDT 24
Finished Apr 16 02:52:23 PM PDT 24
Peak memory 224688 kb
Host smart-977dbe76-ca5b-4fd9-baac-79d97d0d8758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102370048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3102370048
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3586688599
Short name T490
Test name
Test status
Simulation time 21544195 ps
CPU time 0.77 seconds
Started Apr 16 02:52:14 PM PDT 24
Finished Apr 16 02:52:17 PM PDT 24
Peak memory 206620 kb
Host smart-0e3317c8-7235-4218-8d08-85e4d59dde0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586688599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3586688599
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.200308919
Short name T166
Test name
Test status
Simulation time 10615088715 ps
CPU time 30.4 seconds
Started Apr 16 02:52:16 PM PDT 24
Finished Apr 16 02:52:48 PM PDT 24
Peak memory 235204 kb
Host smart-1c7ef4fc-e9e5-48fb-87a3-0b1e1b3cea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200308919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.200308919
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3142625038
Short name T36
Test name
Test status
Simulation time 330383736 ps
CPU time 1.19 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:52:26 PM PDT 24
Peak memory 235504 kb
Host smart-c2503603-2599-4eb2-bc2e-5540eade3ba1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142625038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3142625038
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1143915117
Short name T454
Test name
Test status
Simulation time 60145713 ps
CPU time 1.51 seconds
Started Apr 16 02:52:16 PM PDT 24
Finished Apr 16 02:52:19 PM PDT 24
Peak memory 216504 kb
Host smart-be3d231e-3209-41cb-b5a9-c83d3249c537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143915117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1143915117
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.766292050
Short name T714
Test name
Test status
Simulation time 51662679 ps
CPU time 0.97 seconds
Started Apr 16 02:52:20 PM PDT 24
Finished Apr 16 02:52:22 PM PDT 24
Peak memory 206860 kb
Host smart-bfc20dae-7124-406a-ac87-e49ed6b28705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766292050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.766292050
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3023068389
Short name T487
Test name
Test status
Simulation time 104890653 ps
CPU time 0.82 seconds
Started Apr 16 02:52:35 PM PDT 24
Finished Apr 16 02:52:36 PM PDT 24
Peak memory 206636 kb
Host smart-82d7775a-74a0-4573-b042-1112deb55ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023068389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3023068389
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3068533372
Short name T293
Test name
Test status
Simulation time 1005669492 ps
CPU time 14.08 seconds
Started Apr 16 02:52:36 PM PDT 24
Finished Apr 16 02:52:51 PM PDT 24
Peak memory 249924 kb
Host smart-ce102abd-ae4b-4521-a035-e07561a11759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068533372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3068533372
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1507813487
Short name T171
Test name
Test status
Simulation time 1409413505 ps
CPU time 13.1 seconds
Started Apr 16 02:52:35 PM PDT 24
Finished Apr 16 02:52:49 PM PDT 24
Peak memory 219300 kb
Host smart-3523d726-f4b2-4def-8c91-00f5d166a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507813487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1507813487
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2716328161
Short name T243
Test name
Test status
Simulation time 15934534548 ps
CPU time 75.74 seconds
Started Apr 16 02:52:34 PM PDT 24
Finished Apr 16 02:53:51 PM PDT 24
Peak memory 240772 kb
Host smart-8604a372-9f6d-4a3c-a657-aeb7e2a810ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716328161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2716328161
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1874178378
Short name T690
Test name
Test status
Simulation time 27106007 ps
CPU time 1.09 seconds
Started Apr 16 02:52:33 PM PDT 24
Finished Apr 16 02:52:35 PM PDT 24
Peak memory 216988 kb
Host smart-0ad02349-ae8b-436e-b798-831c81312a1c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874178378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1874178378
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2814993620
Short name T591
Test name
Test status
Simulation time 4364280811 ps
CPU time 22.18 seconds
Started Apr 16 02:52:35 PM PDT 24
Finished Apr 16 02:52:58 PM PDT 24
Peak memory 221564 kb
Host smart-1b927f4d-db27-4f9b-8265-97948aa27c91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2814993620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2814993620
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3511171318
Short name T717
Test name
Test status
Simulation time 6231296957 ps
CPU time 40.45 seconds
Started Apr 16 02:52:30 PM PDT 24
Finished Apr 16 02:53:12 PM PDT 24
Peak memory 216636 kb
Host smart-e3e70b51-e7b3-44f8-8262-0b96ab24064b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511171318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3511171318
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3022861811
Short name T417
Test name
Test status
Simulation time 893531572 ps
CPU time 2.7 seconds
Started Apr 16 02:52:36 PM PDT 24
Finished Apr 16 02:52:40 PM PDT 24
Peak memory 216540 kb
Host smart-a127b64c-95cb-47cd-91ea-a033ad7c57cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022861811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3022861811
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3179134232
Short name T671
Test name
Test status
Simulation time 101370239 ps
CPU time 1.51 seconds
Started Apr 16 02:52:35 PM PDT 24
Finished Apr 16 02:52:38 PM PDT 24
Peak memory 216776 kb
Host smart-5b75290a-4e36-46f3-b670-25a883ab17b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179134232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3179134232
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.296678667
Short name T565
Test name
Test status
Simulation time 195002439 ps
CPU time 0.89 seconds
Started Apr 16 02:52:31 PM PDT 24
Finished Apr 16 02:52:32 PM PDT 24
Peak memory 206792 kb
Host smart-f0bf98c7-a5ff-4e32-be3b-d3de95419c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296678667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.296678667
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3785026857
Short name T691
Test name
Test status
Simulation time 1063276913 ps
CPU time 5.79 seconds
Started Apr 16 02:52:36 PM PDT 24
Finished Apr 16 02:52:43 PM PDT 24
Peak memory 224736 kb
Host smart-3447bbca-b08a-4622-8a88-db625e4c6302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785026857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3785026857
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3374145129
Short name T411
Test name
Test status
Simulation time 11658513 ps
CPU time 0.69 seconds
Started Apr 16 02:52:43 PM PDT 24
Finished Apr 16 02:52:45 PM PDT 24
Peak memory 205364 kb
Host smart-cbced4da-9b86-4ee0-9d4d-2281dcccb409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374145129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3374145129
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.724697938
Short name T240
Test name
Test status
Simulation time 534297880 ps
CPU time 6.11 seconds
Started Apr 16 02:52:43 PM PDT 24
Finished Apr 16 02:52:50 PM PDT 24
Peak memory 224476 kb
Host smart-c8d87762-127e-47c6-9e29-17de350b0b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724697938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.724697938
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4023892107
Short name T605
Test name
Test status
Simulation time 53332479 ps
CPU time 0.8 seconds
Started Apr 16 02:52:37 PM PDT 24
Finished Apr 16 02:52:39 PM PDT 24
Peak memory 206964 kb
Host smart-b3d4a457-304e-4ad1-84c4-2b35d79c6f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023892107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4023892107
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2419118121
Short name T353
Test name
Test status
Simulation time 12224620531 ps
CPU time 48.8 seconds
Started Apr 16 02:52:41 PM PDT 24
Finished Apr 16 02:53:30 PM PDT 24
Peak memory 241156 kb
Host smart-f9eaa89a-a7e6-4bf9-a129-1275f075f87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419118121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2419118121
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.4162523670
Short name T494
Test name
Test status
Simulation time 28888808 ps
CPU time 1.02 seconds
Started Apr 16 02:52:35 PM PDT 24
Finished Apr 16 02:52:37 PM PDT 24
Peak memory 216884 kb
Host smart-033cfc4b-f3a1-4984-9b55-ac7b6d962b92
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162523670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.4162523670
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.987554318
Short name T338
Test name
Test status
Simulation time 662548751 ps
CPU time 5.24 seconds
Started Apr 16 02:52:37 PM PDT 24
Finished Apr 16 02:52:44 PM PDT 24
Peak memory 216996 kb
Host smart-0927a534-7389-4d0d-9b87-b09566aede37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987554318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.987554318
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.732347839
Short name T321
Test name
Test status
Simulation time 8558393489 ps
CPU time 15.46 seconds
Started Apr 16 02:52:37 PM PDT 24
Finished Apr 16 02:52:54 PM PDT 24
Peak memory 228124 kb
Host smart-59df5237-73fc-4e32-91e8-f6eb78888006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732347839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.732347839
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.810799404
Short name T662
Test name
Test status
Simulation time 490800239 ps
CPU time 3.92 seconds
Started Apr 16 02:52:43 PM PDT 24
Finished Apr 16 02:52:48 PM PDT 24
Peak memory 219132 kb
Host smart-d00c9251-e162-41de-af52-803402b0866e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=810799404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.810799404
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.600799907
Short name T378
Test name
Test status
Simulation time 5525064851 ps
CPU time 28.23 seconds
Started Apr 16 02:52:37 PM PDT 24
Finished Apr 16 02:53:07 PM PDT 24
Peak memory 216556 kb
Host smart-6b55a138-5a90-4338-be00-375e50f1d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600799907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.600799907
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4165987673
Short name T413
Test name
Test status
Simulation time 4104060590 ps
CPU time 6.14 seconds
Started Apr 16 02:52:37 PM PDT 24
Finished Apr 16 02:52:44 PM PDT 24
Peak memory 216616 kb
Host smart-975bd8cd-495b-42e0-8363-d7986d9ea171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165987673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4165987673
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2182210345
Short name T641
Test name
Test status
Simulation time 370221946 ps
CPU time 2.91 seconds
Started Apr 16 02:52:41 PM PDT 24
Finished Apr 16 02:52:45 PM PDT 24
Peak memory 216752 kb
Host smart-2b5ab2a7-97e3-4202-bcf0-ef6ead59480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182210345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2182210345
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3460193764
Short name T589
Test name
Test status
Simulation time 988881190 ps
CPU time 1.07 seconds
Started Apr 16 02:52:34 PM PDT 24
Finished Apr 16 02:52:36 PM PDT 24
Peak memory 206872 kb
Host smart-724d186e-f7c7-467f-8707-827495f5b384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460193764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3460193764
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3351410834
Short name T34
Test name
Test status
Simulation time 14001831 ps
CPU time 0.74 seconds
Started Apr 16 02:52:48 PM PDT 24
Finished Apr 16 02:52:50 PM PDT 24
Peak memory 205784 kb
Host smart-620685ff-1fa4-4468-b50b-b6f8b3cdd476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351410834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3351410834
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3591750552
Short name T279
Test name
Test status
Simulation time 908845000 ps
CPU time 7.33 seconds
Started Apr 16 02:52:43 PM PDT 24
Finished Apr 16 02:52:52 PM PDT 24
Peak memory 219120 kb
Host smart-2d72c739-007f-4edd-a87a-4620c6685676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591750552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3591750552
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4012995364
Short name T415
Test name
Test status
Simulation time 16699729 ps
CPU time 0.76 seconds
Started Apr 16 02:52:43 PM PDT 24
Finished Apr 16 02:52:44 PM PDT 24
Peak memory 206612 kb
Host smart-0d1d69ea-7744-461f-af94-b6cf56533af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012995364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4012995364
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2334074334
Short name T347
Test name
Test status
Simulation time 6581369364 ps
CPU time 19.71 seconds
Started Apr 16 02:52:42 PM PDT 24
Finished Apr 16 02:53:03 PM PDT 24
Peak memory 222760 kb
Host smart-e2be8dd6-3906-4113-b2e1-1fba52885166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334074334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2334074334
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.651602385
Short name T407
Test name
Test status
Simulation time 45100138 ps
CPU time 1.04 seconds
Started Apr 16 02:52:42 PM PDT 24
Finished Apr 16 02:52:44 PM PDT 24
Peak memory 216972 kb
Host smart-761aed59-0384-422b-8f8b-99de0a5ec3bc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651602385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.651602385
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2377287667
Short name T623
Test name
Test status
Simulation time 174835725 ps
CPU time 3.9 seconds
Started Apr 16 02:52:42 PM PDT 24
Finished Apr 16 02:52:47 PM PDT 24
Peak memory 219844 kb
Host smart-12560e26-705a-484f-b346-48c26b7450a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2377287667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2377287667
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1451005808
Short name T614
Test name
Test status
Simulation time 1010066313 ps
CPU time 4.51 seconds
Started Apr 16 02:52:42 PM PDT 24
Finished Apr 16 02:52:47 PM PDT 24
Peak memory 216588 kb
Host smart-5ca32de0-c45f-4fff-b238-3641e20053c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451005808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1451005808
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1038345414
Short name T696
Test name
Test status
Simulation time 390789189 ps
CPU time 6.45 seconds
Started Apr 16 02:52:41 PM PDT 24
Finished Apr 16 02:52:48 PM PDT 24
Peak memory 216488 kb
Host smart-204de7fb-b6e3-4743-97b3-1e2c0851b0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038345414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1038345414
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.311302431
Short name T17
Test name
Test status
Simulation time 114596420 ps
CPU time 1.03 seconds
Started Apr 16 02:52:42 PM PDT 24
Finished Apr 16 02:52:44 PM PDT 24
Peak memory 206868 kb
Host smart-470ad403-4605-40c1-88da-5233cf5bc1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311302431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.311302431
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2689672165
Short name T629
Test name
Test status
Simulation time 14114563 ps
CPU time 0.7 seconds
Started Apr 16 02:52:47 PM PDT 24
Finished Apr 16 02:52:50 PM PDT 24
Peak memory 205376 kb
Host smart-6d6c32ec-8492-4213-a1e7-8f3ae02b777d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689672165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2689672165
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1802798001
Short name T456
Test name
Test status
Simulation time 17333607 ps
CPU time 0.75 seconds
Started Apr 16 02:52:44 PM PDT 24
Finished Apr 16 02:52:46 PM PDT 24
Peak memory 206656 kb
Host smart-e686e4b6-6066-4303-a2cd-42fa0b004c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802798001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1802798001
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2571562344
Short name T352
Test name
Test status
Simulation time 3480917915 ps
CPU time 58.43 seconds
Started Apr 16 02:52:43 PM PDT 24
Finished Apr 16 02:53:43 PM PDT 24
Peak memory 238032 kb
Host smart-abc20f59-46ca-4230-905e-ea9c97ee005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571562344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2571562344
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.614024571
Short name T527
Test name
Test status
Simulation time 825859823 ps
CPU time 4.55 seconds
Started Apr 16 02:52:46 PM PDT 24
Finished Apr 16 02:52:52 PM PDT 24
Peak memory 224784 kb
Host smart-85573906-07dc-4156-bccd-b2a1398a42bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614024571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.614024571
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2012222956
Short name T213
Test name
Test status
Simulation time 25727709779 ps
CPU time 76.02 seconds
Started Apr 16 02:52:46 PM PDT 24
Finished Apr 16 02:54:03 PM PDT 24
Peak memory 224792 kb
Host smart-b537611d-a525-4784-9f0c-5824b2cb57ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012222956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2012222956
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2177117822
Short name T715
Test name
Test status
Simulation time 25618996 ps
CPU time 1 seconds
Started Apr 16 02:52:45 PM PDT 24
Finished Apr 16 02:52:47 PM PDT 24
Peak memory 216944 kb
Host smart-d733ccfb-3397-4fd8-8be9-aa23ec2cd939
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177117822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2177117822
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2853111616
Short name T317
Test name
Test status
Simulation time 3072153551 ps
CPU time 14.13 seconds
Started Apr 16 02:52:46 PM PDT 24
Finished Apr 16 02:53:01 PM PDT 24
Peak memory 221812 kb
Host smart-e54763b9-7eeb-4c5c-aa5d-59a2acb3b966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853111616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2853111616
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1374162468
Short name T724
Test name
Test status
Simulation time 4783271628 ps
CPU time 7.46 seconds
Started Apr 16 02:52:46 PM PDT 24
Finished Apr 16 02:52:56 PM PDT 24
Peak memory 220900 kb
Host smart-77c1d88d-4888-49b8-9d44-4e826c4d693b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1374162468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1374162468
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.540053777
Short name T390
Test name
Test status
Simulation time 5207261087 ps
CPU time 30.22 seconds
Started Apr 16 02:52:48 PM PDT 24
Finished Apr 16 02:53:20 PM PDT 24
Peak memory 216756 kb
Host smart-1a1bb4e6-2b14-4e67-adf4-f613e2fc93dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540053777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.540053777
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1664217551
Short name T482
Test name
Test status
Simulation time 170596349 ps
CPU time 1.23 seconds
Started Apr 16 02:52:45 PM PDT 24
Finished Apr 16 02:52:47 PM PDT 24
Peak memory 207856 kb
Host smart-c1496642-6887-487f-9cc2-01ea44e49736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664217551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1664217551
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2368530774
Short name T670
Test name
Test status
Simulation time 398626513 ps
CPU time 4.48 seconds
Started Apr 16 02:52:45 PM PDT 24
Finished Apr 16 02:52:51 PM PDT 24
Peak memory 216584 kb
Host smart-c0c66f0e-2c7f-40d1-867f-04678d54baa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368530774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2368530774
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.277402238
Short name T400
Test name
Test status
Simulation time 174381018 ps
CPU time 0.73 seconds
Started Apr 16 02:52:46 PM PDT 24
Finished Apr 16 02:52:49 PM PDT 24
Peak memory 205856 kb
Host smart-57ac2c29-e0f1-42d7-96b3-613dc09de867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277402238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.277402238
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1962397096
Short name T571
Test name
Test status
Simulation time 24589232 ps
CPU time 0.76 seconds
Started Apr 16 02:52:57 PM PDT 24
Finished Apr 16 02:52:58 PM PDT 24
Peak memory 204832 kb
Host smart-4175e9be-d7fa-4543-aa48-fc98d8720501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962397096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1962397096
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2839278993
Short name T631
Test name
Test status
Simulation time 61118633 ps
CPU time 0.76 seconds
Started Apr 16 02:52:45 PM PDT 24
Finished Apr 16 02:52:47 PM PDT 24
Peak memory 206652 kb
Host smart-a1ee114b-998d-4253-8985-9bc8370d6389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839278993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2839278993
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2066910119
Short name T288
Test name
Test status
Simulation time 5234404814 ps
CPU time 21.37 seconds
Started Apr 16 02:52:53 PM PDT 24
Finished Apr 16 02:53:16 PM PDT 24
Peak memory 224804 kb
Host smart-5a9defd2-c5e1-4616-bc17-799a193ea761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066910119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2066910119
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2049402467
Short name T345
Test name
Test status
Simulation time 21040595630 ps
CPU time 187.57 seconds
Started Apr 16 02:52:57 PM PDT 24
Finished Apr 16 02:56:05 PM PDT 24
Peak memory 232568 kb
Host smart-ef5666dc-af56-4959-8924-7d94224bed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049402467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2049402467
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.4116000211
Short name T467
Test name
Test status
Simulation time 42588568 ps
CPU time 0.97 seconds
Started Apr 16 02:52:44 PM PDT 24
Finished Apr 16 02:52:47 PM PDT 24
Peak memory 218184 kb
Host smart-27f21047-79e1-4b17-8990-d1a317c3127c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116000211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.4116000211
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.452190674
Short name T369
Test name
Test status
Simulation time 287626849 ps
CPU time 5.74 seconds
Started Apr 16 02:52:54 PM PDT 24
Finished Apr 16 02:53:01 PM PDT 24
Peak memory 236668 kb
Host smart-3b55eb14-f0bf-48f7-964f-31d1898c679a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452190674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.452190674
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2809061150
Short name T524
Test name
Test status
Simulation time 702418310 ps
CPU time 3.41 seconds
Started Apr 16 02:52:51 PM PDT 24
Finished Apr 16 02:52:55 PM PDT 24
Peak memory 220432 kb
Host smart-7d596291-dbc0-45eb-9884-294ef1f809e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2809061150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2809061150
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.727403941
Short name T164
Test name
Test status
Simulation time 5033484888 ps
CPU time 9.38 seconds
Started Apr 16 02:52:45 PM PDT 24
Finished Apr 16 02:52:56 PM PDT 24
Peak memory 216572 kb
Host smart-079c061c-d1a2-4af8-8b0f-7d6269958499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727403941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.727403941
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3177090113
Short name T568
Test name
Test status
Simulation time 53469892 ps
CPU time 2.52 seconds
Started Apr 16 02:52:51 PM PDT 24
Finished Apr 16 02:52:55 PM PDT 24
Peak memory 216580 kb
Host smart-acf84a58-aec5-4535-bb22-8b6369d6a66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177090113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3177090113
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1058543630
Short name T19
Test name
Test status
Simulation time 493907614 ps
CPU time 1.02 seconds
Started Apr 16 02:52:53 PM PDT 24
Finished Apr 16 02:52:55 PM PDT 24
Peak memory 206856 kb
Host smart-26910641-892b-490c-a863-f46a114a5ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058543630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1058543630
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2970807788
Short name T525
Test name
Test status
Simulation time 11905361 ps
CPU time 0.7 seconds
Started Apr 16 02:52:54 PM PDT 24
Finished Apr 16 02:52:56 PM PDT 24
Peak memory 205708 kb
Host smart-042815f9-d5e4-4fbe-8f5c-7e44cee3b4aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970807788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2970807788
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4262038417
Short name T30
Test name
Test status
Simulation time 8014828124 ps
CPU time 22.53 seconds
Started Apr 16 02:52:49 PM PDT 24
Finished Apr 16 02:53:12 PM PDT 24
Peak memory 232796 kb
Host smart-a5abcf1c-49df-4af6-bbdb-0c02d10fdac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262038417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4262038417
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.142482112
Short name T732
Test name
Test status
Simulation time 13868792 ps
CPU time 0.8 seconds
Started Apr 16 02:52:53 PM PDT 24
Finished Apr 16 02:52:55 PM PDT 24
Peak memory 206628 kb
Host smart-81b028de-860c-4dac-af5b-43d500bb9ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142482112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.142482112
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.128092070
Short name T707
Test name
Test status
Simulation time 1133178851 ps
CPU time 18.44 seconds
Started Apr 16 02:52:52 PM PDT 24
Finished Apr 16 02:53:11 PM PDT 24
Peak memory 238104 kb
Host smart-e0d3f12b-ce0c-4f4c-8ab9-060dcbab0000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128092070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.128092070
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.965653031
Short name T190
Test name
Test status
Simulation time 1755713356 ps
CPU time 8.46 seconds
Started Apr 16 02:53:00 PM PDT 24
Finished Apr 16 02:53:10 PM PDT 24
Peak memory 220460 kb
Host smart-bd6bdfbd-31b4-4bee-8102-ddd03b4596b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965653031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.965653031
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.746517255
Short name T445
Test name
Test status
Simulation time 29133513 ps
CPU time 1.03 seconds
Started Apr 16 02:53:01 PM PDT 24
Finished Apr 16 02:53:03 PM PDT 24
Peak memory 218212 kb
Host smart-e45928db-468e-4b02-aac5-6b74863167b7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746517255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.746517255
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.269142869
Short name T283
Test name
Test status
Simulation time 2946675438 ps
CPU time 5.94 seconds
Started Apr 16 02:52:52 PM PDT 24
Finished Apr 16 02:52:58 PM PDT 24
Peak memory 224712 kb
Host smart-f6c6ee9e-071c-4d1f-85d0-aa3f4fdd6661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269142869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.269142869
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3602665587
Short name T642
Test name
Test status
Simulation time 124369945 ps
CPU time 4.21 seconds
Started Apr 16 02:52:57 PM PDT 24
Finished Apr 16 02:53:03 PM PDT 24
Peak memory 223180 kb
Host smart-f1fa44d3-5ec0-4eb8-ad32-8c7dba721d90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3602665587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3602665587
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1086158525
Short name T65
Test name
Test status
Simulation time 17774508492 ps
CPU time 20.98 seconds
Started Apr 16 02:52:48 PM PDT 24
Finished Apr 16 02:53:10 PM PDT 24
Peak memory 216608 kb
Host smart-5b8527db-8572-4101-94a3-8341ab3b69bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086158525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1086158525
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3511126959
Short name T488
Test name
Test status
Simulation time 38727171049 ps
CPU time 29.84 seconds
Started Apr 16 02:52:58 PM PDT 24
Finished Apr 16 02:53:29 PM PDT 24
Peak memory 216584 kb
Host smart-cddc2483-dd81-4bde-9d0c-5ba062e317cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511126959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3511126959
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2149216932
Short name T644
Test name
Test status
Simulation time 187103288 ps
CPU time 2.67 seconds
Started Apr 16 02:52:55 PM PDT 24
Finished Apr 16 02:52:59 PM PDT 24
Peak memory 216764 kb
Host smart-90e8d6ea-68d5-4b48-af02-248061be5763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149216932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2149216932
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3085493946
Short name T701
Test name
Test status
Simulation time 54629127 ps
CPU time 0.71 seconds
Started Apr 16 02:52:55 PM PDT 24
Finished Apr 16 02:52:57 PM PDT 24
Peak memory 205776 kb
Host smart-4c08ec23-a951-43ab-bcdf-bb74f0a27ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085493946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3085493946
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3498797178
Short name T280
Test name
Test status
Simulation time 250065984 ps
CPU time 3.01 seconds
Started Apr 16 02:52:53 PM PDT 24
Finished Apr 16 02:52:58 PM PDT 24
Peak memory 222892 kb
Host smart-ceb2c43f-2db2-4605-ab90-3d1879b44228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498797178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3498797178
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1816652636
Short name T478
Test name
Test status
Simulation time 14000188 ps
CPU time 0.73 seconds
Started Apr 16 02:52:56 PM PDT 24
Finished Apr 16 02:52:58 PM PDT 24
Peak memory 205372 kb
Host smart-c3a1f1df-97b1-49b0-b200-8b4ab076e924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816652636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1816652636
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2256189274
Short name T440
Test name
Test status
Simulation time 27123835 ps
CPU time 0.78 seconds
Started Apr 16 02:52:53 PM PDT 24
Finished Apr 16 02:52:55 PM PDT 24
Peak memory 206648 kb
Host smart-205dd69a-1b10-4bcd-8b84-78f52ef77002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256189274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2256189274
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2776280977
Short name T57
Test name
Test status
Simulation time 32810331609 ps
CPU time 75.84 seconds
Started Apr 16 02:52:54 PM PDT 24
Finished Apr 16 02:54:11 PM PDT 24
Peak memory 232980 kb
Host smart-2f00a49c-8fb2-43a7-ac27-2bdfd1b9bed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776280977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2776280977
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3723787735
Short name T580
Test name
Test status
Simulation time 33842122 ps
CPU time 1.1 seconds
Started Apr 16 02:52:50 PM PDT 24
Finished Apr 16 02:52:52 PM PDT 24
Peak memory 217200 kb
Host smart-ef0d07ea-d0f4-4a5c-a7c2-3d8c612da44d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723787735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3723787735
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1793983515
Short name T439
Test name
Test status
Simulation time 512919077 ps
CPU time 5.72 seconds
Started Apr 16 02:52:52 PM PDT 24
Finished Apr 16 02:53:00 PM PDT 24
Peak memory 218804 kb
Host smart-23b3ff20-6581-4bcc-a291-a4a9097f1a13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1793983515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1793983515
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2987769682
Short name T674
Test name
Test status
Simulation time 4727940610 ps
CPU time 38.83 seconds
Started Apr 16 02:52:48 PM PDT 24
Finished Apr 16 02:53:28 PM PDT 24
Peak memory 216628 kb
Host smart-ddef00b6-96e2-441b-8e3a-1e850a742a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987769682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2987769682
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3929401408
Short name T496
Test name
Test status
Simulation time 39961755466 ps
CPU time 28.62 seconds
Started Apr 16 02:52:50 PM PDT 24
Finished Apr 16 02:53:19 PM PDT 24
Peak memory 216640 kb
Host smart-45096684-9cb2-4236-a401-6eee4c8c16af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929401408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3929401408
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4190831533
Short name T585
Test name
Test status
Simulation time 362699768 ps
CPU time 2.25 seconds
Started Apr 16 02:52:50 PM PDT 24
Finished Apr 16 02:52:53 PM PDT 24
Peak memory 216624 kb
Host smart-46a8f4a2-03cc-464c-b066-498e8c2d466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190831533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4190831533
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.239956434
Short name T416
Test name
Test status
Simulation time 596911145 ps
CPU time 0.96 seconds
Started Apr 16 02:52:53 PM PDT 24
Finished Apr 16 02:52:56 PM PDT 24
Peak memory 206888 kb
Host smart-abbf9165-c52d-4dcd-8a01-7c6ec0648019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239956434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.239956434
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.803227352
Short name T510
Test name
Test status
Simulation time 13302259 ps
CPU time 0.75 seconds
Started Apr 16 02:52:56 PM PDT 24
Finished Apr 16 02:52:58 PM PDT 24
Peak memory 204716 kb
Host smart-1d015165-9257-4c1f-9977-2db594613a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803227352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.803227352
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1920877777
Short name T553
Test name
Test status
Simulation time 60432743 ps
CPU time 0.8 seconds
Started Apr 16 02:52:58 PM PDT 24
Finished Apr 16 02:53:00 PM PDT 24
Peak memory 206616 kb
Host smart-322812a6-006d-4731-93a6-76a6ef6116f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920877777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1920877777
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2641268513
Short name T592
Test name
Test status
Simulation time 17124316 ps
CPU time 1 seconds
Started Apr 16 02:52:58 PM PDT 24
Finished Apr 16 02:53:00 PM PDT 24
Peak memory 216972 kb
Host smart-d6776c4d-891d-49ba-92fe-f3a1937f8359
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641268513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2641268513
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3840901622
Short name T273
Test name
Test status
Simulation time 3304600871 ps
CPU time 10.81 seconds
Started Apr 16 02:52:54 PM PDT 24
Finished Apr 16 02:53:07 PM PDT 24
Peak memory 220672 kb
Host smart-ba1fc252-d8c8-4d0a-b737-7ffb468636cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840901622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3840901622
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.728260991
Short name T618
Test name
Test status
Simulation time 1035837317 ps
CPU time 13.56 seconds
Started Apr 16 02:52:56 PM PDT 24
Finished Apr 16 02:53:10 PM PDT 24
Peak memory 220608 kb
Host smart-3fa660bc-6c27-433f-80c9-a7d3b53ad4be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=728260991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.728260991
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2177957315
Short name T14
Test name
Test status
Simulation time 33540495813 ps
CPU time 21.83 seconds
Started Apr 16 02:52:55 PM PDT 24
Finished Apr 16 02:53:18 PM PDT 24
Peak memory 216576 kb
Host smart-3b0fe4f0-f78f-4b06-a5d9-cba71bd8c00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177957315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2177957315
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1303742683
Short name T739
Test name
Test status
Simulation time 11961452255 ps
CPU time 31.76 seconds
Started Apr 16 02:53:02 PM PDT 24
Finished Apr 16 02:53:35 PM PDT 24
Peak memory 216624 kb
Host smart-c2328d88-d648-4827-a9bd-5e861b1bafcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303742683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1303742683
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3692577300
Short name T677
Test name
Test status
Simulation time 176637997 ps
CPU time 1.58 seconds
Started Apr 16 02:53:02 PM PDT 24
Finished Apr 16 02:53:05 PM PDT 24
Peak memory 216592 kb
Host smart-6e42ab6b-f721-49c1-b139-b2c42b4bf02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692577300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3692577300
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3342702476
Short name T406
Test name
Test status
Simulation time 26495789 ps
CPU time 0.89 seconds
Started Apr 16 02:53:02 PM PDT 24
Finished Apr 16 02:53:04 PM PDT 24
Peak memory 206060 kb
Host smart-bcc1203f-bf13-4531-a1b8-d8707ac13952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342702476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3342702476
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1642770008
Short name T646
Test name
Test status
Simulation time 22052779 ps
CPU time 0.76 seconds
Started Apr 16 02:52:59 PM PDT 24
Finished Apr 16 02:53:02 PM PDT 24
Peak memory 205372 kb
Host smart-dae80c26-ddde-4f7b-ae00-cbf0ffed2570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642770008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1642770008
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.377017749
Short name T414
Test name
Test status
Simulation time 26582677 ps
CPU time 0.76 seconds
Started Apr 16 02:53:00 PM PDT 24
Finished Apr 16 02:53:02 PM PDT 24
Peak memory 206636 kb
Host smart-24f0e11a-3005-403c-b4de-e47f853d7c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377017749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.377017749
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2634208033
Short name T45
Test name
Test status
Simulation time 134758241473 ps
CPU time 160.39 seconds
Started Apr 16 02:52:59 PM PDT 24
Finished Apr 16 02:55:40 PM PDT 24
Peak memory 219044 kb
Host smart-5628c5c7-d1d2-4f5d-a249-d34a42dd1785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634208033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2634208033
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3616978024
Short name T500
Test name
Test status
Simulation time 27985477 ps
CPU time 1.06 seconds
Started Apr 16 02:52:57 PM PDT 24
Finished Apr 16 02:52:59 PM PDT 24
Peak memory 216956 kb
Host smart-e17b9a26-1772-4fde-b19b-a65cacbf6a39
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616978024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3616978024
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2418540057
Short name T78
Test name
Test status
Simulation time 6095405242 ps
CPU time 16.45 seconds
Started Apr 16 02:53:06 PM PDT 24
Finished Apr 16 02:53:24 PM PDT 24
Peak memory 217132 kb
Host smart-df073a03-f1f5-4658-bed1-3ed60200e572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418540057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2418540057
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2960102166
Short name T502
Test name
Test status
Simulation time 1106248288 ps
CPU time 8.09 seconds
Started Apr 16 02:53:00 PM PDT 24
Finished Apr 16 02:53:09 PM PDT 24
Peak memory 222460 kb
Host smart-943abfbb-3b2c-4af0-a678-4b084d1da2bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2960102166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2960102166
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1666475951
Short name T658
Test name
Test status
Simulation time 1026778544 ps
CPU time 3.84 seconds
Started Apr 16 02:53:07 PM PDT 24
Finished Apr 16 02:53:11 PM PDT 24
Peak memory 216428 kb
Host smart-daa42fc6-95a3-471a-a385-a70a030d0253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666475951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1666475951
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.245634374
Short name T465
Test name
Test status
Simulation time 842847230 ps
CPU time 2.46 seconds
Started Apr 16 02:53:06 PM PDT 24
Finished Apr 16 02:53:09 PM PDT 24
Peak memory 216368 kb
Host smart-e661e7ca-fa3b-4593-be37-a4557e124392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245634374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.245634374
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.401166653
Short name T647
Test name
Test status
Simulation time 32864484 ps
CPU time 1.01 seconds
Started Apr 16 02:52:58 PM PDT 24
Finished Apr 16 02:53:00 PM PDT 24
Peak memory 207164 kb
Host smart-88d2964a-6b83-4da7-9f69-1ff87f509799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401166653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.401166653
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1980174051
Short name T431
Test name
Test status
Simulation time 89803840 ps
CPU time 0.99 seconds
Started Apr 16 02:53:05 PM PDT 24
Finished Apr 16 02:53:07 PM PDT 24
Peak memory 206868 kb
Host smart-bddeebaa-79a7-4f69-8c10-a9f7dca7a87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980174051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1980174051
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3657841405
Short name T457
Test name
Test status
Simulation time 12478080 ps
CPU time 0.74 seconds
Started Apr 16 02:53:04 PM PDT 24
Finished Apr 16 02:53:05 PM PDT 24
Peak memory 205384 kb
Host smart-f51dfb6f-baf7-45b1-bcd5-fda1f3fd75af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657841405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3657841405
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.929126797
Short name T692
Test name
Test status
Simulation time 243823815 ps
CPU time 2.97 seconds
Started Apr 16 02:53:07 PM PDT 24
Finished Apr 16 02:53:11 PM PDT 24
Peak memory 217104 kb
Host smart-cc3b235d-7878-4ae6-a1e1-2e21754d334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929126797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.929126797
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1327824322
Short name T602
Test name
Test status
Simulation time 51175228 ps
CPU time 0.76 seconds
Started Apr 16 02:52:58 PM PDT 24
Finished Apr 16 02:53:00 PM PDT 24
Peak memory 206956 kb
Host smart-0e8a8ecd-0a89-4a94-84c3-29bdbfe332f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327824322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1327824322
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2760478671
Short name T167
Test name
Test status
Simulation time 326529097 ps
CPU time 6.53 seconds
Started Apr 16 02:53:03 PM PDT 24
Finished Apr 16 02:53:11 PM PDT 24
Peak memory 218692 kb
Host smart-81336822-cc40-4686-a51d-da6379a71353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760478671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2760478671
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2241458808
Short name T679
Test name
Test status
Simulation time 3437233822 ps
CPU time 18.17 seconds
Started Apr 16 02:53:03 PM PDT 24
Finished Apr 16 02:53:22 PM PDT 24
Peak memory 217112 kb
Host smart-019ace1b-4ea4-4082-b6f5-ef26138b225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241458808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2241458808
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1501018820
Short name T39
Test name
Test status
Simulation time 26151031 ps
CPU time 1.07 seconds
Started Apr 16 02:53:02 PM PDT 24
Finished Apr 16 02:53:04 PM PDT 24
Peak memory 217200 kb
Host smart-d152d0ba-b8a4-4fb5-8de9-1d89e4b6c9eb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501018820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1501018820
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.807076914
Short name T738
Test name
Test status
Simulation time 1005382076 ps
CPU time 4.38 seconds
Started Apr 16 02:53:01 PM PDT 24
Finished Apr 16 02:53:06 PM PDT 24
Peak memory 220852 kb
Host smart-2bb2a57f-2246-444f-bc53-1d65e63061c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=807076914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.807076914
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3352452037
Short name T384
Test name
Test status
Simulation time 2961582205 ps
CPU time 8.39 seconds
Started Apr 16 02:52:58 PM PDT 24
Finished Apr 16 02:53:08 PM PDT 24
Peak memory 216652 kb
Host smart-a8c24ad7-c6ef-4185-8d2a-58b4badbd3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352452037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3352452037
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3122625249
Short name T601
Test name
Test status
Simulation time 3526173317 ps
CPU time 7.09 seconds
Started Apr 16 02:53:07 PM PDT 24
Finished Apr 16 02:53:15 PM PDT 24
Peak memory 216508 kb
Host smart-6bd0ad99-50d2-4b41-b3ee-67faa44b2098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122625249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3122625249
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1802788928
Short name T552
Test name
Test status
Simulation time 285149970 ps
CPU time 2.03 seconds
Started Apr 16 02:53:03 PM PDT 24
Finished Apr 16 02:53:06 PM PDT 24
Peak memory 216536 kb
Host smart-24ce3f63-eb6a-4f60-95b1-25ca14253de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802788928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1802788928
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3894613564
Short name T704
Test name
Test status
Simulation time 202099831 ps
CPU time 0.98 seconds
Started Apr 16 02:52:56 PM PDT 24
Finished Apr 16 02:52:58 PM PDT 24
Peak memory 206816 kb
Host smart-2b9e662f-3c32-4abc-b288-516b21968512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894613564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3894613564
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2898911479
Short name T506
Test name
Test status
Simulation time 29326491 ps
CPU time 0.74 seconds
Started Apr 16 02:52:16 PM PDT 24
Finished Apr 16 02:52:18 PM PDT 24
Peak memory 205080 kb
Host smart-3ae5d613-f0b9-40ff-879c-495ba2be8316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898911479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
898911479
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.40056898
Short name T450
Test name
Test status
Simulation time 14668886 ps
CPU time 0.82 seconds
Started Apr 16 02:52:16 PM PDT 24
Finished Apr 16 02:52:18 PM PDT 24
Peak memory 205564 kb
Host smart-3fdd7bcc-7723-4b88-a84f-cf08ddb0ad6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40056898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.40056898
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1303232014
Short name T106
Test name
Test status
Simulation time 1785520141 ps
CPU time 5.17 seconds
Started Apr 16 02:52:22 PM PDT 24
Finished Apr 16 02:52:29 PM PDT 24
Peak memory 223980 kb
Host smart-ff668411-fe9d-476a-8083-74169b3d1bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303232014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1303232014
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3135935213
Short name T637
Test name
Test status
Simulation time 153459233 ps
CPU time 2.84 seconds
Started Apr 16 02:52:12 PM PDT 24
Finished Apr 16 02:52:16 PM PDT 24
Peak memory 221116 kb
Host smart-b9539310-2b66-4582-a0b3-4728c93bbc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135935213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3135935213
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2989044157
Short name T476
Test name
Test status
Simulation time 115883851 ps
CPU time 1.08 seconds
Started Apr 16 02:52:13 PM PDT 24
Finished Apr 16 02:52:16 PM PDT 24
Peak memory 216944 kb
Host smart-ecc5451e-28a7-4a6c-9b9d-f39a30ffbd3e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989044157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2989044157
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4204567530
Short name T253
Test name
Test status
Simulation time 1499634273 ps
CPU time 5.39 seconds
Started Apr 16 02:52:15 PM PDT 24
Finished Apr 16 02:52:22 PM PDT 24
Peak memory 219120 kb
Host smart-04498dc2-e132-4d0b-877f-5ccaad9b60fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204567530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4204567530
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.298089810
Short name T543
Test name
Test status
Simulation time 425290652 ps
CPU time 4.6 seconds
Started Apr 16 02:52:25 PM PDT 24
Finished Apr 16 02:52:32 PM PDT 24
Peak memory 219980 kb
Host smart-ce75e494-b639-45e4-b020-492852e375a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=298089810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.298089810
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.335946523
Short name T51
Test name
Test status
Simulation time 62395846 ps
CPU time 1.04 seconds
Started Apr 16 02:52:24 PM PDT 24
Finished Apr 16 02:52:27 PM PDT 24
Peak memory 235404 kb
Host smart-721d1c79-3349-448a-9ced-d5b68b558263
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335946523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.335946523
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1986312465
Short name T425
Test name
Test status
Simulation time 8060590700 ps
CPU time 6.97 seconds
Started Apr 16 02:52:14 PM PDT 24
Finished Apr 16 02:52:23 PM PDT 24
Peak memory 216528 kb
Host smart-c8e4a0ac-6c80-49f0-aa23-3e0c5b6e4ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986312465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1986312465
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2416895786
Short name T447
Test name
Test status
Simulation time 289191632 ps
CPU time 3.01 seconds
Started Apr 16 02:52:12 PM PDT 24
Finished Apr 16 02:52:16 PM PDT 24
Peak memory 216324 kb
Host smart-2240dd39-807d-4396-9c40-6316a55def43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416895786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2416895786
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2361627402
Short name T404
Test name
Test status
Simulation time 36350425 ps
CPU time 0.82 seconds
Started Apr 16 02:52:13 PM PDT 24
Finished Apr 16 02:52:15 PM PDT 24
Peak memory 205872 kb
Host smart-a78eb086-a678-4a26-8943-cf34ed54d959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361627402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2361627402
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.849108013
Short name T223
Test name
Test status
Simulation time 125583991 ps
CPU time 2.47 seconds
Started Apr 16 02:52:15 PM PDT 24
Finished Apr 16 02:52:19 PM PDT 24
Peak memory 216604 kb
Host smart-233690c6-c239-45e2-929f-4aa43ce3c609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849108013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.849108013
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1717734528
Short name T712
Test name
Test status
Simulation time 22226563 ps
CPU time 0.69 seconds
Started Apr 16 02:53:11 PM PDT 24
Finished Apr 16 02:53:13 PM PDT 24
Peak memory 204824 kb
Host smart-e0b47b28-873e-482b-86f0-f012dbe896fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717734528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1717734528
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2447230369
Short name T421
Test name
Test status
Simulation time 19758843 ps
CPU time 0.73 seconds
Started Apr 16 02:53:03 PM PDT 24
Finished Apr 16 02:53:05 PM PDT 24
Peak memory 205600 kb
Host smart-0de59d26-395c-46fe-b5df-796b0becb743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447230369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2447230369
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2732336230
Short name T556
Test name
Test status
Simulation time 1285216761 ps
CPU time 24.61 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:37 PM PDT 24
Peak memory 233956 kb
Host smart-9e84cb82-ce13-42e6-8b34-5d434f938c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732336230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2732336230
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.967938660
Short name T165
Test name
Test status
Simulation time 7267954299 ps
CPU time 20.93 seconds
Started Apr 16 02:53:07 PM PDT 24
Finished Apr 16 02:53:29 PM PDT 24
Peak memory 217928 kb
Host smart-5ccb13c8-8c42-4b35-94b0-834385585be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967938660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.967938660
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2760952171
Short name T326
Test name
Test status
Simulation time 1851968569 ps
CPU time 3.95 seconds
Started Apr 16 02:53:01 PM PDT 24
Finished Apr 16 02:53:06 PM PDT 24
Peak memory 222532 kb
Host smart-76ee19f9-a094-45b0-b4b3-a94eba94bde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760952171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2760952171
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.51848231
Short name T573
Test name
Test status
Simulation time 3874466311 ps
CPU time 6.72 seconds
Started Apr 16 02:53:05 PM PDT 24
Finished Apr 16 02:53:12 PM PDT 24
Peak memory 221556 kb
Host smart-fb9321af-dbee-40c3-a230-6fe1c6b5039e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=51848231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direc
t.51848231
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1572224508
Short name T154
Test name
Test status
Simulation time 59391596 ps
CPU time 1.09 seconds
Started Apr 16 02:53:04 PM PDT 24
Finished Apr 16 02:53:06 PM PDT 24
Peak memory 206856 kb
Host smart-1a4748ee-868a-4c05-aa5f-2fb0f536094f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572224508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1572224508
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.95945695
Short name T67
Test name
Test status
Simulation time 2901769332 ps
CPU time 14.2 seconds
Started Apr 16 02:53:01 PM PDT 24
Finished Apr 16 02:53:17 PM PDT 24
Peak memory 216668 kb
Host smart-fd62bb59-5595-4452-9c8b-51782cff95d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95945695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.95945695
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2920034613
Short name T526
Test name
Test status
Simulation time 411747978 ps
CPU time 3.21 seconds
Started Apr 16 02:53:06 PM PDT 24
Finished Apr 16 02:53:11 PM PDT 24
Peak memory 216356 kb
Host smart-a1bda8ee-3288-43b9-be71-0c3464bb2b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920034613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2920034613
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.782271360
Short name T727
Test name
Test status
Simulation time 356421063 ps
CPU time 16.54 seconds
Started Apr 16 02:53:02 PM PDT 24
Finished Apr 16 02:53:19 PM PDT 24
Peak memory 218324 kb
Host smart-a16a5af6-5406-4c73-9384-ca571c20c8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782271360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.782271360
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1947817888
Short name T667
Test name
Test status
Simulation time 28392251 ps
CPU time 0.83 seconds
Started Apr 16 02:52:59 PM PDT 24
Finished Apr 16 02:53:01 PM PDT 24
Peak memory 205872 kb
Host smart-21670578-ca70-402d-b03c-9ade7d334c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947817888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1947817888
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3225892089
Short name T517
Test name
Test status
Simulation time 22445962 ps
CPU time 0.73 seconds
Started Apr 16 02:53:09 PM PDT 24
Finished Apr 16 02:53:11 PM PDT 24
Peak memory 205696 kb
Host smart-9e938cb1-9da6-4a33-82da-06bc6658c0e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225892089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3225892089
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2854594823
Short name T520
Test name
Test status
Simulation time 57202040 ps
CPU time 0.87 seconds
Started Apr 16 02:53:09 PM PDT 24
Finished Apr 16 02:53:10 PM PDT 24
Peak memory 205624 kb
Host smart-a67159c4-afce-4738-9563-1b8ace631b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854594823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2854594823
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1617052599
Short name T689
Test name
Test status
Simulation time 17000183672 ps
CPU time 75.58 seconds
Started Apr 16 02:53:13 PM PDT 24
Finished Apr 16 02:54:30 PM PDT 24
Peak memory 249392 kb
Host smart-7b3ff92e-3f9a-43ec-b65d-bca1182a4a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617052599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1617052599
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4239578991
Short name T194
Test name
Test status
Simulation time 19933535441 ps
CPU time 33.71 seconds
Started Apr 16 02:53:03 PM PDT 24
Finished Apr 16 02:53:38 PM PDT 24
Peak memory 218240 kb
Host smart-4065e2d1-0e41-4e01-8030-4a46648b73c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239578991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4239578991
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.4273163010
Short name T477
Test name
Test status
Simulation time 258936429 ps
CPU time 4.54 seconds
Started Apr 16 02:53:09 PM PDT 24
Finished Apr 16 02:53:14 PM PDT 24
Peak memory 219268 kb
Host smart-4cd4399e-aff8-4e96-8184-6ac64f87e8fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4273163010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.4273163010
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1391211566
Short name T725
Test name
Test status
Simulation time 10671963717 ps
CPU time 27.62 seconds
Started Apr 16 02:53:07 PM PDT 24
Finished Apr 16 02:53:35 PM PDT 24
Peak memory 218836 kb
Host smart-581f58fa-62d4-4482-8762-de4891f52495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391211566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1391211566
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1843394703
Short name T538
Test name
Test status
Simulation time 2402036332 ps
CPU time 9.46 seconds
Started Apr 16 02:53:14 PM PDT 24
Finished Apr 16 02:53:25 PM PDT 24
Peak memory 216588 kb
Host smart-b363b889-3a63-4f1e-a9be-8d374f891245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843394703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1843394703
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3689876081
Short name T435
Test name
Test status
Simulation time 15792068 ps
CPU time 0.75 seconds
Started Apr 16 02:53:05 PM PDT 24
Finished Apr 16 02:53:07 PM PDT 24
Peak memory 205780 kb
Host smart-5cc2235d-0820-4c9d-95b9-60d52baa433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689876081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3689876081
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.334299944
Short name T409
Test name
Test status
Simulation time 117238125 ps
CPU time 0.85 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:12 PM PDT 24
Peak memory 206840 kb
Host smart-6c010919-f983-4e51-8007-05d356ac8e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334299944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.334299944
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.424146393
Short name T313
Test name
Test status
Simulation time 33053981009 ps
CPU time 24.35 seconds
Started Apr 16 02:53:12 PM PDT 24
Finished Apr 16 02:53:38 PM PDT 24
Peak memory 233048 kb
Host smart-6f18188b-2a43-4f49-9218-1fb39f22af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424146393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.424146393
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.490344085
Short name T597
Test name
Test status
Simulation time 12610503 ps
CPU time 0.67 seconds
Started Apr 16 02:53:17 PM PDT 24
Finished Apr 16 02:53:19 PM PDT 24
Peak memory 205340 kb
Host smart-c0f3dd0b-2fbc-4274-8f7c-15ac25d1416c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490344085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.490344085
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3452095073
Short name T200
Test name
Test status
Simulation time 1353304929 ps
CPU time 7.65 seconds
Started Apr 16 02:53:13 PM PDT 24
Finished Apr 16 02:53:22 PM PDT 24
Peak memory 223028 kb
Host smart-c6d07b86-4da3-4064-9a6f-402d6a611536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452095073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3452095073
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1802001919
Short name T516
Test name
Test status
Simulation time 62417623 ps
CPU time 0.77 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:13 PM PDT 24
Peak memory 206960 kb
Host smart-3ace4817-8107-4281-8f25-b9a566fecade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802001919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1802001919
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1264660627
Short name T709
Test name
Test status
Simulation time 30850238944 ps
CPU time 67.17 seconds
Started Apr 16 02:53:16 PM PDT 24
Finished Apr 16 02:54:24 PM PDT 24
Peak memory 249360 kb
Host smart-5c338fe7-a88a-44e8-9cf3-cb85ce3381b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264660627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1264660627
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1567481259
Short name T48
Test name
Test status
Simulation time 4954079706 ps
CPU time 49.35 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:54:01 PM PDT 24
Peak memory 232812 kb
Host smart-bd1d1dd5-a0e2-4c1c-8083-73538974a85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567481259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1567481259
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.230301492
Short name T231
Test name
Test status
Simulation time 4866092353 ps
CPU time 7.61 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:19 PM PDT 24
Peak memory 224544 kb
Host smart-c1ece374-f161-4155-af78-1d746d38e0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230301492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.230301492
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2459272878
Short name T531
Test name
Test status
Simulation time 1839201685 ps
CPU time 6.38 seconds
Started Apr 16 02:53:11 PM PDT 24
Finished Apr 16 02:53:19 PM PDT 24
Peak memory 219244 kb
Host smart-4e8e7c73-702d-45c1-aa7d-53a4fa33b666
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2459272878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2459272878
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1641595284
Short name T388
Test name
Test status
Simulation time 32295412996 ps
CPU time 47.74 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:59 PM PDT 24
Peak memory 216548 kb
Host smart-44564ade-e21f-4285-b2f1-033d270906f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641595284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1641595284
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1552901171
Short name T654
Test name
Test status
Simulation time 1568512159 ps
CPU time 10.71 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:22 PM PDT 24
Peak memory 216524 kb
Host smart-613ca672-5e72-4f96-8f40-08aa14fd83d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552901171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1552901171
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1994247436
Short name T523
Test name
Test status
Simulation time 248550849 ps
CPU time 1.72 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:14 PM PDT 24
Peak memory 216608 kb
Host smart-94c5da9a-8bed-4af7-8e49-e569808629e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994247436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1994247436
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3047358317
Short name T485
Test name
Test status
Simulation time 145487961 ps
CPU time 0.99 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:13 PM PDT 24
Peak memory 206876 kb
Host smart-65bd0fca-ba64-4ee1-844b-776a1c4d61c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047358317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3047358317
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3989767032
Short name T643
Test name
Test status
Simulation time 33751897 ps
CPU time 0.74 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:12 PM PDT 24
Peak memory 204840 kb
Host smart-871c90d7-bd89-4aab-8b05-05ef06a331e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989767032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3989767032
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3296003163
Short name T437
Test name
Test status
Simulation time 25124833 ps
CPU time 0.79 seconds
Started Apr 16 02:53:06 PM PDT 24
Finished Apr 16 02:53:08 PM PDT 24
Peak memory 206620 kb
Host smart-8b7c5ba9-3606-444e-b6c5-de72470dfb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296003163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3296003163
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4035747096
Short name T282
Test name
Test status
Simulation time 297664226 ps
CPU time 3.59 seconds
Started Apr 16 02:53:17 PM PDT 24
Finished Apr 16 02:53:21 PM PDT 24
Peak memory 218792 kb
Host smart-c22e0dca-9c5f-4479-b43b-97a7874dff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035747096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4035747096
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1449181005
Short name T681
Test name
Test status
Simulation time 174673011 ps
CPU time 3.57 seconds
Started Apr 16 02:53:15 PM PDT 24
Finished Apr 16 02:53:19 PM PDT 24
Peak memory 222956 kb
Host smart-e88138f3-3c55-4be7-8d8c-fa9289ef5d08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449181005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1449181005
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.893940385
Short name T358
Test name
Test status
Simulation time 34033605 ps
CPU time 0.89 seconds
Started Apr 16 02:53:09 PM PDT 24
Finished Apr 16 02:53:11 PM PDT 24
Peak memory 206920 kb
Host smart-c446f9b4-29b1-4317-a6da-320de8ef7cba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893940385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.893940385
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1200933617
Short name T395
Test name
Test status
Simulation time 10213973171 ps
CPU time 50.95 seconds
Started Apr 16 02:53:16 PM PDT 24
Finished Apr 16 02:54:08 PM PDT 24
Peak memory 216688 kb
Host smart-9a813791-d8df-4991-ba90-2ad2e7e146ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200933617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1200933617
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4133368524
Short name T471
Test name
Test status
Simulation time 1124826157 ps
CPU time 7.73 seconds
Started Apr 16 02:53:11 PM PDT 24
Finished Apr 16 02:53:21 PM PDT 24
Peak memory 216516 kb
Host smart-bfc482a2-f2d6-4445-a6ff-57d4b66d29fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133368524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4133368524
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.878579273
Short name T657
Test name
Test status
Simulation time 71758458 ps
CPU time 0.95 seconds
Started Apr 16 02:53:15 PM PDT 24
Finished Apr 16 02:53:16 PM PDT 24
Peak memory 206564 kb
Host smart-75325232-9081-4c75-a243-776ab6d109a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878579273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.878579273
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2794856735
Short name T561
Test name
Test status
Simulation time 639579087 ps
CPU time 1.17 seconds
Started Apr 16 02:53:13 PM PDT 24
Finished Apr 16 02:53:16 PM PDT 24
Peak memory 206484 kb
Host smart-3b5a3fca-67ec-4872-9ae5-138eacb4c5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794856735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2794856735
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1980481322
Short name T31
Test name
Test status
Simulation time 17365970190 ps
CPU time 10.56 seconds
Started Apr 16 02:53:09 PM PDT 24
Finished Apr 16 02:53:21 PM PDT 24
Peak memory 221576 kb
Host smart-54cf0487-2856-4331-9a7f-f041601de934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980481322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1980481322
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1458745269
Short name T479
Test name
Test status
Simulation time 19279408 ps
CPU time 0.68 seconds
Started Apr 16 02:53:16 PM PDT 24
Finished Apr 16 02:53:17 PM PDT 24
Peak memory 205708 kb
Host smart-72d0de27-8ecf-4e54-9521-b018f3e2747f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458745269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1458745269
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.262324646
Short name T492
Test name
Test status
Simulation time 78787027 ps
CPU time 0.76 seconds
Started Apr 16 02:53:12 PM PDT 24
Finished Apr 16 02:53:14 PM PDT 24
Peak memory 206652 kb
Host smart-1a7686db-c0a8-40be-832e-23af43791ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262324646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.262324646
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3352149214
Short name T93
Test name
Test status
Simulation time 984237552 ps
CPU time 4 seconds
Started Apr 16 02:53:14 PM PDT 24
Finished Apr 16 02:53:19 PM PDT 24
Peak memory 217008 kb
Host smart-fb9e2478-77c0-432b-b2c0-a4d4278a6022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352149214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3352149214
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3904971984
Short name T175
Test name
Test status
Simulation time 2129734803 ps
CPU time 4.86 seconds
Started Apr 16 02:53:17 PM PDT 24
Finished Apr 16 02:53:23 PM PDT 24
Peak memory 224696 kb
Host smart-67218798-c70f-495e-8edf-1f4579e1f565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904971984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3904971984
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1226994763
Short name T539
Test name
Test status
Simulation time 8746940723 ps
CPU time 8.85 seconds
Started Apr 16 02:53:13 PM PDT 24
Finished Apr 16 02:53:23 PM PDT 24
Peak memory 220072 kb
Host smart-4cfa6e4e-7c65-4288-abd5-90dde575cf19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1226994763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1226994763
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4188195765
Short name T396
Test name
Test status
Simulation time 10448950534 ps
CPU time 22.25 seconds
Started Apr 16 02:53:13 PM PDT 24
Finished Apr 16 02:53:36 PM PDT 24
Peak memory 217964 kb
Host smart-ac7a0d0e-8d4a-4f2c-bf10-e00f64521d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188195765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4188195765
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3916576647
Short name T711
Test name
Test status
Simulation time 1814998359 ps
CPU time 5.46 seconds
Started Apr 16 02:53:11 PM PDT 24
Finished Apr 16 02:53:18 PM PDT 24
Peak memory 216456 kb
Host smart-e5520a82-5aa9-414c-9261-7d0dcc80ae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916576647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3916576647
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.972840576
Short name T593
Test name
Test status
Simulation time 127267953 ps
CPU time 1.25 seconds
Started Apr 16 02:53:11 PM PDT 24
Finished Apr 16 02:53:14 PM PDT 24
Peak memory 208328 kb
Host smart-10444da3-ad01-4fd8-a3a8-6a01205a8c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972840576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.972840576
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.146733512
Short name T617
Test name
Test status
Simulation time 466427486 ps
CPU time 1.1 seconds
Started Apr 16 02:53:10 PM PDT 24
Finished Apr 16 02:53:13 PM PDT 24
Peak memory 206900 kb
Host smart-755233bd-8423-4701-8779-43e7e81df641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146733512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.146733512
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2781529357
Short name T73
Test name
Test status
Simulation time 2590786081 ps
CPU time 4.8 seconds
Started Apr 16 02:53:11 PM PDT 24
Finished Apr 16 02:53:17 PM PDT 24
Peak memory 218796 kb
Host smart-16228daf-1996-4e94-ac31-41d2330849ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781529357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2781529357
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.754720980
Short name T613
Test name
Test status
Simulation time 23285845 ps
CPU time 0.66 seconds
Started Apr 16 02:53:21 PM PDT 24
Finished Apr 16 02:53:22 PM PDT 24
Peak memory 205732 kb
Host smart-381e7b53-8b2d-43a5-9c8c-cacf9383cb18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754720980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.754720980
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4126652033
Short name T684
Test name
Test status
Simulation time 47299698 ps
CPU time 0.79 seconds
Started Apr 16 02:53:18 PM PDT 24
Finished Apr 16 02:53:20 PM PDT 24
Peak memory 206636 kb
Host smart-6779592f-d60d-4ac0-9405-2fd12ed43ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126652033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4126652033
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3295036332
Short name T295
Test name
Test status
Simulation time 7533204402 ps
CPU time 115.15 seconds
Started Apr 16 02:53:18 PM PDT 24
Finished Apr 16 02:55:14 PM PDT 24
Peak memory 253512 kb
Host smart-f717c6b1-c0f5-43e9-972f-9f7bff063cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295036332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3295036332
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1600446776
Short name T332
Test name
Test status
Simulation time 6464561156 ps
CPU time 23.04 seconds
Started Apr 16 02:53:22 PM PDT 24
Finished Apr 16 02:53:46 PM PDT 24
Peak memory 236016 kb
Host smart-a9d1185a-6dad-4779-9962-f6e442768f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600446776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1600446776
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1400805322
Short name T323
Test name
Test status
Simulation time 536079033 ps
CPU time 8.02 seconds
Started Apr 16 02:53:18 PM PDT 24
Finished Apr 16 02:53:27 PM PDT 24
Peak memory 236000 kb
Host smart-daabb644-cc8b-4ecc-9e1f-63a116dff822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400805322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1400805322
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1543086379
Short name T603
Test name
Test status
Simulation time 527505706 ps
CPU time 6.17 seconds
Started Apr 16 02:53:18 PM PDT 24
Finished Apr 16 02:53:25 PM PDT 24
Peak memory 222988 kb
Host smart-ac76715a-c279-4411-ad2d-dc3a3e8915da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1543086379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1543086379
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2136188347
Short name T375
Test name
Test status
Simulation time 5363254234 ps
CPU time 8.5 seconds
Started Apr 16 02:53:17 PM PDT 24
Finished Apr 16 02:53:26 PM PDT 24
Peak memory 216628 kb
Host smart-6b290da6-d8cc-4c76-93e0-6d31f9e10f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136188347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2136188347
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2549164456
Short name T530
Test name
Test status
Simulation time 3399988270 ps
CPU time 10.24 seconds
Started Apr 16 02:53:22 PM PDT 24
Finished Apr 16 02:53:33 PM PDT 24
Peak memory 216544 kb
Host smart-0b6d9e4d-bab2-4fec-8042-596f1c32c159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549164456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2549164456
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1919117122
Short name T663
Test name
Test status
Simulation time 426866455 ps
CPU time 2.3 seconds
Started Apr 16 02:53:18 PM PDT 24
Finished Apr 16 02:53:21 PM PDT 24
Peak memory 216588 kb
Host smart-ad77b7f5-6d22-47e5-97cc-d3bfdbe125e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919117122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1919117122
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.955741839
Short name T698
Test name
Test status
Simulation time 66836400 ps
CPU time 0.88 seconds
Started Apr 16 02:53:23 PM PDT 24
Finished Apr 16 02:53:24 PM PDT 24
Peak memory 205836 kb
Host smart-b4134615-e1b0-41c3-b3c7-9bdcffe565c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955741839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.955741839
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.508958261
Short name T534
Test name
Test status
Simulation time 16300134 ps
CPU time 0.79 seconds
Started Apr 16 02:53:24 PM PDT 24
Finished Apr 16 02:53:26 PM PDT 24
Peak memory 205416 kb
Host smart-54ed9159-bdb7-4231-9722-176a16e1f996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508958261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.508958261
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2706307041
Short name T729
Test name
Test status
Simulation time 590529439 ps
CPU time 3.94 seconds
Started Apr 16 02:53:23 PM PDT 24
Finished Apr 16 02:53:28 PM PDT 24
Peak memory 219392 kb
Host smart-e329c4bc-f8c5-4307-a12e-bad37e9cf745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706307041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2706307041
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.364950824
Short name T463
Test name
Test status
Simulation time 16360032 ps
CPU time 0.77 seconds
Started Apr 16 02:53:23 PM PDT 24
Finished Apr 16 02:53:25 PM PDT 24
Peak memory 205596 kb
Host smart-ebc2badf-5ac4-49d5-a1cf-5d44081d821f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364950824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.364950824
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.312076452
Short name T69
Test name
Test status
Simulation time 2247164890 ps
CPU time 5.31 seconds
Started Apr 16 02:53:22 PM PDT 24
Finished Apr 16 02:53:28 PM PDT 24
Peak memory 222516 kb
Host smart-e4b962d2-4ec8-4587-b6c4-5aa82ac381ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312076452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.312076452
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.344560991
Short name T703
Test name
Test status
Simulation time 1038136990 ps
CPU time 4.2 seconds
Started Apr 16 02:53:23 PM PDT 24
Finished Apr 16 02:53:28 PM PDT 24
Peak memory 223072 kb
Host smart-49c8d930-d186-43d1-b311-b54a93d6cd74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=344560991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.344560991
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4210333921
Short name T622
Test name
Test status
Simulation time 6928431438 ps
CPU time 20.96 seconds
Started Apr 16 02:53:23 PM PDT 24
Finished Apr 16 02:53:45 PM PDT 24
Peak memory 216576 kb
Host smart-db2e04df-a864-4198-8923-413a011dea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210333921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4210333921
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2583291823
Short name T55
Test name
Test status
Simulation time 93400776 ps
CPU time 1.06 seconds
Started Apr 16 02:53:27 PM PDT 24
Finished Apr 16 02:53:29 PM PDT 24
Peak memory 208032 kb
Host smart-60227435-2374-4d1e-a755-87c3e0769edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583291823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2583291823
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1471533378
Short name T545
Test name
Test status
Simulation time 129923306 ps
CPU time 1.1 seconds
Started Apr 16 02:53:22 PM PDT 24
Finished Apr 16 02:53:24 PM PDT 24
Peak memory 206864 kb
Host smart-d49b81a6-d052-4ee1-9b14-8f803786d5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471533378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1471533378
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3103946210
Short name T559
Test name
Test status
Simulation time 11439923 ps
CPU time 0.67 seconds
Started Apr 16 02:53:33 PM PDT 24
Finished Apr 16 02:53:36 PM PDT 24
Peak memory 205340 kb
Host smart-86cd6ede-3216-4a32-98e5-e8deafed7e82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103946210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3103946210
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3110585529
Short name T529
Test name
Test status
Simulation time 67867847 ps
CPU time 0.8 seconds
Started Apr 16 02:53:24 PM PDT 24
Finished Apr 16 02:53:26 PM PDT 24
Peak memory 206624 kb
Host smart-d9aa7ffc-b3f3-4826-a00b-c0137276d685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110585529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3110585529
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.940005991
Short name T350
Test name
Test status
Simulation time 51888769561 ps
CPU time 108.87 seconds
Started Apr 16 02:53:26 PM PDT 24
Finished Apr 16 02:55:16 PM PDT 24
Peak memory 249412 kb
Host smart-ac401e08-8595-4443-89fd-9d8d1c7b2fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940005991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.940005991
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.418815372
Short name T328
Test name
Test status
Simulation time 1507074472 ps
CPU time 7.93 seconds
Started Apr 16 02:53:27 PM PDT 24
Finished Apr 16 02:53:36 PM PDT 24
Peak memory 219316 kb
Host smart-28827fc2-2ca3-42c5-a82f-f2edfc836053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418815372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.418815372
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1808386011
Short name T113
Test name
Test status
Simulation time 8177379167 ps
CPU time 68.34 seconds
Started Apr 16 02:53:28 PM PDT 24
Finished Apr 16 02:54:38 PM PDT 24
Peak memory 240420 kb
Host smart-2047efc3-3e3c-4f55-83e0-c307ccadb5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808386011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1808386011
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1625102539
Short name T146
Test name
Test status
Simulation time 369803904 ps
CPU time 3.63 seconds
Started Apr 16 02:53:28 PM PDT 24
Finished Apr 16 02:53:32 PM PDT 24
Peak memory 222412 kb
Host smart-82e180e4-53e9-470c-9eed-00897ec4a687
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1625102539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1625102539
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3996187214
Short name T740
Test name
Test status
Simulation time 33834186 ps
CPU time 0.96 seconds
Started Apr 16 02:53:28 PM PDT 24
Finished Apr 16 02:53:30 PM PDT 24
Peak memory 207284 kb
Host smart-5fc2d8ab-8045-4dfa-95ed-0db705762434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996187214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3996187214
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.280297454
Short name T708
Test name
Test status
Simulation time 2088221464 ps
CPU time 7.76 seconds
Started Apr 16 02:53:21 PM PDT 24
Finished Apr 16 02:53:30 PM PDT 24
Peak memory 216588 kb
Host smart-a563394d-1d69-46a7-b250-414d859f56e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280297454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.280297454
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3607957343
Short name T557
Test name
Test status
Simulation time 19278145 ps
CPU time 0.85 seconds
Started Apr 16 02:53:20 PM PDT 24
Finished Apr 16 02:53:22 PM PDT 24
Peak memory 205784 kb
Host smart-0abb0c1e-222e-4999-850b-de7e7d63e398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607957343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3607957343
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.566408836
Short name T412
Test name
Test status
Simulation time 98484604 ps
CPU time 0.78 seconds
Started Apr 16 02:53:23 PM PDT 24
Finished Apr 16 02:53:24 PM PDT 24
Peak memory 205844 kb
Host smart-9d5e2391-120d-4372-8a27-0c6b5b9ad2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566408836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.566408836
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3150474612
Short name T695
Test name
Test status
Simulation time 13413488 ps
CPU time 0.72 seconds
Started Apr 16 02:53:33 PM PDT 24
Finished Apr 16 02:53:35 PM PDT 24
Peak memory 205372 kb
Host smart-3bb0ba9f-0bfe-4da4-b216-9104c5af5ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150474612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3150474612
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1521307945
Short name T438
Test name
Test status
Simulation time 15914642 ps
CPU time 0.74 seconds
Started Apr 16 02:53:25 PM PDT 24
Finished Apr 16 02:53:27 PM PDT 24
Peak memory 205948 kb
Host smart-4504c2c1-4f5b-42cc-a83f-67f0f9a55610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521307945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1521307945
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3599376883
Short name T312
Test name
Test status
Simulation time 2698924338 ps
CPU time 14.54 seconds
Started Apr 16 02:53:33 PM PDT 24
Finished Apr 16 02:53:49 PM PDT 24
Peak memory 222580 kb
Host smart-05db9690-38a1-4f30-9d32-8a3a25154c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599376883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3599376883
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.269822901
Short name T74
Test name
Test status
Simulation time 42655815 ps
CPU time 2.62 seconds
Started Apr 16 02:53:31 PM PDT 24
Finished Apr 16 02:53:35 PM PDT 24
Peak memory 223200 kb
Host smart-2bba6ff1-4f4d-478a-b736-1d9ca6b81a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269822901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.269822901
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3308848715
Short name T668
Test name
Test status
Simulation time 3327234415 ps
CPU time 10.06 seconds
Started Apr 16 02:53:31 PM PDT 24
Finished Apr 16 02:53:42 PM PDT 24
Peak memory 223128 kb
Host smart-ff5d5c5e-9e83-4ddc-b5d9-00fefeb7ee79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3308848715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3308848715
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3449776965
Short name T720
Test name
Test status
Simulation time 8544192006 ps
CPU time 19.16 seconds
Started Apr 16 02:53:33 PM PDT 24
Finished Apr 16 02:53:54 PM PDT 24
Peak memory 216532 kb
Host smart-25288025-9fbd-4c80-9c3a-f733f7968388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449776965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3449776965
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2675013840
Short name T20
Test name
Test status
Simulation time 7696950222 ps
CPU time 15.08 seconds
Started Apr 16 02:53:29 PM PDT 24
Finished Apr 16 02:53:45 PM PDT 24
Peak memory 216608 kb
Host smart-9e222a73-7e7b-46fb-b64c-77b8affe97bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675013840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2675013840
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3905055994
Short name T509
Test name
Test status
Simulation time 34628967 ps
CPU time 1.24 seconds
Started Apr 16 02:53:28 PM PDT 24
Finished Apr 16 02:53:31 PM PDT 24
Peak memory 216484 kb
Host smart-29484e87-abe1-41d2-9daa-895361e4578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905055994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3905055994
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.806926307
Short name T455
Test name
Test status
Simulation time 323157461 ps
CPU time 1.24 seconds
Started Apr 16 02:53:29 PM PDT 24
Finished Apr 16 02:53:31 PM PDT 24
Peak memory 206892 kb
Host smart-ecaad62d-eb9f-4b54-abf1-2e3bea0db4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806926307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.806926307
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2814105069
Short name T324
Test name
Test status
Simulation time 19014700839 ps
CPU time 12.74 seconds
Started Apr 16 02:53:24 PM PDT 24
Finished Apr 16 02:53:38 PM PDT 24
Peak memory 217772 kb
Host smart-24802db6-4d6e-4ca0-8188-a0fe4101f856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814105069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2814105069
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2555026988
Short name T35
Test name
Test status
Simulation time 62543487 ps
CPU time 0.71 seconds
Started Apr 16 02:53:34 PM PDT 24
Finished Apr 16 02:53:36 PM PDT 24
Peak memory 205716 kb
Host smart-91ca04b9-829f-4eac-bc07-a23087543b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555026988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2555026988
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1150408845
Short name T550
Test name
Test status
Simulation time 186422406 ps
CPU time 3.93 seconds
Started Apr 16 02:53:32 PM PDT 24
Finished Apr 16 02:53:38 PM PDT 24
Peak memory 223296 kb
Host smart-fb5e9303-dd68-46e5-835e-69b08886f718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150408845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1150408845
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2406832569
Short name T570
Test name
Test status
Simulation time 40272688 ps
CPU time 0.79 seconds
Started Apr 16 02:53:34 PM PDT 24
Finished Apr 16 02:53:36 PM PDT 24
Peak memory 206568 kb
Host smart-28764e62-0ec6-4306-b0b1-c1fde1634c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406832569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2406832569
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3029305006
Short name T318
Test name
Test status
Simulation time 13181122426 ps
CPU time 24.51 seconds
Started Apr 16 02:53:31 PM PDT 24
Finished Apr 16 02:53:56 PM PDT 24
Peak memory 224240 kb
Host smart-44cf7c68-cc68-4845-9b31-a80ac4a2e703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029305006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3029305006
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3770501573
Short name T186
Test name
Test status
Simulation time 271283160 ps
CPU time 3.93 seconds
Started Apr 16 02:53:35 PM PDT 24
Finished Apr 16 02:53:41 PM PDT 24
Peak memory 224708 kb
Host smart-d208f175-8092-4247-9345-61ebbfcb257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770501573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3770501573
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.863437988
Short name T686
Test name
Test status
Simulation time 130021216 ps
CPU time 4.29 seconds
Started Apr 16 02:53:35 PM PDT 24
Finished Apr 16 02:53:41 PM PDT 24
Peak memory 220460 kb
Host smart-0673f483-439a-4786-9305-cca572fa696f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=863437988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.863437988
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.957628905
Short name T397
Test name
Test status
Simulation time 10227778221 ps
CPU time 28.58 seconds
Started Apr 16 02:53:37 PM PDT 24
Finished Apr 16 02:54:07 PM PDT 24
Peak memory 216616 kb
Host smart-3ae54f57-8072-4eb0-8cce-62efca635f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957628905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.957628905
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1096057938
Short name T441
Test name
Test status
Simulation time 1218485997 ps
CPU time 4.73 seconds
Started Apr 16 02:53:31 PM PDT 24
Finished Apr 16 02:53:37 PM PDT 24
Peak memory 209076 kb
Host smart-4a78b2a8-e802-47ee-b475-ab65d2f15f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096057938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1096057938
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.282239730
Short name T474
Test name
Test status
Simulation time 559606554 ps
CPU time 1.72 seconds
Started Apr 16 02:53:31 PM PDT 24
Finished Apr 16 02:53:34 PM PDT 24
Peak memory 216596 kb
Host smart-fd3157a9-5f70-4a47-9f14-9bc0fe6f3307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282239730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.282239730
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2622855952
Short name T100
Test name
Test status
Simulation time 45635674 ps
CPU time 0.73 seconds
Started Apr 16 02:53:37 PM PDT 24
Finished Apr 16 02:53:40 PM PDT 24
Peak memory 205840 kb
Host smart-d29e8a42-a4ab-49e2-b493-c35c196ff143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622855952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2622855952
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1465092948
Short name T233
Test name
Test status
Simulation time 8882100630 ps
CPU time 9.73 seconds
Started Apr 16 02:53:30 PM PDT 24
Finished Apr 16 02:53:41 PM PDT 24
Peak memory 233004 kb
Host smart-56db645c-b2b3-4bb8-a1f9-d4c75c62d385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465092948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1465092948
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2736965101
Short name T735
Test name
Test status
Simulation time 54175004 ps
CPU time 0.69 seconds
Started Apr 16 02:52:20 PM PDT 24
Finished Apr 16 02:52:22 PM PDT 24
Peak memory 205376 kb
Host smart-2acd5881-9032-4f80-afef-f7573ff11d3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736965101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
736965101
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2852535255
Short name T638
Test name
Test status
Simulation time 18937442 ps
CPU time 0.8 seconds
Started Apr 16 02:52:11 PM PDT 24
Finished Apr 16 02:52:12 PM PDT 24
Peak memory 206928 kb
Host smart-77bbee86-3afa-4a22-bb6b-dbc13b17ebfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852535255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2852535255
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1486361945
Short name T296
Test name
Test status
Simulation time 308146935 ps
CPU time 8.03 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:31 PM PDT 24
Peak memory 232900 kb
Host smart-d69f94b1-7b3c-453b-ab86-a65c7d7b0319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486361945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1486361945
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1478772529
Short name T528
Test name
Test status
Simulation time 136915872 ps
CPU time 4.39 seconds
Started Apr 16 02:52:14 PM PDT 24
Finished Apr 16 02:52:20 PM PDT 24
Peak memory 224728 kb
Host smart-2ba99331-adf0-4955-b063-c10dd3b54fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478772529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1478772529
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.4165005619
Short name T661
Test name
Test status
Simulation time 131622549 ps
CPU time 1.12 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:52:26 PM PDT 24
Peak memory 216960 kb
Host smart-0947a3eb-ea2f-467b-8445-b44fd99ddf8f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165005619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.4165005619
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.946150122
Short name T340
Test name
Test status
Simulation time 1048939170 ps
CPU time 3.76 seconds
Started Apr 16 02:52:24 PM PDT 24
Finished Apr 16 02:52:30 PM PDT 24
Peak memory 222316 kb
Host smart-db661bb9-6e9e-45f7-9fb3-5775238a82aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946150122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
946150122
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1849487678
Short name T319
Test name
Test status
Simulation time 13596415789 ps
CPU time 11.22 seconds
Started Apr 16 02:52:20 PM PDT 24
Finished Apr 16 02:52:33 PM PDT 24
Peak memory 236656 kb
Host smart-4876e264-0208-4be5-87c8-f64f81e55196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849487678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1849487678
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3742366213
Short name T672
Test name
Test status
Simulation time 3732720326 ps
CPU time 10.25 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:31 PM PDT 24
Peak memory 219272 kb
Host smart-3bee74b6-677e-4e27-9c74-6fd3398c88be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742366213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3742366213
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1966249401
Short name T50
Test name
Test status
Simulation time 342030198 ps
CPU time 1.13 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:25 PM PDT 24
Peak memory 235444 kb
Host smart-02947102-9b42-4b45-b1f3-3fbb28128011
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966249401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1966249401
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.93276199
Short name T382
Test name
Test status
Simulation time 19198661280 ps
CPU time 29.46 seconds
Started Apr 16 02:52:17 PM PDT 24
Finished Apr 16 02:52:48 PM PDT 24
Peak memory 220820 kb
Host smart-835987e3-a6f1-4124-8734-90680f4f0862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93276199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.93276199
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2524576347
Short name T675
Test name
Test status
Simulation time 2732696351 ps
CPU time 8.98 seconds
Started Apr 16 02:52:17 PM PDT 24
Finished Apr 16 02:52:27 PM PDT 24
Peak memory 216636 kb
Host smart-9a3948b4-52fe-4ef7-b68e-11f746e3749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524576347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2524576347
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1921215655
Short name T694
Test name
Test status
Simulation time 142235035 ps
CPU time 1.66 seconds
Started Apr 16 02:52:25 PM PDT 24
Finished Apr 16 02:52:28 PM PDT 24
Peak memory 216812 kb
Host smart-e013456a-037b-4f21-9d9a-2f7c0526d1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921215655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1921215655
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2334335937
Short name T522
Test name
Test status
Simulation time 295429631 ps
CPU time 0.94 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:24 PM PDT 24
Peak memory 206852 kb
Host smart-ee47f4ec-005d-4a6f-9eba-8d431192433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334335937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2334335937
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3560878400
Short name T697
Test name
Test status
Simulation time 14877158 ps
CPU time 0.79 seconds
Started Apr 16 02:53:42 PM PDT 24
Finished Apr 16 02:53:44 PM PDT 24
Peak memory 204832 kb
Host smart-53b62f61-0ae0-4df5-b1a2-9a0871b24dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560878400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3560878400
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1884532943
Short name T408
Test name
Test status
Simulation time 21275456 ps
CPU time 0.75 seconds
Started Apr 16 02:53:33 PM PDT 24
Finished Apr 16 02:53:36 PM PDT 24
Peak memory 206648 kb
Host smart-d9ac1f24-798f-47de-a93f-5bd900927950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884532943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1884532943
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1640672015
Short name T636
Test name
Test status
Simulation time 14512033832 ps
CPU time 50.09 seconds
Started Apr 16 02:53:32 PM PDT 24
Finished Apr 16 02:54:23 PM PDT 24
Peak memory 233020 kb
Host smart-e780e495-8c19-4cfc-a1a3-5151c834ad19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640672015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1640672015
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.338955615
Short name T91
Test name
Test status
Simulation time 877786953 ps
CPU time 9.02 seconds
Started Apr 16 02:53:32 PM PDT 24
Finished Apr 16 02:53:43 PM PDT 24
Peak memory 218892 kb
Host smart-6246ec6e-139b-49f6-8b15-20524fdbe58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338955615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.338955615
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2094517255
Short name T62
Test name
Test status
Simulation time 17291944135 ps
CPU time 16.18 seconds
Started Apr 16 02:53:36 PM PDT 24
Finished Apr 16 02:53:54 PM PDT 24
Peak memory 224808 kb
Host smart-d7746375-8215-4c4c-9b7a-3ece011db81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094517255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2094517255
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2986980013
Short name T452
Test name
Test status
Simulation time 2274863178 ps
CPU time 16.56 seconds
Started Apr 16 02:53:35 PM PDT 24
Finished Apr 16 02:53:53 PM PDT 24
Peak memory 220692 kb
Host smart-893e72dc-36aa-4470-8d4a-9b7eb571af4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2986980013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2986980013
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4090152317
Short name T676
Test name
Test status
Simulation time 6715209206 ps
CPU time 42.59 seconds
Started Apr 16 02:53:31 PM PDT 24
Finished Apr 16 02:54:15 PM PDT 24
Peak memory 216544 kb
Host smart-8a58bcf0-a3d8-4912-891c-8fefff75e38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090152317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4090152317
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.312441757
Short name T18
Test name
Test status
Simulation time 8148949088 ps
CPU time 3.57 seconds
Started Apr 16 02:53:33 PM PDT 24
Finished Apr 16 02:53:38 PM PDT 24
Peak memory 216632 kb
Host smart-73494e17-619e-4516-9fd6-196c847c65fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312441757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.312441757
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.298635957
Short name T615
Test name
Test status
Simulation time 135795249 ps
CPU time 1.1 seconds
Started Apr 16 02:53:34 PM PDT 24
Finished Apr 16 02:53:37 PM PDT 24
Peak memory 207900 kb
Host smart-a05bbffa-b7dd-487d-b775-e4ba149e0e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298635957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.298635957
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1725761593
Short name T575
Test name
Test status
Simulation time 16035442 ps
CPU time 0.72 seconds
Started Apr 16 02:53:32 PM PDT 24
Finished Apr 16 02:53:34 PM PDT 24
Peak memory 205844 kb
Host smart-1070a736-7670-4128-a49d-ecc33b9a69af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725761593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1725761593
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2768634862
Short name T442
Test name
Test status
Simulation time 48871021 ps
CPU time 0.74 seconds
Started Apr 16 02:53:35 PM PDT 24
Finished Apr 16 02:53:38 PM PDT 24
Peak memory 205404 kb
Host smart-6dda25b6-5d4c-4183-9069-c2486a47c75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768634862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2768634862
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3612238912
Short name T660
Test name
Test status
Simulation time 146408312 ps
CPU time 0.77 seconds
Started Apr 16 02:53:38 PM PDT 24
Finished Apr 16 02:53:40 PM PDT 24
Peak memory 206648 kb
Host smart-c42290de-1e4b-4bec-817c-fe85f5190a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612238912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3612238912
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1371113056
Short name T731
Test name
Test status
Simulation time 1682297888 ps
CPU time 13.78 seconds
Started Apr 16 02:53:38 PM PDT 24
Finished Apr 16 02:53:53 PM PDT 24
Peak memory 250212 kb
Host smart-c9e30cdd-866b-4c4f-a391-c65150847862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371113056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1371113056
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2067042563
Short name T327
Test name
Test status
Simulation time 12865246304 ps
CPU time 34.84 seconds
Started Apr 16 02:53:37 PM PDT 24
Finished Apr 16 02:54:13 PM PDT 24
Peak memory 223264 kb
Host smart-6c16d26b-3182-4dfa-834c-c7fbdd19fa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067042563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2067042563
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2748821022
Short name T331
Test name
Test status
Simulation time 23455820546 ps
CPU time 13.07 seconds
Started Apr 16 02:53:45 PM PDT 24
Finished Apr 16 02:53:59 PM PDT 24
Peak memory 223156 kb
Host smart-75d12004-084d-4e06-8025-0ad7a00b4753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748821022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2748821022
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3237865775
Short name T196
Test name
Test status
Simulation time 6117307566 ps
CPU time 8.87 seconds
Started Apr 16 02:53:37 PM PDT 24
Finished Apr 16 02:53:47 PM PDT 24
Peak memory 218692 kb
Host smart-06df9bcf-cf0f-4f36-99dc-372e0a890288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237865775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3237865775
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1950149382
Short name T493
Test name
Test status
Simulation time 211295714 ps
CPU time 4.96 seconds
Started Apr 16 02:53:39 PM PDT 24
Finished Apr 16 02:53:45 PM PDT 24
Peak memory 221824 kb
Host smart-db9e7b6c-5850-43b5-a42a-731c17cd2390
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1950149382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1950149382
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1160075250
Short name T547
Test name
Test status
Simulation time 764881632 ps
CPU time 7.65 seconds
Started Apr 16 02:53:40 PM PDT 24
Finished Apr 16 02:53:49 PM PDT 24
Peak memory 216856 kb
Host smart-afc6f2b0-28f9-4ff0-b87a-bde4f024fbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160075250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1160075250
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1197917018
Short name T505
Test name
Test status
Simulation time 647774545 ps
CPU time 2.05 seconds
Started Apr 16 02:53:37 PM PDT 24
Finished Apr 16 02:53:41 PM PDT 24
Peak memory 216568 kb
Host smart-e95783b1-1fd6-4aec-ba24-aa0d0e9f4ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197917018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1197917018
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1845482129
Short name T393
Test name
Test status
Simulation time 973229306 ps
CPU time 9.5 seconds
Started Apr 16 02:53:38 PM PDT 24
Finished Apr 16 02:53:49 PM PDT 24
Peak memory 216768 kb
Host smart-0a34824a-f528-485f-9f84-d118c034b0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845482129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1845482129
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3375308624
Short name T491
Test name
Test status
Simulation time 405176471 ps
CPU time 1.01 seconds
Started Apr 16 02:53:38 PM PDT 24
Finished Apr 16 02:53:40 PM PDT 24
Peak memory 206892 kb
Host smart-e3724ae9-6d97-4186-8836-09559aaacb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375308624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3375308624
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1375128518
Short name T309
Test name
Test status
Simulation time 8693201638 ps
CPU time 26.44 seconds
Started Apr 16 02:53:35 PM PDT 24
Finished Apr 16 02:54:04 PM PDT 24
Peak memory 237864 kb
Host smart-db04539a-7178-4527-b432-2aa491e706fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375128518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1375128518
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3873153606
Short name T563
Test name
Test status
Simulation time 20124709 ps
CPU time 0.74 seconds
Started Apr 16 02:53:41 PM PDT 24
Finished Apr 16 02:53:43 PM PDT 24
Peak memory 205404 kb
Host smart-3b38ab1e-3b48-41d3-a6a3-b9ac4a279920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873153606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3873153606
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3239624659
Short name T315
Test name
Test status
Simulation time 287830369 ps
CPU time 2.29 seconds
Started Apr 16 02:53:43 PM PDT 24
Finished Apr 16 02:53:47 PM PDT 24
Peak memory 218764 kb
Host smart-a0b9f16e-a642-48fe-8f18-0b44d3e9cfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239624659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3239624659
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3702463331
Short name T424
Test name
Test status
Simulation time 37587296 ps
CPU time 0.77 seconds
Started Apr 16 02:53:39 PM PDT 24
Finished Apr 16 02:53:41 PM PDT 24
Peak memory 206656 kb
Host smart-549c92a2-cec7-4c0a-9a19-180fe5913b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702463331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3702463331
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2721377911
Short name T544
Test name
Test status
Simulation time 6194917650 ps
CPU time 95.98 seconds
Started Apr 16 02:53:42 PM PDT 24
Finished Apr 16 02:55:20 PM PDT 24
Peak memory 232972 kb
Host smart-89c89526-c0fc-4bfb-89cb-1b2bba407d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721377911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2721377911
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1700846329
Short name T90
Test name
Test status
Simulation time 1369705755 ps
CPU time 7.63 seconds
Started Apr 16 02:53:42 PM PDT 24
Finished Apr 16 02:53:51 PM PDT 24
Peak memory 232908 kb
Host smart-7a5d7036-ddcf-47e1-8033-fbeef3507bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700846329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1700846329
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3487974341
Short name T254
Test name
Test status
Simulation time 658990488 ps
CPU time 3.64 seconds
Started Apr 16 02:53:36 PM PDT 24
Finished Apr 16 02:53:42 PM PDT 24
Peak memory 219064 kb
Host smart-912448a6-aaf2-42db-9859-281485da236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487974341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3487974341
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2854496945
Short name T247
Test name
Test status
Simulation time 963528604 ps
CPU time 6.31 seconds
Started Apr 16 02:53:35 PM PDT 24
Finished Apr 16 02:53:43 PM PDT 24
Peak memory 218992 kb
Host smart-90ed8674-b304-4782-95cc-788abee72033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854496945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2854496945
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1628404466
Short name T461
Test name
Test status
Simulation time 2903210449 ps
CPU time 14.64 seconds
Started Apr 16 02:53:40 PM PDT 24
Finished Apr 16 02:53:56 PM PDT 24
Peak memory 218896 kb
Host smart-91ed4c1f-14ef-4305-a51b-d2633f3847cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1628404466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1628404466
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.404660656
Short name T484
Test name
Test status
Simulation time 147407840 ps
CPU time 1 seconds
Started Apr 16 02:53:41 PM PDT 24
Finished Apr 16 02:53:44 PM PDT 24
Peak memory 206920 kb
Host smart-80d2da77-d712-4850-9696-2cf6e8437211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404660656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.404660656
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3442490619
Short name T158
Test name
Test status
Simulation time 2193594223 ps
CPU time 21.32 seconds
Started Apr 16 02:53:37 PM PDT 24
Finished Apr 16 02:54:00 PM PDT 24
Peak memory 216656 kb
Host smart-49416768-7b47-4131-bd45-e6b61e81e0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442490619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3442490619
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.686986660
Short name T576
Test name
Test status
Simulation time 3401984299 ps
CPU time 8.51 seconds
Started Apr 16 02:53:38 PM PDT 24
Finished Apr 16 02:53:48 PM PDT 24
Peak memory 216656 kb
Host smart-08609e9c-1c1f-4657-9a56-e6e0c6f2bd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686986660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.686986660
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1919796792
Short name T508
Test name
Test status
Simulation time 731568628 ps
CPU time 3.3 seconds
Started Apr 16 02:53:38 PM PDT 24
Finished Apr 16 02:53:43 PM PDT 24
Peak memory 216568 kb
Host smart-ed4184d4-db7a-4ccc-9204-f1eecdddffe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919796792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1919796792
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.655813205
Short name T734
Test name
Test status
Simulation time 566047027 ps
CPU time 0.91 seconds
Started Apr 16 02:53:37 PM PDT 24
Finished Apr 16 02:53:40 PM PDT 24
Peak memory 205864 kb
Host smart-ce10271b-a4e8-42e6-ac3a-53a496d99590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655813205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.655813205
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.52914497
Short name T480
Test name
Test status
Simulation time 26955070 ps
CPU time 0.72 seconds
Started Apr 16 02:53:48 PM PDT 24
Finished Apr 16 02:53:50 PM PDT 24
Peak memory 205768 kb
Host smart-5c776eab-c4a0-43e7-a7df-df6664325f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52914497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.52914497
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3057662703
Short name T448
Test name
Test status
Simulation time 138406541 ps
CPU time 3.47 seconds
Started Apr 16 02:53:41 PM PDT 24
Finished Apr 16 02:53:45 PM PDT 24
Peak memory 217108 kb
Host smart-c90eb3c8-216c-4f7f-b63a-ce438538c803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057662703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3057662703
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1648448394
Short name T608
Test name
Test status
Simulation time 15508100 ps
CPU time 0.79 seconds
Started Apr 16 02:53:43 PM PDT 24
Finished Apr 16 02:53:45 PM PDT 24
Peak memory 206648 kb
Host smart-9994e47e-4d8b-45a2-b97a-6d00b6b8e3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648448394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1648448394
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4015115414
Short name T107
Test name
Test status
Simulation time 9651148661 ps
CPU time 40.66 seconds
Started Apr 16 02:53:44 PM PDT 24
Finished Apr 16 02:54:26 PM PDT 24
Peak memory 219136 kb
Host smart-a761afa5-10b3-4c81-a3fa-f6311738b64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015115414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4015115414
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.376363637
Short name T429
Test name
Test status
Simulation time 900480123 ps
CPU time 4.13 seconds
Started Apr 16 02:53:41 PM PDT 24
Finished Apr 16 02:53:47 PM PDT 24
Peak memory 220332 kb
Host smart-76b088cb-175e-40b7-a094-2c17d315bbe9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=376363637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.376363637
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2867334039
Short name T356
Test name
Test status
Simulation time 492654252 ps
CPU time 0.96 seconds
Started Apr 16 02:53:44 PM PDT 24
Finished Apr 16 02:53:47 PM PDT 24
Peak memory 206968 kb
Host smart-7d9d3c88-c094-43f7-b353-cf00128c2f79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867334039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2867334039
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1410786971
Short name T632
Test name
Test status
Simulation time 7023768887 ps
CPU time 23.9 seconds
Started Apr 16 02:53:41 PM PDT 24
Finished Apr 16 02:54:06 PM PDT 24
Peak memory 220512 kb
Host smart-eb1811dd-254c-47de-874d-4b688587fbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410786971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1410786971
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3742321597
Short name T21
Test name
Test status
Simulation time 71515133 ps
CPU time 1.28 seconds
Started Apr 16 02:53:40 PM PDT 24
Finished Apr 16 02:53:42 PM PDT 24
Peak memory 208124 kb
Host smart-49db1c8c-1acb-4fe4-a2f3-869720201df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742321597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3742321597
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3361929911
Short name T628
Test name
Test status
Simulation time 53260152 ps
CPU time 2.34 seconds
Started Apr 16 02:53:42 PM PDT 24
Finished Apr 16 02:53:46 PM PDT 24
Peak memory 216640 kb
Host smart-1a1cdbc3-353b-484f-b237-872f6f67d6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361929911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3361929911
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3511254855
Short name T627
Test name
Test status
Simulation time 357049491 ps
CPU time 0.91 seconds
Started Apr 16 02:53:39 PM PDT 24
Finished Apr 16 02:53:41 PM PDT 24
Peak memory 205828 kb
Host smart-495093ab-7bae-4852-b839-913b479c334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511254855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3511254855
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2694454028
Short name T419
Test name
Test status
Simulation time 11736469 ps
CPU time 0.68 seconds
Started Apr 16 02:53:52 PM PDT 24
Finished Apr 16 02:53:53 PM PDT 24
Peak memory 205372 kb
Host smart-f6cda050-14b5-489b-9088-f59ba9e7751a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694454028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2694454028
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3963917725
Short name T307
Test name
Test status
Simulation time 7448914015 ps
CPU time 24.49 seconds
Started Apr 16 02:53:46 PM PDT 24
Finished Apr 16 02:54:12 PM PDT 24
Peak memory 218836 kb
Host smart-9884bca5-fc34-494b-8796-83941230599e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963917725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3963917725
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.707735242
Short name T650
Test name
Test status
Simulation time 51589971 ps
CPU time 0.75 seconds
Started Apr 16 02:53:44 PM PDT 24
Finished Apr 16 02:53:46 PM PDT 24
Peak memory 206928 kb
Host smart-2d29b72a-b840-4ff7-8dec-6dafff8b4d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707735242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.707735242
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2152265222
Short name T291
Test name
Test status
Simulation time 15457759494 ps
CPU time 64.17 seconds
Started Apr 16 02:53:47 PM PDT 24
Finished Apr 16 02:54:53 PM PDT 24
Peak memory 241216 kb
Host smart-3a419b1c-fff4-465e-a24b-905314353924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152265222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2152265222
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1602525688
Short name T188
Test name
Test status
Simulation time 535380513 ps
CPU time 4.06 seconds
Started Apr 16 02:53:54 PM PDT 24
Finished Apr 16 02:53:59 PM PDT 24
Peak memory 224720 kb
Host smart-a5cfbf2b-3c4c-4e79-ac09-f833e11eb9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602525688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1602525688
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1505580275
Short name T172
Test name
Test status
Simulation time 227193255 ps
CPU time 3.95 seconds
Started Apr 16 02:53:50 PM PDT 24
Finished Apr 16 02:53:54 PM PDT 24
Peak memory 216836 kb
Host smart-eb8aaf1b-4487-42ec-9ba4-63251b50e70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505580275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1505580275
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3458329482
Short name T257
Test name
Test status
Simulation time 25989249012 ps
CPU time 15.16 seconds
Started Apr 16 02:53:49 PM PDT 24
Finished Apr 16 02:54:05 PM PDT 24
Peak memory 222136 kb
Host smart-ff6e8ccd-086d-4add-af85-c0f7b8623238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458329482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3458329482
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2378169675
Short name T586
Test name
Test status
Simulation time 133046767 ps
CPU time 3.64 seconds
Started Apr 16 02:53:45 PM PDT 24
Finished Apr 16 02:53:50 PM PDT 24
Peak memory 222940 kb
Host smart-93141664-e5a3-48fe-89bf-f2083c47c08f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2378169675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2378169675
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1902804242
Short name T514
Test name
Test status
Simulation time 54346065 ps
CPU time 1.05 seconds
Started Apr 16 02:53:42 PM PDT 24
Finished Apr 16 02:53:45 PM PDT 24
Peak memory 207216 kb
Host smart-28222d1b-b2c8-4c7a-8a26-e88de5c05057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902804242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1902804242
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2283776884
Short name T398
Test name
Test status
Simulation time 2372173764 ps
CPU time 6.38 seconds
Started Apr 16 02:53:52 PM PDT 24
Finished Apr 16 02:53:59 PM PDT 24
Peak memory 216636 kb
Host smart-6b6bc1dd-a052-4b8a-93a5-4c591ea9b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283776884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2283776884
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3941222968
Short name T473
Test name
Test status
Simulation time 12207549598 ps
CPU time 18.63 seconds
Started Apr 16 02:53:47 PM PDT 24
Finished Apr 16 02:54:07 PM PDT 24
Peak memory 216612 kb
Host smart-463bd465-480f-4da7-9d78-be5b3d0e2fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941222968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3941222968
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.383903604
Short name T625
Test name
Test status
Simulation time 23757615 ps
CPU time 1.43 seconds
Started Apr 16 02:53:46 PM PDT 24
Finished Apr 16 02:53:48 PM PDT 24
Peak memory 216504 kb
Host smart-de0356ba-dfc5-4d99-8952-62da5273b3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383903604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.383903604
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2485900290
Short name T475
Test name
Test status
Simulation time 75191064 ps
CPU time 0.79 seconds
Started Apr 16 02:53:47 PM PDT 24
Finished Apr 16 02:53:49 PM PDT 24
Peak memory 205876 kb
Host smart-ffe26be4-ce4a-4c48-8792-6c59bcbcda3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485900290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2485900290
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.109786467
Short name T54
Test name
Test status
Simulation time 34543439 ps
CPU time 0.73 seconds
Started Apr 16 02:53:53 PM PDT 24
Finished Apr 16 02:53:55 PM PDT 24
Peak memory 205748 kb
Host smart-eb4f28e6-7ad9-4274-ac24-d8f962061377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109786467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.109786467
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3047471367
Short name T633
Test name
Test status
Simulation time 32828211 ps
CPU time 0.72 seconds
Started Apr 16 02:53:48 PM PDT 24
Finished Apr 16 02:53:50 PM PDT 24
Peak memory 205580 kb
Host smart-3cba358e-fd8d-4bc8-b5fb-922ff44a9cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047471367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3047471367
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_intercept.16707011
Short name T225
Test name
Test status
Simulation time 3654314427 ps
CPU time 17.46 seconds
Started Apr 16 02:53:46 PM PDT 24
Finished Apr 16 02:54:05 PM PDT 24
Peak memory 224116 kb
Host smart-3a0f9f14-4c0c-4d71-8acf-a281c3e07dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16707011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.16707011
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1775346754
Short name T248
Test name
Test status
Simulation time 446156127 ps
CPU time 3.86 seconds
Started Apr 16 02:53:48 PM PDT 24
Finished Apr 16 02:53:53 PM PDT 24
Peak memory 222824 kb
Host smart-56b72d8a-c950-459f-8f1c-3a49f1573d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775346754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1775346754
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.396882047
Short name T79
Test name
Test status
Simulation time 14107628494 ps
CPU time 19.93 seconds
Started Apr 16 02:53:47 PM PDT 24
Finished Apr 16 02:54:08 PM PDT 24
Peak memory 226492 kb
Host smart-285b6014-6ae5-4e08-aa65-6e0a85375452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396882047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.396882047
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2692700191
Short name T702
Test name
Test status
Simulation time 264569617 ps
CPU time 6.42 seconds
Started Apr 16 02:53:52 PM PDT 24
Finished Apr 16 02:53:59 PM PDT 24
Peak memory 222924 kb
Host smart-64455764-14a2-49b2-bce6-2fafbd638aa5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2692700191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2692700191
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1590088807
Short name T610
Test name
Test status
Simulation time 84617505 ps
CPU time 1.11 seconds
Started Apr 16 02:53:48 PM PDT 24
Finished Apr 16 02:53:50 PM PDT 24
Peak memory 206760 kb
Host smart-0a0459f8-f06e-4efe-8fea-1689d10ca8b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590088807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1590088807
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1864696956
Short name T540
Test name
Test status
Simulation time 1229499084 ps
CPU time 6.67 seconds
Started Apr 16 02:53:47 PM PDT 24
Finished Apr 16 02:53:55 PM PDT 24
Peak memory 216524 kb
Host smart-5beb7f08-7c94-4141-b346-0192d46741d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864696956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1864696956
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1320972106
Short name T58
Test name
Test status
Simulation time 511289258 ps
CPU time 6.44 seconds
Started Apr 16 02:53:46 PM PDT 24
Finished Apr 16 02:53:54 PM PDT 24
Peak memory 216692 kb
Host smart-0d490f91-b53a-407b-8c23-61f7c1be5513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320972106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1320972106
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.262717391
Short name T645
Test name
Test status
Simulation time 86906803 ps
CPU time 0.77 seconds
Started Apr 16 02:53:47 PM PDT 24
Finished Apr 16 02:53:50 PM PDT 24
Peak memory 205916 kb
Host smart-a3edb33f-b625-436e-b29a-f3fb15cda3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262717391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.262717391
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1357247913
Short name T322
Test name
Test status
Simulation time 2216497280 ps
CPU time 10.57 seconds
Started Apr 16 02:53:48 PM PDT 24
Finished Apr 16 02:54:00 PM PDT 24
Peak memory 238184 kb
Host smart-47e1954e-5367-4f85-b5e7-d4ba57e46467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357247913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1357247913
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3757925930
Short name T519
Test name
Test status
Simulation time 45143235 ps
CPU time 0.68 seconds
Started Apr 16 02:53:56 PM PDT 24
Finished Apr 16 02:53:58 PM PDT 24
Peak memory 205424 kb
Host smart-72af0d9a-5e0c-480a-8e48-8d44f4af5937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757925930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3757925930
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.327069357
Short name T719
Test name
Test status
Simulation time 136873952 ps
CPU time 0.82 seconds
Started Apr 16 02:53:53 PM PDT 24
Finished Apr 16 02:53:55 PM PDT 24
Peak memory 206956 kb
Host smart-62eb91ef-9c3f-46a0-95a1-b6359b151fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327069357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.327069357
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3272760380
Short name T346
Test name
Test status
Simulation time 1219844121 ps
CPU time 15.12 seconds
Started Apr 16 02:53:53 PM PDT 24
Finished Apr 16 02:54:09 PM PDT 24
Peak memory 240340 kb
Host smart-b8bc2553-f473-41ad-bafb-48a4a8e51021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272760380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3272760380
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1669867359
Short name T687
Test name
Test status
Simulation time 2909081681 ps
CPU time 13.59 seconds
Started Apr 16 02:53:51 PM PDT 24
Finished Apr 16 02:54:06 PM PDT 24
Peak memory 222868 kb
Host smart-b38cc7e1-716b-40e9-9826-97158df5ee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669867359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1669867359
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1366861184
Short name T305
Test name
Test status
Simulation time 12481311302 ps
CPU time 14.73 seconds
Started Apr 16 02:53:51 PM PDT 24
Finished Apr 16 02:54:07 PM PDT 24
Peak memory 236232 kb
Host smart-e36df6cd-395a-458f-a0ce-5c8583d7c309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366861184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1366861184
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.572394147
Short name T726
Test name
Test status
Simulation time 1387997075 ps
CPU time 12.48 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:54:09 PM PDT 24
Peak memory 222468 kb
Host smart-d1f6b23a-4c9e-47d0-a286-af1de62c8c81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=572394147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.572394147
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2947536452
Short name T43
Test name
Test status
Simulation time 210373068 ps
CPU time 1.07 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:53:57 PM PDT 24
Peak memory 207268 kb
Host smart-f13b8810-f05a-4e19-acc2-5119dd0eb6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947536452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2947536452
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1107668762
Short name T377
Test name
Test status
Simulation time 193519585 ps
CPU time 2.26 seconds
Started Apr 16 02:53:51 PM PDT 24
Finished Apr 16 02:53:54 PM PDT 24
Peak memory 216500 kb
Host smart-bbd73c7c-c60c-44e9-9b61-767c475badbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107668762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1107668762
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2182838357
Short name T503
Test name
Test status
Simulation time 3686369431 ps
CPU time 9.4 seconds
Started Apr 16 02:53:56 PM PDT 24
Finished Apr 16 02:54:07 PM PDT 24
Peak memory 216576 kb
Host smart-55037bd0-3900-4b46-89dd-2d12fee47507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182838357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2182838357
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4083480268
Short name T428
Test name
Test status
Simulation time 36962475 ps
CPU time 0.79 seconds
Started Apr 16 02:53:50 PM PDT 24
Finished Apr 16 02:53:51 PM PDT 24
Peak memory 206592 kb
Host smart-82984e8f-9b4b-4103-8664-0e4124ac600c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083480268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4083480268
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2373403256
Short name T423
Test name
Test status
Simulation time 210101547 ps
CPU time 0.91 seconds
Started Apr 16 02:53:51 PM PDT 24
Finished Apr 16 02:53:53 PM PDT 24
Peak memory 206868 kb
Host smart-20e88bdb-b909-4325-a379-bafa9bd94d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373403256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2373403256
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1866149438
Short name T619
Test name
Test status
Simulation time 42599958 ps
CPU time 0.71 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:53:57 PM PDT 24
Peak memory 205388 kb
Host smart-d407561a-671e-4db2-83a5-464840d51a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866149438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1866149438
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1154297610
Short name T271
Test name
Test status
Simulation time 3645649385 ps
CPU time 25.62 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:54:22 PM PDT 24
Peak memory 216856 kb
Host smart-ff27f489-6b86-4957-8416-3ff820e28fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154297610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1154297610
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1321511117
Short name T652
Test name
Test status
Simulation time 15090619 ps
CPU time 0.79 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:53:58 PM PDT 24
Peak memory 206660 kb
Host smart-9fb60494-c962-44e5-8363-fb94ce2051d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321511117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1321511117
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2349116360
Short name T325
Test name
Test status
Simulation time 16275115175 ps
CPU time 39.4 seconds
Started Apr 16 02:53:54 PM PDT 24
Finished Apr 16 02:54:34 PM PDT 24
Peak memory 233376 kb
Host smart-897f314a-f264-4d50-a5d9-f312af8d3504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349116360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2349116360
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1977997240
Short name T148
Test name
Test status
Simulation time 3236758087 ps
CPU time 20.2 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:54:16 PM PDT 24
Peak memory 220596 kb
Host smart-84569be1-ae06-4d3e-8117-16a1b3b9ef03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1977997240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1977997240
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.891275284
Short name T16
Test name
Test status
Simulation time 20630390191 ps
CPU time 12.12 seconds
Started Apr 16 02:53:57 PM PDT 24
Finished Apr 16 02:54:11 PM PDT 24
Peak memory 216708 kb
Host smart-89e47cfd-f4ed-4307-9962-8530613ca0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891275284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.891275284
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3892616803
Short name T737
Test name
Test status
Simulation time 66591463210 ps
CPU time 29.52 seconds
Started Apr 16 02:53:55 PM PDT 24
Finished Apr 16 02:54:26 PM PDT 24
Peak memory 216608 kb
Host smart-0949ed9f-a544-4f4c-b398-2440f2981688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892616803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3892616803
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1271166157
Short name T566
Test name
Test status
Simulation time 84714474 ps
CPU time 1.76 seconds
Started Apr 16 02:53:54 PM PDT 24
Finished Apr 16 02:53:57 PM PDT 24
Peak memory 216576 kb
Host smart-342f85db-73a1-4101-8fac-98a255fd036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271166157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1271166157
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2498451552
Short name T722
Test name
Test status
Simulation time 287594201 ps
CPU time 0.84 seconds
Started Apr 16 02:53:54 PM PDT 24
Finished Apr 16 02:53:56 PM PDT 24
Peak memory 205824 kb
Host smart-f75efd3e-c622-4329-8d1c-058ac33ce140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498451552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2498451552
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1137833728
Short name T584
Test name
Test status
Simulation time 57716931 ps
CPU time 0.71 seconds
Started Apr 16 02:53:57 PM PDT 24
Finished Apr 16 02:53:59 PM PDT 24
Peak memory 205356 kb
Host smart-74837c13-695d-44ca-9a0e-60e878eb1e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137833728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1137833728
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3729474147
Short name T590
Test name
Test status
Simulation time 37755109 ps
CPU time 0.76 seconds
Started Apr 16 02:53:57 PM PDT 24
Finished Apr 16 02:53:59 PM PDT 24
Peak memory 205608 kb
Host smart-821c3a46-9bf5-4760-87f2-4f1c7b63ca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729474147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3729474147
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2143188713
Short name T373
Test name
Test status
Simulation time 45651400586 ps
CPU time 154.43 seconds
Started Apr 16 02:53:58 PM PDT 24
Finished Apr 16 02:56:33 PM PDT 24
Peak memory 265840 kb
Host smart-254087f3-8a1e-4f45-95e9-a4c5f5b33f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143188713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2143188713
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4000892786
Short name T208
Test name
Test status
Simulation time 3767481191 ps
CPU time 8.1 seconds
Started Apr 16 02:54:00 PM PDT 24
Finished Apr 16 02:54:09 PM PDT 24
Peak memory 218808 kb
Host smart-1d112374-7cce-4dc0-a3ec-82a6f1ab4bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000892786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4000892786
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2499858593
Short name T579
Test name
Test status
Simulation time 89311492 ps
CPU time 3.75 seconds
Started Apr 16 02:54:03 PM PDT 24
Finished Apr 16 02:54:07 PM PDT 24
Peak memory 222556 kb
Host smart-e8cb9b0a-b668-4e6e-b6a2-9a0931c9910c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2499858593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2499858593
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4004310497
Short name T153
Test name
Test status
Simulation time 473311745 ps
CPU time 1.03 seconds
Started Apr 16 02:53:56 PM PDT 24
Finished Apr 16 02:53:59 PM PDT 24
Peak memory 207352 kb
Host smart-0cc9e60b-9b95-4533-8da5-eb0c4da2f097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004310497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4004310497
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2039141676
Short name T66
Test name
Test status
Simulation time 1402110946 ps
CPU time 3.12 seconds
Started Apr 16 02:54:03 PM PDT 24
Finished Apr 16 02:54:07 PM PDT 24
Peak memory 216724 kb
Host smart-31329801-6c72-41cc-a8c9-768429372453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039141676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2039141676
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3700933577
Short name T430
Test name
Test status
Simulation time 18576263580 ps
CPU time 24.07 seconds
Started Apr 16 02:53:56 PM PDT 24
Finished Apr 16 02:54:21 PM PDT 24
Peak memory 216568 kb
Host smart-aedca44d-17f7-41e0-bc75-280d0b3b4fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700933577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3700933577
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2342796628
Short name T458
Test name
Test status
Simulation time 40305683 ps
CPU time 0.78 seconds
Started Apr 16 02:53:57 PM PDT 24
Finished Apr 16 02:53:59 PM PDT 24
Peak memory 205828 kb
Host smart-77868a01-beaf-42bf-9c3d-bf28ff524c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342796628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2342796628
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3145379885
Short name T468
Test name
Test status
Simulation time 21547731 ps
CPU time 0.77 seconds
Started Apr 16 02:53:58 PM PDT 24
Finished Apr 16 02:54:00 PM PDT 24
Peak memory 205856 kb
Host smart-79b90093-7eb6-449a-9891-35585725714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145379885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3145379885
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.192607268
Short name T741
Test name
Test status
Simulation time 33298355311 ps
CPU time 25.27 seconds
Started Apr 16 02:54:03 PM PDT 24
Finished Apr 16 02:54:29 PM PDT 24
Peak memory 241028 kb
Host smart-253ce9e7-d809-49e6-99d3-86799a67fa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192607268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.192607268
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.58716849
Short name T721
Test name
Test status
Simulation time 18210323 ps
CPU time 0.74 seconds
Started Apr 16 02:54:05 PM PDT 24
Finished Apr 16 02:54:06 PM PDT 24
Peak memory 205416 kb
Host smart-d920e681-d998-4abc-bdfd-6d3d38f0552d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58716849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.58716849
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3886752082
Short name T648
Test name
Test status
Simulation time 16691191 ps
CPU time 0.83 seconds
Started Apr 16 02:54:00 PM PDT 24
Finished Apr 16 02:54:02 PM PDT 24
Peak memory 206632 kb
Host smart-385ce48f-7e2c-4cb3-a363-c83835cf15d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886752082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3886752082
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4173170183
Short name T9
Test name
Test status
Simulation time 3972881605 ps
CPU time 11.59 seconds
Started Apr 16 02:54:05 PM PDT 24
Finished Apr 16 02:54:17 PM PDT 24
Peak memory 221984 kb
Host smart-bc8396d9-f31c-4185-a359-e08bea810a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173170183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4173170183
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2805738897
Short name T434
Test name
Test status
Simulation time 484307031 ps
CPU time 4.04 seconds
Started Apr 16 02:54:03 PM PDT 24
Finished Apr 16 02:54:08 PM PDT 24
Peak memory 222984 kb
Host smart-60904a11-37e2-4956-a100-ae1fbf51ab26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2805738897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2805738897
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2441149193
Short name T521
Test name
Test status
Simulation time 154199274 ps
CPU time 1.03 seconds
Started Apr 16 02:54:01 PM PDT 24
Finished Apr 16 02:54:03 PM PDT 24
Peak memory 206828 kb
Host smart-e4ad3743-eedc-4a93-af47-9ab8946f61d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441149193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2441149193
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2513318869
Short name T387
Test name
Test status
Simulation time 559395165 ps
CPU time 8.52 seconds
Started Apr 16 02:54:04 PM PDT 24
Finished Apr 16 02:54:14 PM PDT 24
Peak memory 216596 kb
Host smart-0d84d17f-5afa-44ee-985c-7de062e2750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513318869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2513318869
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.728725033
Short name T466
Test name
Test status
Simulation time 4389086555 ps
CPU time 2.58 seconds
Started Apr 16 02:54:04 PM PDT 24
Finished Apr 16 02:54:08 PM PDT 24
Peak memory 208152 kb
Host smart-7878817c-cc35-4f16-9ab9-e2ce4a73f8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728725033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.728725033
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1053685941
Short name T449
Test name
Test status
Simulation time 872059318 ps
CPU time 5.43 seconds
Started Apr 16 02:54:02 PM PDT 24
Finished Apr 16 02:54:08 PM PDT 24
Peak memory 216780 kb
Host smart-436982bb-c9ab-40f7-baa4-c67973b06206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053685941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1053685941
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3191739716
Short name T548
Test name
Test status
Simulation time 293884950 ps
CPU time 0.9 seconds
Started Apr 16 02:54:02 PM PDT 24
Finished Apr 16 02:54:03 PM PDT 24
Peak memory 206880 kb
Host smart-c4b1af60-2f3f-48d7-9d91-109ca24ca565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191739716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3191739716
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2426543260
Short name T640
Test name
Test status
Simulation time 50608892 ps
CPU time 0.72 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:52:26 PM PDT 24
Peak memory 205420 kb
Host smart-f649b6bc-e7a5-4d34-a643-f318e97565c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426543260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
426543260
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2526230996
Short name T612
Test name
Test status
Simulation time 17723145 ps
CPU time 0.75 seconds
Started Apr 16 02:52:17 PM PDT 24
Finished Apr 16 02:52:19 PM PDT 24
Peak memory 205616 kb
Host smart-ce2fb133-fd37-4b2d-9ae0-a2d9f6a61146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526230996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2526230996
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4205005536
Short name T178
Test name
Test status
Simulation time 634502373 ps
CPU time 3.66 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:24 PM PDT 24
Peak memory 222132 kb
Host smart-445e80ce-15ee-42fd-bc3d-72e16b41f2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205005536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4205005536
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.320682987
Short name T174
Test name
Test status
Simulation time 1861148088 ps
CPU time 5.97 seconds
Started Apr 16 02:52:18 PM PDT 24
Finished Apr 16 02:52:25 PM PDT 24
Peak memory 218820 kb
Host smart-cd6e18d1-8c5c-4d04-9d02-7df60c2cf2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320682987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.320682987
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1690348208
Short name T569
Test name
Test status
Simulation time 107754315 ps
CPU time 0.99 seconds
Started Apr 16 02:52:15 PM PDT 24
Finished Apr 16 02:52:18 PM PDT 24
Peak memory 218180 kb
Host smart-24c55e27-b4a6-4d1f-871f-1609eb7ceb77
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690348208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1690348208
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2649693283
Short name T56
Test name
Test status
Simulation time 281577127 ps
CPU time 2.77 seconds
Started Apr 16 02:52:17 PM PDT 24
Finished Apr 16 02:52:22 PM PDT 24
Peak memory 222800 kb
Host smart-56055a9e-1c53-48a6-a408-129383ea044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649693283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2649693283
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3406751974
Short name T199
Test name
Test status
Simulation time 1578982566 ps
CPU time 4.89 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:28 PM PDT 24
Peak memory 222920 kb
Host smart-7eb74fe1-5cbc-4b1d-a9a3-644fdc07cd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406751974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3406751974
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1194043552
Short name T742
Test name
Test status
Simulation time 512995680 ps
CPU time 5.87 seconds
Started Apr 16 02:52:20 PM PDT 24
Finished Apr 16 02:52:28 PM PDT 24
Peak memory 221968 kb
Host smart-b55a8161-2106-4b84-a598-38b86804651a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1194043552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1194043552
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3196270253
Short name T52
Test name
Test status
Simulation time 330870442 ps
CPU time 1.23 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:25 PM PDT 24
Peak memory 235460 kb
Host smart-e12a4e37-b3cc-43ce-81a5-c3068494eb39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196270253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3196270253
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3226920386
Short name T391
Test name
Test status
Simulation time 11484226922 ps
CPU time 64.52 seconds
Started Apr 16 02:52:17 PM PDT 24
Finished Apr 16 02:53:23 PM PDT 24
Peak memory 216624 kb
Host smart-68809d8f-fd34-49d4-a24c-655496404634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226920386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3226920386
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1143018740
Short name T542
Test name
Test status
Simulation time 6508678370 ps
CPU time 9.07 seconds
Started Apr 16 02:52:22 PM PDT 24
Finished Apr 16 02:52:34 PM PDT 24
Peak memory 216540 kb
Host smart-f101ba58-3837-4f47-a258-bb3ff07bb96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143018740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1143018740
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2738663521
Short name T433
Test name
Test status
Simulation time 190932415 ps
CPU time 2.24 seconds
Started Apr 16 02:52:20 PM PDT 24
Finished Apr 16 02:52:24 PM PDT 24
Peak memory 216472 kb
Host smart-21bfc2c0-9b30-4f3f-89ef-662b4063848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738663521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2738663521
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1572633494
Short name T635
Test name
Test status
Simulation time 325752399 ps
CPU time 0.84 seconds
Started Apr 16 02:52:17 PM PDT 24
Finished Apr 16 02:52:20 PM PDT 24
Peak memory 205872 kb
Host smart-970c1bd6-9df8-4c66-93d6-6273a1b67211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572633494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1572633494
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2179838317
Short name T512
Test name
Test status
Simulation time 88518324 ps
CPU time 0.69 seconds
Started Apr 16 02:54:10 PM PDT 24
Finished Apr 16 02:54:12 PM PDT 24
Peak memory 205392 kb
Host smart-6a493366-f74c-4013-bcdc-658fd9983bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179838317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2179838317
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1516989159
Short name T201
Test name
Test status
Simulation time 3290790897 ps
CPU time 32.81 seconds
Started Apr 16 02:54:10 PM PDT 24
Finished Apr 16 02:54:44 PM PDT 24
Peak memory 218696 kb
Host smart-9861bf0c-73f3-47ad-9890-23974f9ffd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516989159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1516989159
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1042831217
Short name T24
Test name
Test status
Simulation time 18429631 ps
CPU time 0.84 seconds
Started Apr 16 02:54:06 PM PDT 24
Finished Apr 16 02:54:07 PM PDT 24
Peak memory 205624 kb
Host smart-ccf81454-0422-4938-8882-fd1c6f1353ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042831217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1042831217
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4173206352
Short name T728
Test name
Test status
Simulation time 48216687847 ps
CPU time 165.7 seconds
Started Apr 16 02:54:12 PM PDT 24
Finished Apr 16 02:56:59 PM PDT 24
Peak memory 265116 kb
Host smart-0711bba9-2f82-4d80-b4c6-79b976d05c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173206352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4173206352
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4093915986
Short name T486
Test name
Test status
Simulation time 1235221249 ps
CPU time 2.3 seconds
Started Apr 16 02:54:11 PM PDT 24
Finished Apr 16 02:54:14 PM PDT 24
Peak memory 217644 kb
Host smart-6309af62-0111-4033-9dc8-df253871e237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093915986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4093915986
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2486212702
Short name T60
Test name
Test status
Simulation time 215365356 ps
CPU time 4.73 seconds
Started Apr 16 02:54:09 PM PDT 24
Finished Apr 16 02:54:15 PM PDT 24
Peak memory 220888 kb
Host smart-4444643c-7c09-4882-87ca-e625f490d780
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2486212702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2486212702
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1511186962
Short name T392
Test name
Test status
Simulation time 12849130868 ps
CPU time 33.36 seconds
Started Apr 16 02:54:08 PM PDT 24
Finished Apr 16 02:54:43 PM PDT 24
Peak memory 216596 kb
Host smart-761d6e84-277b-4e90-ba23-8ec7cf79463b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511186962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1511186962
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.16054010
Short name T607
Test name
Test status
Simulation time 1993739456 ps
CPU time 9.98 seconds
Started Apr 16 02:54:07 PM PDT 24
Finished Apr 16 02:54:18 PM PDT 24
Peak memory 216408 kb
Host smart-bae3837c-1861-4aa3-b91b-9fa8e152c939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16054010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.16054010
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3182151841
Short name T609
Test name
Test status
Simulation time 707530474 ps
CPU time 13.14 seconds
Started Apr 16 02:54:08 PM PDT 24
Finished Apr 16 02:54:23 PM PDT 24
Peak memory 216720 kb
Host smart-03a74193-634c-4f66-8d4f-a2ce36458744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182151841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3182151841
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1827158081
Short name T462
Test name
Test status
Simulation time 505315316 ps
CPU time 1.05 seconds
Started Apr 16 02:54:14 PM PDT 24
Finished Apr 16 02:54:16 PM PDT 24
Peak memory 206864 kb
Host smart-359560ac-454d-4468-bccc-746350715974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827158081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1827158081
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2027155381
Short name T664
Test name
Test status
Simulation time 11704422 ps
CPU time 0.7 seconds
Started Apr 16 02:54:14 PM PDT 24
Finished Apr 16 02:54:16 PM PDT 24
Peak memory 205300 kb
Host smart-7cd5ac35-e4ef-4354-a922-ed8b35c7718f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027155381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2027155381
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3759932135
Short name T88
Test name
Test status
Simulation time 677052545 ps
CPU time 3.38 seconds
Started Apr 16 02:54:06 PM PDT 24
Finished Apr 16 02:54:11 PM PDT 24
Peak memory 223192 kb
Host smart-48ebbe1f-11b1-45f8-858c-ce77d126d9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759932135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3759932135
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.4244107883
Short name T420
Test name
Test status
Simulation time 100352136 ps
CPU time 0.76 seconds
Started Apr 16 02:54:09 PM PDT 24
Finished Apr 16 02:54:11 PM PDT 24
Peak memory 206640 kb
Host smart-2393ab33-af39-407a-a482-7b0456b9b581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244107883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.4244107883
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1593473470
Short name T289
Test name
Test status
Simulation time 18357706584 ps
CPU time 53.92 seconds
Started Apr 16 02:54:08 PM PDT 24
Finished Apr 16 02:55:03 PM PDT 24
Peak memory 240476 kb
Host smart-2c1aee0d-9a3f-4925-a9bb-ec76dd0829d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593473470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1593473470
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3512056429
Short name T515
Test name
Test status
Simulation time 438611872 ps
CPU time 5.13 seconds
Started Apr 16 02:54:12 PM PDT 24
Finished Apr 16 02:54:18 PM PDT 24
Peak memory 221704 kb
Host smart-3c7c108e-00b6-4a2c-9dcd-7bf2c073cbc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3512056429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3512056429
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3897005599
Short name T616
Test name
Test status
Simulation time 2566983034 ps
CPU time 6.64 seconds
Started Apr 16 02:54:07 PM PDT 24
Finished Apr 16 02:54:15 PM PDT 24
Peak memory 216648 kb
Host smart-e7f85c13-41ed-481d-a91d-ad3599a0a72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897005599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3897005599
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.996821283
Short name T499
Test name
Test status
Simulation time 13948906628 ps
CPU time 8.25 seconds
Started Apr 16 02:54:07 PM PDT 24
Finished Apr 16 02:54:16 PM PDT 24
Peak memory 216620 kb
Host smart-3be1485c-3705-4192-adb1-9e7087330707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996821283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.996821283
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2590832234
Short name T699
Test name
Test status
Simulation time 538440537 ps
CPU time 1.86 seconds
Started Apr 16 02:54:09 PM PDT 24
Finished Apr 16 02:54:12 PM PDT 24
Peak memory 216508 kb
Host smart-99b9c22a-bdbe-4dee-840a-2455b288dee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590832234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2590832234
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1154357946
Short name T669
Test name
Test status
Simulation time 48765740 ps
CPU time 0.76 seconds
Started Apr 16 02:54:14 PM PDT 24
Finished Apr 16 02:54:16 PM PDT 24
Peak memory 205832 kb
Host smart-1d7ea3ef-3a7d-4e21-920b-4b8224c6b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154357946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1154357946
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1663784190
Short name T562
Test name
Test status
Simulation time 44833967 ps
CPU time 0.73 seconds
Started Apr 16 02:54:43 PM PDT 24
Finished Apr 16 02:54:45 PM PDT 24
Peak memory 204816 kb
Host smart-af85c46f-fade-4a48-a9d0-5d3cc30d5aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663784190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1663784190
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1478267980
Short name T624
Test name
Test status
Simulation time 23573935 ps
CPU time 0.74 seconds
Started Apr 16 02:54:13 PM PDT 24
Finished Apr 16 02:54:15 PM PDT 24
Peak memory 206976 kb
Host smart-37c8f843-4f3e-4fb8-b007-a72f246b7f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478267980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1478267980
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3219856191
Short name T63
Test name
Test status
Simulation time 322053134 ps
CPU time 12.04 seconds
Started Apr 16 02:54:15 PM PDT 24
Finished Apr 16 02:54:28 PM PDT 24
Peak memory 248444 kb
Host smart-5cf90f8c-8215-4f34-b443-c9fa2b1f7337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219856191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3219856191
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.849210485
Short name T204
Test name
Test status
Simulation time 2517425323 ps
CPU time 11.83 seconds
Started Apr 16 02:54:14 PM PDT 24
Finished Apr 16 02:54:27 PM PDT 24
Peak memory 239968 kb
Host smart-488be82b-af67-4b8a-9712-4d5d175e8319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849210485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.849210485
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3798781728
Short name T147
Test name
Test status
Simulation time 540281650 ps
CPU time 3.44 seconds
Started Apr 16 02:54:12 PM PDT 24
Finished Apr 16 02:54:16 PM PDT 24
Peak memory 220628 kb
Host smart-e68e03e8-478f-49a5-b623-888c5bce69f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3798781728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3798781728
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.759010733
Short name T383
Test name
Test status
Simulation time 2381199498 ps
CPU time 34.79 seconds
Started Apr 16 02:54:11 PM PDT 24
Finished Apr 16 02:54:46 PM PDT 24
Peak memory 216580 kb
Host smart-11854be6-5a47-4415-9b02-de3d3b2bd429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759010733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.759010733
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3739047398
Short name T533
Test name
Test status
Simulation time 3863535507 ps
CPU time 7.39 seconds
Started Apr 16 02:54:14 PM PDT 24
Finished Apr 16 02:54:23 PM PDT 24
Peak memory 216628 kb
Host smart-4e92dea5-beda-48ae-b18c-c27f472c8c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739047398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3739047398
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1347023706
Short name T497
Test name
Test status
Simulation time 65718847 ps
CPU time 1.12 seconds
Started Apr 16 02:54:10 PM PDT 24
Finished Apr 16 02:54:13 PM PDT 24
Peak memory 208064 kb
Host smart-e5171bc3-bc10-49d9-84bd-6ecab84074a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347023706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1347023706
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2802014832
Short name T710
Test name
Test status
Simulation time 139183545 ps
CPU time 0.9 seconds
Started Apr 16 02:54:13 PM PDT 24
Finished Apr 16 02:54:16 PM PDT 24
Peak memory 206884 kb
Host smart-612fa358-ec40-4c81-8c8d-322b0516d9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802014832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2802014832
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2216906429
Short name T258
Test name
Test status
Simulation time 1220978549 ps
CPU time 4.8 seconds
Started Apr 16 02:54:17 PM PDT 24
Finished Apr 16 02:54:23 PM PDT 24
Peak memory 234132 kb
Host smart-56e9acf7-603e-47ac-9048-7350cf8913ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216906429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2216906429
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.327412929
Short name T532
Test name
Test status
Simulation time 11516795 ps
CPU time 0.69 seconds
Started Apr 16 02:54:18 PM PDT 24
Finished Apr 16 02:54:20 PM PDT 24
Peak memory 205384 kb
Host smart-2cfeef28-0723-424b-ac76-7a9861a1c0a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327412929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.327412929
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3687597932
Short name T25
Test name
Test status
Simulation time 20314757 ps
CPU time 0.77 seconds
Started Apr 16 02:54:17 PM PDT 24
Finished Apr 16 02:54:19 PM PDT 24
Peak memory 206656 kb
Host smart-440d0628-a46c-4dfa-9b81-eeb0b155d2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687597932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3687597932
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.880641349
Short name T286
Test name
Test status
Simulation time 945825497 ps
CPU time 13.24 seconds
Started Apr 16 02:54:19 PM PDT 24
Finished Apr 16 02:54:34 PM PDT 24
Peak memory 232968 kb
Host smart-98026779-7cfd-419b-bd94-799c0cc10769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880641349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.880641349
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4112747127
Short name T599
Test name
Test status
Simulation time 598191805 ps
CPU time 3.59 seconds
Started Apr 16 02:54:18 PM PDT 24
Finished Apr 16 02:54:23 PM PDT 24
Peak memory 218856 kb
Host smart-031328ff-324b-4349-ba54-fe67e243c680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112747127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4112747127
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2387332778
Short name T246
Test name
Test status
Simulation time 5082494187 ps
CPU time 20.85 seconds
Started Apr 16 02:54:18 PM PDT 24
Finished Apr 16 02:54:40 PM PDT 24
Peak memory 237048 kb
Host smart-18d6ec3a-ea6c-4ff6-be61-bf1d2eb313d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387332778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2387332778
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.571792751
Short name T94
Test name
Test status
Simulation time 1669055565 ps
CPU time 3.28 seconds
Started Apr 16 02:54:17 PM PDT 24
Finished Apr 16 02:54:21 PM PDT 24
Peak memory 218688 kb
Host smart-9c1381ed-ec9f-45d8-b04b-e75776daed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571792751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.571792751
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1649266967
Short name T581
Test name
Test status
Simulation time 752970538 ps
CPU time 5.31 seconds
Started Apr 16 02:54:17 PM PDT 24
Finished Apr 16 02:54:24 PM PDT 24
Peak memory 219344 kb
Host smart-7522acb3-7c1a-4b00-b73a-6bb1caeb3b64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1649266967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1649266967
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1605475254
Short name T381
Test name
Test status
Simulation time 12350973915 ps
CPU time 40.48 seconds
Started Apr 16 02:54:16 PM PDT 24
Finished Apr 16 02:54:57 PM PDT 24
Peak memory 216584 kb
Host smart-cafba717-aeae-4fff-80f4-77b7c080761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605475254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1605475254
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.262265138
Short name T12
Test name
Test status
Simulation time 2579119652 ps
CPU time 4.4 seconds
Started Apr 16 02:54:19 PM PDT 24
Finished Apr 16 02:54:25 PM PDT 24
Peak memory 216592 kb
Host smart-2d0d9a94-581d-4b4e-9015-724ef16b1448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262265138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.262265138
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1719333343
Short name T680
Test name
Test status
Simulation time 178156540 ps
CPU time 1.42 seconds
Started Apr 16 02:54:18 PM PDT 24
Finished Apr 16 02:54:20 PM PDT 24
Peak memory 216724 kb
Host smart-194474ef-0ed9-4307-8334-63c08d8278e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719333343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1719333343
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.370002815
Short name T22
Test name
Test status
Simulation time 125652374 ps
CPU time 0.8 seconds
Started Apr 16 02:54:18 PM PDT 24
Finished Apr 16 02:54:20 PM PDT 24
Peak memory 205840 kb
Host smart-582cce0c-8280-4817-8159-0d251a03445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370002815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.370002815
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1887621314
Short name T222
Test name
Test status
Simulation time 40580536 ps
CPU time 2.3 seconds
Started Apr 16 02:54:17 PM PDT 24
Finished Apr 16 02:54:20 PM PDT 24
Peak memory 221920 kb
Host smart-5671ae03-1e11-406d-a670-d4b910b120c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887621314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1887621314
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1817203072
Short name T33
Test name
Test status
Simulation time 35359268 ps
CPU time 0.77 seconds
Started Apr 16 02:54:25 PM PDT 24
Finished Apr 16 02:54:27 PM PDT 24
Peak memory 205392 kb
Host smart-abfdc674-4fae-47ab-88f9-8043a6d4e782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817203072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1817203072
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2406915293
Short name T26
Test name
Test status
Simulation time 57825458 ps
CPU time 2.55 seconds
Started Apr 16 02:54:19 PM PDT 24
Finished Apr 16 02:54:23 PM PDT 24
Peak memory 222560 kb
Host smart-e864a6d9-0eb7-403e-a406-c2f9315063e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406915293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2406915293
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3454931164
Short name T666
Test name
Test status
Simulation time 82062741 ps
CPU time 0.76 seconds
Started Apr 16 02:54:15 PM PDT 24
Finished Apr 16 02:54:17 PM PDT 24
Peak memory 206624 kb
Host smart-ce8de6ee-55a8-4822-84f5-9ad2e0615fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454931164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3454931164
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1786788084
Short name T284
Test name
Test status
Simulation time 383781184 ps
CPU time 7.85 seconds
Started Apr 16 02:54:20 PM PDT 24
Finished Apr 16 02:54:30 PM PDT 24
Peak memory 232708 kb
Host smart-94fefa77-8f17-43b9-9214-4fe41b54ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786788084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1786788084
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2273956066
Short name T639
Test name
Test status
Simulation time 6371789005 ps
CPU time 5.69 seconds
Started Apr 16 02:54:21 PM PDT 24
Finished Apr 16 02:54:29 PM PDT 24
Peak memory 224188 kb
Host smart-07a211e7-d8d7-43e3-9763-af12892eb361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273956066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2273956066
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1504735265
Short name T453
Test name
Test status
Simulation time 989662215 ps
CPU time 4.36 seconds
Started Apr 16 02:54:23 PM PDT 24
Finished Apr 16 02:54:29 PM PDT 24
Peak memory 223076 kb
Host smart-aaa6c1c6-fbcd-4093-9bdb-648b1dfc10b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1504735265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1504735265
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1839991962
Short name T578
Test name
Test status
Simulation time 16831124495 ps
CPU time 26.22 seconds
Started Apr 16 02:54:17 PM PDT 24
Finished Apr 16 02:54:45 PM PDT 24
Peak memory 216584 kb
Host smart-a5c5022f-887f-4a87-8b1d-1481b1bb4cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839991962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1839991962
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2027765728
Short name T626
Test name
Test status
Simulation time 6117683857 ps
CPU time 14.99 seconds
Started Apr 16 02:54:20 PM PDT 24
Finished Apr 16 02:54:36 PM PDT 24
Peak memory 216636 kb
Host smart-bba9e4cc-4f33-4f76-8abd-3f222feeac6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027765728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2027765728
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3287535085
Short name T574
Test name
Test status
Simulation time 498166550 ps
CPU time 5.33 seconds
Started Apr 16 02:54:15 PM PDT 24
Finished Apr 16 02:54:22 PM PDT 24
Peak memory 216532 kb
Host smart-b89293fc-4e41-401b-8a07-97c8d20cf506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287535085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3287535085
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1547752334
Short name T507
Test name
Test status
Simulation time 62534657 ps
CPU time 0.8 seconds
Started Apr 16 02:54:19 PM PDT 24
Finished Apr 16 02:54:21 PM PDT 24
Peak memory 205852 kb
Host smart-7677cfc4-50e0-41b3-9850-63a54f41201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547752334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1547752334
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.71958207
Short name T558
Test name
Test status
Simulation time 13129122 ps
CPU time 0.74 seconds
Started Apr 16 02:54:27 PM PDT 24
Finished Apr 16 02:54:29 PM PDT 24
Peak memory 204852 kb
Host smart-a042dd34-3503-44bc-9ab7-36aec7b225e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71958207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.71958207
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1641939112
Short name T426
Test name
Test status
Simulation time 17096074 ps
CPU time 0.75 seconds
Started Apr 16 02:54:20 PM PDT 24
Finished Apr 16 02:54:23 PM PDT 24
Peak memory 206668 kb
Host smart-060df560-68c1-474d-824a-7dc5caaeeee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641939112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1641939112
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3497706044
Short name T287
Test name
Test status
Simulation time 3724566635 ps
CPU time 31.49 seconds
Started Apr 16 02:54:30 PM PDT 24
Finished Apr 16 02:55:04 PM PDT 24
Peak memory 240280 kb
Host smart-4b51e1df-2fce-4f1c-8cbf-e4e43552c62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497706044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3497706044
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.11806250
Short name T264
Test name
Test status
Simulation time 96851745 ps
CPU time 3.11 seconds
Started Apr 16 02:54:29 PM PDT 24
Finished Apr 16 02:54:34 PM PDT 24
Peak memory 219228 kb
Host smart-c11c82a9-f2e2-449f-8672-c296e482c329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11806250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.11806250
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2550931032
Short name T267
Test name
Test status
Simulation time 1391949025 ps
CPU time 5.67 seconds
Started Apr 16 02:54:21 PM PDT 24
Finished Apr 16 02:54:28 PM PDT 24
Peak memory 224760 kb
Host smart-1471f6ad-f43f-459c-aaaf-8fde54cc250b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550931032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2550931032
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3182402043
Short name T202
Test name
Test status
Simulation time 503442141 ps
CPU time 4.69 seconds
Started Apr 16 02:54:25 PM PDT 24
Finished Apr 16 02:54:31 PM PDT 24
Peak memory 221008 kb
Host smart-897d4081-3866-4528-8b47-4eec1abaa9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182402043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3182402043
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2435342550
Short name T549
Test name
Test status
Simulation time 1414630419 ps
CPU time 19.31 seconds
Started Apr 16 02:54:25 PM PDT 24
Finished Apr 16 02:54:46 PM PDT 24
Peak memory 218776 kb
Host smart-0ee60f64-8627-4feb-aea7-ce45e3d05e5c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2435342550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2435342550
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4023355167
Short name T37
Test name
Test status
Simulation time 71537175 ps
CPU time 0.94 seconds
Started Apr 16 02:54:25 PM PDT 24
Finished Apr 16 02:54:28 PM PDT 24
Peak memory 206980 kb
Host smart-a0604bc3-f131-4092-b32e-037c001cd666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023355167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4023355167
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2940882790
Short name T389
Test name
Test status
Simulation time 11468987168 ps
CPU time 15.05 seconds
Started Apr 16 02:54:22 PM PDT 24
Finished Apr 16 02:54:39 PM PDT 24
Peak memory 216568 kb
Host smart-58e09afa-d7a1-4677-a298-06be91236bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940882790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2940882790
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.503240000
Short name T656
Test name
Test status
Simulation time 1258656151 ps
CPU time 5.98 seconds
Started Apr 16 02:54:21 PM PDT 24
Finished Apr 16 02:54:29 PM PDT 24
Peak memory 216352 kb
Host smart-56417d4f-9739-4171-a744-47291e5b677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503240000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.503240000
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.945219228
Short name T541
Test name
Test status
Simulation time 129975352 ps
CPU time 2.4 seconds
Started Apr 16 02:54:20 PM PDT 24
Finished Apr 16 02:54:24 PM PDT 24
Peak memory 217744 kb
Host smart-590edadc-ad6b-49fe-a5dc-057a9051ebf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945219228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.945219228
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2102935417
Short name T403
Test name
Test status
Simulation time 430051967 ps
CPU time 0.8 seconds
Started Apr 16 02:54:22 PM PDT 24
Finished Apr 16 02:54:25 PM PDT 24
Peak memory 205840 kb
Host smart-6b41c069-1b79-4ba9-b665-fd09aa6a4b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102935417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2102935417
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3542511193
Short name T410
Test name
Test status
Simulation time 44227011 ps
CPU time 0.73 seconds
Started Apr 16 02:54:32 PM PDT 24
Finished Apr 16 02:54:34 PM PDT 24
Peak memory 205412 kb
Host smart-8302cabc-dc97-410f-8f8e-58834769228c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542511193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3542511193
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.440625784
Short name T444
Test name
Test status
Simulation time 17288839 ps
CPU time 0.79 seconds
Started Apr 16 02:54:27 PM PDT 24
Finished Apr 16 02:54:30 PM PDT 24
Peak memory 207008 kb
Host smart-b4742f3f-32c2-4b13-9633-012b9b46d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440625784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.440625784
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1621111657
Short name T268
Test name
Test status
Simulation time 1157131952 ps
CPU time 4.16 seconds
Started Apr 16 02:54:31 PM PDT 24
Finished Apr 16 02:54:37 PM PDT 24
Peak memory 221440 kb
Host smart-dca4e115-44cb-4b01-a354-a6269e022b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621111657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1621111657
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.123242080
Short name T38
Test name
Test status
Simulation time 11135866887 ps
CPU time 112.31 seconds
Started Apr 16 02:54:32 PM PDT 24
Finished Apr 16 02:56:26 PM PDT 24
Peak memory 230796 kb
Host smart-1518f4ec-c36c-4f03-962a-46b4dcee8f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123242080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.123242080
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2221467653
Short name T176
Test name
Test status
Simulation time 198308793 ps
CPU time 4.04 seconds
Started Apr 16 02:54:25 PM PDT 24
Finished Apr 16 02:54:31 PM PDT 24
Peak memory 222748 kb
Host smart-c8adc9f6-1388-478e-bfeb-318b5a22e9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221467653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2221467653
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.243868250
Short name T232
Test name
Test status
Simulation time 968929589 ps
CPU time 2.73 seconds
Started Apr 16 02:54:28 PM PDT 24
Finished Apr 16 02:54:33 PM PDT 24
Peak memory 222480 kb
Host smart-d43e7703-b7aa-4ddf-ad74-3a3a30164fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243868250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.243868250
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1020989750
Short name T583
Test name
Test status
Simulation time 868116475 ps
CPU time 8.52 seconds
Started Apr 16 02:54:35 PM PDT 24
Finished Apr 16 02:54:45 PM PDT 24
Peak memory 222364 kb
Host smart-05d48f90-536b-437e-ab48-501abbca7964
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1020989750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1020989750
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2318716153
Short name T99
Test name
Test status
Simulation time 682634684 ps
CPU time 9.71 seconds
Started Apr 16 02:54:30 PM PDT 24
Finished Apr 16 02:54:42 PM PDT 24
Peak memory 216580 kb
Host smart-4c016594-ad10-40a4-a711-500dd10e70fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318716153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2318716153
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.615368493
Short name T620
Test name
Test status
Simulation time 1261612578 ps
CPU time 8.6 seconds
Started Apr 16 02:54:26 PM PDT 24
Finished Apr 16 02:54:36 PM PDT 24
Peak memory 216544 kb
Host smart-6bde72e2-0392-4733-8a44-98e35cee6192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615368493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.615368493
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1043270757
Short name T685
Test name
Test status
Simulation time 937472181 ps
CPU time 8.74 seconds
Started Apr 16 02:54:27 PM PDT 24
Finished Apr 16 02:54:38 PM PDT 24
Peak memory 216500 kb
Host smart-0acec128-e0de-4aa6-a4e5-3301dbdb46dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043270757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1043270757
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2402770512
Short name T546
Test name
Test status
Simulation time 373755194 ps
CPU time 1.02 seconds
Started Apr 16 02:54:27 PM PDT 24
Finished Apr 16 02:54:30 PM PDT 24
Peak memory 205836 kb
Host smart-f5d34e75-fbd3-4ced-b21f-42513dc44923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402770512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2402770512
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3987717987
Short name T159
Test name
Test status
Simulation time 339901572 ps
CPU time 7.3 seconds
Started Apr 16 02:54:28 PM PDT 24
Finished Apr 16 02:54:38 PM PDT 24
Peak memory 232868 kb
Host smart-4acb5330-5cd1-467f-8acc-440ec51606de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987717987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3987717987
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1226670668
Short name T518
Test name
Test status
Simulation time 25153192 ps
CPU time 0.73 seconds
Started Apr 16 02:54:33 PM PDT 24
Finished Apr 16 02:54:36 PM PDT 24
Peak memory 205720 kb
Host smart-9929a11c-6ece-4b1e-bb72-15b80e0fc47b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226670668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1226670668
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2203493887
Short name T718
Test name
Test status
Simulation time 81269989 ps
CPU time 0.73 seconds
Started Apr 16 02:54:33 PM PDT 24
Finished Apr 16 02:54:35 PM PDT 24
Peak memory 206612 kb
Host smart-60293757-d84f-4f8e-9266-50fa616b1aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203493887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2203493887
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.168775288
Short name T348
Test name
Test status
Simulation time 841728552 ps
CPU time 22.01 seconds
Started Apr 16 02:54:34 PM PDT 24
Finished Apr 16 02:54:58 PM PDT 24
Peak memory 232964 kb
Host smart-a9366b27-b0b6-496a-983f-3f11ddfbc292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168775288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.168775288
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1103451890
Short name T207
Test name
Test status
Simulation time 221183753 ps
CPU time 5.53 seconds
Started Apr 16 02:54:32 PM PDT 24
Finished Apr 16 02:54:40 PM PDT 24
Peak memory 222064 kb
Host smart-2bcdff99-e5c9-4cab-a181-c040c21fe323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103451890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1103451890
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1383310389
Short name T302
Test name
Test status
Simulation time 38609846913 ps
CPU time 29.93 seconds
Started Apr 16 02:54:34 PM PDT 24
Finished Apr 16 02:55:06 PM PDT 24
Peak memory 232960 kb
Host smart-648f6999-c527-4f33-859e-c361f73a1717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383310389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1383310389
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1009393644
Short name T504
Test name
Test status
Simulation time 551489038 ps
CPU time 6.04 seconds
Started Apr 16 02:54:32 PM PDT 24
Finished Apr 16 02:54:40 PM PDT 24
Peak memory 220156 kb
Host smart-122bcbca-1a86-4e5a-af4d-dea839338acc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1009393644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1009393644
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2889630304
Short name T733
Test name
Test status
Simulation time 6496192620 ps
CPU time 11.43 seconds
Started Apr 16 02:54:30 PM PDT 24
Finished Apr 16 02:54:44 PM PDT 24
Peak memory 216620 kb
Host smart-b94f5fb6-d018-4bb1-8597-3790f1bf50d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889630304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2889630304
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3380617849
Short name T630
Test name
Test status
Simulation time 788192145 ps
CPU time 5.86 seconds
Started Apr 16 02:54:32 PM PDT 24
Finished Apr 16 02:54:40 PM PDT 24
Peak memory 216476 kb
Host smart-01af8cd4-12f6-47fe-9858-9201c36a13d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380617849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3380617849
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2386610883
Short name T611
Test name
Test status
Simulation time 400607242 ps
CPU time 2.4 seconds
Started Apr 16 02:54:33 PM PDT 24
Finished Apr 16 02:54:38 PM PDT 24
Peak memory 216576 kb
Host smart-c68f2885-dedf-44f6-ab94-a79bd47f69b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386610883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2386610883
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.247958696
Short name T554
Test name
Test status
Simulation time 66476042 ps
CPU time 0.72 seconds
Started Apr 16 02:54:33 PM PDT 24
Finished Apr 16 02:54:36 PM PDT 24
Peak memory 205856 kb
Host smart-6e7ecd0d-18e6-4809-b34c-6e9741a9a169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247958696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.247958696
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1534255204
Short name T370
Test name
Test status
Simulation time 4125059379 ps
CPU time 12.71 seconds
Started Apr 16 02:54:35 PM PDT 24
Finished Apr 16 02:54:49 PM PDT 24
Peak memory 223340 kb
Host smart-32034191-788a-4e57-9ac2-b407d58c9868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534255204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1534255204
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1965146708
Short name T706
Test name
Test status
Simulation time 24229129 ps
CPU time 0.73 seconds
Started Apr 16 02:54:41 PM PDT 24
Finished Apr 16 02:54:42 PM PDT 24
Peak memory 204816 kb
Host smart-eb08372a-db8f-4b51-acbe-7f673160ec8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965146708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1965146708
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3289195737
Short name T470
Test name
Test status
Simulation time 16442483 ps
CPU time 0.79 seconds
Started Apr 16 02:54:32 PM PDT 24
Finished Apr 16 02:54:34 PM PDT 24
Peak memory 206624 kb
Host smart-06ad6ccc-b29d-4a25-ae12-b9cf037419d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289195737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3289195737
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2996719105
Short name T87
Test name
Test status
Simulation time 6680199934 ps
CPU time 74.95 seconds
Started Apr 16 02:54:36 PM PDT 24
Finished Apr 16 02:55:52 PM PDT 24
Peak memory 240600 kb
Host smart-29880fda-46ff-4b87-ad31-161123755dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996719105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2996719105
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2143702870
Short name T265
Test name
Test status
Simulation time 4600665776 ps
CPU time 11.34 seconds
Started Apr 16 02:54:36 PM PDT 24
Finished Apr 16 02:54:48 PM PDT 24
Peak memory 223600 kb
Host smart-4c9fd1ba-afc7-4e26-b0fc-e7e3233a9774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143702870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2143702870
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2624076986
Short name T308
Test name
Test status
Simulation time 31502642451 ps
CPU time 74.23 seconds
Started Apr 16 02:54:36 PM PDT 24
Finished Apr 16 02:55:51 PM PDT 24
Peak memory 224752 kb
Host smart-b5de32c3-d9e8-42fc-a29a-c742ea568724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624076986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2624076986
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.495017455
Short name T59
Test name
Test status
Simulation time 499108251 ps
CPU time 3.95 seconds
Started Apr 16 02:54:37 PM PDT 24
Finished Apr 16 02:54:42 PM PDT 24
Peak memory 224708 kb
Host smart-0d164c18-19ba-47be-b11b-aaf171bf0a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495017455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.495017455
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1527503783
Short name T95
Test name
Test status
Simulation time 737667125 ps
CPU time 5.43 seconds
Started Apr 16 02:54:36 PM PDT 24
Finished Apr 16 02:54:43 PM PDT 24
Peak memory 220696 kb
Host smart-a09bf246-d430-4e99-ba3e-a0dd7b277c36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1527503783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1527503783
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2480260163
Short name T688
Test name
Test status
Simulation time 9250428498 ps
CPU time 21.2 seconds
Started Apr 16 02:54:34 PM PDT 24
Finished Apr 16 02:54:57 PM PDT 24
Peak memory 216600 kb
Host smart-08a65949-50e0-42e5-994e-1a9948f73fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480260163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2480260163
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2304413120
Short name T606
Test name
Test status
Simulation time 1382999791 ps
CPU time 7.62 seconds
Started Apr 16 02:54:33 PM PDT 24
Finished Apr 16 02:54:43 PM PDT 24
Peak memory 216500 kb
Host smart-b94a3ed1-b4ef-4987-a0cf-fdad2f93b89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304413120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2304413120
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3388183485
Short name T459
Test name
Test status
Simulation time 189053983 ps
CPU time 3.19 seconds
Started Apr 16 02:54:36 PM PDT 24
Finished Apr 16 02:54:41 PM PDT 24
Peak memory 216536 kb
Host smart-0768ae31-fcb6-445f-808b-e0a130557164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388183485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3388183485
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3027794918
Short name T498
Test name
Test status
Simulation time 41543711 ps
CPU time 0.7 seconds
Started Apr 16 02:54:32 PM PDT 24
Finished Apr 16 02:54:35 PM PDT 24
Peak memory 205848 kb
Host smart-097e73cd-15f9-4ff7-a8a4-e5df34dc1bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027794918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3027794918
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3014013012
Short name T551
Test name
Test status
Simulation time 48103316 ps
CPU time 2.33 seconds
Started Apr 16 02:54:39 PM PDT 24
Finished Apr 16 02:54:42 PM PDT 24
Peak memory 219396 kb
Host smart-f05b9e1a-d5d5-44d6-b272-bc651df0ca50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014013012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3014013012
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1168420779
Short name T161
Test name
Test status
Simulation time 30081270 ps
CPU time 0.68 seconds
Started Apr 16 02:54:41 PM PDT 24
Finished Apr 16 02:54:42 PM PDT 24
Peak memory 204816 kb
Host smart-637668e8-3115-4318-878d-ac16b75b78e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168420779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1168420779
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3615213584
Short name T535
Test name
Test status
Simulation time 15541362 ps
CPU time 0.75 seconds
Started Apr 16 02:54:40 PM PDT 24
Finished Apr 16 02:54:41 PM PDT 24
Peak memory 206592 kb
Host smart-1097c104-80f9-4994-8bba-e70093cc370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615213584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3615213584
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_intercept.370769459
Short name T329
Test name
Test status
Simulation time 2493105155 ps
CPU time 19.28 seconds
Started Apr 16 02:54:44 PM PDT 24
Finished Apr 16 02:55:04 PM PDT 24
Peak memory 218912 kb
Host smart-59244246-4a6d-4489-a3a6-c992ec34e03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370769459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.370769459
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1655709848
Short name T234
Test name
Test status
Simulation time 1933610329 ps
CPU time 9.57 seconds
Started Apr 16 02:54:42 PM PDT 24
Finished Apr 16 02:54:53 PM PDT 24
Peak memory 219136 kb
Host smart-c85c88c8-e825-49c7-ab5e-ae7f9f0efc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655709848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1655709848
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2931862310
Short name T730
Test name
Test status
Simulation time 678726338 ps
CPU time 5.1 seconds
Started Apr 16 02:54:44 PM PDT 24
Finished Apr 16 02:54:50 PM PDT 24
Peak memory 224156 kb
Host smart-86149e06-9fd7-4701-9e5d-28a2da7a33d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931862310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2931862310
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.925354400
Short name T481
Test name
Test status
Simulation time 1084556845 ps
CPU time 14.51 seconds
Started Apr 16 02:54:41 PM PDT 24
Finished Apr 16 02:54:56 PM PDT 24
Peak memory 220068 kb
Host smart-04c4075e-48db-4cb8-bfd9-cf092ecbb793
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=925354400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.925354400
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4094479729
Short name T379
Test name
Test status
Simulation time 18052315000 ps
CPU time 37.47 seconds
Started Apr 16 02:54:42 PM PDT 24
Finished Apr 16 02:55:20 PM PDT 24
Peak memory 216648 kb
Host smart-76fed173-65c3-41da-982b-12c7342667a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094479729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4094479729
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.689169160
Short name T582
Test name
Test status
Simulation time 913667778 ps
CPU time 1.62 seconds
Started Apr 16 02:54:49 PM PDT 24
Finished Apr 16 02:54:52 PM PDT 24
Peak memory 207936 kb
Host smart-e87f9e7d-7587-4be9-9c58-99bdd0d73ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689169160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.689169160
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1220550948
Short name T483
Test name
Test status
Simulation time 45394003 ps
CPU time 2.15 seconds
Started Apr 16 02:54:42 PM PDT 24
Finished Apr 16 02:54:46 PM PDT 24
Peak memory 216520 kb
Host smart-cafa9488-ad7a-4332-870c-2d8327550b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220550948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1220550948
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.989023755
Short name T649
Test name
Test status
Simulation time 53712134 ps
CPU time 0.73 seconds
Started Apr 16 02:54:40 PM PDT 24
Finished Apr 16 02:54:42 PM PDT 24
Peak memory 205852 kb
Host smart-ac8b1495-1faf-4aab-8998-9582f22b75ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989023755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.989023755
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1154456231
Short name T600
Test name
Test status
Simulation time 11967510 ps
CPU time 0.72 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:21 PM PDT 24
Peak memory 205752 kb
Host smart-31887e8d-03c7-4e18-a1b1-f08a30a0575d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154456231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
154456231
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2865343285
Short name T311
Test name
Test status
Simulation time 227415523 ps
CPU time 4.32 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:27 PM PDT 24
Peak memory 218796 kb
Host smart-95b38a39-3ab8-44c5-b576-8093dab9cec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865343285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2865343285
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1513068984
Short name T443
Test name
Test status
Simulation time 16610638 ps
CPU time 0.76 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:52:26 PM PDT 24
Peak memory 205592 kb
Host smart-13f64c95-f417-48a0-bbf2-835957cf5b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513068984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1513068984
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3348061015
Short name T349
Test name
Test status
Simulation time 4831084068 ps
CPU time 30.52 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:52:56 PM PDT 24
Peak memory 250732 kb
Host smart-e4f62294-89b5-4f93-9416-e0ed6a644583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348061015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3348061015
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3075861089
Short name T432
Test name
Test status
Simulation time 6686842305 ps
CPU time 6.71 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:27 PM PDT 24
Peak memory 218916 kb
Host smart-ef6b79cf-6155-4ad1-b1c5-a9af7c7f6fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075861089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3075861089
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1974750498
Short name T511
Test name
Test status
Simulation time 167812409 ps
CPU time 1.07 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:22 PM PDT 24
Peak memory 216936 kb
Host smart-5b0636cb-94a9-4a31-bce3-6ea360c66366
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974750498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1974750498
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1504706078
Short name T256
Test name
Test status
Simulation time 2189745380 ps
CPU time 8.84 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:29 PM PDT 24
Peak memory 222932 kb
Host smart-a5813240-ed3c-4604-825b-a676abec5e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504706078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1504706078
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3854125192
Short name T427
Test name
Test status
Simulation time 7862418334 ps
CPU time 6.27 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:27 PM PDT 24
Peak memory 219072 kb
Host smart-c7776a87-8631-451a-ba31-b9ea2c632e3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3854125192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3854125192
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.248799460
Short name T560
Test name
Test status
Simulation time 2228990245 ps
CPU time 11.17 seconds
Started Apr 16 02:52:22 PM PDT 24
Finished Apr 16 02:52:35 PM PDT 24
Peak memory 216560 kb
Host smart-79609467-731c-4372-88d0-55d533d1676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248799460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.248799460
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1022323849
Short name T596
Test name
Test status
Simulation time 1592188591 ps
CPU time 6.48 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:27 PM PDT 24
Peak memory 216520 kb
Host smart-78aae17d-828e-4b2c-9fa6-d997549cca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022323849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1022323849
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1606295963
Short name T673
Test name
Test status
Simulation time 101701225 ps
CPU time 4.33 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:52:30 PM PDT 24
Peak memory 216568 kb
Host smart-dfbed5f5-cdd8-44a9-9657-58426dff36ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606295963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1606295963
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1918108139
Short name T472
Test name
Test status
Simulation time 188944485 ps
CPU time 0.89 seconds
Started Apr 16 02:52:20 PM PDT 24
Finished Apr 16 02:52:22 PM PDT 24
Peak memory 206912 kb
Host smart-7aa93c6b-bbc3-4e72-a594-8ac914a609c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918108139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1918108139
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3347612665
Short name T555
Test name
Test status
Simulation time 3690854864 ps
CPU time 5.14 seconds
Started Apr 16 02:52:22 PM PDT 24
Finished Apr 16 02:52:30 PM PDT 24
Peak memory 222280 kb
Host smart-b00127ea-0f77-479b-96bf-1999c5245425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347612665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3347612665
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1336775539
Short name T495
Test name
Test status
Simulation time 15556312 ps
CPU time 0.71 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:52:26 PM PDT 24
Peak memory 205400 kb
Host smart-f3af60b3-b0a0-4174-8211-74650a58bacc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336775539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
336775539
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2749661270
Short name T604
Test name
Test status
Simulation time 245651092 ps
CPU time 2.52 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:52:28 PM PDT 24
Peak memory 221036 kb
Host smart-a4a0e051-9165-418c-88ef-f0d4e584e714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749661270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2749661270
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1638634483
Short name T501
Test name
Test status
Simulation time 56940162 ps
CPU time 0.76 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:24 PM PDT 24
Peak memory 206956 kb
Host smart-2f512880-526a-4b4a-8a03-5704eabc975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638634483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1638634483
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.4148970519
Short name T683
Test name
Test status
Simulation time 147171681 ps
CPU time 1.08 seconds
Started Apr 16 02:52:20 PM PDT 24
Finished Apr 16 02:52:23 PM PDT 24
Peak memory 218204 kb
Host smart-da19287f-14bd-4991-859c-ae3fe3ed2d84
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148970519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.4148970519
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1038472332
Short name T8
Test name
Test status
Simulation time 9883083457 ps
CPU time 11.44 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:35 PM PDT 24
Peak memory 218636 kb
Host smart-1f03f109-802f-4245-a8c2-23472f137d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038472332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1038472332
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2588635950
Short name T594
Test name
Test status
Simulation time 748533358 ps
CPU time 5.62 seconds
Started Apr 16 02:52:24 PM PDT 24
Finished Apr 16 02:52:32 PM PDT 24
Peak memory 220860 kb
Host smart-7df1ae1f-9894-47db-94f0-d27a056c44d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2588635950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2588635950
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1780422630
Short name T359
Test name
Test status
Simulation time 486100822 ps
CPU time 1.03 seconds
Started Apr 16 02:52:25 PM PDT 24
Finished Apr 16 02:52:28 PM PDT 24
Peak memory 207148 kb
Host smart-6d52af1a-0bad-4e50-8cd8-575310d4c19c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780422630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1780422630
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2586198317
Short name T577
Test name
Test status
Simulation time 878224484 ps
CPU time 3.71 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:27 PM PDT 24
Peak memory 216544 kb
Host smart-b4508b32-730d-4604-93aa-94b2ef7a9ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586198317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2586198317
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.723308680
Short name T621
Test name
Test status
Simulation time 16012518 ps
CPU time 0.81 seconds
Started Apr 16 02:52:28 PM PDT 24
Finished Apr 16 02:52:30 PM PDT 24
Peak memory 206512 kb
Host smart-1aba9e0e-6974-494f-ac21-c90f02875c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723308680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.723308680
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3398344893
Short name T567
Test name
Test status
Simulation time 86585359 ps
CPU time 1.01 seconds
Started Apr 16 02:52:19 PM PDT 24
Finished Apr 16 02:52:22 PM PDT 24
Peak memory 206944 kb
Host smart-5a942858-bf99-416b-b10f-989bf5865cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398344893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3398344893
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.133475929
Short name T32
Test name
Test status
Simulation time 668240573 ps
CPU time 6.11 seconds
Started Apr 16 02:52:21 PM PDT 24
Finished Apr 16 02:52:30 PM PDT 24
Peak memory 234872 kb
Host smart-affac5f1-8fb7-492b-98a8-370eadc21b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133475929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.133475929
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4272697479
Short name T399
Test name
Test status
Simulation time 108520541 ps
CPU time 0.78 seconds
Started Apr 16 02:52:32 PM PDT 24
Finished Apr 16 02:52:34 PM PDT 24
Peak memory 204856 kb
Host smart-64ced925-0d2c-4559-871e-609f6aeb1aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272697479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
272697479
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1764122174
Short name T587
Test name
Test status
Simulation time 45870863 ps
CPU time 0.75 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:52:26 PM PDT 24
Peak memory 205620 kb
Host smart-a97e37c8-0437-459b-86fe-a8e4088304dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764122174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1764122174
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1122011149
Short name T314
Test name
Test status
Simulation time 287605771 ps
CPU time 6.57 seconds
Started Apr 16 02:52:25 PM PDT 24
Finished Apr 16 02:52:34 PM PDT 24
Peak memory 232976 kb
Host smart-c8745e0b-6600-434c-96d0-ff49a34a6096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122011149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1122011149
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1445602834
Short name T13
Test name
Test status
Simulation time 25152793 ps
CPU time 1.1 seconds
Started Apr 16 02:52:36 PM PDT 24
Finished Apr 16 02:52:39 PM PDT 24
Peak memory 216964 kb
Host smart-77fe14dc-5948-4605-bb10-3db8147af439
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445602834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1445602834
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3346418597
Short name T183
Test name
Test status
Simulation time 37051802617 ps
CPU time 24.76 seconds
Started Apr 16 02:52:24 PM PDT 24
Finished Apr 16 02:52:51 PM PDT 24
Peak memory 237056 kb
Host smart-dd1d76e0-24dc-4c73-a240-aef216297936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346418597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3346418597
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2547051336
Short name T418
Test name
Test status
Simulation time 1586740392 ps
CPU time 6.2 seconds
Started Apr 16 02:52:24 PM PDT 24
Finished Apr 16 02:52:32 PM PDT 24
Peak memory 222952 kb
Host smart-edb768fb-057f-433e-b924-4693b7f7e647
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2547051336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2547051336
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4064599090
Short name T385
Test name
Test status
Simulation time 40503454336 ps
CPU time 34.74 seconds
Started Apr 16 02:52:25 PM PDT 24
Finished Apr 16 02:53:02 PM PDT 24
Peak memory 216544 kb
Host smart-9d2ca75f-179e-43ab-bb2d-aa58bdafb7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064599090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4064599090
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1425987256
Short name T713
Test name
Test status
Simulation time 1761322015 ps
CPU time 4.74 seconds
Started Apr 16 02:52:24 PM PDT 24
Finished Apr 16 02:52:31 PM PDT 24
Peak memory 216552 kb
Host smart-3a76a7fb-49ab-4479-b306-711fefa44072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425987256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1425987256
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4146070593
Short name T682
Test name
Test status
Simulation time 1153597600 ps
CPU time 8.39 seconds
Started Apr 16 02:52:23 PM PDT 24
Finished Apr 16 02:52:33 PM PDT 24
Peak memory 216620 kb
Host smart-20e4d3ed-2b8e-426f-9c5c-6dd75704c98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146070593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4146070593
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3877051348
Short name T513
Test name
Test status
Simulation time 119744810 ps
CPU time 0.99 seconds
Started Apr 16 02:52:24 PM PDT 24
Finished Apr 16 02:52:27 PM PDT 24
Peak memory 206336 kb
Host smart-07fca73f-2ab5-45f2-97e7-d84396e7c0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877051348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3877051348
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3231709632
Short name T217
Test name
Test status
Simulation time 3186540052 ps
CPU time 12.19 seconds
Started Apr 16 02:52:22 PM PDT 24
Finished Apr 16 02:52:36 PM PDT 24
Peak memory 234092 kb
Host smart-96b3eaf0-4553-4e1f-b718-ed44261f85a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231709632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3231709632
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1611345353
Short name T723
Test name
Test status
Simulation time 91680802 ps
CPU time 0.69 seconds
Started Apr 16 02:52:26 PM PDT 24
Finished Apr 16 02:52:28 PM PDT 24
Peak memory 205396 kb
Host smart-554f9571-be93-406a-be34-1f9f574cf846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611345353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
611345353
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1674208552
Short name T634
Test name
Test status
Simulation time 24198659 ps
CPU time 0.76 seconds
Started Apr 16 02:52:29 PM PDT 24
Finished Apr 16 02:52:31 PM PDT 24
Peak memory 206644 kb
Host smart-2f4cfc44-14f6-4bf2-8f41-72555edc21c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674208552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1674208552
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3490206406
Short name T235
Test name
Test status
Simulation time 121745797 ps
CPU time 3.95 seconds
Started Apr 16 02:52:28 PM PDT 24
Finished Apr 16 02:52:33 PM PDT 24
Peak memory 223000 kb
Host smart-9aaa6f91-0c14-414a-beff-c9a3a1dcb8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490206406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3490206406
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3761251482
Short name T460
Test name
Test status
Simulation time 17057916 ps
CPU time 0.99 seconds
Started Apr 16 02:52:30 PM PDT 24
Finished Apr 16 02:52:31 PM PDT 24
Peak memory 218136 kb
Host smart-ff63ac71-2c12-4807-9b81-677d21f75751
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761251482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3761251482
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1917045427
Short name T180
Test name
Test status
Simulation time 8566583270 ps
CPU time 23.7 seconds
Started Apr 16 02:52:32 PM PDT 24
Finished Apr 16 02:52:56 PM PDT 24
Peak memory 232980 kb
Host smart-e6bb7c2c-226b-47a9-baea-e19375055450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917045427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1917045427
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1844077791
Short name T700
Test name
Test status
Simulation time 893873687 ps
CPU time 3.83 seconds
Started Apr 16 02:52:29 PM PDT 24
Finished Apr 16 02:52:34 PM PDT 24
Peak memory 221644 kb
Host smart-0fe1ee2a-2659-4a8a-996e-49ae889e8f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844077791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1844077791
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.97909935
Short name T595
Test name
Test status
Simulation time 5052956922 ps
CPU time 14.68 seconds
Started Apr 16 02:52:28 PM PDT 24
Finished Apr 16 02:52:44 PM PDT 24
Peak memory 221032 kb
Host smart-b1f6a333-2212-42ed-87ba-36a5ad98922e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=97909935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct
.97909935
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1894259759
Short name T374
Test name
Test status
Simulation time 4268375036 ps
CPU time 17.07 seconds
Started Apr 16 02:52:29 PM PDT 24
Finished Apr 16 02:52:47 PM PDT 24
Peak memory 216608 kb
Host smart-a289c6f9-157c-44dd-a066-3984471678c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894259759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1894259759
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.485570841
Short name T678
Test name
Test status
Simulation time 6578119736 ps
CPU time 2.45 seconds
Started Apr 16 02:52:29 PM PDT 24
Finished Apr 16 02:52:33 PM PDT 24
Peak memory 208172 kb
Host smart-7603613b-1887-43b2-a2b7-130cbf94a38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485570841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.485570841
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3881441631
Short name T446
Test name
Test status
Simulation time 65769066 ps
CPU time 0.75 seconds
Started Apr 16 02:52:29 PM PDT 24
Finished Apr 16 02:52:31 PM PDT 24
Peak memory 205868 kb
Host smart-d5915e80-af7d-42e1-b861-f11a19d1b119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881441631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3881441631
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3100667944
Short name T651
Test name
Test status
Simulation time 42751070 ps
CPU time 0.77 seconds
Started Apr 16 02:52:29 PM PDT 24
Finished Apr 16 02:52:31 PM PDT 24
Peak memory 205868 kb
Host smart-4674ce2d-a461-4138-a926-96aa6a708d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100667944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3100667944
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3241059112
Short name T160
Test name
Test status
Simulation time 6593254115 ps
CPU time 15.13 seconds
Started Apr 16 02:52:27 PM PDT 24
Finished Apr 16 02:52:44 PM PDT 24
Peak memory 233028 kb
Host smart-744510f8-6194-460b-92e2-68539cc42248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241059112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3241059112
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4264729730
Short name T598
Test name
Test status
Simulation time 19614863 ps
CPU time 0.72 seconds
Started Apr 16 02:52:37 PM PDT 24
Finished Apr 16 02:52:38 PM PDT 24
Peak memory 205728 kb
Host smart-1f6a2169-dc63-4743-8995-5faa66b7b714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264729730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
264729730
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3891829837
Short name T705
Test name
Test status
Simulation time 223247928 ps
CPU time 3.41 seconds
Started Apr 16 02:52:30 PM PDT 24
Finished Apr 16 02:52:34 PM PDT 24
Peak memory 222880 kb
Host smart-1e511821-4129-4e78-8b2f-516cdb803b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891829837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3891829837
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3644808723
Short name T588
Test name
Test status
Simulation time 46407867 ps
CPU time 0.78 seconds
Started Apr 16 02:52:27 PM PDT 24
Finished Apr 16 02:52:29 PM PDT 24
Peak memory 205624 kb
Host smart-fd33d7d6-ee35-4208-8f9e-d8c43707d0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644808723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3644808723
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1861633022
Short name T354
Test name
Test status
Simulation time 2356737824 ps
CPU time 38.16 seconds
Started Apr 16 02:52:35 PM PDT 24
Finished Apr 16 02:53:14 PM PDT 24
Peak memory 235052 kb
Host smart-99b5c899-a61d-417e-85f0-f54635ad764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861633022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1861633022
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.993004077
Short name T3
Test name
Test status
Simulation time 241560336 ps
CPU time 0.99 seconds
Started Apr 16 02:52:27 PM PDT 24
Finished Apr 16 02:52:29 PM PDT 24
Peak memory 216872 kb
Host smart-f3ef239d-b842-48f6-b576-0a90d59f062d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993004077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.993004077
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3183675298
Short name T261
Test name
Test status
Simulation time 4199366311 ps
CPU time 8.2 seconds
Started Apr 16 02:52:37 PM PDT 24
Finished Apr 16 02:52:46 PM PDT 24
Peak memory 221868 kb
Host smart-47dd0f9b-076e-4a55-bb47-c0aaf444ce80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183675298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3183675298
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.309383438
Short name T112
Test name
Test status
Simulation time 1917673150 ps
CPU time 16.63 seconds
Started Apr 16 02:52:31 PM PDT 24
Finished Apr 16 02:52:48 PM PDT 24
Peak memory 221580 kb
Host smart-964a5d3b-57bb-4500-825e-0ecc8254127b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=309383438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.309383438
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3362708958
Short name T655
Test name
Test status
Simulation time 2480914595 ps
CPU time 6.59 seconds
Started Apr 16 02:52:32 PM PDT 24
Finished Apr 16 02:52:41 PM PDT 24
Peak memory 216632 kb
Host smart-7db44a14-2cea-440c-8e66-708a84bd5554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362708958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3362708958
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1154927889
Short name T469
Test name
Test status
Simulation time 1097726645 ps
CPU time 7.86 seconds
Started Apr 16 02:52:30 PM PDT 24
Finished Apr 16 02:52:39 PM PDT 24
Peak memory 216812 kb
Host smart-5641e998-b205-495f-ac3b-473154a1bca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154927889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1154927889
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2722543664
Short name T564
Test name
Test status
Simulation time 21748544 ps
CPU time 0.9 seconds
Started Apr 16 02:52:35 PM PDT 24
Finished Apr 16 02:52:37 PM PDT 24
Peak memory 206972 kb
Host smart-f41b74c7-8f25-4748-81e9-b2036aa046a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722543664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2722543664
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1681746212
Short name T537
Test name
Test status
Simulation time 853929791 ps
CPU time 0.9 seconds
Started Apr 16 02:52:32 PM PDT 24
Finished Apr 16 02:52:34 PM PDT 24
Peak memory 206864 kb
Host smart-a031b3ce-d501-4b8b-b0a2-7956aa15c1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681746212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1681746212
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3061761513
Short name T229
Test name
Test status
Simulation time 8125718034 ps
CPU time 24.29 seconds
Started Apr 16 02:52:33 PM PDT 24
Finished Apr 16 02:52:59 PM PDT 24
Peak memory 232716 kb
Host smart-9aa3d0b1-69aa-46c5-b0ac-55df8c4832d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061761513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3061761513
Directory /workspace/9.spi_device_upload/latest
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