Unified Coverage Report :: Module :: spid_csb_sync

Module : spid_csb_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_sys_cmdfifo_set	75.54	90.91	50.00			85.71
tb.dut.u_spid_csb_sync	95.24	100.00	100.00			85.71

---

Module Instance : tb.dut.u_upload.u_sys_cmdfifo_set

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.54	90.91	50.00			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.34	94.12	50.00			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.27	68.81	25.00		0.00	42.55	20.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_count_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_spid_csb_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	100.00	100.00			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	100.00			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.03	90.27	78.43	96.94		78.12	86.36	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_count_sync	100.00	100.00				100.00

Line Coverage for Module : spid_csb_sync

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	32	4	4	100.00
ALWAYS	44	3	3	100.00
ALWAYS	63	3	3	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
33	1	1
35	1	1
36	1	1
			MISSING_ELSE
44	1	1
45	1	1
47	1	1
63	1	1
64	1	1
66	1	1
70	1	1

---

Cond Coverage for Module : spid_csb_sync

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sys_toggle != sys_toggle_last)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

Branch Coverage for Module : spid_csb_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
IF	32	3	3	100.00
IF	44	2	2	100.00
IF	63	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	35	if (sck_pulse_en_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	44	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set

	Line No.	Total	Covered	Percent
TOTAL		11	10	90.91
ALWAYS	32	4	3	75.00
ALWAYS	44	3	3	100.00
ALWAYS	63	3	3	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
33	1	1
35	1	1
36	0	1
			MISSING_ELSE
44	1	1
45	1	1
47	1	1
63	1	1
64	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sys_toggle != sys_toggle_last)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
IF	32	3	2	66.67
IF	44	2	2	100.00
IF	63	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	35	if (sck_pulse_en_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	44	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_csb_sync

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	32	4	4	100.00
ALWAYS	44	3	3	100.00
ALWAYS	63	3	3	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
33	1	1
35	1	1
36	1	1
			==> MISSING_ELSE
44	1	1
45	1	1
47	1	1
63	1	1
64	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.u_spid_csb_sync

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sys_toggle != sys_toggle_last)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_spid_csb_sync

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
IF	32	3	2	66.67
IF	44	2	2	100.00
IF	63	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	35	if (sck_pulse_en_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Not Covered

	LineNo.	Expression
-1-:	44	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3