Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3815 |
0 |
0 |
T40 |
53916 |
4 |
0 |
0 |
T41 |
5733 |
13 |
0 |
0 |
T119 |
6415 |
281 |
0 |
0 |
T120 |
2275 |
2 |
0 |
0 |
T121 |
4922 |
83 |
0 |
0 |
T124 |
28172 |
3 |
0 |
0 |
T125 |
107869 |
1 |
0 |
0 |
T126 |
2717 |
46 |
0 |
0 |
T130 |
11432 |
177 |
0 |
0 |
T139 |
55807 |
5 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3587 |
0 |
0 |
T125 |
107869 |
97 |
0 |
0 |
T133 |
6646 |
7 |
0 |
0 |
T134 |
103912 |
412 |
0 |
0 |
T142 |
4636 |
2 |
0 |
0 |
T144 |
7047 |
7 |
0 |
0 |
T146 |
111087 |
761 |
0 |
0 |
T150 |
78394 |
123 |
0 |
0 |
T157 |
17874 |
77 |
0 |
0 |
T160 |
21007 |
34 |
0 |
0 |
T161 |
18260 |
49 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3482 |
0 |
0 |
T125 |
107869 |
110 |
0 |
0 |
T134 |
103912 |
391 |
0 |
0 |
T142 |
4636 |
4 |
0 |
0 |
T144 |
7047 |
2 |
0 |
0 |
T146 |
111087 |
756 |
0 |
0 |
T150 |
78394 |
112 |
0 |
0 |
T157 |
17874 |
33 |
0 |
0 |
T160 |
21007 |
96 |
0 |
0 |
T161 |
18260 |
44 |
0 |
0 |
T162 |
14995 |
75 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
4007 |
0 |
0 |
T125 |
107869 |
277 |
0 |
0 |
T134 |
103912 |
463 |
0 |
0 |
T142 |
4636 |
6 |
0 |
0 |
T144 |
7047 |
5 |
0 |
0 |
T146 |
111087 |
738 |
0 |
0 |
T150 |
78394 |
152 |
0 |
0 |
T157 |
17874 |
51 |
0 |
0 |
T160 |
21007 |
96 |
0 |
0 |
T161 |
18260 |
55 |
0 |
0 |
T162 |
14995 |
28 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
9932 |
0 |
0 |
T125 |
107869 |
2407 |
0 |
0 |
T134 |
103912 |
411 |
0 |
0 |
T142 |
4636 |
7 |
0 |
0 |
T144 |
7047 |
2 |
0 |
0 |
T146 |
111087 |
699 |
0 |
0 |
T150 |
78394 |
147 |
0 |
0 |
T157 |
17874 |
52 |
0 |
0 |
T160 |
21007 |
93 |
0 |
0 |
T161 |
18260 |
25 |
0 |
0 |
T162 |
14995 |
67 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
9064 |
0 |
0 |
T125 |
107869 |
1715 |
0 |
0 |
T133 |
6646 |
79 |
0 |
0 |
T134 |
103912 |
472 |
0 |
0 |
T142 |
4636 |
143 |
0 |
0 |
T144 |
7047 |
63 |
0 |
0 |
T146 |
111087 |
764 |
0 |
0 |
T150 |
78394 |
125 |
0 |
0 |
T157 |
17874 |
75 |
0 |
0 |
T160 |
21007 |
92 |
0 |
0 |
T161 |
18260 |
31 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
8818 |
0 |
0 |
T125 |
107869 |
2029 |
0 |
0 |
T133 |
6646 |
49 |
0 |
0 |
T134 |
103912 |
453 |
0 |
0 |
T142 |
4636 |
2 |
0 |
0 |
T144 |
7047 |
160 |
0 |
0 |
T146 |
111087 |
698 |
0 |
0 |
T150 |
78394 |
103 |
0 |
0 |
T157 |
17874 |
41 |
0 |
0 |
T160 |
21007 |
59 |
0 |
0 |
T161 |
18260 |
22 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
9656 |
0 |
0 |
T125 |
107869 |
1589 |
0 |
0 |
T130 |
11432 |
8 |
0 |
0 |
T133 |
6646 |
74 |
0 |
0 |
T134 |
103912 |
501 |
0 |
0 |
T142 |
4636 |
112 |
0 |
0 |
T144 |
7047 |
58 |
0 |
0 |
T146 |
111087 |
774 |
0 |
0 |
T150 |
78394 |
124 |
0 |
0 |
T157 |
17874 |
57 |
0 |
0 |
T160 |
21007 |
109 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
7856 |
0 |
0 |
T125 |
107869 |
1447 |
0 |
0 |
T133 |
6646 |
68 |
0 |
0 |
T134 |
103912 |
400 |
0 |
0 |
T142 |
4636 |
121 |
0 |
0 |
T144 |
7047 |
100 |
0 |
0 |
T146 |
111087 |
769 |
0 |
0 |
T150 |
78394 |
144 |
0 |
0 |
T157 |
17874 |
55 |
0 |
0 |
T160 |
21007 |
78 |
0 |
0 |
T161 |
18260 |
29 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
9112 |
0 |
0 |
T125 |
107869 |
2191 |
0 |
0 |
T130 |
11432 |
1 |
0 |
0 |
T134 |
103912 |
467 |
0 |
0 |
T142 |
4636 |
95 |
0 |
0 |
T144 |
7047 |
4 |
0 |
0 |
T146 |
111087 |
706 |
0 |
0 |
T150 |
78394 |
137 |
0 |
0 |
T157 |
17874 |
63 |
0 |
0 |
T160 |
21007 |
108 |
0 |
0 |
T161 |
18260 |
21 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
9276 |
0 |
0 |
T125 |
107869 |
1442 |
0 |
0 |
T130 |
11432 |
8 |
0 |
0 |
T133 |
6646 |
76 |
0 |
0 |
T134 |
103912 |
428 |
0 |
0 |
T142 |
4636 |
102 |
0 |
0 |
T146 |
111087 |
814 |
0 |
0 |
T150 |
78394 |
128 |
0 |
0 |
T157 |
17874 |
34 |
0 |
0 |
T160 |
21007 |
49 |
0 |
0 |
T161 |
18260 |
43 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
9255 |
0 |
0 |
T125 |
107869 |
2343 |
0 |
0 |
T132 |
22171 |
5 |
0 |
0 |
T133 |
6646 |
49 |
0 |
0 |
T134 |
103912 |
481 |
0 |
0 |
T142 |
4636 |
2 |
0 |
0 |
T144 |
7047 |
50 |
0 |
0 |
T146 |
111087 |
757 |
0 |
0 |
T150 |
78394 |
130 |
0 |
0 |
T157 |
17874 |
107 |
0 |
0 |
T160 |
21007 |
90 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5598 |
0 |
0 |
T125 |
107869 |
783 |
0 |
0 |
T131 |
15757 |
2 |
0 |
0 |
T133 |
6646 |
28 |
0 |
0 |
T134 |
103912 |
418 |
0 |
0 |
T142 |
4636 |
6 |
0 |
0 |
T144 |
7047 |
36 |
0 |
0 |
T146 |
111087 |
748 |
0 |
0 |
T150 |
78394 |
146 |
0 |
0 |
T157 |
17874 |
61 |
0 |
0 |
T160 |
21007 |
99 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5747 |
0 |
0 |
T125 |
107869 |
893 |
0 |
0 |
T133 |
6646 |
20 |
0 |
0 |
T134 |
103912 |
420 |
0 |
0 |
T142 |
4636 |
4 |
0 |
0 |
T144 |
7047 |
20 |
0 |
0 |
T146 |
111087 |
712 |
0 |
0 |
T150 |
78394 |
136 |
0 |
0 |
T157 |
17874 |
31 |
0 |
0 |
T160 |
21007 |
53 |
0 |
0 |
T161 |
18260 |
28 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5428 |
0 |
0 |
T125 |
107869 |
787 |
0 |
0 |
T133 |
6646 |
8 |
0 |
0 |
T134 |
103912 |
372 |
0 |
0 |
T142 |
4636 |
7 |
0 |
0 |
T146 |
111087 |
729 |
0 |
0 |
T150 |
78394 |
123 |
0 |
0 |
T157 |
17874 |
57 |
0 |
0 |
T160 |
21007 |
75 |
0 |
0 |
T161 |
18260 |
36 |
0 |
0 |
T162 |
14995 |
48 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5393 |
0 |
0 |
T125 |
107869 |
727 |
0 |
0 |
T133 |
6646 |
11 |
0 |
0 |
T134 |
103912 |
435 |
0 |
0 |
T142 |
4636 |
2 |
0 |
0 |
T144 |
7047 |
62 |
0 |
0 |
T146 |
111087 |
671 |
0 |
0 |
T150 |
78394 |
128 |
0 |
0 |
T157 |
17874 |
49 |
0 |
0 |
T160 |
21007 |
91 |
0 |
0 |
T161 |
18260 |
28 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5705 |
0 |
0 |
T125 |
107869 |
785 |
0 |
0 |
T134 |
103912 |
361 |
0 |
0 |
T142 |
4636 |
6 |
0 |
0 |
T144 |
7047 |
35 |
0 |
0 |
T146 |
111087 |
666 |
0 |
0 |
T150 |
78394 |
167 |
0 |
0 |
T157 |
17874 |
55 |
0 |
0 |
T160 |
21007 |
81 |
0 |
0 |
T161 |
18260 |
61 |
0 |
0 |
T162 |
14995 |
56 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5751 |
0 |
0 |
T125 |
107869 |
898 |
0 |
0 |
T133 |
6646 |
84 |
0 |
0 |
T134 |
103912 |
431 |
0 |
0 |
T142 |
4636 |
41 |
0 |
0 |
T144 |
7047 |
30 |
0 |
0 |
T146 |
111087 |
749 |
0 |
0 |
T150 |
78394 |
126 |
0 |
0 |
T157 |
17874 |
38 |
0 |
0 |
T160 |
21007 |
30 |
0 |
0 |
T161 |
18260 |
25 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5942 |
0 |
0 |
T125 |
107869 |
867 |
0 |
0 |
T133 |
6646 |
27 |
0 |
0 |
T134 |
103912 |
445 |
0 |
0 |
T142 |
4636 |
34 |
0 |
0 |
T144 |
7047 |
41 |
0 |
0 |
T146 |
111087 |
744 |
0 |
0 |
T150 |
78394 |
124 |
0 |
0 |
T157 |
17874 |
84 |
0 |
0 |
T160 |
21007 |
104 |
0 |
0 |
T161 |
18260 |
31 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5674 |
0 |
0 |
T125 |
107869 |
740 |
0 |
0 |
T133 |
6646 |
11 |
0 |
0 |
T134 |
103912 |
449 |
0 |
0 |
T142 |
4636 |
47 |
0 |
0 |
T144 |
7047 |
69 |
0 |
0 |
T146 |
111087 |
689 |
0 |
0 |
T150 |
78394 |
123 |
0 |
0 |
T157 |
17874 |
53 |
0 |
0 |
T160 |
21007 |
52 |
0 |
0 |
T161 |
18260 |
49 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
6258 |
0 |
0 |
T125 |
107869 |
895 |
0 |
0 |
T132 |
22171 |
3 |
0 |
0 |
T133 |
6646 |
52 |
0 |
0 |
T134 |
103912 |
509 |
0 |
0 |
T142 |
4636 |
40 |
0 |
0 |
T144 |
7047 |
24 |
0 |
0 |
T146 |
111087 |
738 |
0 |
0 |
T150 |
78394 |
128 |
0 |
0 |
T157 |
17874 |
102 |
0 |
0 |
T160 |
21007 |
83 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5927 |
0 |
0 |
T125 |
107869 |
702 |
0 |
0 |
T133 |
6646 |
23 |
0 |
0 |
T134 |
103912 |
401 |
0 |
0 |
T142 |
4636 |
5 |
0 |
0 |
T144 |
7047 |
7 |
0 |
0 |
T146 |
111087 |
819 |
0 |
0 |
T150 |
78394 |
152 |
0 |
0 |
T157 |
17874 |
76 |
0 |
0 |
T160 |
21007 |
113 |
0 |
0 |
T161 |
18260 |
75 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5529 |
0 |
0 |
T125 |
107869 |
739 |
0 |
0 |
T133 |
6646 |
43 |
0 |
0 |
T134 |
103912 |
443 |
0 |
0 |
T144 |
7047 |
57 |
0 |
0 |
T146 |
111087 |
725 |
0 |
0 |
T150 |
78394 |
92 |
0 |
0 |
T157 |
17874 |
24 |
0 |
0 |
T160 |
21007 |
57 |
0 |
0 |
T161 |
18260 |
88 |
0 |
0 |
T162 |
14995 |
41 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5693 |
0 |
0 |
T125 |
107869 |
809 |
0 |
0 |
T133 |
6646 |
27 |
0 |
0 |
T134 |
103912 |
456 |
0 |
0 |
T142 |
4636 |
34 |
0 |
0 |
T144 |
7047 |
32 |
0 |
0 |
T146 |
111087 |
805 |
0 |
0 |
T150 |
78394 |
160 |
0 |
0 |
T157 |
17874 |
81 |
0 |
0 |
T160 |
21007 |
113 |
0 |
0 |
T161 |
18260 |
43 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5627 |
0 |
0 |
T125 |
107869 |
782 |
0 |
0 |
T130 |
11432 |
1 |
0 |
0 |
T133 |
6646 |
21 |
0 |
0 |
T134 |
103912 |
481 |
0 |
0 |
T142 |
4636 |
2 |
0 |
0 |
T144 |
7047 |
15 |
0 |
0 |
T146 |
111087 |
767 |
0 |
0 |
T150 |
78394 |
129 |
0 |
0 |
T157 |
17874 |
15 |
0 |
0 |
T160 |
21007 |
146 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5857 |
0 |
0 |
T125 |
107869 |
732 |
0 |
0 |
T133 |
6646 |
8 |
0 |
0 |
T134 |
103912 |
447 |
0 |
0 |
T142 |
4636 |
54 |
0 |
0 |
T144 |
7047 |
42 |
0 |
0 |
T146 |
111087 |
727 |
0 |
0 |
T150 |
78394 |
124 |
0 |
0 |
T157 |
17874 |
58 |
0 |
0 |
T160 |
21007 |
32 |
0 |
0 |
T161 |
18260 |
49 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5730 |
0 |
0 |
T125 |
107869 |
879 |
0 |
0 |
T133 |
6646 |
66 |
0 |
0 |
T134 |
103912 |
416 |
0 |
0 |
T142 |
4636 |
8 |
0 |
0 |
T144 |
7047 |
37 |
0 |
0 |
T146 |
111087 |
775 |
0 |
0 |
T150 |
78394 |
120 |
0 |
0 |
T157 |
17874 |
76 |
0 |
0 |
T160 |
21007 |
53 |
0 |
0 |
T161 |
18260 |
39 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5356 |
0 |
0 |
T125 |
107869 |
830 |
0 |
0 |
T132 |
22171 |
5 |
0 |
0 |
T133 |
6646 |
47 |
0 |
0 |
T134 |
103912 |
452 |
0 |
0 |
T144 |
7047 |
38 |
0 |
0 |
T146 |
111087 |
736 |
0 |
0 |
T150 |
78394 |
132 |
0 |
0 |
T157 |
17874 |
81 |
0 |
0 |
T160 |
21007 |
83 |
0 |
0 |
T161 |
18260 |
22 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
6025 |
0 |
0 |
T125 |
107869 |
905 |
0 |
0 |
T133 |
6646 |
45 |
0 |
0 |
T134 |
103912 |
465 |
0 |
0 |
T142 |
4636 |
40 |
0 |
0 |
T144 |
7047 |
52 |
0 |
0 |
T146 |
111087 |
763 |
0 |
0 |
T150 |
78394 |
95 |
0 |
0 |
T157 |
17874 |
61 |
0 |
0 |
T160 |
21007 |
34 |
0 |
0 |
T161 |
18260 |
36 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5875 |
0 |
0 |
T125 |
107869 |
1020 |
0 |
0 |
T131 |
15757 |
1 |
0 |
0 |
T133 |
6646 |
54 |
0 |
0 |
T134 |
103912 |
391 |
0 |
0 |
T142 |
4636 |
5 |
0 |
0 |
T144 |
7047 |
4 |
0 |
0 |
T146 |
111087 |
671 |
0 |
0 |
T150 |
78394 |
136 |
0 |
0 |
T157 |
17874 |
65 |
0 |
0 |
T160 |
21007 |
75 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5740 |
0 |
0 |
T125 |
107869 |
847 |
0 |
0 |
T133 |
6646 |
82 |
0 |
0 |
T134 |
103912 |
477 |
0 |
0 |
T142 |
4636 |
4 |
0 |
0 |
T144 |
7047 |
30 |
0 |
0 |
T146 |
111087 |
672 |
0 |
0 |
T150 |
78394 |
156 |
0 |
0 |
T157 |
17874 |
93 |
0 |
0 |
T160 |
21007 |
97 |
0 |
0 |
T161 |
18260 |
62 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5951 |
0 |
0 |
T125 |
107869 |
834 |
0 |
0 |
T133 |
6646 |
19 |
0 |
0 |
T134 |
103912 |
478 |
0 |
0 |
T142 |
4636 |
7 |
0 |
0 |
T144 |
7047 |
10 |
0 |
0 |
T146 |
111087 |
772 |
0 |
0 |
T150 |
78394 |
161 |
0 |
0 |
T157 |
17874 |
35 |
0 |
0 |
T160 |
21007 |
77 |
0 |
0 |
T161 |
18260 |
33 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5612 |
0 |
0 |
T125 |
107869 |
667 |
0 |
0 |
T133 |
6646 |
24 |
0 |
0 |
T134 |
103912 |
531 |
0 |
0 |
T142 |
4636 |
2 |
0 |
0 |
T144 |
7047 |
27 |
0 |
0 |
T146 |
111087 |
735 |
0 |
0 |
T150 |
78394 |
158 |
0 |
0 |
T157 |
17874 |
60 |
0 |
0 |
T160 |
21007 |
98 |
0 |
0 |
T161 |
18260 |
49 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5729 |
0 |
0 |
T125 |
107869 |
825 |
0 |
0 |
T130 |
11432 |
3 |
0 |
0 |
T133 |
6646 |
28 |
0 |
0 |
T134 |
103912 |
442 |
0 |
0 |
T142 |
4636 |
51 |
0 |
0 |
T144 |
7047 |
37 |
0 |
0 |
T146 |
111087 |
681 |
0 |
0 |
T150 |
78394 |
114 |
0 |
0 |
T157 |
17874 |
55 |
0 |
0 |
T160 |
21007 |
62 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5602 |
0 |
0 |
T125 |
107869 |
842 |
0 |
0 |
T134 |
103912 |
459 |
0 |
0 |
T142 |
4636 |
41 |
0 |
0 |
T144 |
7047 |
39 |
0 |
0 |
T146 |
111087 |
728 |
0 |
0 |
T150 |
78394 |
145 |
0 |
0 |
T157 |
17874 |
71 |
0 |
0 |
T160 |
21007 |
43 |
0 |
0 |
T161 |
18260 |
22 |
0 |
0 |
T162 |
14995 |
26 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5805 |
0 |
0 |
T125 |
107869 |
735 |
0 |
0 |
T133 |
6646 |
17 |
0 |
0 |
T134 |
103912 |
456 |
0 |
0 |
T142 |
4636 |
6 |
0 |
0 |
T144 |
7047 |
33 |
0 |
0 |
T146 |
111087 |
761 |
0 |
0 |
T150 |
78394 |
133 |
0 |
0 |
T157 |
17874 |
66 |
0 |
0 |
T160 |
21007 |
73 |
0 |
0 |
T161 |
18260 |
49 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3715 |
0 |
0 |
T125 |
107869 |
182 |
0 |
0 |
T133 |
6646 |
8 |
0 |
0 |
T134 |
103912 |
382 |
0 |
0 |
T142 |
4636 |
9 |
0 |
0 |
T144 |
7047 |
7 |
0 |
0 |
T146 |
111087 |
768 |
0 |
0 |
T150 |
78394 |
159 |
0 |
0 |
T157 |
17874 |
44 |
0 |
0 |
T160 |
21007 |
63 |
0 |
0 |
T161 |
18260 |
39 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3394 |
0 |
0 |
T125 |
107869 |
208 |
0 |
0 |
T133 |
6646 |
3 |
0 |
0 |
T134 |
103912 |
415 |
0 |
0 |
T142 |
4636 |
1 |
0 |
0 |
T144 |
7047 |
10 |
0 |
0 |
T146 |
111087 |
665 |
0 |
0 |
T150 |
78394 |
78 |
0 |
0 |
T157 |
17874 |
14 |
0 |
0 |
T160 |
21007 |
53 |
0 |
0 |
T161 |
18260 |
20 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3854 |
0 |
0 |
T125 |
107869 |
184 |
0 |
0 |
T133 |
6646 |
5 |
0 |
0 |
T134 |
103912 |
419 |
0 |
0 |
T144 |
7047 |
7 |
0 |
0 |
T146 |
111087 |
789 |
0 |
0 |
T150 |
78394 |
168 |
0 |
0 |
T157 |
17874 |
56 |
0 |
0 |
T160 |
21007 |
73 |
0 |
0 |
T161 |
18260 |
52 |
0 |
0 |
T162 |
14995 |
66 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3816 |
0 |
0 |
T125 |
107869 |
171 |
0 |
0 |
T133 |
6646 |
4 |
0 |
0 |
T134 |
103912 |
486 |
0 |
0 |
T142 |
4636 |
4 |
0 |
0 |
T144 |
7047 |
1 |
0 |
0 |
T146 |
111087 |
716 |
0 |
0 |
T150 |
78394 |
147 |
0 |
0 |
T157 |
17874 |
93 |
0 |
0 |
T160 |
21007 |
63 |
0 |
0 |
T161 |
18260 |
14 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
4144 |
0 |
0 |
T125 |
107869 |
355 |
0 |
0 |
T134 |
103912 |
444 |
0 |
0 |
T142 |
4636 |
16 |
0 |
0 |
T144 |
7047 |
6 |
0 |
0 |
T146 |
111087 |
752 |
0 |
0 |
T150 |
78394 |
129 |
0 |
0 |
T157 |
17874 |
49 |
0 |
0 |
T160 |
21007 |
62 |
0 |
0 |
T161 |
18260 |
34 |
0 |
0 |
T162 |
14995 |
46 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
5294 |
0 |
0 |
T2 |
4727 |
42 |
0 |
0 |
T3 |
212601 |
0 |
0 |
0 |
T4 |
14155 |
0 |
0 |
0 |
T5 |
665039 |
0 |
0 |
0 |
T6 |
307946 |
0 |
0 |
0 |
T7 |
38044 |
0 |
0 |
0 |
T8 |
29474 |
0 |
0 |
0 |
T9 |
20807 |
0 |
0 |
0 |
T12 |
14036 |
0 |
0 |
0 |
T14 |
857 |
0 |
0 |
0 |
T43 |
0 |
92 |
0 |
0 |
T134 |
0 |
480 |
0 |
0 |
T142 |
0 |
8 |
0 |
0 |
T144 |
0 |
37 |
0 |
0 |
T163 |
0 |
60 |
0 |
0 |
T164 |
0 |
69 |
0 |
0 |
T165 |
0 |
17 |
0 |
0 |
T166 |
0 |
21 |
0 |
0 |
T167 |
0 |
10 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3589 |
0 |
0 |
T125 |
107869 |
191 |
0 |
0 |
T134 |
103912 |
414 |
0 |
0 |
T142 |
4636 |
4 |
0 |
0 |
T144 |
7047 |
17 |
0 |
0 |
T146 |
111087 |
729 |
0 |
0 |
T150 |
78394 |
126 |
0 |
0 |
T157 |
17874 |
39 |
0 |
0 |
T160 |
21007 |
25 |
0 |
0 |
T161 |
18260 |
41 |
0 |
0 |
T162 |
14995 |
64 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3552 |
0 |
0 |
T125 |
107869 |
192 |
0 |
0 |
T131 |
15757 |
16 |
0 |
0 |
T133 |
6646 |
7 |
0 |
0 |
T134 |
103912 |
389 |
0 |
0 |
T142 |
4636 |
6 |
0 |
0 |
T144 |
7047 |
3 |
0 |
0 |
T146 |
111087 |
766 |
0 |
0 |
T150 |
78394 |
155 |
0 |
0 |
T157 |
17874 |
81 |
0 |
0 |
T160 |
21007 |
72 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3681 |
0 |
0 |
T125 |
107869 |
134 |
0 |
0 |
T133 |
6646 |
2 |
0 |
0 |
T134 |
103912 |
468 |
0 |
0 |
T142 |
4636 |
4 |
0 |
0 |
T144 |
7047 |
10 |
0 |
0 |
T146 |
111087 |
714 |
0 |
0 |
T150 |
78394 |
161 |
0 |
0 |
T157 |
17874 |
36 |
0 |
0 |
T160 |
21007 |
65 |
0 |
0 |
T161 |
18260 |
34 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3425 |
0 |
0 |
T125 |
107869 |
120 |
0 |
0 |
T133 |
6646 |
2 |
0 |
0 |
T134 |
103912 |
451 |
0 |
0 |
T142 |
4636 |
3 |
0 |
0 |
T146 |
111087 |
704 |
0 |
0 |
T150 |
78394 |
119 |
0 |
0 |
T157 |
17874 |
49 |
0 |
0 |
T160 |
21007 |
58 |
0 |
0 |
T161 |
18260 |
14 |
0 |
0 |
T162 |
14995 |
47 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3400 |
0 |
0 |
T125 |
107869 |
118 |
0 |
0 |
T133 |
6646 |
4 |
0 |
0 |
T134 |
103912 |
391 |
0 |
0 |
T142 |
4636 |
3 |
0 |
0 |
T144 |
7047 |
4 |
0 |
0 |
T146 |
111087 |
724 |
0 |
0 |
T150 |
78394 |
113 |
0 |
0 |
T157 |
17874 |
74 |
0 |
0 |
T160 |
21007 |
51 |
0 |
0 |
T161 |
18260 |
38 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3769 |
0 |
0 |
T125 |
107869 |
114 |
0 |
0 |
T134 |
103912 |
462 |
0 |
0 |
T142 |
4636 |
3 |
0 |
0 |
T144 |
7047 |
10 |
0 |
0 |
T146 |
111087 |
747 |
0 |
0 |
T150 |
78394 |
147 |
0 |
0 |
T157 |
17874 |
37 |
0 |
0 |
T160 |
21007 |
131 |
0 |
0 |
T161 |
18260 |
36 |
0 |
0 |
T162 |
14995 |
69 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
4183 |
0 |
0 |
T125 |
107869 |
283 |
0 |
0 |
T133 |
6646 |
6 |
0 |
0 |
T134 |
103912 |
472 |
0 |
0 |
T142 |
4636 |
14 |
0 |
0 |
T144 |
7047 |
4 |
0 |
0 |
T146 |
111087 |
764 |
0 |
0 |
T150 |
78394 |
160 |
0 |
0 |
T157 |
17874 |
93 |
0 |
0 |
T160 |
21007 |
54 |
0 |
0 |
T161 |
18260 |
37 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3576 |
0 |
0 |
T125 |
107869 |
123 |
0 |
0 |
T134 |
103912 |
488 |
0 |
0 |
T142 |
4636 |
7 |
0 |
0 |
T144 |
7047 |
1 |
0 |
0 |
T146 |
111087 |
689 |
0 |
0 |
T150 |
78394 |
104 |
0 |
0 |
T157 |
17874 |
97 |
0 |
0 |
T160 |
21007 |
56 |
0 |
0 |
T161 |
18260 |
10 |
0 |
0 |
T162 |
14995 |
50 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
4200 |
0 |
0 |
T125 |
107869 |
338 |
0 |
0 |
T133 |
6646 |
16 |
0 |
0 |
T134 |
103912 |
404 |
0 |
0 |
T142 |
4636 |
2 |
0 |
0 |
T144 |
7047 |
12 |
0 |
0 |
T146 |
111087 |
729 |
0 |
0 |
T150 |
78394 |
122 |
0 |
0 |
T157 |
17874 |
18 |
0 |
0 |
T160 |
21007 |
39 |
0 |
0 |
T161 |
18260 |
101 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3709 |
0 |
0 |
T125 |
107869 |
161 |
0 |
0 |
T132 |
22171 |
5 |
0 |
0 |
T133 |
6646 |
8 |
0 |
0 |
T134 |
103912 |
452 |
0 |
0 |
T142 |
4636 |
14 |
0 |
0 |
T144 |
7047 |
13 |
0 |
0 |
T146 |
111087 |
735 |
0 |
0 |
T150 |
78394 |
130 |
0 |
0 |
T157 |
17874 |
67 |
0 |
0 |
T160 |
21007 |
55 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3529 |
0 |
0 |
T125 |
107869 |
87 |
0 |
0 |
T133 |
6646 |
4 |
0 |
0 |
T134 |
103912 |
406 |
0 |
0 |
T142 |
4636 |
1 |
0 |
0 |
T146 |
111087 |
768 |
0 |
0 |
T150 |
78394 |
161 |
0 |
0 |
T157 |
17874 |
44 |
0 |
0 |
T160 |
21007 |
62 |
0 |
0 |
T161 |
18260 |
30 |
0 |
0 |
T162 |
14995 |
48 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3503 |
0 |
0 |
T125 |
107869 |
111 |
0 |
0 |
T133 |
6646 |
3 |
0 |
0 |
T134 |
103912 |
423 |
0 |
0 |
T142 |
4636 |
3 |
0 |
0 |
T144 |
7047 |
9 |
0 |
0 |
T146 |
111087 |
769 |
0 |
0 |
T150 |
78394 |
172 |
0 |
0 |
T157 |
17874 |
70 |
0 |
0 |
T160 |
21007 |
115 |
0 |
0 |
T161 |
18260 |
29 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3394 |
0 |
0 |
T125 |
107869 |
90 |
0 |
0 |
T133 |
6646 |
9 |
0 |
0 |
T134 |
103912 |
407 |
0 |
0 |
T142 |
4636 |
6 |
0 |
0 |
T144 |
7047 |
5 |
0 |
0 |
T146 |
111087 |
711 |
0 |
0 |
T150 |
78394 |
125 |
0 |
0 |
T157 |
17874 |
98 |
0 |
0 |
T160 |
21007 |
35 |
0 |
0 |
T161 |
18260 |
26 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3621 |
0 |
0 |
T125 |
107869 |
143 |
0 |
0 |
T133 |
6646 |
5 |
0 |
0 |
T134 |
103912 |
407 |
0 |
0 |
T142 |
4636 |
8 |
0 |
0 |
T144 |
7047 |
1 |
0 |
0 |
T146 |
111087 |
672 |
0 |
0 |
T150 |
78394 |
151 |
0 |
0 |
T157 |
17874 |
61 |
0 |
0 |
T160 |
21007 |
88 |
0 |
0 |
T161 |
18260 |
64 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3733 |
0 |
0 |
T125 |
107869 |
129 |
0 |
0 |
T131 |
15757 |
7 |
0 |
0 |
T134 |
103912 |
467 |
0 |
0 |
T142 |
4636 |
3 |
0 |
0 |
T144 |
7047 |
2 |
0 |
0 |
T146 |
111087 |
753 |
0 |
0 |
T150 |
78394 |
159 |
0 |
0 |
T157 |
17874 |
82 |
0 |
0 |
T160 |
21007 |
38 |
0 |
0 |
T161 |
18260 |
37 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112478380 |
3581 |
0 |
0 |
T125 |
107869 |
119 |
0 |
0 |
T133 |
6646 |
3 |
0 |
0 |
T134 |
103912 |
401 |
0 |
0 |
T142 |
4636 |
3 |
0 |
0 |
T146 |
111087 |
694 |
0 |
0 |
T150 |
78394 |
155 |
0 |
0 |
T157 |
17874 |
78 |
0 |
0 |
T160 |
21007 |
47 |
0 |
0 |
T161 |
18260 |
62 |
0 |
0 |
T162 |
14995 |
23 |
0 |
0 |