Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3709946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4124582

1

T1

26

T2

2238

T3

936

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4343387	1			T1	1		T2	2837		T3	77
values[0x0]	1745042	1			T1	18		T2	454		T3	471
values[0x1]	1746099	1			T1	13		T2	437		T3	422

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2622853	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5211675

1

T1

26

T2

2513

T3

942

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29101	1			T3	2		T5	1		T6	17
valid_sources[0x01]	31254	1			T2	5		T3	2		T6	6
valid_sources[0x02]	27378	1			T2	66		T3	6		T6	6
valid_sources[0x03]	26829	1			T2	12		T3	7		T8	231
valid_sources[0x04]	30714	1			T3	8		T6	1		T8	267
valid_sources[0x05]	28788	1			T2	36		T3	5		T6	5
valid_sources[0x06]	29415	1			T3	2		T6	5		T8	191
valid_sources[0x07]	28003	1			T3	6		T6	11		T7	1
valid_sources[0x08]	29614	1			T3	6		T6	4		T8	220
valid_sources[0x09]	30352	1			T3	6		T6	4		T8	224
valid_sources[0x0a]	39990	1			T3	7		T6	10		T8	240
valid_sources[0x0b]	31384	1			T3	3		T6	7		T7	1
valid_sources[0x0c]	28641	1			T3	2		T6	16		T8	223
valid_sources[0x0d]	30278	1			T3	4		T6	24		T8	225
valid_sources[0x0e]	35270	1			T3	3		T6	2		T8	234
valid_sources[0x0f]	32098	1			T3	3		T6	14		T8	226
valid_sources[0x10]	30053	1			T2	12		T3	2		T6	7
valid_sources[0x11]	31022	1			T3	5		T8	226		T9	17
valid_sources[0x12]	31531	1			T3	2		T6	8		T7	1
valid_sources[0x13]	29364	1			T3	2		T5	1		T8	235
valid_sources[0x14]	28210	1			T3	5		T6	2		T7	1
valid_sources[0x15]	31847	1			T3	7		T8	240		T9	17
valid_sources[0x16]	29487	1			T3	2		T8	231		T9	11
valid_sources[0x17]	30005	1			T3	2		T6	3		T8	221
valid_sources[0x18]	29827	1			T3	6		T8	225		T9	18
valid_sources[0x19]	29201	1			T2	187		T3	9		T6	13
valid_sources[0x1a]	29022	1			T3	3		T6	4		T8	258
valid_sources[0x1b]	34814	1			T3	7		T6	11		T8	219
valid_sources[0x1c]	29192	1			T3	1		T6	1		T8	199
valid_sources[0x1d]	33319	1			T2	42		T3	3		T6	3
valid_sources[0x1e]	32290	1			T3	5		T6	14		T8	213
valid_sources[0x1f]	37673	1			T2	50		T3	5		T6	7
valid_sources[0x20]	27762	1			T3	5		T5	11		T6	2
valid_sources[0x21]	28143	1			T3	6		T6	14		T8	223
valid_sources[0x22]	43570	1			T2	90		T3	6		T6	6
valid_sources[0x23]	29119	1			T2	3		T3	2		T6	31
valid_sources[0x24]	29335	1			T3	3		T6	11		T8	204
valid_sources[0x25]	29762	1			T3	9		T5	2		T7	1
valid_sources[0x26]	30626	1			T3	1		T6	38		T8	240
valid_sources[0x27]	29400	1			T3	2		T5	7		T6	1
valid_sources[0x28]	29644	1			T3	5		T6	4		T8	260
valid_sources[0x29]	32100	1			T2	12		T3	3		T6	7
valid_sources[0x2a]	30495	1			T3	1		T6	10		T8	186
valid_sources[0x2b]	30289	1			T3	4		T6	1		T8	260
valid_sources[0x2c]	29314	1			T3	3		T8	249		T9	8
valid_sources[0x2d]	32350	1			T3	5		T5	2		T6	19
valid_sources[0x2e]	28450	1			T2	36		T3	3		T8	208
valid_sources[0x2f]	29908	1			T2	51		T3	8		T6	6
valid_sources[0x30]	39607	1			T2	45		T3	9		T5	2
valid_sources[0x31]	29072	1			T3	10		T6	3		T8	240
valid_sources[0x32]	31873	1			T2	61		T3	3		T6	2
valid_sources[0x33]	29914	1			T3	5		T6	12		T8	228
valid_sources[0x34]	28376	1			T3	2		T6	5		T8	242
valid_sources[0x35]	31245	1			T3	2		T6	27		T8	247
valid_sources[0x36]	26969	1			T2	11		T3	2		T5	2
valid_sources[0x37]	29735	1			T3	6		T6	12		T8	233
valid_sources[0x38]	37491	1			T3	1		T5	1		T6	8
valid_sources[0x39]	30256	1			T3	5		T8	246		T9	8
valid_sources[0x3a]	30745	1			T2	34		T3	7		T6	5
valid_sources[0x3b]	30970	1			T2	14		T3	1		T6	4
valid_sources[0x3c]	32173	1			T2	139		T3	2		T8	205
valid_sources[0x3d]	33231	1			T2	82		T3	5		T6	12
valid_sources[0x3e]	29800	1			T3	2		T6	2		T8	224
valid_sources[0x3f]	31084	1			T3	1		T6	16		T8	238
valid_sources[0x40]	32775	1			T2	37		T3	1		T6	7
valid_sources[0x41]	31030	1			T2	23		T3	4		T6	11
valid_sources[0x42]	29586	1			T3	4		T6	13		T8	228
valid_sources[0x43]	29893	1			T2	1		T3	5		T6	7
valid_sources[0x44]	30716	1			T2	2		T3	7		T6	5
valid_sources[0x45]	31425	1			T1	32		T2	12		T3	7
valid_sources[0x46]	32668	1			T2	84		T3	1		T6	7
valid_sources[0x47]	34067	1			T2	7		T3	6		T5	4
valid_sources[0x48]	30900	1			T2	41		T3	4		T8	229
valid_sources[0x49]	28952	1			T2	11		T8	250		T9	7
valid_sources[0x4a]	29631	1			T3	3		T6	15		T8	214
valid_sources[0x4b]	29231	1			T3	6		T5	6		T6	10
valid_sources[0x4c]	27441	1			T3	1		T6	13		T8	247
valid_sources[0x4d]	30020	1			T3	3		T6	1		T8	208
valid_sources[0x4e]	26829	1			T2	20		T3	3		T5	1
valid_sources[0x4f]	28086	1			T2	136		T3	6		T6	6
valid_sources[0x50]	31060	1			T3	2		T6	14		T8	212
valid_sources[0x51]	28544	1			T3	1		T6	6		T8	241
valid_sources[0x52]	29259	1			T2	68		T3	1		T5	14
valid_sources[0x53]	27969	1			T3	3		T6	33		T7	1
valid_sources[0x54]	27699	1			T3	1		T6	19		T8	228
valid_sources[0x55]	33832	1			T3	5		T6	2		T8	225
valid_sources[0x56]	33287	1			T2	18		T3	2		T6	18
valid_sources[0x57]	30678	1			T3	3		T5	8		T6	5
valid_sources[0x58]	32588	1			T3	2		T6	14		T8	229
valid_sources[0x59]	29126	1			T3	2		T6	5		T8	222
valid_sources[0x5a]	30129	1			T3	2		T6	4		T8	212
valid_sources[0x5b]	28904	1			T3	7		T6	6		T8	212
valid_sources[0x5c]	30429	1			T3	4		T6	5		T8	223
valid_sources[0x5d]	32144	1			T2	9		T3	11		T6	14
valid_sources[0x5e]	33205	1			T2	2		T3	4		T6	9
valid_sources[0x5f]	30146	1			T3	8		T5	4		T8	233
valid_sources[0x60]	33993	1			T2	11		T3	3		T6	19
valid_sources[0x61]	28413	1			T2	67		T3	6		T6	12
valid_sources[0x62]	34112	1			T2	24		T3	4		T6	1
valid_sources[0x63]	31839	1			T3	2		T5	6		T6	11
valid_sources[0x64]	28591	1			T3	2		T5	15		T8	227
valid_sources[0x65]	31209	1			T3	2		T6	17		T8	250
valid_sources[0x66]	27526	1			T2	18		T3	3		T8	235
valid_sources[0x67]	27783	1			T2	35		T3	7		T6	2
valid_sources[0x68]	29508	1			T2	15		T3	5		T8	229
valid_sources[0x69]	33040	1			T2	37		T3	8		T5	2
valid_sources[0x6a]	28872	1			T3	5		T5	3		T8	239
valid_sources[0x6b]	31290	1			T3	2		T5	7		T6	7
valid_sources[0x6c]	28115	1			T6	24		T8	215		T9	14
valid_sources[0x6d]	28919	1			T3	4		T5	3		T6	12
valid_sources[0x6e]	29734	1			T3	6		T6	14		T8	236
valid_sources[0x6f]	31130	1			T2	18		T3	3		T6	3
valid_sources[0x70]	30326	1			T2	1		T3	2		T6	17
valid_sources[0x71]	29875	1			T3	6		T6	5		T8	235
valid_sources[0x72]	29809	1			T3	3		T5	6		T8	216
valid_sources[0x73]	39931	1			T2	9		T3	5		T6	5
valid_sources[0x74]	31796	1			T2	39		T3	4		T6	13
valid_sources[0x75]	30190	1			T2	55		T3	4		T6	5
valid_sources[0x76]	28796	1			T2	8		T3	1		T6	4
valid_sources[0x77]	29865	1			T2	27		T3	5		T6	16
valid_sources[0x78]	30958	1			T3	4		T6	22		T8	216
valid_sources[0x79]	29825	1			T3	1		T6	10		T8	232
valid_sources[0x7a]	27741	1			T3	3		T5	5		T8	225
valid_sources[0x7b]	32302	1			T3	3		T6	12		T8	239
valid_sources[0x7c]	28855	1			T2	10		T3	5		T6	1
valid_sources[0x7d]	33993	1			T3	2		T6	4		T8	232
valid_sources[0x7e]	32266	1			T3	4		T5	5		T6	3
valid_sources[0x7f]	30543	1			T2	52		T3	2		T6	11
valid_sources[0x80]	36714	1			T5	3		T8	219		T9	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

982210

1

T1

1

T2

1354

T3

46

values[0x0]

all_enables

biggest_size

1583208

1

T1

15

T2

452

T3

470

values[0x1]

all_enables

biggest_size

1559164

1

T1

10

T2

432

T3

420