Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3726898

1

T1

6

T2

1490

T3

34

full_word

4123419

1

T1

26

T2

2238

T3

936

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7849907	1			T1	32		T2	3728		T3	970
auto[TlIntgErrCmd]	143	1			T98	7		T102	15		T103	8
auto[TlIntgErrData]	143	1			T98	2		T102	8		T103	4
auto[TlIntgErrBoth]	124	1			T98	1		T102	7		T103	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4344099

1

T1

1

T2

2837

T3

77

auto[1]

3506218

1

T1

31

T2

891

T3

893

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3361731	1			T2	1483		T3	31		T4	4
auto[TlIntgErrNone]	partial	auto[1]	364787	1			T1	6		T2	7		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	982182	1			T1	1		T2	1354		T3	46
auto[TlIntgErrNone]	full_word	auto[1]	3141207	1			T1	25		T2	884		T3	890
auto[TlIntgErrCmd]	partial	auto[0]	65	1			T98	3		T102	5		T103	4
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T98	3		T102	9		T103	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T253	1		T254	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T98	1		T102	1		T103	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T98	1		T102	3		T103	1
auto[TlIntgErrData]	partial	auto[1]	66	1			T98	1		T102	5		T103	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T103	2		T120	2		T165	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T253	1		T254	1		T255	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T102	4		T103	4		T120	4
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T102	3		T103	4		T120	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T120	1		T256	1		T257	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T98	1		T120	1		T121	1