Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T16
1	0	Covered	T8,T10,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Unreachable
1	1	Covered	T8,T10,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T16,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T16,T18
1	0	Covered	T8,T16,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T8,T16,T18

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T10
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	695164296	557590599	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	695164296	3256412	0	0
GntImpliesValid_A	695164296	3256412	0	0
GrantKnown_A	695164296	557590599	0	0
IdxKnown_A	695164296	557590599	0	0
IndexIsCorrect_A	695164296	3256412	0	0
LockArbDecision_A	695164296	0	0	0
NoReadyValidNoGrant_A	695164296	0	0	0
ReadyAndValidImplyGrant_A	695164296	3256412	0	0
ReqAndReadyImplyGrant_A	695164296	3256412	0	0
ReqImpliesValid_A	695164296	3256412	0	0
ReqStaysHighUntilGranted0_M	695164296	0	0	0
RoundRobin_A	695164296	5	0	926
ValidKnown_A	695164296	557590599	0	0
gen_data_port_assertion.DataFlow_A	695164296	3256412	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	557590599	0	0
T1	3683	3606	0	0
T2	113224	92634	0	0
T3	537537	304476	0	0
T4	1510	1416	0	0
T5	2502	2406	0	0
T6	203367	117251	0	0
T7	1156	1059	0	0
T8	2214047	1246964	0	0
T9	94764	85533	0	0
T10	648755	535607	0	0
T11	257960	128610	0	0
T12	61680	30840	0	0
T13	21488	10744	0	0
T14	25336	25336	0	0
T16	0	175248	0	0
T18	0	92568	0	0
T19	0	44720	0	0
T21	0	51632	0	0
T27	0	338880	0	0
T28	0	121672	0	0
T42	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	3256412	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	2214047	19254	0	0
T9	94764	832	0	0
T10	648755	6061	0	0
T11	777645	832	0	0
T12	61680	832	0	0
T13	21488	832	0	0
T14	50672	0	0	0
T15	30336	0	0	0
T16	257348	13015	0	0
T18	0	6891	0	0
T21	0	2295	0	0
T27	0	10570	0	0
T28	0	5594	0	0
T29	0	4155	0	0
T36	31728	0	0	0
T37	0	3578	0	0
T39	0	2183	0	0
T40	0	185	0	0
T41	0	4665	0	0
T43	0	274	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	3256412	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	2214047	19254	0	0
T9	94764	832	0	0
T10	648755	6061	0	0
T11	777645	832	0	0
T12	61680	832	0	0
T13	21488	832	0	0
T14	50672	0	0	0
T15	30336	0	0	0
T16	257348	13015	0	0
T18	0	6891	0	0
T21	0	2295	0	0
T27	0	10570	0	0
T28	0	5594	0	0
T29	0	4155	0	0
T36	31728	0	0	0
T37	0	3578	0	0
T39	0	2183	0	0
T40	0	185	0	0
T41	0	4665	0	0
T43	0	274	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	557590599	0	0
T1	3683	3606	0	0
T2	113224	92634	0	0
T3	537537	304476	0	0
T4	1510	1416	0	0
T5	2502	2406	0	0
T6	203367	117251	0	0
T7	1156	1059	0	0
T8	2214047	1246964	0	0
T9	94764	85533	0	0
T10	648755	535607	0	0
T11	257960	128610	0	0
T12	61680	30840	0	0
T13	21488	10744	0	0
T14	25336	25336	0	0
T16	0	175248	0	0
T18	0	92568	0	0
T19	0	44720	0	0
T21	0	51632	0	0
T27	0	338880	0	0
T28	0	121672	0	0
T42	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	557590599	0	0
T1	3683	3606	0	0
T2	113224	92634	0	0
T3	537537	304476	0	0
T4	1510	1416	0	0
T5	2502	2406	0	0
T6	203367	117251	0	0
T7	1156	1059	0	0
T8	2214047	1246964	0	0
T9	94764	85533	0	0
T10	648755	535607	0	0
T11	257960	128610	0	0
T12	61680	30840	0	0
T13	21488	10744	0	0
T14	25336	25336	0	0
T16	0	175248	0	0
T18	0	92568	0	0
T19	0	44720	0	0
T21	0	51632	0	0
T27	0	338880	0	0
T28	0	121672	0	0
T42	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	3256412	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	2214047	19254	0	0
T9	94764	832	0	0
T10	648755	6061	0	0
T11	777645	832	0	0
T12	61680	832	0	0
T13	21488	832	0	0
T14	50672	0	0	0
T15	30336	0	0	0
T16	257348	13015	0	0
T18	0	6891	0	0
T21	0	2295	0	0
T27	0	10570	0	0
T28	0	5594	0	0
T29	0	4155	0	0
T36	31728	0	0	0
T37	0	3578	0	0
T39	0	2183	0	0
T40	0	185	0	0
T41	0	4665	0	0
T43	0	274	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	3256412	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	2214047	19254	0	0
T9	94764	832	0	0
T10	648755	6061	0	0
T11	777645	832	0	0
T12	61680	832	0	0
T13	21488	832	0	0
T14	50672	0	0	0
T15	30336	0	0	0
T16	257348	13015	0	0
T18	0	6891	0	0
T21	0	2295	0	0
T27	0	10570	0	0
T28	0	5594	0	0
T29	0	4155	0	0
T36	31728	0	0	0
T37	0	3578	0	0
T39	0	2183	0	0
T40	0	185	0	0
T41	0	4665	0	0
T43	0	274	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	3256412	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	2214047	19254	0	0
T9	94764	832	0	0
T10	648755	6061	0	0
T11	777645	832	0	0
T12	61680	832	0	0
T13	21488	832	0	0
T14	50672	0	0	0
T15	30336	0	0	0
T16	257348	13015	0	0
T18	0	6891	0	0
T21	0	2295	0	0
T27	0	10570	0	0
T28	0	5594	0	0
T29	0	4155	0	0
T36	31728	0	0	0
T37	0	3578	0	0
T39	0	2183	0	0
T40	0	185	0	0
T41	0	4665	0	0
T43	0	274	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	3256412	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	2214047	19254	0	0
T9	94764	832	0	0
T10	648755	6061	0	0
T11	777645	832	0	0
T12	61680	832	0	0
T13	21488	832	0	0
T14	50672	0	0	0
T15	30336	0	0	0
T16	257348	13015	0	0
T18	0	6891	0	0
T21	0	2295	0	0
T27	0	10570	0	0
T28	0	5594	0	0
T29	0	4155	0	0
T36	31728	0	0	0
T37	0	3578	0	0
T39	0	2183	0	0
T40	0	185	0	0
T41	0	4665	0	0
T43	0	274	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	5	0	926
T44	230277	1	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	203547	0	0	1
T50	3431	0	0	1
T51	1808	0	0	1
T52	81139	0	0	1
T53	510992	0	0	1
T54	887658	0	0	1
T55	114419	0	0	1
T56	6120	0	0	1
T57	760986	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	557590599	0	0
T1	3683	3606	0	0
T2	113224	92634	0	0
T3	537537	304476	0	0
T4	1510	1416	0	0
T5	2502	2406	0	0
T6	203367	117251	0	0
T7	1156	1059	0	0
T8	2214047	1246964	0	0
T9	94764	85533	0	0
T10	648755	535607	0	0
T11	257960	128610	0	0
T12	61680	30840	0	0
T13	21488	10744	0	0
T14	25336	25336	0	0
T16	0	175248	0	0
T18	0	92568	0	0
T19	0	44720	0	0
T21	0	51632	0	0
T27	0	338880	0	0
T28	0	121672	0	0
T42	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695164296	3256412	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	2214047	19254	0	0
T9	94764	832	0	0
T10	648755	6061	0	0
T11	777645	832	0	0
T12	61680	832	0	0
T13	21488	832	0	0
T14	50672	0	0	0
T15	30336	0	0	0
T16	257348	13015	0	0
T18	0	6891	0	0
T21	0	2295	0	0
T27	0	10570	0	0
T28	0	5594	0	0
T29	0	4155	0	0
T36	31728	0	0	0
T37	0	3578	0	0
T39	0	2183	0	0
T40	0	185	0	0
T41	0	4665	0	0
T43	0	274	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T16
1	0	Covered	T8,T10,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Unreachable
1	1	Covered	T8,T10,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T10,T16
0	0	1	Unreachable
0	0	0	Covered	T1,T8,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	136149086	29526771	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	136149086	652131	0	0
GntImpliesValid_A	136149086	652131	0	0
GrantKnown_A	136149086	29526771	0	0
IdxKnown_A	136149086	29526771	0	0
IndexIsCorrect_A	136149086	652131	0	0
LockArbDecision_A	136149086	0	0	0
NoReadyValidNoGrant_A	136149086	0	0	0
ReadyAndValidImplyGrant_A	136149086	652131	0	0
ReqAndReadyImplyGrant_A	136149086	652131	0	0
ReqImpliesValid_A	136149086	652131	0	0
ReqStaysHighUntilGranted0_M	136149086	0	0	0
RoundRobin_A	136149086	0	0	0
ValidKnown_A	136149086	29526771	0	0
gen_data_port_assertion.DataFlow_A	136149086	652131	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	29526771	0	0
T1	720	720	0	0
T2	20500	0	0	0
T3	232793	0	0	0
T6	85535	0	0	0
T8	958634	72056	0	0
T9	9107	0	0	0
T10	108693	104328	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T16	0	175248	0	0
T18	0	92568	0	0
T19	0	44720	0	0
T21	0	51632	0	0
T27	0	338880	0	0
T28	0	121672	0	0
T42	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	652131	0	0
T8	958634	2280	0	0
T9	9107	0	0	0
T10	108693	4231	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	5663	0	0
T18	0	2822	0	0
T21	0	2289	0	0
T27	0	5792	0	0
T28	0	5579	0	0
T36	15864	0	0	0
T37	0	3578	0	0
T40	0	185	0	0
T41	0	3624	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	652131	0	0
T8	958634	2280	0	0
T9	9107	0	0	0
T10	108693	4231	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	5663	0	0
T18	0	2822	0	0
T21	0	2289	0	0
T27	0	5792	0	0
T28	0	5579	0	0
T36	15864	0	0	0
T37	0	3578	0	0
T40	0	185	0	0
T41	0	3624	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	29526771	0	0
T1	720	720	0	0
T2	20500	0	0	0
T3	232793	0	0	0
T6	85535	0	0	0
T8	958634	72056	0	0
T9	9107	0	0	0
T10	108693	104328	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T16	0	175248	0	0
T18	0	92568	0	0
T19	0	44720	0	0
T21	0	51632	0	0
T27	0	338880	0	0
T28	0	121672	0	0
T42	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	29526771	0	0
T1	720	720	0	0
T2	20500	0	0	0
T3	232793	0	0	0
T6	85535	0	0	0
T8	958634	72056	0	0
T9	9107	0	0	0
T10	108693	104328	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T16	0	175248	0	0
T18	0	92568	0	0
T19	0	44720	0	0
T21	0	51632	0	0
T27	0	338880	0	0
T28	0	121672	0	0
T42	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	652131	0	0
T8	958634	2280	0	0
T9	9107	0	0	0
T10	108693	4231	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	5663	0	0
T18	0	2822	0	0
T21	0	2289	0	0
T27	0	5792	0	0
T28	0	5579	0	0
T36	15864	0	0	0
T37	0	3578	0	0
T40	0	185	0	0
T41	0	3624	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	652131	0	0
T8	958634	2280	0	0
T9	9107	0	0	0
T10	108693	4231	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	5663	0	0
T18	0	2822	0	0
T21	0	2289	0	0
T27	0	5792	0	0
T28	0	5579	0	0
T36	15864	0	0	0
T37	0	3578	0	0
T40	0	185	0	0
T41	0	3624	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	652131	0	0
T8	958634	2280	0	0
T9	9107	0	0	0
T10	108693	4231	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	5663	0	0
T18	0	2822	0	0
T21	0	2289	0	0
T27	0	5792	0	0
T28	0	5579	0	0
T36	15864	0	0	0
T37	0	3578	0	0
T40	0	185	0	0
T41	0	3624	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	652131	0	0
T8	958634	2280	0	0
T9	9107	0	0	0
T10	108693	4231	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	5663	0	0
T18	0	2822	0	0
T21	0	2289	0	0
T27	0	5792	0	0
T28	0	5579	0	0
T36	15864	0	0	0
T37	0	3578	0	0
T40	0	185	0	0
T41	0	3624	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	29526771	0	0
T1	720	720	0	0
T2	20500	0	0	0
T3	232793	0	0	0
T6	85535	0	0	0
T8	958634	72056	0	0
T9	9107	0	0	0
T10	108693	104328	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T16	0	175248	0	0
T18	0	92568	0	0
T19	0	44720	0	0
T21	0	51632	0	0
T27	0	338880	0	0
T28	0	121672	0	0
T42	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	652131	0	0
T8	958634	2280	0	0
T9	9107	0	0	0
T10	108693	4231	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	5663	0	0
T18	0	2822	0	0
T21	0	2289	0	0
T27	0	5792	0	0
T28	0	5579	0	0
T36	15864	0	0	0
T37	0	3578	0	0
T40	0	185	0	0
T41	0	3624	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T16,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T16,T18
1	0	Covered	T8,T16,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T8,T16,T18

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T16,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T16,T18
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T16,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T16,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	136149086	105279968	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	136149086	481474	0	0
GntImpliesValid_A	136149086	481474	0	0
GrantKnown_A	136149086	105279968	0	0
IdxKnown_A	136149086	105279968	0	0
IndexIsCorrect_A	136149086	481474	0	0
LockArbDecision_A	136149086	0	0	0
NoReadyValidNoGrant_A	136149086	0	0	0
ReadyAndValidImplyGrant_A	136149086	481474	0	0
ReqAndReadyImplyGrant_A	136149086	481474	0	0
ReqImpliesValid_A	136149086	481474	0	0
ReqStaysHighUntilGranted0_M	136149086	0	0	0
RoundRobin_A	136149086	0	0	0
ValidKnown_A	136149086	105279968	0	0
gen_data_port_assertion.DataFlow_A	136149086	481474	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	105279968	0	0
T2	20500	20500	0	0
T3	232793	232580	0	0
T6	85535	85040	0	0
T8	958634	878136	0	0
T9	9107	9044	0	0
T10	108693	0	0	0
T11	128980	128610	0	0
T12	30840	30840	0	0
T13	10744	10744	0	0
T14	25336	25336	0	0
T15	0	15168	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	481474	0	0
T8	958634	3872	0	0
T9	9107	0	0	0
T10	108693	0	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	7352	0	0
T18	0	4069	0	0
T21	0	6	0	0
T27	0	4778	0	0
T28	0	15	0	0
T29	0	4155	0	0
T36	15864	0	0	0
T39	0	2183	0	0
T41	0	1041	0	0
T43	0	274	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	481474	0	0
T8	958634	3872	0	0
T9	9107	0	0	0
T10	108693	0	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	7352	0	0
T18	0	4069	0	0
T21	0	6	0	0
T27	0	4778	0	0
T28	0	15	0	0
T29	0	4155	0	0
T36	15864	0	0	0
T39	0	2183	0	0
T41	0	1041	0	0
T43	0	274	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	105279968	0	0
T2	20500	20500	0	0
T3	232793	232580	0	0
T6	85535	85040	0	0
T8	958634	878136	0	0
T9	9107	9044	0	0
T10	108693	0	0	0
T11	128980	128610	0	0
T12	30840	30840	0	0
T13	10744	10744	0	0
T14	25336	25336	0	0
T15	0	15168	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	105279968	0	0
T2	20500	20500	0	0
T3	232793	232580	0	0
T6	85535	85040	0	0
T8	958634	878136	0	0
T9	9107	9044	0	0
T10	108693	0	0	0
T11	128980	128610	0	0
T12	30840	30840	0	0
T13	10744	10744	0	0
T14	25336	25336	0	0
T15	0	15168	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	481474	0	0
T8	958634	3872	0	0
T9	9107	0	0	0
T10	108693	0	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	7352	0	0
T18	0	4069	0	0
T21	0	6	0	0
T27	0	4778	0	0
T28	0	15	0	0
T29	0	4155	0	0
T36	15864	0	0	0
T39	0	2183	0	0
T41	0	1041	0	0
T43	0	274	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	481474	0	0
T8	958634	3872	0	0
T9	9107	0	0	0
T10	108693	0	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	7352	0	0
T18	0	4069	0	0
T21	0	6	0	0
T27	0	4778	0	0
T28	0	15	0	0
T29	0	4155	0	0
T36	15864	0	0	0
T39	0	2183	0	0
T41	0	1041	0	0
T43	0	274	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	481474	0	0
T8	958634	3872	0	0
T9	9107	0	0	0
T10	108693	0	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	7352	0	0
T18	0	4069	0	0
T21	0	6	0	0
T27	0	4778	0	0
T28	0	15	0	0
T29	0	4155	0	0
T36	15864	0	0	0
T39	0	2183	0	0
T41	0	1041	0	0
T43	0	274	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	481474	0	0
T8	958634	3872	0	0
T9	9107	0	0	0
T10	108693	0	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	7352	0	0
T18	0	4069	0	0
T21	0	6	0	0
T27	0	4778	0	0
T28	0	15	0	0
T29	0	4155	0	0
T36	15864	0	0	0
T39	0	2183	0	0
T41	0	1041	0	0
T43	0	274	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	105279968	0	0
T2	20500	20500	0	0
T3	232793	232580	0	0
T6	85535	85040	0	0
T8	958634	878136	0	0
T9	9107	9044	0	0
T10	108693	0	0	0
T11	128980	128610	0	0
T12	30840	30840	0	0
T13	10744	10744	0	0
T14	25336	25336	0	0
T15	0	15168	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136149086	481474	0	0
T8	958634	3872	0	0
T9	9107	0	0	0
T10	108693	0	0	0
T11	128980	0	0	0
T12	30840	0	0	0
T13	10744	0	0	0
T14	25336	0	0	0
T15	15168	0	0	0
T16	128674	7352	0	0
T18	0	4069	0	0
T21	0	6	0	0
T27	0	4778	0	0
T28	0	15	0	0
T29	0	4155	0	0
T36	15864	0	0	0
T39	0	2183	0	0
T41	0	1041	0	0
T43	0	274	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T10
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422866124	422783860	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	422866124	2122807	0	0
GntImpliesValid_A	422866124	2122807	0	0
GrantKnown_A	422866124	422783860	0	0
IdxKnown_A	422866124	422783860	0	0
IndexIsCorrect_A	422866124	2122807	0	0
LockArbDecision_A	422866124	0	0	0
NoReadyValidNoGrant_A	422866124	0	0	0
ReadyAndValidImplyGrant_A	422866124	2122807	0	0
ReqAndReadyImplyGrant_A	422866124	2122807	0	0
ReqImpliesValid_A	422866124	2122807	0	0
ReqStaysHighUntilGranted0_M	422866124	0	0	0
RoundRobin_A	422866124	5	0	926
ValidKnown_A	422866124	422783860	0	0
gen_data_port_assertion.DataFlow_A	422866124	2122807	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	422783860	0	0
T1	2963	2886	0	0
T2	72224	72134	0	0
T3	71951	71896	0	0
T4	1510	1416	0	0
T5	2502	2406	0	0
T6	32297	32211	0	0
T7	1156	1059	0	0
T8	296779	296772	0	0
T9	76550	76489	0	0
T10	431369	431279	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	2122807	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	296779	13102	0	0
T9	76550	832	0	0
T10	431369	1830	0	0
T11	519685	832	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	2122807	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	296779	13102	0	0
T9	76550	832	0	0
T10	431369	1830	0	0
T11	519685	832	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	422783860	0	0
T1	2963	2886	0	0
T2	72224	72134	0	0
T3	71951	71896	0	0
T4	1510	1416	0	0
T5	2502	2406	0	0
T6	32297	32211	0	0
T7	1156	1059	0	0
T8	296779	296772	0	0
T9	76550	76489	0	0
T10	431369	431279	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	422783860	0	0
T1	2963	2886	0	0
T2	72224	72134	0	0
T3	71951	71896	0	0
T4	1510	1416	0	0
T5	2502	2406	0	0
T6	32297	32211	0	0
T7	1156	1059	0	0
T8	296779	296772	0	0
T9	76550	76489	0	0
T10	431369	431279	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	2122807	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	296779	13102	0	0
T9	76550	832	0	0
T10	431369	1830	0	0
T11	519685	832	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	2122807	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	296779	13102	0	0
T9	76550	832	0	0
T10	431369	1830	0	0
T11	519685	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	2122807	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	296779	13102	0	0
T9	76550	832	0	0
T10	431369	1830	0	0
T11	519685	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	2122807	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	296779	13102	0	0
T9	76550	832	0	0
T10	431369	1830	0	0
T11	519685	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	5	0	926
T44	230277	1	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	203547	0	0	1
T50	3431	0	0	1
T51	1808	0	0	1
T52	81139	0	0	1
T53	510992	0	0	1
T54	887658	0	0	1
T55	114419	0	0	1
T56	6120	0	0	1
T57	760986	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	422783860	0	0
T1	2963	2886	0	0
T2	72224	72134	0	0
T3	71951	71896	0	0
T4	1510	1416	0	0
T5	2502	2406	0	0
T6	32297	32211	0	0
T7	1156	1059	0	0
T8	296779	296772	0	0
T9	76550	76489	0	0
T10	431369	431279	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422866124	2122807	0	0
T2	72224	832	0	0
T3	71951	832	0	0
T4	1510	0	0	0
T5	2502	200	0	0
T6	32297	832	0	0
T7	1156	0	0	0
T8	296779	13102	0	0
T9	76550	832	0	0
T10	431369	1830	0	0
T11	519685	832	0	0
T12	0	832	0	0
T13	0	832	0	0