Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3008 |
0 |
0 |
T99 |
13512 |
109 |
0 |
0 |
T100 |
11802 |
164 |
0 |
0 |
T101 |
10600 |
3 |
0 |
0 |
T102 |
28495 |
4 |
0 |
0 |
T104 |
9587 |
7 |
0 |
0 |
T105 |
1963 |
1 |
0 |
0 |
T111 |
6204 |
51 |
0 |
0 |
T119 |
12448 |
10 |
0 |
0 |
T120 |
76908 |
2 |
0 |
0 |
T121 |
29576 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2587 |
0 |
0 |
T88 |
4280 |
23 |
0 |
0 |
T98 |
33697 |
35 |
0 |
0 |
T101 |
10600 |
17 |
0 |
0 |
T104 |
9587 |
8 |
0 |
0 |
T125 |
38806 |
239 |
0 |
0 |
T130 |
3731 |
2 |
0 |
0 |
T162 |
271969 |
664 |
0 |
0 |
T163 |
21609 |
81 |
0 |
0 |
T164 |
14764 |
42 |
0 |
0 |
T165 |
61307 |
34 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2577 |
0 |
0 |
T88 |
4280 |
15 |
0 |
0 |
T98 |
33697 |
40 |
0 |
0 |
T101 |
10600 |
11 |
0 |
0 |
T104 |
9587 |
23 |
0 |
0 |
T125 |
38806 |
211 |
0 |
0 |
T130 |
3731 |
3 |
0 |
0 |
T162 |
271969 |
674 |
0 |
0 |
T163 |
21609 |
71 |
0 |
0 |
T164 |
14764 |
35 |
0 |
0 |
T165 |
61307 |
37 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2712 |
0 |
0 |
T88 |
4280 |
15 |
0 |
0 |
T98 |
33697 |
77 |
0 |
0 |
T101 |
10600 |
29 |
0 |
0 |
T104 |
9587 |
21 |
0 |
0 |
T125 |
38806 |
260 |
0 |
0 |
T130 |
3731 |
7 |
0 |
0 |
T162 |
271969 |
666 |
0 |
0 |
T163 |
21609 |
58 |
0 |
0 |
T164 |
14764 |
15 |
0 |
0 |
T165 |
61307 |
90 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
6305 |
0 |
0 |
T88 |
4280 |
17 |
0 |
0 |
T98 |
33697 |
527 |
0 |
0 |
T101 |
10600 |
28 |
0 |
0 |
T104 |
9587 |
253 |
0 |
0 |
T125 |
38806 |
281 |
0 |
0 |
T130 |
3731 |
134 |
0 |
0 |
T162 |
271969 |
658 |
0 |
0 |
T163 |
21609 |
78 |
0 |
0 |
T164 |
14764 |
56 |
0 |
0 |
T165 |
61307 |
627 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
5962 |
0 |
0 |
T88 |
4280 |
14 |
0 |
0 |
T98 |
33697 |
686 |
0 |
0 |
T101 |
10600 |
144 |
0 |
0 |
T104 |
9587 |
19 |
0 |
0 |
T125 |
38806 |
223 |
0 |
0 |
T130 |
3731 |
121 |
0 |
0 |
T162 |
271969 |
618 |
0 |
0 |
T163 |
21609 |
67 |
0 |
0 |
T164 |
14764 |
37 |
0 |
0 |
T165 |
61307 |
686 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
5691 |
0 |
0 |
T88 |
4280 |
10 |
0 |
0 |
T98 |
33697 |
645 |
0 |
0 |
T101 |
10600 |
8 |
0 |
0 |
T104 |
9587 |
166 |
0 |
0 |
T125 |
38806 |
250 |
0 |
0 |
T130 |
3731 |
8 |
0 |
0 |
T162 |
271969 |
674 |
0 |
0 |
T163 |
21609 |
56 |
0 |
0 |
T164 |
14764 |
71 |
0 |
0 |
T165 |
61307 |
630 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
5310 |
0 |
0 |
T88 |
4280 |
14 |
0 |
0 |
T98 |
33697 |
364 |
0 |
0 |
T101 |
10600 |
117 |
0 |
0 |
T104 |
9587 |
16 |
0 |
0 |
T115 |
8560 |
3 |
0 |
0 |
T125 |
38806 |
213 |
0 |
0 |
T130 |
3731 |
7 |
0 |
0 |
T162 |
271969 |
691 |
0 |
0 |
T163 |
21609 |
51 |
0 |
0 |
T164 |
14764 |
44 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
6610 |
0 |
0 |
T88 |
4280 |
15 |
0 |
0 |
T98 |
33697 |
748 |
0 |
0 |
T101 |
10600 |
154 |
0 |
0 |
T104 |
9587 |
142 |
0 |
0 |
T125 |
38806 |
246 |
0 |
0 |
T130 |
3731 |
129 |
0 |
0 |
T162 |
271969 |
690 |
0 |
0 |
T163 |
21609 |
57 |
0 |
0 |
T164 |
14764 |
61 |
0 |
0 |
T165 |
61307 |
717 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
5585 |
0 |
0 |
T88 |
4280 |
8 |
0 |
0 |
T98 |
33697 |
272 |
0 |
0 |
T101 |
10600 |
288 |
0 |
0 |
T104 |
9587 |
13 |
0 |
0 |
T125 |
38806 |
245 |
0 |
0 |
T130 |
3731 |
1 |
0 |
0 |
T162 |
271969 |
589 |
0 |
0 |
T163 |
21609 |
53 |
0 |
0 |
T164 |
14764 |
53 |
0 |
0 |
T165 |
61307 |
459 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
7079 |
0 |
0 |
T88 |
4280 |
13 |
0 |
0 |
T98 |
33697 |
846 |
0 |
0 |
T101 |
10600 |
132 |
0 |
0 |
T104 |
9587 |
155 |
0 |
0 |
T125 |
38806 |
263 |
0 |
0 |
T130 |
3731 |
5 |
0 |
0 |
T162 |
271969 |
686 |
0 |
0 |
T163 |
21609 |
61 |
0 |
0 |
T164 |
14764 |
38 |
0 |
0 |
T165 |
61307 |
686 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
7277 |
0 |
0 |
T88 |
4280 |
19 |
0 |
0 |
T98 |
33697 |
708 |
0 |
0 |
T101 |
10600 |
149 |
0 |
0 |
T104 |
9587 |
298 |
0 |
0 |
T125 |
38806 |
244 |
0 |
0 |
T130 |
3731 |
138 |
0 |
0 |
T162 |
271969 |
753 |
0 |
0 |
T163 |
21609 |
53 |
0 |
0 |
T164 |
14764 |
52 |
0 |
0 |
T165 |
61307 |
719 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
4111 |
0 |
0 |
T88 |
4280 |
15 |
0 |
0 |
T98 |
33697 |
404 |
0 |
0 |
T101 |
10600 |
73 |
0 |
0 |
T104 |
9587 |
106 |
0 |
0 |
T125 |
38806 |
250 |
0 |
0 |
T130 |
3731 |
4 |
0 |
0 |
T162 |
271969 |
715 |
0 |
0 |
T163 |
21609 |
35 |
0 |
0 |
T164 |
14764 |
31 |
0 |
0 |
T165 |
61307 |
310 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
4114 |
0 |
0 |
T88 |
4280 |
14 |
0 |
0 |
T98 |
33697 |
322 |
0 |
0 |
T101 |
10600 |
11 |
0 |
0 |
T104 |
9587 |
72 |
0 |
0 |
T125 |
38806 |
215 |
0 |
0 |
T130 |
3731 |
45 |
0 |
0 |
T162 |
271969 |
666 |
0 |
0 |
T163 |
21609 |
71 |
0 |
0 |
T164 |
14764 |
12 |
0 |
0 |
T165 |
61307 |
353 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
4249 |
0 |
0 |
T88 |
4280 |
11 |
0 |
0 |
T98 |
33697 |
241 |
0 |
0 |
T101 |
10600 |
78 |
0 |
0 |
T104 |
9587 |
117 |
0 |
0 |
T125 |
38806 |
251 |
0 |
0 |
T130 |
3731 |
1 |
0 |
0 |
T162 |
271969 |
651 |
0 |
0 |
T163 |
21609 |
57 |
0 |
0 |
T164 |
14764 |
40 |
0 |
0 |
T165 |
61307 |
283 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3942 |
0 |
0 |
T88 |
4280 |
15 |
0 |
0 |
T98 |
33697 |
231 |
0 |
0 |
T101 |
10600 |
76 |
0 |
0 |
T104 |
9587 |
64 |
0 |
0 |
T125 |
38806 |
239 |
0 |
0 |
T130 |
3731 |
4 |
0 |
0 |
T162 |
271969 |
698 |
0 |
0 |
T163 |
21609 |
54 |
0 |
0 |
T164 |
14764 |
36 |
0 |
0 |
T165 |
61307 |
260 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
4052 |
0 |
0 |
T88 |
4280 |
12 |
0 |
0 |
T98 |
33697 |
165 |
0 |
0 |
T101 |
10600 |
66 |
0 |
0 |
T104 |
9587 |
9 |
0 |
0 |
T125 |
38806 |
265 |
0 |
0 |
T130 |
3731 |
50 |
0 |
0 |
T162 |
271969 |
628 |
0 |
0 |
T163 |
21609 |
60 |
0 |
0 |
T164 |
14764 |
28 |
0 |
0 |
T165 |
61307 |
297 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
4093 |
0 |
0 |
T88 |
4280 |
15 |
0 |
0 |
T98 |
33697 |
201 |
0 |
0 |
T101 |
10600 |
80 |
0 |
0 |
T104 |
9587 |
61 |
0 |
0 |
T125 |
38806 |
246 |
0 |
0 |
T130 |
3731 |
1 |
0 |
0 |
T162 |
271969 |
625 |
0 |
0 |
T163 |
21609 |
59 |
0 |
0 |
T164 |
14764 |
70 |
0 |
0 |
T165 |
61307 |
348 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3873 |
0 |
0 |
T88 |
4280 |
6 |
0 |
0 |
T98 |
33697 |
180 |
0 |
0 |
T100 |
11802 |
7 |
0 |
0 |
T101 |
10600 |
27 |
0 |
0 |
T104 |
9587 |
9 |
0 |
0 |
T125 |
38806 |
258 |
0 |
0 |
T130 |
3731 |
4 |
0 |
0 |
T162 |
271969 |
681 |
0 |
0 |
T163 |
21609 |
70 |
0 |
0 |
T164 |
14764 |
62 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3967 |
0 |
0 |
T88 |
4280 |
11 |
0 |
0 |
T98 |
33697 |
200 |
0 |
0 |
T101 |
10600 |
77 |
0 |
0 |
T104 |
9587 |
107 |
0 |
0 |
T125 |
38806 |
234 |
0 |
0 |
T130 |
3731 |
8 |
0 |
0 |
T162 |
271969 |
626 |
0 |
0 |
T163 |
21609 |
57 |
0 |
0 |
T164 |
14764 |
68 |
0 |
0 |
T165 |
61307 |
288 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3937 |
0 |
0 |
T88 |
4280 |
8 |
0 |
0 |
T98 |
33697 |
140 |
0 |
0 |
T101 |
10600 |
16 |
0 |
0 |
T104 |
9587 |
62 |
0 |
0 |
T125 |
38806 |
236 |
0 |
0 |
T130 |
3731 |
6 |
0 |
0 |
T162 |
271969 |
697 |
0 |
0 |
T163 |
21609 |
66 |
0 |
0 |
T164 |
14764 |
57 |
0 |
0 |
T165 |
61307 |
317 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3899 |
0 |
0 |
T88 |
4280 |
4 |
0 |
0 |
T98 |
33697 |
183 |
0 |
0 |
T100 |
11802 |
4 |
0 |
0 |
T101 |
10600 |
67 |
0 |
0 |
T104 |
9587 |
122 |
0 |
0 |
T125 |
38806 |
209 |
0 |
0 |
T162 |
271969 |
741 |
0 |
0 |
T163 |
21609 |
124 |
0 |
0 |
T164 |
14764 |
43 |
0 |
0 |
T165 |
61307 |
278 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
4129 |
0 |
0 |
T88 |
4280 |
15 |
0 |
0 |
T98 |
33697 |
151 |
0 |
0 |
T101 |
10600 |
62 |
0 |
0 |
T104 |
9587 |
71 |
0 |
0 |
T125 |
38806 |
213 |
0 |
0 |
T130 |
3731 |
45 |
0 |
0 |
T162 |
271969 |
690 |
0 |
0 |
T163 |
21609 |
35 |
0 |
0 |
T164 |
14764 |
66 |
0 |
0 |
T165 |
61307 |
263 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3919 |
0 |
0 |
T88 |
4280 |
12 |
0 |
0 |
T98 |
33697 |
123 |
0 |
0 |
T101 |
10600 |
120 |
0 |
0 |
T104 |
9587 |
10 |
0 |
0 |
T125 |
38806 |
239 |
0 |
0 |
T130 |
3731 |
6 |
0 |
0 |
T162 |
271969 |
718 |
0 |
0 |
T163 |
21609 |
74 |
0 |
0 |
T164 |
14764 |
26 |
0 |
0 |
T165 |
61307 |
342 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3946 |
0 |
0 |
T88 |
4280 |
17 |
0 |
0 |
T98 |
33697 |
287 |
0 |
0 |
T101 |
10600 |
15 |
0 |
0 |
T104 |
9587 |
12 |
0 |
0 |
T125 |
38806 |
281 |
0 |
0 |
T130 |
3731 |
7 |
0 |
0 |
T162 |
271969 |
729 |
0 |
0 |
T163 |
21609 |
71 |
0 |
0 |
T164 |
14764 |
35 |
0 |
0 |
T165 |
61307 |
438 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3960 |
0 |
0 |
T88 |
4280 |
20 |
0 |
0 |
T98 |
33697 |
320 |
0 |
0 |
T101 |
10600 |
66 |
0 |
0 |
T104 |
9587 |
9 |
0 |
0 |
T125 |
38806 |
173 |
0 |
0 |
T130 |
3731 |
2 |
0 |
0 |
T162 |
271969 |
616 |
0 |
0 |
T163 |
21609 |
50 |
0 |
0 |
T164 |
14764 |
61 |
0 |
0 |
T165 |
61307 |
354 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
4213 |
0 |
0 |
T88 |
4280 |
20 |
0 |
0 |
T98 |
33697 |
275 |
0 |
0 |
T101 |
10600 |
78 |
0 |
0 |
T104 |
9587 |
67 |
0 |
0 |
T125 |
38806 |
255 |
0 |
0 |
T130 |
3731 |
4 |
0 |
0 |
T162 |
271969 |
680 |
0 |
0 |
T163 |
21609 |
61 |
0 |
0 |
T164 |
14764 |
25 |
0 |
0 |
T165 |
61307 |
304 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3766 |
0 |
0 |
T88 |
4280 |
9 |
0 |
0 |
T98 |
33697 |
244 |
0 |
0 |
T101 |
10600 |
36 |
0 |
0 |
T104 |
9587 |
105 |
0 |
0 |
T125 |
38806 |
245 |
0 |
0 |
T130 |
3731 |
5 |
0 |
0 |
T162 |
271969 |
641 |
0 |
0 |
T163 |
21609 |
88 |
0 |
0 |
T164 |
14764 |
57 |
0 |
0 |
T165 |
61307 |
312 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3810 |
0 |
0 |
T88 |
4280 |
16 |
0 |
0 |
T98 |
33697 |
247 |
0 |
0 |
T101 |
10600 |
101 |
0 |
0 |
T104 |
9587 |
70 |
0 |
0 |
T125 |
38806 |
207 |
0 |
0 |
T130 |
3731 |
40 |
0 |
0 |
T162 |
271969 |
644 |
0 |
0 |
T163 |
21609 |
58 |
0 |
0 |
T164 |
14764 |
25 |
0 |
0 |
T165 |
61307 |
286 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3716 |
0 |
0 |
T88 |
4280 |
4 |
0 |
0 |
T98 |
33697 |
225 |
0 |
0 |
T101 |
10600 |
113 |
0 |
0 |
T104 |
9587 |
22 |
0 |
0 |
T125 |
38806 |
218 |
0 |
0 |
T130 |
3731 |
3 |
0 |
0 |
T162 |
271969 |
669 |
0 |
0 |
T163 |
21609 |
53 |
0 |
0 |
T164 |
14764 |
66 |
0 |
0 |
T165 |
61307 |
369 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3963 |
0 |
0 |
T88 |
4280 |
18 |
0 |
0 |
T98 |
33697 |
395 |
0 |
0 |
T101 |
10600 |
10 |
0 |
0 |
T104 |
9587 |
128 |
0 |
0 |
T125 |
38806 |
242 |
0 |
0 |
T130 |
3731 |
39 |
0 |
0 |
T162 |
271969 |
666 |
0 |
0 |
T163 |
21609 |
34 |
0 |
0 |
T164 |
14764 |
16 |
0 |
0 |
T165 |
61307 |
270 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
4138 |
0 |
0 |
T88 |
4280 |
14 |
0 |
0 |
T98 |
33697 |
190 |
0 |
0 |
T101 |
10600 |
58 |
0 |
0 |
T104 |
9587 |
81 |
0 |
0 |
T125 |
38806 |
210 |
0 |
0 |
T130 |
3731 |
3 |
0 |
0 |
T162 |
271969 |
735 |
0 |
0 |
T163 |
21609 |
100 |
0 |
0 |
T164 |
14764 |
89 |
0 |
0 |
T165 |
61307 |
222 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3806 |
0 |
0 |
T88 |
4280 |
12 |
0 |
0 |
T98 |
33697 |
166 |
0 |
0 |
T101 |
10600 |
13 |
0 |
0 |
T104 |
9587 |
19 |
0 |
0 |
T125 |
38806 |
264 |
0 |
0 |
T130 |
3731 |
59 |
0 |
0 |
T162 |
271969 |
707 |
0 |
0 |
T163 |
21609 |
47 |
0 |
0 |
T164 |
14764 |
51 |
0 |
0 |
T165 |
61307 |
399 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
4261 |
0 |
0 |
T88 |
4280 |
19 |
0 |
0 |
T98 |
33697 |
265 |
0 |
0 |
T101 |
10600 |
52 |
0 |
0 |
T104 |
9587 |
109 |
0 |
0 |
T125 |
38806 |
275 |
0 |
0 |
T130 |
3731 |
2 |
0 |
0 |
T162 |
271969 |
720 |
0 |
0 |
T163 |
21609 |
41 |
0 |
0 |
T164 |
14764 |
47 |
0 |
0 |
T165 |
61307 |
224 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3694 |
0 |
0 |
T88 |
4280 |
8 |
0 |
0 |
T98 |
33697 |
117 |
0 |
0 |
T101 |
10600 |
48 |
0 |
0 |
T104 |
9587 |
22 |
0 |
0 |
T115 |
8560 |
8 |
0 |
0 |
T125 |
38806 |
212 |
0 |
0 |
T130 |
3731 |
44 |
0 |
0 |
T162 |
271969 |
607 |
0 |
0 |
T163 |
21609 |
33 |
0 |
0 |
T164 |
14764 |
19 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3607 |
0 |
0 |
T88 |
4280 |
6 |
0 |
0 |
T98 |
33697 |
268 |
0 |
0 |
T101 |
10600 |
50 |
0 |
0 |
T104 |
9587 |
23 |
0 |
0 |
T125 |
38806 |
253 |
0 |
0 |
T130 |
3731 |
55 |
0 |
0 |
T162 |
271969 |
677 |
0 |
0 |
T163 |
21609 |
41 |
0 |
0 |
T164 |
14764 |
55 |
0 |
0 |
T165 |
61307 |
304 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2611 |
0 |
0 |
T88 |
4280 |
9 |
0 |
0 |
T98 |
33697 |
73 |
0 |
0 |
T100 |
11802 |
9 |
0 |
0 |
T101 |
10600 |
38 |
0 |
0 |
T104 |
9587 |
15 |
0 |
0 |
T125 |
38806 |
221 |
0 |
0 |
T130 |
3731 |
2 |
0 |
0 |
T162 |
271969 |
649 |
0 |
0 |
T163 |
21609 |
48 |
0 |
0 |
T164 |
14764 |
57 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2765 |
0 |
0 |
T88 |
4280 |
6 |
0 |
0 |
T98 |
33697 |
37 |
0 |
0 |
T101 |
10600 |
25 |
0 |
0 |
T104 |
9587 |
18 |
0 |
0 |
T125 |
38806 |
209 |
0 |
0 |
T130 |
3731 |
7 |
0 |
0 |
T162 |
271969 |
731 |
0 |
0 |
T163 |
21609 |
40 |
0 |
0 |
T164 |
14764 |
26 |
0 |
0 |
T165 |
61307 |
72 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2834 |
0 |
0 |
T88 |
4280 |
18 |
0 |
0 |
T98 |
33697 |
45 |
0 |
0 |
T101 |
10600 |
22 |
0 |
0 |
T104 |
9587 |
22 |
0 |
0 |
T125 |
38806 |
238 |
0 |
0 |
T130 |
3731 |
11 |
0 |
0 |
T162 |
271969 |
700 |
0 |
0 |
T163 |
21609 |
72 |
0 |
0 |
T164 |
14764 |
73 |
0 |
0 |
T165 |
61307 |
93 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2527 |
0 |
0 |
T88 |
4280 |
7 |
0 |
0 |
T98 |
33697 |
46 |
0 |
0 |
T101 |
10600 |
19 |
0 |
0 |
T104 |
9587 |
19 |
0 |
0 |
T125 |
38806 |
224 |
0 |
0 |
T130 |
3731 |
2 |
0 |
0 |
T162 |
271969 |
716 |
0 |
0 |
T163 |
21609 |
70 |
0 |
0 |
T164 |
14764 |
24 |
0 |
0 |
T165 |
61307 |
49 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2911 |
0 |
0 |
T88 |
4280 |
5 |
0 |
0 |
T98 |
33697 |
97 |
0 |
0 |
T101 |
10600 |
32 |
0 |
0 |
T104 |
9587 |
23 |
0 |
0 |
T125 |
38806 |
237 |
0 |
0 |
T130 |
3731 |
7 |
0 |
0 |
T162 |
271969 |
666 |
0 |
0 |
T163 |
21609 |
69 |
0 |
0 |
T164 |
14764 |
53 |
0 |
0 |
T165 |
61307 |
87 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
4060 |
0 |
0 |
T66 |
3338 |
0 |
0 |
0 |
T71 |
4128 |
0 |
0 |
0 |
T72 |
837 |
0 |
0 |
0 |
T73 |
1557 |
0 |
0 |
0 |
T74 |
1063 |
0 |
0 |
0 |
T75 |
3411 |
0 |
0 |
0 |
T76 |
78280 |
0 |
0 |
0 |
T91 |
0 |
29 |
0 |
0 |
T149 |
0 |
69 |
0 |
0 |
T150 |
0 |
58 |
0 |
0 |
T153 |
4085 |
86 |
0 |
0 |
T166 |
0 |
15 |
0 |
0 |
T167 |
0 |
15 |
0 |
0 |
T168 |
0 |
37 |
0 |
0 |
T169 |
0 |
25 |
0 |
0 |
T170 |
0 |
14 |
0 |
0 |
T171 |
0 |
4 |
0 |
0 |
T172 |
14725 |
0 |
0 |
0 |
T173 |
58457 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2808 |
0 |
0 |
T88 |
4280 |
2 |
0 |
0 |
T98 |
33697 |
51 |
0 |
0 |
T101 |
10600 |
15 |
0 |
0 |
T104 |
9587 |
18 |
0 |
0 |
T125 |
38806 |
283 |
0 |
0 |
T130 |
3731 |
12 |
0 |
0 |
T162 |
271969 |
752 |
0 |
0 |
T163 |
21609 |
83 |
0 |
0 |
T164 |
14764 |
51 |
0 |
0 |
T165 |
61307 |
71 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2637 |
0 |
0 |
T88 |
4280 |
13 |
0 |
0 |
T98 |
33697 |
48 |
0 |
0 |
T101 |
10600 |
26 |
0 |
0 |
T104 |
9587 |
20 |
0 |
0 |
T125 |
38806 |
232 |
0 |
0 |
T130 |
3731 |
9 |
0 |
0 |
T162 |
271969 |
670 |
0 |
0 |
T163 |
21609 |
58 |
0 |
0 |
T164 |
14764 |
84 |
0 |
0 |
T165 |
61307 |
64 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2604 |
0 |
0 |
T88 |
4280 |
10 |
0 |
0 |
T98 |
33697 |
44 |
0 |
0 |
T101 |
10600 |
11 |
0 |
0 |
T104 |
9587 |
11 |
0 |
0 |
T125 |
38806 |
231 |
0 |
0 |
T130 |
3731 |
3 |
0 |
0 |
T162 |
271969 |
687 |
0 |
0 |
T163 |
21609 |
123 |
0 |
0 |
T164 |
14764 |
31 |
0 |
0 |
T165 |
61307 |
42 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2561 |
0 |
0 |
T88 |
4280 |
15 |
0 |
0 |
T98 |
33697 |
41 |
0 |
0 |
T101 |
10600 |
19 |
0 |
0 |
T104 |
9587 |
13 |
0 |
0 |
T125 |
38806 |
260 |
0 |
0 |
T162 |
271969 |
720 |
0 |
0 |
T163 |
21609 |
46 |
0 |
0 |
T164 |
14764 |
26 |
0 |
0 |
T165 |
61307 |
43 |
0 |
0 |
T174 |
13340 |
57 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2492 |
0 |
0 |
T88 |
4280 |
21 |
0 |
0 |
T98 |
33697 |
21 |
0 |
0 |
T101 |
10600 |
9 |
0 |
0 |
T104 |
9587 |
14 |
0 |
0 |
T125 |
38806 |
272 |
0 |
0 |
T130 |
3731 |
3 |
0 |
0 |
T162 |
271969 |
636 |
0 |
0 |
T163 |
21609 |
84 |
0 |
0 |
T164 |
14764 |
23 |
0 |
0 |
T165 |
61307 |
61 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2418 |
0 |
0 |
T88 |
4280 |
21 |
0 |
0 |
T98 |
33697 |
25 |
0 |
0 |
T101 |
10600 |
20 |
0 |
0 |
T104 |
9587 |
8 |
0 |
0 |
T125 |
38806 |
248 |
0 |
0 |
T130 |
3731 |
3 |
0 |
0 |
T162 |
271969 |
651 |
0 |
0 |
T163 |
21609 |
42 |
0 |
0 |
T164 |
14764 |
27 |
0 |
0 |
T165 |
61307 |
38 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3009 |
0 |
0 |
T88 |
4280 |
13 |
0 |
0 |
T98 |
33697 |
73 |
0 |
0 |
T101 |
10600 |
31 |
0 |
0 |
T104 |
9587 |
21 |
0 |
0 |
T125 |
38806 |
258 |
0 |
0 |
T130 |
3731 |
3 |
0 |
0 |
T162 |
271969 |
767 |
0 |
0 |
T163 |
21609 |
75 |
0 |
0 |
T164 |
14764 |
87 |
0 |
0 |
T165 |
61307 |
117 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2490 |
0 |
0 |
T88 |
4280 |
14 |
0 |
0 |
T98 |
33697 |
33 |
0 |
0 |
T101 |
10600 |
19 |
0 |
0 |
T104 |
9587 |
12 |
0 |
0 |
T125 |
38806 |
251 |
0 |
0 |
T162 |
271969 |
654 |
0 |
0 |
T163 |
21609 |
96 |
0 |
0 |
T164 |
14764 |
1 |
0 |
0 |
T165 |
61307 |
33 |
0 |
0 |
T174 |
13340 |
38 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
3020 |
0 |
0 |
T88 |
4280 |
18 |
0 |
0 |
T98 |
33697 |
75 |
0 |
0 |
T101 |
10600 |
35 |
0 |
0 |
T104 |
9587 |
25 |
0 |
0 |
T125 |
38806 |
256 |
0 |
0 |
T162 |
271969 |
660 |
0 |
0 |
T163 |
21609 |
81 |
0 |
0 |
T164 |
14764 |
28 |
0 |
0 |
T165 |
61307 |
141 |
0 |
0 |
T174 |
13340 |
46 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2485 |
0 |
0 |
T88 |
4280 |
1 |
0 |
0 |
T98 |
33697 |
50 |
0 |
0 |
T101 |
10600 |
11 |
0 |
0 |
T104 |
9587 |
19 |
0 |
0 |
T125 |
38806 |
216 |
0 |
0 |
T130 |
3731 |
8 |
0 |
0 |
T162 |
271969 |
725 |
0 |
0 |
T163 |
21609 |
50 |
0 |
0 |
T164 |
14764 |
45 |
0 |
0 |
T165 |
61307 |
49 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2589 |
0 |
0 |
T88 |
4280 |
12 |
0 |
0 |
T98 |
33697 |
27 |
0 |
0 |
T101 |
10600 |
12 |
0 |
0 |
T104 |
9587 |
7 |
0 |
0 |
T125 |
38806 |
268 |
0 |
0 |
T162 |
271969 |
676 |
0 |
0 |
T163 |
21609 |
93 |
0 |
0 |
T164 |
14764 |
76 |
0 |
0 |
T165 |
61307 |
36 |
0 |
0 |
T174 |
13340 |
48 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2431 |
0 |
0 |
T88 |
4280 |
15 |
0 |
0 |
T98 |
33697 |
27 |
0 |
0 |
T101 |
10600 |
20 |
0 |
0 |
T104 |
9587 |
14 |
0 |
0 |
T125 |
38806 |
211 |
0 |
0 |
T130 |
3731 |
6 |
0 |
0 |
T162 |
271969 |
667 |
0 |
0 |
T163 |
21609 |
42 |
0 |
0 |
T164 |
14764 |
3 |
0 |
0 |
T165 |
61307 |
40 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2586 |
0 |
0 |
T88 |
4280 |
19 |
0 |
0 |
T98 |
33697 |
32 |
0 |
0 |
T101 |
10600 |
3 |
0 |
0 |
T104 |
9587 |
21 |
0 |
0 |
T125 |
38806 |
238 |
0 |
0 |
T130 |
3731 |
3 |
0 |
0 |
T162 |
271969 |
731 |
0 |
0 |
T163 |
21609 |
84 |
0 |
0 |
T164 |
14764 |
24 |
0 |
0 |
T165 |
61307 |
47 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2605 |
0 |
0 |
T88 |
4280 |
7 |
0 |
0 |
T98 |
33697 |
41 |
0 |
0 |
T101 |
10600 |
21 |
0 |
0 |
T104 |
9587 |
13 |
0 |
0 |
T125 |
38806 |
296 |
0 |
0 |
T130 |
3731 |
8 |
0 |
0 |
T162 |
271969 |
729 |
0 |
0 |
T163 |
21609 |
61 |
0 |
0 |
T164 |
14764 |
28 |
0 |
0 |
T165 |
61307 |
32 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2334 |
0 |
0 |
T88 |
4280 |
14 |
0 |
0 |
T98 |
33697 |
31 |
0 |
0 |
T101 |
10600 |
20 |
0 |
0 |
T104 |
9587 |
21 |
0 |
0 |
T125 |
38806 |
226 |
0 |
0 |
T130 |
3731 |
2 |
0 |
0 |
T162 |
271969 |
647 |
0 |
0 |
T163 |
21609 |
53 |
0 |
0 |
T164 |
14764 |
18 |
0 |
0 |
T165 |
61307 |
40 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425467587 |
2669 |
0 |
0 |
T88 |
4280 |
9 |
0 |
0 |
T98 |
33697 |
42 |
0 |
0 |
T101 |
10600 |
20 |
0 |
0 |
T104 |
9587 |
17 |
0 |
0 |
T125 |
38806 |
245 |
0 |
0 |
T130 |
3731 |
3 |
0 |
0 |
T162 |
271969 |
733 |
0 |
0 |
T163 |
21609 |
56 |
0 |
0 |
T164 |
14764 |
47 |
0 |
0 |
T165 |
61307 |
20 |
0 |
0 |