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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 98.35 94.20 98.61 89.36 97.14 95.81 98.17


Total test records in report: 1101
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T1011 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4145987344 May 16 12:59:35 PM PDT 24 May 16 01:00:16 PM PDT 24 14645113 ps
T174 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4139669453 May 16 12:59:41 PM PDT 24 May 16 01:00:21 PM PDT 24 476435909 ps
T1012 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.47065801 May 16 12:59:40 PM PDT 24 May 16 01:00:18 PM PDT 24 28178535 ps
T1013 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4159834282 May 16 12:59:36 PM PDT 24 May 16 01:00:17 PM PDT 24 13128127 ps
T114 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.125069507 May 16 12:59:26 PM PDT 24 May 16 01:00:08 PM PDT 24 680805379 ps
T1014 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.995508535 May 16 12:59:26 PM PDT 24 May 16 01:00:05 PM PDT 24 229864837 ps
T112 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1401295229 May 16 12:59:28 PM PDT 24 May 16 01:00:08 PM PDT 24 271852114 ps
T1015 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2897700463 May 16 12:59:09 PM PDT 24 May 16 12:59:44 PM PDT 24 52313899 ps
T1016 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2534640379 May 16 12:59:11 PM PDT 24 May 16 12:59:46 PM PDT 24 17944724 ps
T1017 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.801853297 May 16 12:59:41 PM PDT 24 May 16 01:00:19 PM PDT 24 28952284 ps
T1018 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2560110730 May 16 12:59:43 PM PDT 24 May 16 01:00:26 PM PDT 24 375238591 ps
T1019 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3935423030 May 16 12:59:10 PM PDT 24 May 16 12:59:45 PM PDT 24 14998497 ps
T1020 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.323943546 May 16 12:59:16 PM PDT 24 May 16 12:59:54 PM PDT 24 27440466 ps
T118 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.528012472 May 16 12:59:28 PM PDT 24 May 16 01:00:08 PM PDT 24 41629285 ps
T1021 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2339065769 May 16 12:59:30 PM PDT 24 May 16 01:00:11 PM PDT 24 2545600240 ps
T117 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.382132542 May 16 12:59:35 PM PDT 24 May 16 01:00:18 PM PDT 24 434471288 ps
T135 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4224032561 May 16 12:59:17 PM PDT 24 May 16 12:59:55 PM PDT 24 164739419 ps
T1022 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.5518154 May 16 12:59:23 PM PDT 24 May 16 12:59:59 PM PDT 24 11595390 ps
T1023 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2731543694 May 16 12:59:26 PM PDT 24 May 16 01:00:04 PM PDT 24 11785113 ps
T1024 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1968524671 May 16 12:59:34 PM PDT 24 May 16 01:00:16 PM PDT 24 40529223 ps
T1025 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1368673662 May 16 12:59:27 PM PDT 24 May 16 01:00:05 PM PDT 24 66473530 ps
T1026 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.512688277 May 16 12:59:10 PM PDT 24 May 16 12:59:46 PM PDT 24 111202254 ps
T1027 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1342629758 May 16 12:59:14 PM PDT 24 May 16 12:59:52 PM PDT 24 63685313 ps
T1028 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4216400588 May 16 12:59:36 PM PDT 24 May 16 01:00:16 PM PDT 24 17940464 ps
T1029 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1080342502 May 16 12:59:16 PM PDT 24 May 16 12:59:54 PM PDT 24 54144014 ps
T1030 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2914851623 May 16 12:59:11 PM PDT 24 May 16 12:59:48 PM PDT 24 30974899 ps
T1031 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.260999182 May 16 12:59:26 PM PDT 24 May 16 01:00:07 PM PDT 24 529008731 ps
T1032 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1362333428 May 16 12:59:25 PM PDT 24 May 16 01:00:03 PM PDT 24 45801312 ps
T1033 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1987002003 May 16 12:59:25 PM PDT 24 May 16 01:00:13 PM PDT 24 196293954 ps
T1034 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1958447259 May 16 12:59:43 PM PDT 24 May 16 01:00:21 PM PDT 24 153744247 ps
T1035 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2802688077 May 16 12:59:17 PM PDT 24 May 16 01:00:20 PM PDT 24 1810251311 ps
T1036 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4121531745 May 16 12:59:15 PM PDT 24 May 16 12:59:52 PM PDT 24 17553438 ps
T1037 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2069097758 May 16 12:59:11 PM PDT 24 May 16 12:59:48 PM PDT 24 27891448 ps
T1038 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3614396848 May 16 12:59:25 PM PDT 24 May 16 01:00:05 PM PDT 24 144907567 ps
T256 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1539237144 May 16 12:59:28 PM PDT 24 May 16 01:00:13 PM PDT 24 1208793252 ps
T1039 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.428055801 May 16 12:59:35 PM PDT 24 May 16 01:00:15 PM PDT 24 13295564 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3339033023 May 16 12:59:09 PM PDT 24 May 16 01:00:00 PM PDT 24 12161568760 ps
T254 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3033136211 May 16 12:59:14 PM PDT 24 May 16 01:00:04 PM PDT 24 2069403959 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3990019395 May 16 12:59:25 PM PDT 24 May 16 01:00:03 PM PDT 24 17837963 ps
T1042 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.509554281 May 16 12:59:26 PM PDT 24 May 16 01:00:07 PM PDT 24 81389209 ps
T1043 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4137489663 May 16 12:59:22 PM PDT 24 May 16 12:59:58 PM PDT 24 775298274 ps
T1044 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3690492214 May 16 12:59:24 PM PDT 24 May 16 01:00:01 PM PDT 24 12152399 ps
T1045 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1606485121 May 16 12:59:17 PM PDT 24 May 16 12:59:54 PM PDT 24 81783101 ps
T1046 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3853518184 May 16 12:59:36 PM PDT 24 May 16 01:00:16 PM PDT 24 12550408 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2472322208 May 16 12:59:20 PM PDT 24 May 16 01:00:08 PM PDT 24 221120472 ps
T1048 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2334820349 May 16 12:59:24 PM PDT 24 May 16 01:00:00 PM PDT 24 20388768 ps
T1049 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3332667800 May 16 12:59:38 PM PDT 24 May 16 01:00:17 PM PDT 24 49128629 ps
T1050 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.651785765 May 16 12:59:26 PM PDT 24 May 16 01:00:06 PM PDT 24 424261286 ps
T1051 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1843437075 May 16 12:59:28 PM PDT 24 May 16 01:00:20 PM PDT 24 1703240869 ps
T1052 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.545584517 May 16 12:59:21 PM PDT 24 May 16 01:00:01 PM PDT 24 1170207586 ps
T1053 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2299545991 May 16 12:59:16 PM PDT 24 May 16 12:59:54 PM PDT 24 29711609 ps
T1054 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.697569030 May 16 12:59:25 PM PDT 24 May 16 01:00:05 PM PDT 24 98816983 ps
T1055 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3776381671 May 16 12:59:25 PM PDT 24 May 16 01:00:03 PM PDT 24 30516759 ps
T1056 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2992730447 May 16 12:59:37 PM PDT 24 May 16 01:00:17 PM PDT 24 13313095 ps
T1057 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3800652661 May 16 12:59:29 PM PDT 24 May 16 01:00:08 PM PDT 24 369902857 ps
T1058 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3755736759 May 16 12:59:25 PM PDT 24 May 16 01:00:05 PM PDT 24 125032425 ps
T1059 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1820503928 May 16 12:59:29 PM PDT 24 May 16 01:00:08 PM PDT 24 134116403 ps
T1060 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.75097509 May 16 12:59:36 PM PDT 24 May 16 01:00:24 PM PDT 24 547265290 ps
T1061 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2266759425 May 16 12:59:36 PM PDT 24 May 16 01:00:19 PM PDT 24 195802354 ps
T1062 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1653597173 May 16 12:59:13 PM PDT 24 May 16 01:00:07 PM PDT 24 307125592 ps
T1063 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.538484610 May 16 12:59:13 PM PDT 24 May 16 01:00:28 PM PDT 24 10791781444 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3704343318 May 16 12:59:14 PM PDT 24 May 16 12:59:53 PM PDT 24 387577329 ps
T257 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2128387732 May 16 12:59:28 PM PDT 24 May 16 01:00:20 PM PDT 24 698917107 ps
T1065 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4137565474 May 16 12:59:36 PM PDT 24 May 16 01:00:16 PM PDT 24 53527041 ps
T1066 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3637120253 May 16 12:59:27 PM PDT 24 May 16 01:00:07 PM PDT 24 126992178 ps
T1067 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3303350675 May 16 12:59:24 PM PDT 24 May 16 01:00:01 PM PDT 24 112575969 ps
T1068 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3499143867 May 16 12:59:36 PM PDT 24 May 16 01:00:17 PM PDT 24 63372403 ps
T1069 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2874027489 May 16 12:59:26 PM PDT 24 May 16 01:00:06 PM PDT 24 432596618 ps
T1070 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.29455285 May 16 12:59:21 PM PDT 24 May 16 01:00:00 PM PDT 24 343559385 ps
T1071 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.18025832 May 16 12:59:19 PM PDT 24 May 16 12:59:56 PM PDT 24 199487993 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3622704044 May 16 12:59:19 PM PDT 24 May 16 12:59:56 PM PDT 24 13418225 ps
T1073 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3120613345 May 16 12:59:17 PM PDT 24 May 16 12:59:54 PM PDT 24 47064244 ps
T1074 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1966918673 May 16 12:59:16 PM PDT 24 May 16 12:59:53 PM PDT 24 48505630 ps
T1075 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3885652453 May 16 12:59:38 PM PDT 24 May 16 01:00:19 PM PDT 24 135916193 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2157458027 May 16 12:59:17 PM PDT 24 May 16 12:59:57 PM PDT 24 219979477 ps
T1077 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2719538325 May 16 12:59:25 PM PDT 24 May 16 01:00:10 PM PDT 24 302790654 ps
T1078 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.571754476 May 16 12:59:37 PM PDT 24 May 16 01:00:17 PM PDT 24 41051833 ps
T1079 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3828798306 May 16 12:59:25 PM PDT 24 May 16 01:00:03 PM PDT 24 17616431 ps
T1080 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3219899352 May 16 12:59:26 PM PDT 24 May 16 01:00:05 PM PDT 24 154087622 ps
T1081 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3233776043 May 16 12:59:37 PM PDT 24 May 16 01:00:16 PM PDT 24 42600963 ps
T1082 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.473017889 May 16 12:59:15 PM PDT 24 May 16 12:59:55 PM PDT 24 97778192 ps
T1083 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.573120397 May 16 12:59:35 PM PDT 24 May 16 01:00:15 PM PDT 24 13372245 ps
T1084 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.85471129 May 16 12:59:11 PM PDT 24 May 16 12:59:56 PM PDT 24 752293733 ps
T255 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1862121118 May 16 12:59:27 PM PDT 24 May 16 01:00:26 PM PDT 24 3177699955 ps
T1085 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.503940461 May 16 12:59:26 PM PDT 24 May 16 01:00:04 PM PDT 24 16655117 ps
T1086 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.460192303 May 16 12:59:37 PM PDT 24 May 16 01:00:18 PM PDT 24 26693665 ps
T1087 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3786294171 May 16 12:59:23 PM PDT 24 May 16 01:00:18 PM PDT 24 3093316365 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4212194888 May 16 12:59:14 PM PDT 24 May 16 12:59:53 PM PDT 24 66739502 ps
T1089 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2509162817 May 16 12:59:19 PM PDT 24 May 16 12:59:55 PM PDT 24 22409078 ps
T1090 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2786233851 May 16 12:59:41 PM PDT 24 May 16 01:00:21 PM PDT 24 137981920 ps
T1091 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.860740205 May 16 12:59:29 PM PDT 24 May 16 01:00:09 PM PDT 24 524972539 ps
T1092 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2560146176 May 16 12:59:35 PM PDT 24 May 16 01:00:16 PM PDT 24 104062500 ps
T1093 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3630419602 May 16 12:59:11 PM PDT 24 May 16 01:00:08 PM PDT 24 621649849 ps
T1094 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3889488995 May 16 12:59:22 PM PDT 24 May 16 12:59:59 PM PDT 24 28130957 ps
T1095 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.339443446 May 16 12:59:32 PM PDT 24 May 16 01:00:13 PM PDT 24 123357137 ps
T1096 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.30366804 May 16 12:59:37 PM PDT 24 May 16 01:00:18 PM PDT 24 12966969 ps
T1097 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2818602179 May 16 12:59:38 PM PDT 24 May 16 01:00:17 PM PDT 24 23031067 ps
T1098 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1732512844 May 16 12:59:11 PM PDT 24 May 16 12:59:48 PM PDT 24 253785376 ps
T1099 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3260732444 May 16 12:59:17 PM PDT 24 May 16 12:59:56 PM PDT 24 966488526 ps
T1100 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1598133063 May 16 12:59:20 PM PDT 24 May 16 01:00:17 PM PDT 24 1246074592 ps
T1101 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2413445465 May 16 12:59:13 PM PDT 24 May 16 12:59:49 PM PDT 24 28520800 ps

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.504187670
Short name T8
Test name
Test status
Simulation time 30283427677 ps
CPU time 342.18 seconds
Started May 16 01:28:51 PM PDT 24
Finished May 16 01:34:46 PM PDT 24
Peak memory 254848 kb
Host smart-be09b09f-7fa4-4267-8519-e7370869977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504187670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.504187670
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1899188393
Short name T16
Test name
Test status
Simulation time 70959262691 ps
CPU time 349.8 seconds
Started May 16 01:28:05 PM PDT 24
Finished May 16 01:34:10 PM PDT 24
Peak memory 268824 kb
Host smart-29448df2-15c9-4380-aebf-87fefefddef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899188393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1899188393
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.587118985
Short name T63
Test name
Test status
Simulation time 60120625816 ps
CPU time 553.17 seconds
Started May 16 01:28:41 PM PDT 24
Finished May 16 01:38:06 PM PDT 24
Peak memory 252328 kb
Host smart-47dc2c30-9f9f-4931-b814-eb0cf5c9cfde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587118985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.587118985
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3667841234
Short name T101
Test name
Test status
Simulation time 110453734 ps
CPU time 2.6 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 217964 kb
Host smart-0aa5e904-7aa3-453d-8a0c-87e5db9f8411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667841234 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3667841234
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3073601731
Short name T81
Test name
Test status
Simulation time 438449673589 ps
CPU time 980.05 seconds
Started May 16 01:27:51 PM PDT 24
Finished May 16 01:44:29 PM PDT 24
Peak memory 273916 kb
Host smart-3ef72395-99ca-4055-a0e0-c59d0ff2ca8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073601731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3073601731
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2396192756
Short name T167
Test name
Test status
Simulation time 47444827773 ps
CPU time 206.63 seconds
Started May 16 01:28:00 PM PDT 24
Finished May 16 01:31:43 PM PDT 24
Peak memory 267740 kb
Host smart-8e62edaa-0b54-4c87-a0d1-5b2b4a4dfcbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396192756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2396192756
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.94580972
Short name T65
Test name
Test status
Simulation time 17489541 ps
CPU time 0.76 seconds
Started May 16 01:26:24 PM PDT 24
Finished May 16 01:26:43 PM PDT 24
Peak memory 215996 kb
Host smart-bd231c64-6718-436a-ac3e-b576a0e0d322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94580972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.94580972
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2241930852
Short name T18
Test name
Test status
Simulation time 76455094623 ps
CPU time 246.56 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:31:29 PM PDT 24
Peak memory 249464 kb
Host smart-e6ee6ece-a8bb-42b4-9b83-287450b9d4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241930852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2241930852
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3322152004
Short name T176
Test name
Test status
Simulation time 311352390199 ps
CPU time 1412.14 seconds
Started May 16 01:28:50 PM PDT 24
Finished May 16 01:52:35 PM PDT 24
Peak memory 283580 kb
Host smart-841be360-3971-45e8-9b7b-db26dae895c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322152004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3322152004
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1014444346
Short name T66
Test name
Test status
Simulation time 33733414 ps
CPU time 0.97 seconds
Started May 16 01:26:20 PM PDT 24
Finished May 16 01:26:37 PM PDT 24
Peak memory 234176 kb
Host smart-edc33bed-1439-4167-9fb2-30c30ab1b0e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014444346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1014444346
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.226619893
Short name T226
Test name
Test status
Simulation time 220913754284 ps
CPU time 695.6 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:38:26 PM PDT 24
Peak memory 286724 kb
Host smart-8cb9d513-9f60-461b-95e0-4a8d9b6754d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226619893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.226619893
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.959514009
Short name T154
Test name
Test status
Simulation time 231330779 ps
CPU time 9.5 seconds
Started May 16 01:29:17 PM PDT 24
Finished May 16 01:29:39 PM PDT 24
Peak memory 240952 kb
Host smart-0db1fe99-ded9-45c5-a723-5c1165351ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959514009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.959514009
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.479949267
Short name T29
Test name
Test status
Simulation time 420012249944 ps
CPU time 748.27 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:39:55 PM PDT 24
Peak memory 256392 kb
Host smart-d48b583b-392d-4ad3-b2c5-0336c47ddc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479949267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.479949267
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2118250947
Short name T120
Test name
Test status
Simulation time 6991730018 ps
CPU time 20.68 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:26 PM PDT 24
Peak memory 216680 kb
Host smart-ef635c9f-e7f9-4ad0-aa78-e227c06bf763
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118250947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2118250947
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3906245420
Short name T126
Test name
Test status
Simulation time 147970913 ps
CPU time 2.3 seconds
Started May 16 12:59:24 PM PDT 24
Finished May 16 01:00:03 PM PDT 24
Peak memory 215772 kb
Host smart-d91679bc-2b73-43cd-a804-d4914570fd68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906245420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
906245420
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4010302221
Short name T99
Test name
Test status
Simulation time 2702880706 ps
CPU time 3.81 seconds
Started May 16 12:59:29 PM PDT 24
Finished May 16 01:00:09 PM PDT 24
Peak memory 216028 kb
Host smart-62e36ebe-7d46-4ccc-a80e-c51e93191dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010302221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4010302221
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1297710963
Short name T30
Test name
Test status
Simulation time 476317510140 ps
CPU time 413.63 seconds
Started May 16 01:27:25 PM PDT 24
Finished May 16 01:34:40 PM PDT 24
Peak memory 265780 kb
Host smart-0cc448bf-0dbe-467e-a9b9-b7392269e64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297710963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1297710963
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.4193077261
Short name T178
Test name
Test status
Simulation time 6228354234 ps
CPU time 88.26 seconds
Started May 16 01:26:18 PM PDT 24
Finished May 16 01:28:03 PM PDT 24
Peak memory 249380 kb
Host smart-5d6640b5-fdd1-4471-975c-5f412e3da215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193077261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4193077261
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2651697440
Short name T5
Test name
Test status
Simulation time 25049571 ps
CPU time 1.02 seconds
Started May 16 01:26:21 PM PDT 24
Finished May 16 01:26:39 PM PDT 24
Peak memory 218000 kb
Host smart-bd6cf7c2-e6c5-4060-926d-713f79a0026a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651697440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2651697440
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2913983153
Short name T233
Test name
Test status
Simulation time 28064968025 ps
CPU time 101.61 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:30:26 PM PDT 24
Peak memory 251248 kb
Host smart-3ab1f944-8bdf-4523-ac63-401b4d8ace07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913983153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2913983153
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1958632625
Short name T170
Test name
Test status
Simulation time 96886664481 ps
CPU time 173.52 seconds
Started May 16 01:27:00 PM PDT 24
Finished May 16 01:30:15 PM PDT 24
Peak memory 270124 kb
Host smart-d9f5ddf6-2eb4-4939-9358-79b42d178677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958632625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1958632625
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4076457911
Short name T44
Test name
Test status
Simulation time 44284711095 ps
CPU time 262.89 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:31:45 PM PDT 24
Peak memory 265776 kb
Host smart-aa5d519d-87db-4273-993f-dcd40fcf8776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076457911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4076457911
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.170533659
Short name T32
Test name
Test status
Simulation time 86787014007 ps
CPU time 262.46 seconds
Started May 16 01:27:11 PM PDT 24
Finished May 16 01:31:56 PM PDT 24
Peak memory 256636 kb
Host smart-b59d99d6-68bb-4d34-9955-55afc85ead6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170533659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.170533659
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1525824011
Short name T240
Test name
Test status
Simulation time 27718370474 ps
CPU time 404.25 seconds
Started May 16 01:27:46 PM PDT 24
Finished May 16 01:34:48 PM PDT 24
Peak memory 282148 kb
Host smart-48fd5082-efc5-4ddf-be6d-994249cf82e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525824011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1525824011
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.500517139
Short name T321
Test name
Test status
Simulation time 35270827 ps
CPU time 0.72 seconds
Started May 16 01:27:38 PM PDT 24
Finished May 16 01:27:57 PM PDT 24
Peak memory 205464 kb
Host smart-14df8bd1-fb5d-43e7-be1c-77bd75376076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500517139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.500517139
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.252420952
Short name T83
Test name
Test status
Simulation time 65630833362 ps
CPU time 575.66 seconds
Started May 16 01:26:54 PM PDT 24
Finished May 16 01:36:46 PM PDT 24
Peak memory 265804 kb
Host smart-4977d656-0f62-4b94-9d00-fb89d54dbe6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252420952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.252420952
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.125069507
Short name T114
Test name
Test status
Simulation time 680805379 ps
CPU time 4.27 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 215884 kb
Host smart-7ad45ec8-b99d-44b9-a41e-bd64da381b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125069507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.125069507
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2723500175
Short name T217
Test name
Test status
Simulation time 11685535429 ps
CPU time 99.05 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:29:04 PM PDT 24
Peak memory 256644 kb
Host smart-8499bc57-1937-442c-9675-934bc147929b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723500175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2723500175
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2108121561
Short name T244
Test name
Test status
Simulation time 180096936225 ps
CPU time 352.53 seconds
Started May 16 01:28:39 PM PDT 24
Finished May 16 01:34:44 PM PDT 24
Peak memory 262812 kb
Host smart-afa3dfcd-f422-40cb-9673-132551077c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108121561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2108121561
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_intercept.390728555
Short name T9
Test name
Test status
Simulation time 781139055 ps
CPU time 7.66 seconds
Started May 16 01:27:04 PM PDT 24
Finished May 16 01:27:34 PM PDT 24
Peak memory 234012 kb
Host smart-4c264d33-a964-4678-ab4d-aebfc441c76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390728555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.390728555
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2939430257
Short name T90
Test name
Test status
Simulation time 1024519520 ps
CPU time 10.51 seconds
Started May 16 01:26:41 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 216440 kb
Host smart-eff62327-1e9e-454c-9223-41ac4d2f9e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939430257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2939430257
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1733552123
Short name T103
Test name
Test status
Simulation time 935099208 ps
CPU time 12.51 seconds
Started May 16 12:59:12 PM PDT 24
Finished May 16 12:59:59 PM PDT 24
Peak memory 217256 kb
Host smart-ef2ad0e5-f2c8-4227-8865-61222714d7e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733552123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1733552123
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3629552922
Short name T253
Test name
Test status
Simulation time 819354680 ps
CPU time 13.16 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 215824 kb
Host smart-4af7d2b4-e5b3-4079-aad9-123399f8054a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629552922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3629552922
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3158627363
Short name T62
Test name
Test status
Simulation time 107029445 ps
CPU time 1.03 seconds
Started May 16 01:27:08 PM PDT 24
Finished May 16 01:27:31 PM PDT 24
Peak memory 206620 kb
Host smart-28c7309e-9d8f-4f05-b9c1-e90eb782a439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158627363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3158627363
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3672177985
Short name T293
Test name
Test status
Simulation time 1454150954 ps
CPU time 22.93 seconds
Started May 16 01:27:06 PM PDT 24
Finished May 16 01:27:51 PM PDT 24
Peak memory 232716 kb
Host smart-248d50b9-3419-4827-8920-a2cb4abea553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672177985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3672177985
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3754553670
Short name T216
Test name
Test status
Simulation time 28099511487 ps
CPU time 104.71 seconds
Started May 16 01:27:11 PM PDT 24
Finished May 16 01:29:17 PM PDT 24
Peak memory 250904 kb
Host smart-d296e121-400a-4299-815c-f5aeec5554e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754553670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3754553670
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1362810851
Short name T28
Test name
Test status
Simulation time 39622984653 ps
CPU time 356.98 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:33:36 PM PDT 24
Peak memory 251880 kb
Host smart-2b01478f-81fc-4d59-a840-01331232bd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362810851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1362810851
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2546970514
Short name T183
Test name
Test status
Simulation time 26510194190 ps
CPU time 216.16 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:31:32 PM PDT 24
Peak memory 250768 kb
Host smart-3c603358-4758-416a-ba0d-6c505c36d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546970514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2546970514
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4059096437
Short name T208
Test name
Test status
Simulation time 12588272588 ps
CPU time 200.53 seconds
Started May 16 01:28:39 PM PDT 24
Finished May 16 01:32:12 PM PDT 24
Peak memory 252668 kb
Host smart-f73311fe-aaf8-4dcc-a920-5b2fab0ad8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059096437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4059096437
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2914830212
Short name T224
Test name
Test status
Simulation time 12393835013 ps
CPU time 72.28 seconds
Started May 16 01:28:47 PM PDT 24
Finished May 16 01:30:11 PM PDT 24
Peak memory 249288 kb
Host smart-d6d30087-b0d1-435b-a116-294696f98477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914830212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2914830212
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_intercept.991794504
Short name T96
Test name
Test status
Simulation time 545203737 ps
CPU time 4.3 seconds
Started May 16 01:26:24 PM PDT 24
Finished May 16 01:26:46 PM PDT 24
Peak memory 233588 kb
Host smart-d5515c18-4c5c-4fa2-b189-02d09d4713db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991794504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.991794504
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1633491363
Short name T212
Test name
Test status
Simulation time 108544413630 ps
CPU time 388.98 seconds
Started May 16 01:26:55 PM PDT 24
Finished May 16 01:33:41 PM PDT 24
Peak memory 254064 kb
Host smart-62e1ffa6-4c81-4e5a-b311-ba68c113f50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633491363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1633491363
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.524498383
Short name T192
Test name
Test status
Simulation time 246076034848 ps
CPU time 440.71 seconds
Started May 16 01:27:15 PM PDT 24
Finished May 16 01:34:58 PM PDT 24
Peak memory 255088 kb
Host smart-b27f4529-e7e1-424e-8cf1-89eead82e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524498383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.524498383
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.50662855
Short name T34
Test name
Test status
Simulation time 42980989347 ps
CPU time 473.73 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:35:30 PM PDT 24
Peak memory 273752 kb
Host smart-ada45ffe-03de-4daf-b495-d1b2df06a70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50662855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress
_all.50662855
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.878529114
Short name T250
Test name
Test status
Simulation time 33769568654 ps
CPU time 60.21 seconds
Started May 16 01:27:26 PM PDT 24
Finished May 16 01:28:46 PM PDT 24
Peak memory 236260 kb
Host smart-956cce4e-e9af-4315-b593-1531af16226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878529114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.878529114
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2559590213
Short name T113
Test name
Test status
Simulation time 171828205 ps
CPU time 2.72 seconds
Started May 16 12:59:35 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 215896 kb
Host smart-188c8165-89fb-4977-9f91-45ed773f2a4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559590213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2559590213
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3849174676
Short name T89
Test name
Test status
Simulation time 74050983 ps
CPU time 1.11 seconds
Started May 16 12:59:11 PM PDT 24
Finished May 16 12:59:46 PM PDT 24
Peak memory 207288 kb
Host smart-de1b70d5-ab17-4806-9f58-fc1a9cfa2d0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849174676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3849174676
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1920682634
Short name T23
Test name
Test status
Simulation time 35155817907 ps
CPU time 204.02 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:31:19 PM PDT 24
Peak memory 249464 kb
Host smart-8a8672bb-a28e-47b8-8a2e-f4b731ad6cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920682634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1920682634
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3339033023
Short name T1040
Test name
Test status
Simulation time 12161568760 ps
CPU time 15.32 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 01:00:00 PM PDT 24
Peak memory 215884 kb
Host smart-82db440e-4f3e-4fd0-b11b-d459ebb3a163
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339033023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3339033023
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.538484610
Short name T1063
Test name
Test status
Simulation time 10791781444 ps
CPU time 39.15 seconds
Started May 16 12:59:13 PM PDT 24
Finished May 16 01:00:28 PM PDT 24
Peak memory 215820 kb
Host smart-d0ab4447-38ff-4079-8654-98c32420dda2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538484610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.538484610
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3704343318
Short name T1064
Test name
Test status
Simulation time 387577329 ps
CPU time 2.89 seconds
Started May 16 12:59:14 PM PDT 24
Finished May 16 12:59:53 PM PDT 24
Peak memory 218308 kb
Host smart-63d142d0-a3c9-465b-aad1-d8e126ece165
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704343318 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3704343318
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4212194888
Short name T1088
Test name
Test status
Simulation time 66739502 ps
CPU time 1.93 seconds
Started May 16 12:59:14 PM PDT 24
Finished May 16 12:59:53 PM PDT 24
Peak memory 215756 kb
Host smart-8aa7d333-35f0-449b-aa23-0e8c8a6de5f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212194888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
212194888
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3935423030
Short name T1019
Test name
Test status
Simulation time 14998497 ps
CPU time 0.7 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 203904 kb
Host smart-4eee3f3c-36c2-4e95-a54c-875fcb9746cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935423030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
935423030
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2069097758
Short name T1037
Test name
Test status
Simulation time 27891448 ps
CPU time 1.88 seconds
Started May 16 12:59:11 PM PDT 24
Finished May 16 12:59:48 PM PDT 24
Peak memory 215776 kb
Host smart-abe6ae4c-807a-4867-81bf-d12b26a47a97
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069097758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2069097758
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2534640379
Short name T1016
Test name
Test status
Simulation time 17944724 ps
CPU time 0.67 seconds
Started May 16 12:59:11 PM PDT 24
Finished May 16 12:59:46 PM PDT 24
Peak memory 203772 kb
Host smart-96b75797-2ffa-4fdb-b2ce-4c8c53d2e4ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534640379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2534640379
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1342629758
Short name T1027
Test name
Test status
Simulation time 63685313 ps
CPU time 1.94 seconds
Started May 16 12:59:14 PM PDT 24
Finished May 16 12:59:52 PM PDT 24
Peak memory 215836 kb
Host smart-19e53b6c-d63e-4a8f-b947-34734076dcb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342629758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1342629758
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2914851623
Short name T1030
Test name
Test status
Simulation time 30974899 ps
CPU time 2.04 seconds
Started May 16 12:59:11 PM PDT 24
Finished May 16 12:59:48 PM PDT 24
Peak memory 215964 kb
Host smart-74cf5e76-abde-44d8-9190-1f67eac62aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914851623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
914851623
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3630419602
Short name T1093
Test name
Test status
Simulation time 621649849 ps
CPU time 21.5 seconds
Started May 16 12:59:11 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 215688 kb
Host smart-f811fe9e-ccd6-42fd-af72-3a480862b18f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630419602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3630419602
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.24794765
Short name T978
Test name
Test status
Simulation time 6954503847 ps
CPU time 36.82 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 01:00:21 PM PDT 24
Peak memory 215752 kb
Host smart-503a67ea-4bb6-4bbb-930b-b3490194e5e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24794765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
bit_bash.24794765
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.503250199
Short name T86
Test name
Test status
Simulation time 149604945 ps
CPU time 1.18 seconds
Started May 16 12:59:12 PM PDT 24
Finished May 16 12:59:47 PM PDT 24
Peak memory 207588 kb
Host smart-8eebab9c-3f66-4b3d-bab5-a88da1ff3548
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503250199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.503250199
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3651227659
Short name T104
Test name
Test status
Simulation time 383546896 ps
CPU time 2.65 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 12:59:46 PM PDT 24
Peak memory 216824 kb
Host smart-a041ecda-1783-4f62-975a-7d1f1705a0d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651227659 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3651227659
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3296888378
Short name T988
Test name
Test status
Simulation time 20169412 ps
CPU time 1.27 seconds
Started May 16 12:59:08 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 215632 kb
Host smart-4141f589-4837-484f-a6c3-552b92ee7cd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296888378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
296888378
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3394640149
Short name T997
Test name
Test status
Simulation time 17925256 ps
CPU time 0.73 seconds
Started May 16 12:59:07 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 204248 kb
Host smart-d08c87bc-8af7-4bfa-8a2b-136d0b8ffcf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394640149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
394640149
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2398622328
Short name T127
Test name
Test status
Simulation time 257155060 ps
CPU time 2.13 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 12:59:47 PM PDT 24
Peak memory 215664 kb
Host smart-ace55dfb-b4f9-4241-a866-0d70cecca03b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398622328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2398622328
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2413445465
Short name T1101
Test name
Test status
Simulation time 28520800 ps
CPU time 0.65 seconds
Started May 16 12:59:13 PM PDT 24
Finished May 16 12:59:49 PM PDT 24
Peak memory 203860 kb
Host smart-367c7d2c-b666-4df5-966b-8d8e3cf1cffb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413445465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2413445465
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3964965224
Short name T164
Test name
Test status
Simulation time 922844841 ps
CPU time 3.17 seconds
Started May 16 12:59:11 PM PDT 24
Finished May 16 12:59:49 PM PDT 24
Peak memory 215760 kb
Host smart-6bf2c5cf-42ef-4d02-a71e-b9c8d970ba4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964965224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3964965224
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.512688277
Short name T1026
Test name
Test status
Simulation time 111202254 ps
CPU time 1.68 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 12:59:46 PM PDT 24
Peak memory 215904 kb
Host smart-162899aa-ed77-4b77-bed9-e62ddf65eb75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512688277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.512688277
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.912301895
Short name T98
Test name
Test status
Simulation time 1404114332 ps
CPU time 7.7 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 12:59:52 PM PDT 24
Peak memory 215748 kb
Host smart-bf9f1ea8-795c-454d-bc3d-56b1f525915e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912301895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.912301895
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1820503928
Short name T1059
Test name
Test status
Simulation time 134116403 ps
CPU time 1.97 seconds
Started May 16 12:59:29 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 215996 kb
Host smart-ccfc69bc-55d5-4c08-81fa-3978014a879a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820503928 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1820503928
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1623093995
Short name T130
Test name
Test status
Simulation time 248910442 ps
CPU time 1.25 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:07 PM PDT 24
Peak memory 215792 kb
Host smart-678ef405-b5bc-4e6b-9643-94ff63a40925
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623093995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1623093995
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.503940461
Short name T1085
Test name
Test status
Simulation time 16655117 ps
CPU time 0.74 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:04 PM PDT 24
Peak memory 204044 kb
Host smart-ecd22a37-364d-4820-b157-fb3c9155eeee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503940461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.503940461
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.470764026
Short name T151
Test name
Test status
Simulation time 352831565 ps
CPU time 2.85 seconds
Started May 16 12:59:30 PM PDT 24
Finished May 16 01:00:10 PM PDT 24
Peak memory 215844 kb
Host smart-51a93b28-4910-4923-91e9-45805f0fbb26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470764026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.470764026
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1401295229
Short name T112
Test name
Test status
Simulation time 271852114 ps
CPU time 3.11 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 216040 kb
Host smart-31eed938-8652-4ca8-b3ec-a336683fba49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401295229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1401295229
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1843437075
Short name T1051
Test name
Test status
Simulation time 1703240869 ps
CPU time 14.61 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:20 PM PDT 24
Peak memory 215988 kb
Host smart-0b2087ff-7dd9-4909-b735-7a38701da560
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843437075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1843437075
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1368408593
Short name T116
Test name
Test status
Simulation time 53185462 ps
CPU time 3.41 seconds
Started May 16 12:59:33 PM PDT 24
Finished May 16 01:00:14 PM PDT 24
Peak memory 218832 kb
Host smart-a15b9d4f-84b8-4b8d-8329-77935b5af4f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368408593 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1368408593
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3800652661
Short name T1057
Test name
Test status
Simulation time 369902857 ps
CPU time 2.67 seconds
Started May 16 12:59:29 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 215792 kb
Host smart-f358b4d6-5db7-46d8-858d-7d1456803c88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800652661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3800652661
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3776381671
Short name T1055
Test name
Test status
Simulation time 30516759 ps
CPU time 0.73 seconds
Started May 16 12:59:25 PM PDT 24
Finished May 16 01:00:03 PM PDT 24
Peak memory 203924 kb
Host smart-3d92313b-d870-4950-9e07-198194f94b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776381671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3776381671
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3755736759
Short name T1058
Test name
Test status
Simulation time 125032425 ps
CPU time 4.02 seconds
Started May 16 12:59:25 PM PDT 24
Finished May 16 01:00:05 PM PDT 24
Peak memory 215768 kb
Host smart-496a6a6b-720a-4e41-9f4c-d93a96be6c54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755736759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3755736759
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3868881168
Short name T111
Test name
Test status
Simulation time 62682901 ps
CPU time 1.93 seconds
Started May 16 12:59:27 PM PDT 24
Finished May 16 01:00:06 PM PDT 24
Peak memory 215916 kb
Host smart-fb36829b-56f0-4bdf-a0f6-e82694464484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868881168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3868881168
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.980186220
Short name T105
Test name
Test status
Simulation time 130965914 ps
CPU time 1.57 seconds
Started May 16 12:59:29 PM PDT 24
Finished May 16 01:00:07 PM PDT 24
Peak memory 215904 kb
Host smart-2d09f64c-0467-488c-8801-168d894e27cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980186220 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.980186220
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1368673662
Short name T1025
Test name
Test status
Simulation time 66473530 ps
CPU time 1.21 seconds
Started May 16 12:59:27 PM PDT 24
Finished May 16 01:00:05 PM PDT 24
Peak memory 207548 kb
Host smart-514f0f6c-853f-4907-ab3c-8811b6a4a0f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368673662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1368673662
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3690492214
Short name T1044
Test name
Test status
Simulation time 12152399 ps
CPU time 0.72 seconds
Started May 16 12:59:24 PM PDT 24
Finished May 16 01:00:01 PM PDT 24
Peak memory 203744 kb
Host smart-f265c4ca-2a1d-4a34-8d48-0e4da22270f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690492214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3690492214
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.860740205
Short name T1091
Test name
Test status
Simulation time 524972539 ps
CPU time 2.9 seconds
Started May 16 12:59:29 PM PDT 24
Finished May 16 01:00:09 PM PDT 24
Peak memory 215760 kb
Host smart-3a2b56d2-5ab7-492d-b72c-5cca998c33b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860740205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.860740205
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.509554281
Short name T1042
Test name
Test status
Simulation time 81389209 ps
CPU time 2.86 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:07 PM PDT 24
Peak memory 215920 kb
Host smart-c6ba8913-4c4a-4240-971c-b25638e8c851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509554281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.509554281
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1521776044
Short name T165
Test name
Test status
Simulation time 625601185 ps
CPU time 14.43 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:18 PM PDT 24
Peak memory 216140 kb
Host smart-0934793d-006b-4eaa-8066-b41971861180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521776044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1521776044
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2628289974
Short name T1003
Test name
Test status
Simulation time 215836559 ps
CPU time 2.88 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 218532 kb
Host smart-ea3d7307-dda0-4157-badc-049e6ca651cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628289974 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2628289974
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3303350675
Short name T1067
Test name
Test status
Simulation time 112575969 ps
CPU time 1.35 seconds
Started May 16 12:59:24 PM PDT 24
Finished May 16 01:00:01 PM PDT 24
Peak memory 215720 kb
Host smart-2a84693f-8635-46e1-b16f-eca4a527a814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303350675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3303350675
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2334820349
Short name T1048
Test name
Test status
Simulation time 20388768 ps
CPU time 0.76 seconds
Started May 16 12:59:24 PM PDT 24
Finished May 16 01:00:00 PM PDT 24
Peak memory 203992 kb
Host smart-720b6bd2-fcde-4c31-ace3-e8132fae6359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334820349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2334820349
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2339065769
Short name T1021
Test name
Test status
Simulation time 2545600240 ps
CPU time 4.11 seconds
Started May 16 12:59:30 PM PDT 24
Finished May 16 01:00:11 PM PDT 24
Peak memory 215840 kb
Host smart-73e6ab66-6eb2-45d2-a951-297f1ac31cd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339065769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2339065769
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1705385399
Short name T989
Test name
Test status
Simulation time 21357790 ps
CPU time 1.35 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:05 PM PDT 24
Peak memory 215996 kb
Host smart-d7292a23-2530-4075-9a08-31edb90a77c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705385399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1705385399
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1539237144
Short name T256
Test name
Test status
Simulation time 1208793252 ps
CPU time 8.09 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:13 PM PDT 24
Peak memory 215788 kb
Host smart-f7ba0caf-4147-41c6-9203-f9ee1782fa15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539237144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1539237144
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.697569030
Short name T1054
Test name
Test status
Simulation time 98816983 ps
CPU time 2.55 seconds
Started May 16 12:59:25 PM PDT 24
Finished May 16 01:00:05 PM PDT 24
Peak memory 215704 kb
Host smart-bcd3e89a-3d7b-4bea-b09b-7e39e646c511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697569030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.697569030
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3400167387
Short name T995
Test name
Test status
Simulation time 35223724 ps
CPU time 0.67 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:06 PM PDT 24
Peak memory 203908 kb
Host smart-3a317d91-6b8f-452a-a5e2-28986187038d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400167387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3400167387
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2078882171
Short name T981
Test name
Test status
Simulation time 44802101 ps
CPU time 2.77 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 215824 kb
Host smart-a816cc8a-d188-4a83-a511-5cdfd3c5e992
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078882171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2078882171
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.910168835
Short name T1010
Test name
Test status
Simulation time 85946267 ps
CPU time 2.63 seconds
Started May 16 12:59:30 PM PDT 24
Finished May 16 01:00:10 PM PDT 24
Peak memory 217308 kb
Host smart-2613bf6f-0488-458e-ac92-2267ecf0612d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910168835 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.910168835
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3219899352
Short name T1080
Test name
Test status
Simulation time 154087622 ps
CPU time 1.35 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:05 PM PDT 24
Peak memory 207520 kb
Host smart-b3e0731e-5ada-4479-86ba-3df9f2b7bbf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219899352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3219899352
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4288280382
Short name T990
Test name
Test status
Simulation time 39239299 ps
CPU time 0.73 seconds
Started May 16 12:59:30 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 203928 kb
Host smart-d78da1d3-0513-45ae-922c-0f590a3fd1e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288280382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4288280382
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.775027239
Short name T992
Test name
Test status
Simulation time 159532649 ps
CPU time 2.76 seconds
Started May 16 12:59:27 PM PDT 24
Finished May 16 01:00:07 PM PDT 24
Peak memory 215748 kb
Host smart-29ade537-936d-4115-bebd-9e9145ef548f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775027239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.775027239
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1862121118
Short name T255
Test name
Test status
Simulation time 3177699955 ps
CPU time 21.13 seconds
Started May 16 12:59:27 PM PDT 24
Finished May 16 01:00:26 PM PDT 24
Peak memory 224104 kb
Host smart-35e52204-3262-43d8-b5d7-dd6f999801e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862121118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1862121118
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2518078401
Short name T119
Test name
Test status
Simulation time 259350210 ps
CPU time 3.79 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:19 PM PDT 24
Peak memory 218152 kb
Host smart-2ee1d9d1-da7c-470d-9c92-ee80aedc0ab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518078401 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2518078401
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4253815791
Short name T131
Test name
Test status
Simulation time 54080397 ps
CPU time 1.86 seconds
Started May 16 12:59:29 PM PDT 24
Finished May 16 01:00:09 PM PDT 24
Peak memory 207520 kb
Host smart-85f1e02e-4cd6-4518-a26b-4b0b0d33ee75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253815791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4253815791
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2731543694
Short name T1023
Test name
Test status
Simulation time 11785113 ps
CPU time 0.7 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:04 PM PDT 24
Peak memory 204260 kb
Host smart-468e420f-175d-45b6-8dff-3cb189eda38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731543694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2731543694
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4139669453
Short name T174
Test name
Test status
Simulation time 476435909 ps
CPU time 3.03 seconds
Started May 16 12:59:41 PM PDT 24
Finished May 16 01:00:21 PM PDT 24
Peak memory 215776 kb
Host smart-e82e54ca-d408-44e4-8a42-bb17cba9fa46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139669453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4139669453
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.339443446
Short name T1095
Test name
Test status
Simulation time 123357137 ps
CPU time 3.2 seconds
Started May 16 12:59:32 PM PDT 24
Finished May 16 01:00:13 PM PDT 24
Peak memory 215872 kb
Host smart-ea984435-f7d8-417c-ac52-4bb901ac7c0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339443446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.339443446
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2719538325
Short name T1077
Test name
Test status
Simulation time 302790654 ps
CPU time 8.38 seconds
Started May 16 12:59:25 PM PDT 24
Finished May 16 01:00:10 PM PDT 24
Peak memory 216056 kb
Host smart-4df99702-fd71-4cfb-b13d-b2e762db3afb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719538325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2719538325
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3885652453
Short name T1075
Test name
Test status
Simulation time 135916193 ps
CPU time 2.69 seconds
Started May 16 12:59:38 PM PDT 24
Finished May 16 01:00:19 PM PDT 24
Peak memory 217084 kb
Host smart-2190f078-c90f-4307-be39-967c1752e959
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885652453 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3885652453
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3765875553
Short name T134
Test name
Test status
Simulation time 137132568 ps
CPU time 2.42 seconds
Started May 16 12:59:37 PM PDT 24
Finished May 16 01:00:18 PM PDT 24
Peak memory 207524 kb
Host smart-971a752f-d888-4bf6-b8db-19a007248add
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765875553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3765875553
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3631671720
Short name T985
Test name
Test status
Simulation time 50065165 ps
CPU time 0.7 seconds
Started May 16 12:59:38 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 203928 kb
Host smart-86769a66-da3d-4ede-8334-5e22a3665d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631671720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3631671720
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4000285481
Short name T1000
Test name
Test status
Simulation time 70160348 ps
CPU time 1.83 seconds
Started May 16 12:59:34 PM PDT 24
Finished May 16 01:00:14 PM PDT 24
Peak memory 215644 kb
Host smart-9c23bfa1-3926-4252-99cd-e4978adab7fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000285481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4000285481
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.75097509
Short name T1060
Test name
Test status
Simulation time 547265290 ps
CPU time 7.87 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:24 PM PDT 24
Peak memory 215836 kb
Host smart-cc0cd391-0f68-4648-917d-401455b29693
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75097509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_
tl_intg_err.75097509
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3444346536
Short name T1002
Test name
Test status
Simulation time 50508413 ps
CPU time 2.44 seconds
Started May 16 12:59:34 PM PDT 24
Finished May 16 01:00:15 PM PDT 24
Peak memory 215908 kb
Host smart-8e9c146c-afa2-4125-8de0-f6ec1fcf41fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444346536 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3444346536
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1968524671
Short name T1024
Test name
Test status
Simulation time 40529223 ps
CPU time 1.25 seconds
Started May 16 12:59:34 PM PDT 24
Finished May 16 01:00:16 PM PDT 24
Peak memory 207476 kb
Host smart-47fe3487-c677-41a5-8bc7-994871d57a98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968524671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1968524671
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.428055801
Short name T1039
Test name
Test status
Simulation time 13295564 ps
CPU time 0.73 seconds
Started May 16 12:59:35 PM PDT 24
Finished May 16 01:00:15 PM PDT 24
Peak memory 204000 kb
Host smart-b9a4f00e-d3db-4a05-ab5c-134b4691aca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428055801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.428055801
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2786233851
Short name T1090
Test name
Test status
Simulation time 137981920 ps
CPU time 2.77 seconds
Started May 16 12:59:41 PM PDT 24
Finished May 16 01:00:21 PM PDT 24
Peak memory 215760 kb
Host smart-874c01ff-a000-499b-9ec2-a1f636c2653b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786233851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2786233851
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.382132542
Short name T117
Test name
Test status
Simulation time 434471288 ps
CPU time 2.99 seconds
Started May 16 12:59:35 PM PDT 24
Finished May 16 01:00:18 PM PDT 24
Peak memory 215896 kb
Host smart-d0ae6b6d-28ff-4f28-9867-3a0af4313113
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382132542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.382132542
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3697797124
Short name T252
Test name
Test status
Simulation time 1123361956 ps
CPU time 13.92 seconds
Started May 16 12:59:40 PM PDT 24
Finished May 16 01:00:31 PM PDT 24
Peak memory 223988 kb
Host smart-ad8a2d20-ad71-4da9-a7c6-0c39f3dc7522
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697797124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3697797124
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3690720973
Short name T1007
Test name
Test status
Simulation time 213591008 ps
CPU time 3.75 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:19 PM PDT 24
Peak memory 217600 kb
Host smart-e924fff4-94af-4893-bc1f-201b8432d0ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690720973 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3690720973
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2560146176
Short name T1092
Test name
Test status
Simulation time 104062500 ps
CPU time 1.92 seconds
Started May 16 12:59:35 PM PDT 24
Finished May 16 01:00:16 PM PDT 24
Peak memory 215748 kb
Host smart-87ff7c50-47aa-4c52-b187-7a44756fe22f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560146176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2560146176
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1341655184
Short name T996
Test name
Test status
Simulation time 22366911 ps
CPU time 0.68 seconds
Started May 16 12:59:41 PM PDT 24
Finished May 16 01:00:19 PM PDT 24
Peak memory 203916 kb
Host smart-8a0976af-5a1c-46f2-85e6-df2acfc50141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341655184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1341655184
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2266759425
Short name T1061
Test name
Test status
Simulation time 195802354 ps
CPU time 2.87 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:19 PM PDT 24
Peak memory 215740 kb
Host smart-b8b07f87-915c-4d8a-b0d1-443cb17f93aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266759425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2266759425
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4179802402
Short name T115
Test name
Test status
Simulation time 174719286 ps
CPU time 2.3 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:18 PM PDT 24
Peak memory 215860 kb
Host smart-0bba5f35-68e9-4348-9d6e-5fda4d6039bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179802402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4179802402
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2560110730
Short name T1018
Test name
Test status
Simulation time 375238591 ps
CPU time 5.9 seconds
Started May 16 12:59:43 PM PDT 24
Finished May 16 01:00:26 PM PDT 24
Peak memory 215828 kb
Host smart-4b4e332e-5624-4d0b-a816-5e2322ed04e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560110730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2560110730
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3589695591
Short name T125
Test name
Test status
Simulation time 3880695654 ps
CPU time 8.64 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 12:59:54 PM PDT 24
Peak memory 207476 kb
Host smart-d3f2054d-3ace-46b6-a18d-eed4a409c331
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589695591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3589695591
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.85471129
Short name T1084
Test name
Test status
Simulation time 752293733 ps
CPU time 10.91 seconds
Started May 16 12:59:11 PM PDT 24
Finished May 16 12:59:56 PM PDT 24
Peak memory 215632 kb
Host smart-66279000-09e4-4a7a-8bce-5143cf54a0d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85471129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
bit_bash.85471129
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.331917693
Short name T87
Test name
Test status
Simulation time 178067690 ps
CPU time 1.38 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 207500 kb
Host smart-3090709c-42ba-43b0-a093-175533bbe78d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331917693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.331917693
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.527265829
Short name T998
Test name
Test status
Simulation time 196211826 ps
CPU time 1.84 seconds
Started May 16 12:59:22 PM PDT 24
Finished May 16 01:00:00 PM PDT 24
Peak memory 216852 kb
Host smart-6dd4ab5e-f6b4-4ee3-8baa-a6f1f5f3e2a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527265829 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.527265829
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4076951186
Short name T128
Test name
Test status
Simulation time 20750011 ps
CPU time 1.33 seconds
Started May 16 12:59:14 PM PDT 24
Finished May 16 12:59:51 PM PDT 24
Peak memory 207460 kb
Host smart-aeefaad2-f470-4ee2-aee3-4b98a0105bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076951186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
076951186
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2425025251
Short name T980
Test name
Test status
Simulation time 54310691 ps
CPU time 0.73 seconds
Started May 16 12:59:10 PM PDT 24
Finished May 16 12:59:45 PM PDT 24
Peak memory 203992 kb
Host smart-5c6ab666-3531-454a-9c1c-b54cf786fe74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425025251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
425025251
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1732512844
Short name T1098
Test name
Test status
Simulation time 253785376 ps
CPU time 2.01 seconds
Started May 16 12:59:11 PM PDT 24
Finished May 16 12:59:48 PM PDT 24
Peak memory 215728 kb
Host smart-a0646bcd-c765-4014-a7ba-9e74504192b7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732512844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1732512844
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2897700463
Short name T1015
Test name
Test status
Simulation time 52313899 ps
CPU time 0.64 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 12:59:44 PM PDT 24
Peak memory 204212 kb
Host smart-473d2907-f561-4c52-8a05-43b60c3ace21
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897700463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2897700463
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2820475705
Short name T983
Test name
Test status
Simulation time 114767525 ps
CPU time 3.75 seconds
Started May 16 12:59:09 PM PDT 24
Finished May 16 12:59:47 PM PDT 24
Peak memory 215748 kb
Host smart-20192604-e367-45c4-9dd7-32bd594f97ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820475705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2820475705
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.451672464
Short name T100
Test name
Test status
Simulation time 491861088 ps
CPU time 2.86 seconds
Started May 16 12:59:12 PM PDT 24
Finished May 16 12:59:49 PM PDT 24
Peak memory 218056 kb
Host smart-f82df772-fa64-495c-a15d-a500086fe581
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451672464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.451672464
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1653597173
Short name T1062
Test name
Test status
Simulation time 307125592 ps
CPU time 18.91 seconds
Started May 16 12:59:13 PM PDT 24
Finished May 16 01:00:07 PM PDT 24
Peak memory 215816 kb
Host smart-6c14d33b-cfca-4226-b41e-ac1facd99003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653597173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1653597173
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3234776437
Short name T1006
Test name
Test status
Simulation time 32992548 ps
CPU time 0.67 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:16 PM PDT 24
Peak memory 203908 kb
Host smart-a4524524-cb6c-40da-9689-1bf993e85d0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234776437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3234776437
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3160841572
Short name T977
Test name
Test status
Simulation time 46326774 ps
CPU time 0.69 seconds
Started May 16 12:59:38 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 204280 kb
Host smart-c35183bf-3200-441b-81ed-a310224fc108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160841572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3160841572
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2693958036
Short name T999
Test name
Test status
Simulation time 52538219 ps
CPU time 0.73 seconds
Started May 16 12:59:40 PM PDT 24
Finished May 16 01:00:19 PM PDT 24
Peak memory 203988 kb
Host smart-85affff7-c152-470b-91f4-120f79f7bd3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693958036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2693958036
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4132777014
Short name T1001
Test name
Test status
Simulation time 35782831 ps
CPU time 0.68 seconds
Started May 16 12:59:35 PM PDT 24
Finished May 16 01:00:15 PM PDT 24
Peak memory 203896 kb
Host smart-282b88c4-1384-4207-b717-fdb54a569781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132777014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4132777014
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3853518184
Short name T1046
Test name
Test status
Simulation time 12550408 ps
CPU time 0.76 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:16 PM PDT 24
Peak memory 204032 kb
Host smart-2eac7dbe-a8ca-4813-9f38-3fa334ae4e68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853518184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3853518184
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2162343863
Short name T1009
Test name
Test status
Simulation time 13293720 ps
CPU time 0.69 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:16 PM PDT 24
Peak memory 204268 kb
Host smart-ad4b0fb9-f9c0-476c-8026-8bdc9d2e5494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162343863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2162343863
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.101558444
Short name T1005
Test name
Test status
Simulation time 35195355 ps
CPU time 0.72 seconds
Started May 16 12:59:37 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 204196 kb
Host smart-47ec4379-0084-4001-b2bf-19e297a18a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101558444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.101558444
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.571754476
Short name T1078
Test name
Test status
Simulation time 41051833 ps
CPU time 0.77 seconds
Started May 16 12:59:37 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 204284 kb
Host smart-8360986a-8c7c-410d-8a69-353040cf60cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571754476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.571754476
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3499143867
Short name T1068
Test name
Test status
Simulation time 63372403 ps
CPU time 0.66 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 203844 kb
Host smart-bcd6eea4-4b89-4656-98c9-fcec28e9b647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499143867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3499143867
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3047697517
Short name T975
Test name
Test status
Simulation time 12689523 ps
CPU time 0.71 seconds
Started May 16 12:59:41 PM PDT 24
Finished May 16 01:00:19 PM PDT 24
Peak memory 204244 kb
Host smart-cc6312b7-9258-4f01-81ba-f012bc33bca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047697517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3047697517
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1598133063
Short name T1100
Test name
Test status
Simulation time 1246074592 ps
CPU time 21.25 seconds
Started May 16 12:59:20 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 215796 kb
Host smart-08a15a78-679b-4c2d-9cb9-87dd8c4c99bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598133063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1598133063
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2802688077
Short name T1035
Test name
Test status
Simulation time 1810251311 ps
CPU time 26.51 seconds
Started May 16 12:59:17 PM PDT 24
Finished May 16 01:00:20 PM PDT 24
Peak memory 207452 kb
Host smart-3b818f92-b991-461e-92c4-76d0e29efc28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802688077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2802688077
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.668848814
Short name T88
Test name
Test status
Simulation time 171312613 ps
CPU time 1.43 seconds
Started May 16 12:59:27 PM PDT 24
Finished May 16 01:00:06 PM PDT 24
Peak memory 216800 kb
Host smart-ac17955b-323b-425f-bea7-57fc996faf28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668848814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.668848814
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.473017889
Short name T1082
Test name
Test status
Simulation time 97778192 ps
CPU time 2.51 seconds
Started May 16 12:59:15 PM PDT 24
Finished May 16 12:59:55 PM PDT 24
Peak memory 217332 kb
Host smart-e9925f0f-d5ca-4c6a-a66f-289461d564eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473017889 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.473017889
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3814533733
Short name T993
Test name
Test status
Simulation time 39099157 ps
CPU time 1.35 seconds
Started May 16 12:59:17 PM PDT 24
Finished May 16 12:59:54 PM PDT 24
Peak memory 215748 kb
Host smart-f4fe54ee-d0ab-49af-bb84-77570daf7322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814533733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
814533733
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3622704044
Short name T1072
Test name
Test status
Simulation time 13418225 ps
CPU time 0.7 seconds
Started May 16 12:59:19 PM PDT 24
Finished May 16 12:59:56 PM PDT 24
Peak memory 203840 kb
Host smart-ffaefbef-f283-48d3-bb66-5106b3276cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622704044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
622704044
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4137489663
Short name T1043
Test name
Test status
Simulation time 775298274 ps
CPU time 2.15 seconds
Started May 16 12:59:22 PM PDT 24
Finished May 16 12:59:58 PM PDT 24
Peak memory 215764 kb
Host smart-144a9750-2da6-415c-b0d4-25292e564e9d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137489663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4137489663
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4121531745
Short name T1036
Test name
Test status
Simulation time 17553438 ps
CPU time 0.63 seconds
Started May 16 12:59:15 PM PDT 24
Finished May 16 12:59:52 PM PDT 24
Peak memory 203848 kb
Host smart-0946519a-36e9-4e24-943a-98833a65c503
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121531745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4121531745
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3400472548
Short name T1008
Test name
Test status
Simulation time 228910497 ps
CPU time 3.86 seconds
Started May 16 12:59:18 PM PDT 24
Finished May 16 12:59:58 PM PDT 24
Peak memory 215824 kb
Host smart-a02233b7-425a-44ec-809a-efaf078fb65c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400472548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3400472548
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3889488995
Short name T1094
Test name
Test status
Simulation time 28130957 ps
CPU time 1.74 seconds
Started May 16 12:59:22 PM PDT 24
Finished May 16 12:59:59 PM PDT 24
Peak memory 216960 kb
Host smart-cb6fbead-37fe-4c5d-a659-0d728bdd9c36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889488995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
889488995
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2472322208
Short name T1047
Test name
Test status
Simulation time 221120472 ps
CPU time 12.44 seconds
Started May 16 12:59:20 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 216112 kb
Host smart-b5533754-eca1-4399-b965-ef21b4eabc33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472322208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2472322208
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1958447259
Short name T1034
Test name
Test status
Simulation time 153744247 ps
CPU time 0.7 seconds
Started May 16 12:59:43 PM PDT 24
Finished May 16 01:00:21 PM PDT 24
Peak memory 203928 kb
Host smart-2fd91371-19f5-450f-b0d5-08169dd95dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958447259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1958447259
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4137565474
Short name T1065
Test name
Test status
Simulation time 53527041 ps
CPU time 0.72 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:16 PM PDT 24
Peak memory 203872 kb
Host smart-cb8606af-d12f-4133-b76a-9cc4545fb5e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137565474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4137565474
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1776388973
Short name T979
Test name
Test status
Simulation time 14536050 ps
CPU time 0.74 seconds
Started May 16 12:59:43 PM PDT 24
Finished May 16 01:00:21 PM PDT 24
Peak memory 204004 kb
Host smart-c2bd2268-a77a-4edb-839e-449f0d3adef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776388973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1776388973
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3632240075
Short name T994
Test name
Test status
Simulation time 14996188 ps
CPU time 0.69 seconds
Started May 16 12:59:37 PM PDT 24
Finished May 16 01:00:18 PM PDT 24
Peak memory 204020 kb
Host smart-bdfb59a0-38b1-4856-be10-4449e150fa15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632240075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3632240075
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3270397683
Short name T976
Test name
Test status
Simulation time 99838613 ps
CPU time 0.8 seconds
Started May 16 12:59:43 PM PDT 24
Finished May 16 01:00:21 PM PDT 24
Peak memory 204004 kb
Host smart-6d3cea94-7ba1-45f8-be1a-d6db2a916b85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270397683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3270397683
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4145987344
Short name T1011
Test name
Test status
Simulation time 14645113 ps
CPU time 0.68 seconds
Started May 16 12:59:35 PM PDT 24
Finished May 16 01:00:16 PM PDT 24
Peak memory 203928 kb
Host smart-9696d2ae-d949-4809-8cff-0703824a91eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145987344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4145987344
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4159834282
Short name T1013
Test name
Test status
Simulation time 13128127 ps
CPU time 0.78 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 203916 kb
Host smart-ee64dca3-be13-4eff-b87e-ab3e13106430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159834282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4159834282
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.30366804
Short name T1096
Test name
Test status
Simulation time 12966969 ps
CPU time 0.76 seconds
Started May 16 12:59:37 PM PDT 24
Finished May 16 01:00:18 PM PDT 24
Peak memory 204280 kb
Host smart-630c7f88-4f5d-4cb7-b6b1-bafd2f6d9e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30366804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.30366804
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3332667800
Short name T1049
Test name
Test status
Simulation time 49128629 ps
CPU time 0.68 seconds
Started May 16 12:59:38 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 204264 kb
Host smart-f5d5a461-8817-43cc-8f8f-7c0b76f81411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332667800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3332667800
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.570980764
Short name T982
Test name
Test status
Simulation time 19234113 ps
CPU time 0.73 seconds
Started May 16 12:59:34 PM PDT 24
Finished May 16 01:00:14 PM PDT 24
Peak memory 203892 kb
Host smart-fcdd6e69-88c4-4c87-8158-3886513cae17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570980764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.570980764
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2787563645
Short name T129
Test name
Test status
Simulation time 1380750141 ps
CPU time 21.07 seconds
Started May 16 12:59:27 PM PDT 24
Finished May 16 01:00:26 PM PDT 24
Peak memory 207552 kb
Host smart-94853ecf-0d4e-4865-a7a9-ddd75335467e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787563645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2787563645
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3818876023
Short name T162
Test name
Test status
Simulation time 2988683574 ps
CPU time 37.7 seconds
Started May 16 12:59:27 PM PDT 24
Finished May 16 01:00:42 PM PDT 24
Peak memory 215860 kb
Host smart-73e23fe3-bf6b-41c4-83d3-94a1fc0cf269
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818876023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3818876023
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1966918673
Short name T1074
Test name
Test status
Simulation time 48505630 ps
CPU time 0.97 seconds
Started May 16 12:59:16 PM PDT 24
Finished May 16 12:59:53 PM PDT 24
Peak memory 207256 kb
Host smart-f0ddcf3b-436b-4d5d-8948-510fcbb7a1f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966918673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1966918673
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3898342253
Short name T122
Test name
Test status
Simulation time 24295999 ps
CPU time 1.63 seconds
Started May 16 12:59:15 PM PDT 24
Finished May 16 12:59:53 PM PDT 24
Peak memory 215880 kb
Host smart-07c225ce-0a4d-405a-b83f-71bd4bc91170
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898342253 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3898342253
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2093906069
Short name T152
Test name
Test status
Simulation time 147014694 ps
CPU time 1.23 seconds
Started May 16 12:59:16 PM PDT 24
Finished May 16 12:59:55 PM PDT 24
Peak memory 215780 kb
Host smart-9a49178b-e062-497b-a87d-9bc109d7c32b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093906069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
093906069
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.287963868
Short name T984
Test name
Test status
Simulation time 28759444 ps
CPU time 0.76 seconds
Started May 16 12:59:16 PM PDT 24
Finished May 16 12:59:54 PM PDT 24
Peak memory 204024 kb
Host smart-6587d77c-9d1d-49df-b4ec-0c0986286796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287963868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.287963868
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4224032561
Short name T135
Test name
Test status
Simulation time 164739419 ps
CPU time 1.71 seconds
Started May 16 12:59:17 PM PDT 24
Finished May 16 12:59:55 PM PDT 24
Peak memory 215756 kb
Host smart-ccda532b-b780-4816-8598-30f7d019f6cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224032561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4224032561
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3990019395
Short name T1041
Test name
Test status
Simulation time 17837963 ps
CPU time 0.63 seconds
Started May 16 12:59:25 PM PDT 24
Finished May 16 01:00:03 PM PDT 24
Peak memory 203864 kb
Host smart-82f4ae77-94d5-4c83-ad51-e52569fa9718
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990019395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3990019395
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2157458027
Short name T1076
Test name
Test status
Simulation time 219979477 ps
CPU time 3.71 seconds
Started May 16 12:59:17 PM PDT 24
Finished May 16 12:59:57 PM PDT 24
Peak memory 215924 kb
Host smart-9c397970-da41-4991-826a-1fcff51a3ef1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157458027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2157458027
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2299545991
Short name T1053
Test name
Test status
Simulation time 29711609 ps
CPU time 1.83 seconds
Started May 16 12:59:16 PM PDT 24
Finished May 16 12:59:54 PM PDT 24
Peak memory 216872 kb
Host smart-b51d82c3-5bf4-4f59-a0de-31d5d38ed7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299545991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
299545991
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1987002003
Short name T1033
Test name
Test status
Simulation time 196293954 ps
CPU time 10.76 seconds
Started May 16 12:59:25 PM PDT 24
Finished May 16 01:00:13 PM PDT 24
Peak memory 215796 kb
Host smart-919dfb6c-e5e9-4089-b7cf-0246666a68e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987002003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1987002003
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4216400588
Short name T1028
Test name
Test status
Simulation time 17940464 ps
CPU time 0.69 seconds
Started May 16 12:59:36 PM PDT 24
Finished May 16 01:00:16 PM PDT 24
Peak memory 204280 kb
Host smart-1ecceda4-36cf-44f9-ad02-58eff30dace8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216400588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4216400588
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.801853297
Short name T1017
Test name
Test status
Simulation time 28952284 ps
CPU time 0.71 seconds
Started May 16 12:59:41 PM PDT 24
Finished May 16 01:00:19 PM PDT 24
Peak memory 203920 kb
Host smart-0771d598-727d-42b2-99b4-2a03d4d6dcbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801853297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.801853297
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3580056396
Short name T1004
Test name
Test status
Simulation time 56124411 ps
CPU time 0.68 seconds
Started May 16 12:59:35 PM PDT 24
Finished May 16 01:00:16 PM PDT 24
Peak memory 204176 kb
Host smart-e7b9a8ef-807e-44ef-a4b5-f352ce2c42ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580056396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3580056396
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.47065801
Short name T1012
Test name
Test status
Simulation time 28178535 ps
CPU time 0.76 seconds
Started May 16 12:59:40 PM PDT 24
Finished May 16 01:00:18 PM PDT 24
Peak memory 203960 kb
Host smart-ef637577-b428-41e8-a633-59ab3f2fe5f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47065801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.47065801
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.460192303
Short name T1086
Test name
Test status
Simulation time 26693665 ps
CPU time 0.74 seconds
Started May 16 12:59:37 PM PDT 24
Finished May 16 01:00:18 PM PDT 24
Peak memory 203880 kb
Host smart-c7c7a9a4-6f5c-4677-ae36-5ad4e2fd7909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460192303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.460192303
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3233776043
Short name T1081
Test name
Test status
Simulation time 42600963 ps
CPU time 0.67 seconds
Started May 16 12:59:37 PM PDT 24
Finished May 16 01:00:16 PM PDT 24
Peak memory 203888 kb
Host smart-0baf03e3-c404-4c5a-ae46-fd9f78bc0f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233776043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3233776043
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.573120397
Short name T1083
Test name
Test status
Simulation time 13372245 ps
CPU time 0.71 seconds
Started May 16 12:59:35 PM PDT 24
Finished May 16 01:00:15 PM PDT 24
Peak memory 203900 kb
Host smart-0d37585a-df50-4448-ad8d-1e0c63ed500e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573120397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.573120397
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4198310698
Short name T986
Test name
Test status
Simulation time 11436742 ps
CPU time 0.74 seconds
Started May 16 12:59:39 PM PDT 24
Finished May 16 01:00:18 PM PDT 24
Peak memory 203948 kb
Host smart-bb4a6acf-cbb3-4c81-a0b8-0a2482fbbbb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198310698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4198310698
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2818602179
Short name T1097
Test name
Test status
Simulation time 23031067 ps
CPU time 0.69 seconds
Started May 16 12:59:38 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 203924 kb
Host smart-d2a7168c-1b76-4c53-982a-7c681c2bda87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818602179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2818602179
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2992730447
Short name T1056
Test name
Test status
Simulation time 13313095 ps
CPU time 0.73 seconds
Started May 16 12:59:37 PM PDT 24
Finished May 16 01:00:17 PM PDT 24
Peak memory 204192 kb
Host smart-727cfdc5-ecfe-40ad-bb23-7b3f259035d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992730447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2992730447
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.260999182
Short name T1031
Test name
Test status
Simulation time 529008731 ps
CPU time 3.27 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:07 PM PDT 24
Peak memory 217588 kb
Host smart-74a27592-b356-4204-98ac-103456dc5bc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260999182 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.260999182
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1080342502
Short name T1029
Test name
Test status
Simulation time 54144014 ps
CPU time 0.75 seconds
Started May 16 12:59:16 PM PDT 24
Finished May 16 12:59:54 PM PDT 24
Peak memory 203896 kb
Host smart-89b48ac0-511c-48b3-a3ae-403620787e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080342502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
080342502
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.323943546
Short name T1020
Test name
Test status
Simulation time 27440466 ps
CPU time 1.78 seconds
Started May 16 12:59:16 PM PDT 24
Finished May 16 12:59:54 PM PDT 24
Peak memory 215768 kb
Host smart-7796cc55-8ddd-4987-b54e-9a0bd02210e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323943546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.323943546
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3637120253
Short name T1066
Test name
Test status
Simulation time 126992178 ps
CPU time 2.18 seconds
Started May 16 12:59:27 PM PDT 24
Finished May 16 01:00:07 PM PDT 24
Peak memory 217108 kb
Host smart-647035d7-c680-4813-8378-d3581cc9c138
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637120253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
637120253
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3325449206
Short name T102
Test name
Test status
Simulation time 1096082251 ps
CPU time 17.75 seconds
Started May 16 12:59:18 PM PDT 24
Finished May 16 01:00:11 PM PDT 24
Peak memory 215824 kb
Host smart-b5e5b689-e4bc-41ff-8798-fc271b437b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325449206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3325449206
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.18025832
Short name T1071
Test name
Test status
Simulation time 199487993 ps
CPU time 1.67 seconds
Started May 16 12:59:19 PM PDT 24
Finished May 16 12:59:56 PM PDT 24
Peak memory 215844 kb
Host smart-cc5eba86-e334-495c-b6b3-a6992e9b79bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025832 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.18025832
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3429876153
Short name T133
Test name
Test status
Simulation time 31604604 ps
CPU time 1.8 seconds
Started May 16 12:59:18 PM PDT 24
Finished May 16 12:59:55 PM PDT 24
Peak memory 207492 kb
Host smart-6c2fa2ca-40a9-4ad6-8a91-feb378f2dbe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429876153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
429876153
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2509162817
Short name T1089
Test name
Test status
Simulation time 22409078 ps
CPU time 0.71 seconds
Started May 16 12:59:19 PM PDT 24
Finished May 16 12:59:55 PM PDT 24
Peak memory 204264 kb
Host smart-421f8619-6fe1-4697-add9-a1b09c0cb44c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509162817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
509162817
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.685827533
Short name T987
Test name
Test status
Simulation time 2109409415 ps
CPU time 3.93 seconds
Started May 16 12:59:19 PM PDT 24
Finished May 16 12:59:58 PM PDT 24
Peak memory 215788 kb
Host smart-a664665b-620c-4337-b911-643f957c9f55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685827533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.685827533
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.545584517
Short name T1052
Test name
Test status
Simulation time 1170207586 ps
CPU time 4.86 seconds
Started May 16 12:59:21 PM PDT 24
Finished May 16 01:00:01 PM PDT 24
Peak memory 217000 kb
Host smart-6595b98d-2107-4795-82d3-36955f7ded91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545584517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.545584517
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.169639172
Short name T121
Test name
Test status
Simulation time 1183115036 ps
CPU time 19.09 seconds
Started May 16 12:59:18 PM PDT 24
Finished May 16 01:00:12 PM PDT 24
Peak memory 216340 kb
Host smart-90b3a4c6-65d5-436f-9333-a3741c64a8f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169639172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.169639172
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1606485121
Short name T1045
Test name
Test status
Simulation time 81783101 ps
CPU time 1.54 seconds
Started May 16 12:59:17 PM PDT 24
Finished May 16 12:59:54 PM PDT 24
Peak memory 215912 kb
Host smart-c4a5d865-07de-4e11-a1f4-df2b694d9dd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606485121 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1606485121
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3260732444
Short name T1099
Test name
Test status
Simulation time 966488526 ps
CPU time 2.67 seconds
Started May 16 12:59:17 PM PDT 24
Finished May 16 12:59:56 PM PDT 24
Peak memory 215780 kb
Host smart-93c7997d-1c19-46cd-8330-5d1720504b10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260732444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
260732444
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3120613345
Short name T1073
Test name
Test status
Simulation time 47064244 ps
CPU time 0.72 seconds
Started May 16 12:59:17 PM PDT 24
Finished May 16 12:59:54 PM PDT 24
Peak memory 204172 kb
Host smart-ed7f9098-7f51-460f-94ed-2c5190364157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120613345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
120613345
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2365693892
Short name T163
Test name
Test status
Simulation time 227476390 ps
CPU time 4.48 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:07 PM PDT 24
Peak memory 215860 kb
Host smart-52899df7-8b08-40c6-9bf0-fd6c32b40ad2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365693892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2365693892
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2443274435
Short name T991
Test name
Test status
Simulation time 78098114 ps
CPU time 2.03 seconds
Started May 16 12:59:15 PM PDT 24
Finished May 16 12:59:54 PM PDT 24
Peak memory 215908 kb
Host smart-805e74a6-0e35-441c-8d1a-03cd144ebe2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443274435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
443274435
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3033136211
Short name T254
Test name
Test status
Simulation time 2069403959 ps
CPU time 13.25 seconds
Started May 16 12:59:14 PM PDT 24
Finished May 16 01:00:04 PM PDT 24
Peak memory 216008 kb
Host smart-4fd30656-6733-43e3-b87f-7f45fe4b372b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033136211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3033136211
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.995508535
Short name T1014
Test name
Test status
Simulation time 229864837 ps
CPU time 1.64 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:05 PM PDT 24
Peak memory 215756 kb
Host smart-8b1ba573-cd30-45c6-af27-fa6f41629444
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995508535 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.995508535
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.588304710
Short name T132
Test name
Test status
Simulation time 53201617 ps
CPU time 1.69 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:06 PM PDT 24
Peak memory 207516 kb
Host smart-354e96e2-8231-4e86-98e7-cc0aa369cf22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588304710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.588304710
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3828798306
Short name T1079
Test name
Test status
Simulation time 17616431 ps
CPU time 0.71 seconds
Started May 16 12:59:25 PM PDT 24
Finished May 16 01:00:03 PM PDT 24
Peak memory 203996 kb
Host smart-93910bdb-da16-4b41-b080-9229e628f32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828798306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
828798306
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.651785765
Short name T1050
Test name
Test status
Simulation time 424261286 ps
CPU time 3.02 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:06 PM PDT 24
Peak memory 215788 kb
Host smart-93049ec2-383b-4b0d-8c6d-ba723f5597e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651785765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.651785765
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.29455285
Short name T1070
Test name
Test status
Simulation time 343559385 ps
CPU time 4.57 seconds
Started May 16 12:59:21 PM PDT 24
Finished May 16 01:00:00 PM PDT 24
Peak memory 216020 kb
Host smart-7070992e-449b-42eb-ae65-c2c3f3eb4888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29455285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.29455285
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3786294171
Short name T1087
Test name
Test status
Simulation time 3093316365 ps
CPU time 18.93 seconds
Started May 16 12:59:23 PM PDT 24
Finished May 16 01:00:18 PM PDT 24
Peak memory 215932 kb
Host smart-19ad16c7-f1e1-4629-842d-ce54229b929a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786294171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3786294171
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3614396848
Short name T1038
Test name
Test status
Simulation time 144907567 ps
CPU time 3.52 seconds
Started May 16 12:59:25 PM PDT 24
Finished May 16 01:00:05 PM PDT 24
Peak memory 217252 kb
Host smart-2fa8a1dd-7c36-4bd4-b613-75c96bd9d2b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614396848 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3614396848
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2874027489
Short name T1069
Test name
Test status
Simulation time 432596618 ps
CPU time 2.52 seconds
Started May 16 12:59:26 PM PDT 24
Finished May 16 01:00:06 PM PDT 24
Peak memory 207484 kb
Host smart-71fcec0e-15b5-40e1-b3f8-531729c13418
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874027489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
874027489
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.5518154
Short name T1022
Test name
Test status
Simulation time 11595390 ps
CPU time 0.73 seconds
Started May 16 12:59:23 PM PDT 24
Finished May 16 12:59:59 PM PDT 24
Peak memory 204020 kb
Host smart-f3630a7c-45fe-4ad6-884e-5e4eb6b8d67d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5518154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.5518154
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1362333428
Short name T1032
Test name
Test status
Simulation time 45801312 ps
CPU time 1.65 seconds
Started May 16 12:59:25 PM PDT 24
Finished May 16 01:00:03 PM PDT 24
Peak memory 215780 kb
Host smart-8e9344bc-a2de-4068-9156-96c62e9ff849
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362333428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1362333428
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.528012472
Short name T118
Test name
Test status
Simulation time 41629285 ps
CPU time 2.65 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:08 PM PDT 24
Peak memory 215860 kb
Host smart-59d7e654-d8f3-45cd-b27c-3682872fd08d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528012472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.528012472
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2128387732
Short name T257
Test name
Test status
Simulation time 698917107 ps
CPU time 14.72 seconds
Started May 16 12:59:28 PM PDT 24
Finished May 16 01:00:20 PM PDT 24
Peak memory 215960 kb
Host smart-358fad29-d7a0-416b-bc16-2ff1e3a1590f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128387732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2128387732
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3902996394
Short name T465
Test name
Test status
Simulation time 14117498 ps
CPU time 0.74 seconds
Started May 16 01:26:19 PM PDT 24
Finished May 16 01:26:36 PM PDT 24
Peak memory 205752 kb
Host smart-6d5b3e47-0e6c-405c-b5dd-a66d3a42ed86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902996394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
902996394
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3526260904
Short name T684
Test name
Test status
Simulation time 361239504 ps
CPU time 2.35 seconds
Started May 16 01:26:17 PM PDT 24
Finished May 16 01:26:35 PM PDT 24
Peak memory 218576 kb
Host smart-83311fe3-910a-4102-a25a-29a72cdf7683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526260904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3526260904
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1056156729
Short name T464
Test name
Test status
Simulation time 29163799 ps
CPU time 0.78 seconds
Started May 16 01:26:21 PM PDT 24
Finished May 16 01:26:39 PM PDT 24
Peak memory 206492 kb
Host smart-8a5962ff-ba43-4257-bd08-6a7331360245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056156729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1056156729
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3932475856
Short name T433
Test name
Test status
Simulation time 3335576389 ps
CPU time 32.93 seconds
Started May 16 01:26:21 PM PDT 24
Finished May 16 01:27:11 PM PDT 24
Peak memory 250388 kb
Host smart-28cfc34d-21cb-4a10-a8e0-5179a9c05fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932475856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3932475856
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1530853446
Short name T466
Test name
Test status
Simulation time 157045131810 ps
CPU time 383.97 seconds
Started May 16 01:26:18 PM PDT 24
Finished May 16 01:32:58 PM PDT 24
Peak memory 251516 kb
Host smart-be9d6b27-d601-4e84-a465-9ade0f970832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530853446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1530853446
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4168306402
Short name T913
Test name
Test status
Simulation time 353266898 ps
CPU time 6.48 seconds
Started May 16 01:26:20 PM PDT 24
Finished May 16 01:26:43 PM PDT 24
Peak memory 233780 kb
Host smart-b36f87ed-fec6-48c2-8a88-1a75d1f8b567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168306402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4168306402
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1540264773
Short name T614
Test name
Test status
Simulation time 4343407054 ps
CPU time 35.52 seconds
Started May 16 01:26:22 PM PDT 24
Finished May 16 01:27:15 PM PDT 24
Peak memory 234772 kb
Host smart-194df10e-aac9-476e-9f3d-85b1d99d4826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540264773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1540264773
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3819996375
Short name T239
Test name
Test status
Simulation time 3804995854 ps
CPU time 5.69 seconds
Started May 16 01:26:21 PM PDT 24
Finished May 16 01:26:44 PM PDT 24
Peak memory 219720 kb
Host smart-881f1df5-44d8-43b6-a7ec-496e027d61dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819996375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3819996375
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.20807773
Short name T746
Test name
Test status
Simulation time 719962528 ps
CPU time 4.37 seconds
Started May 16 01:26:19 PM PDT 24
Finished May 16 01:26:39 PM PDT 24
Peak memory 218912 kb
Host smart-1d7bbd9a-ef73-4ad2-9427-24683955acfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20807773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.20807773
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3467962176
Short name T161
Test name
Test status
Simulation time 3114236595 ps
CPU time 16.9 seconds
Started May 16 01:26:21 PM PDT 24
Finished May 16 01:26:55 PM PDT 24
Peak memory 223092 kb
Host smart-8628878f-b460-45cb-871d-4fbb1f222359
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3467962176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3467962176
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.604863811
Short name T231
Test name
Test status
Simulation time 30639008472 ps
CPU time 151.36 seconds
Started May 16 01:26:18 PM PDT 24
Finished May 16 01:29:06 PM PDT 24
Peak memory 268172 kb
Host smart-2393bf6d-3b46-4aad-b58d-4a868608a004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604863811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.604863811
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1345081603
Short name T838
Test name
Test status
Simulation time 2538766638 ps
CPU time 23.94 seconds
Started May 16 01:26:24 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 216464 kb
Host smart-48184724-94b6-475b-b7d8-b58beed50931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345081603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1345081603
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3474352788
Short name T648
Test name
Test status
Simulation time 724731523 ps
CPU time 4.6 seconds
Started May 16 01:26:24 PM PDT 24
Finished May 16 01:26:47 PM PDT 24
Peak memory 216372 kb
Host smart-fc1dee33-a15d-4a80-b35a-ea275778fb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474352788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3474352788
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2972136401
Short name T80
Test name
Test status
Simulation time 12712500 ps
CPU time 0.7 seconds
Started May 16 01:26:24 PM PDT 24
Finished May 16 01:26:42 PM PDT 24
Peak memory 205520 kb
Host smart-2e6db169-fa3c-49f8-ad30-3e85237b7240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972136401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2972136401
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.925881624
Short name T842
Test name
Test status
Simulation time 32092722 ps
CPU time 0.77 seconds
Started May 16 01:26:19 PM PDT 24
Finished May 16 01:26:36 PM PDT 24
Peak memory 205812 kb
Host smart-d190cc71-8ecc-470f-9774-db6c23e31db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925881624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.925881624
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2843421474
Short name T601
Test name
Test status
Simulation time 18618587425 ps
CPU time 17.3 seconds
Started May 16 01:26:21 PM PDT 24
Finished May 16 01:26:55 PM PDT 24
Peak memory 237092 kb
Host smart-ae9064a8-4aaf-4e9a-b7f4-b0e9f20979c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843421474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2843421474
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1565525741
Short name T485
Test name
Test status
Simulation time 14342871 ps
CPU time 0.71 seconds
Started May 16 01:26:29 PM PDT 24
Finished May 16 01:26:46 PM PDT 24
Peak memory 205380 kb
Host smart-73e53c35-01e2-43fa-8972-7a7477f05692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565525741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
565525741
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3705123131
Short name T537
Test name
Test status
Simulation time 226956573 ps
CPU time 2.42 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:52 PM PDT 24
Peak memory 233488 kb
Host smart-fa09fb12-7411-4f9e-a834-833ecd2d2824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705123131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3705123131
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1848467360
Short name T595
Test name
Test status
Simulation time 62587242 ps
CPU time 0.79 seconds
Started May 16 01:26:18 PM PDT 24
Finished May 16 01:26:34 PM PDT 24
Peak memory 205452 kb
Host smart-4a6df686-c37f-42fd-8ff9-315f764004d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848467360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1848467360
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2558923409
Short name T84
Test name
Test status
Simulation time 9573838122 ps
CPU time 48.86 seconds
Started May 16 01:26:45 PM PDT 24
Finished May 16 01:27:47 PM PDT 24
Peak memory 257456 kb
Host smart-d03dda94-13fc-495f-989d-a9807b000282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558923409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2558923409
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3675761363
Short name T45
Test name
Test status
Simulation time 111643696424 ps
CPU time 266.32 seconds
Started May 16 01:26:46 PM PDT 24
Finished May 16 01:31:27 PM PDT 24
Peak memory 254752 kb
Host smart-cff486dd-11f9-4829-9264-790d39f9adbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675761363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3675761363
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1847124641
Short name T220
Test name
Test status
Simulation time 5068066910 ps
CPU time 108.63 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:28:38 PM PDT 24
Peak memory 252032 kb
Host smart-c7f04a6a-1d80-4022-8d24-5e752aaf8f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847124641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1847124641
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3931473926
Short name T609
Test name
Test status
Simulation time 146597588 ps
CPU time 5.15 seconds
Started May 16 01:26:26 PM PDT 24
Finished May 16 01:26:48 PM PDT 24
Peak memory 224600 kb
Host smart-d5d8ae46-582e-44ae-bee8-c56c5e564d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931473926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3931473926
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3463725233
Short name T459
Test name
Test status
Simulation time 625444800 ps
CPU time 8.54 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:58 PM PDT 24
Peak memory 233644 kb
Host smart-87f33960-ca5e-4254-9919-f0b3fcda6e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463725233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3463725233
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.789959837
Short name T272
Test name
Test status
Simulation time 6678595327 ps
CPU time 26.67 seconds
Started May 16 01:26:27 PM PDT 24
Finished May 16 01:27:10 PM PDT 24
Peak memory 247304 kb
Host smart-45735496-550c-49e2-a573-e4614b01eaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789959837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.789959837
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2596001256
Short name T523
Test name
Test status
Simulation time 59340351 ps
CPU time 1.03 seconds
Started May 16 01:26:21 PM PDT 24
Finished May 16 01:26:39 PM PDT 24
Peak memory 218000 kb
Host smart-7ae32fa8-54ab-42e7-80e2-cf2202a087f0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596001256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2596001256
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3520654466
Short name T691
Test name
Test status
Simulation time 3983829577 ps
CPU time 7.72 seconds
Started May 16 01:26:40 PM PDT 24
Finished May 16 01:27:03 PM PDT 24
Peak memory 229884 kb
Host smart-95e256ed-13c8-4b09-afe3-afdb63bfa319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520654466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3520654466
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.189465480
Short name T412
Test name
Test status
Simulation time 1354974646 ps
CPU time 4.03 seconds
Started May 16 01:26:26 PM PDT 24
Finished May 16 01:26:47 PM PDT 24
Peak memory 233760 kb
Host smart-dd5a1dc6-d785-4476-83a1-30165d899ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189465480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.189465480
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.386884663
Short name T927
Test name
Test status
Simulation time 106532160 ps
CPU time 4 seconds
Started May 16 01:26:29 PM PDT 24
Finished May 16 01:26:49 PM PDT 24
Peak memory 221896 kb
Host smart-7cd25273-8b64-49b8-aa0a-a0d80e4bc171
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=386884663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.386884663
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.787991014
Short name T69
Test name
Test status
Simulation time 39654840 ps
CPU time 1.04 seconds
Started May 16 01:26:24 PM PDT 24
Finished May 16 01:26:43 PM PDT 24
Peak memory 235144 kb
Host smart-c7b2e560-501c-462e-8d29-49a7d06913ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787991014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.787991014
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1255228710
Short name T4
Test name
Test status
Simulation time 60464468 ps
CPU time 0.71 seconds
Started May 16 01:26:16 PM PDT 24
Finished May 16 01:26:33 PM PDT 24
Peak memory 205584 kb
Host smart-9c4cb624-2471-4325-9fb4-e6bf4df9243e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255228710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1255228710
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3589528104
Short name T320
Test name
Test status
Simulation time 4752295133 ps
CPU time 7.34 seconds
Started May 16 01:26:17 PM PDT 24
Finished May 16 01:26:40 PM PDT 24
Peak memory 216480 kb
Host smart-ed1c67ea-0c4d-4798-9f69-839857644c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589528104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3589528104
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1683395519
Short name T370
Test name
Test status
Simulation time 398646181 ps
CPU time 1.49 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 216284 kb
Host smart-57a46b0e-b5d4-4999-982d-fe8cf674870e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683395519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1683395519
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1658798073
Short name T917
Test name
Test status
Simulation time 105857116 ps
CPU time 0.96 seconds
Started May 16 01:26:30 PM PDT 24
Finished May 16 01:26:47 PM PDT 24
Peak memory 205824 kb
Host smart-3588e4ad-d41d-4289-bd70-abe15e48826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658798073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1658798073
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1223264220
Short name T359
Test name
Test status
Simulation time 2816883345 ps
CPU time 5.1 seconds
Started May 16 01:26:29 PM PDT 24
Finished May 16 01:26:51 PM PDT 24
Peak memory 235584 kb
Host smart-2fe2dad9-f6b1-4049-8381-ef676698b91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223264220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1223264220
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3386002815
Short name T592
Test name
Test status
Simulation time 22186678 ps
CPU time 0.76 seconds
Started May 16 01:26:55 PM PDT 24
Finished May 16 01:27:13 PM PDT 24
Peak memory 204720 kb
Host smart-b5b78c98-c22c-4137-82c9-f8959e963de5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386002815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3386002815
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3169841407
Short name T598
Test name
Test status
Simulation time 31946227 ps
CPU time 2.16 seconds
Started May 16 01:26:58 PM PDT 24
Finished May 16 01:27:19 PM PDT 24
Peak memory 218584 kb
Host smart-5a3ebdf0-fdff-4b5b-b941-10db0ba5a71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169841407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3169841407
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3494059918
Short name T858
Test name
Test status
Simulation time 39405856 ps
CPU time 0.78 seconds
Started May 16 01:26:59 PM PDT 24
Finished May 16 01:27:21 PM PDT 24
Peak memory 206456 kb
Host smart-f3e7f606-c119-41c1-9c9c-6dc137165663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494059918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3494059918
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2852072744
Short name T389
Test name
Test status
Simulation time 47221313755 ps
CPU time 178.02 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:30:25 PM PDT 24
Peak memory 249276 kb
Host smart-2fe8ed3c-bef3-459b-9c0b-c675fdb15b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852072744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2852072744
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.759478182
Short name T552
Test name
Test status
Simulation time 2832420660 ps
CPU time 16.84 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:44 PM PDT 24
Peak memory 224804 kb
Host smart-8a556c28-692d-4ecb-9d43-f638560975d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759478182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.759478182
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.228602662
Short name T719
Test name
Test status
Simulation time 12209703969 ps
CPU time 16.18 seconds
Started May 16 01:26:59 PM PDT 24
Finished May 16 01:27:34 PM PDT 24
Peak memory 241108 kb
Host smart-1e304eb7-5ed1-4e51-960c-0c7839d76596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228602662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.228602662
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.480656606
Short name T701
Test name
Test status
Simulation time 1522171253 ps
CPU time 6.88 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:32 PM PDT 24
Peak memory 233244 kb
Host smart-b60ce97b-30ad-4fa9-935c-9c8144ca49fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480656606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.480656606
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3916747023
Short name T628
Test name
Test status
Simulation time 3533491045 ps
CPU time 14.51 seconds
Started May 16 01:27:00 PM PDT 24
Finished May 16 01:27:36 PM PDT 24
Peak memory 238332 kb
Host smart-7bccb7b9-172b-49fe-b64d-312708d3e7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916747023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3916747023
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2326007454
Short name T358
Test name
Test status
Simulation time 16151179 ps
CPU time 1.06 seconds
Started May 16 01:27:00 PM PDT 24
Finished May 16 01:27:22 PM PDT 24
Peak memory 216684 kb
Host smart-381c563e-3923-492c-94ab-657287a85d75
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326007454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2326007454
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1648965621
Short name T492
Test name
Test status
Simulation time 7902639085 ps
CPU time 19.99 seconds
Started May 16 01:27:06 PM PDT 24
Finished May 16 01:27:48 PM PDT 24
Peak memory 222792 kb
Host smart-665c48ce-4dde-43d7-b61a-6a48af9782ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648965621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1648965621
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.385466946
Short name T182
Test name
Test status
Simulation time 8357343253 ps
CPU time 13.06 seconds
Started May 16 01:27:02 PM PDT 24
Finished May 16 01:27:37 PM PDT 24
Peak memory 233808 kb
Host smart-60ca3b5b-ede7-42e0-b463-289676bdcac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385466946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.385466946
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3302124864
Short name T403
Test name
Test status
Simulation time 1763150080 ps
CPU time 3.69 seconds
Started May 16 01:26:57 PM PDT 24
Finished May 16 01:27:18 PM PDT 24
Peak memory 219616 kb
Host smart-38653876-7280-4630-b64b-2aff7f131594
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3302124864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3302124864
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4187993864
Short name T965
Test name
Test status
Simulation time 35496482870 ps
CPU time 47.73 seconds
Started May 16 01:26:59 PM PDT 24
Finished May 16 01:28:08 PM PDT 24
Peak memory 216480 kb
Host smart-587ba47f-10a2-4ce9-afbd-353fd7e8d281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187993864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4187993864
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4124398660
Short name T774
Test name
Test status
Simulation time 12010881233 ps
CPU time 14.08 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:41 PM PDT 24
Peak memory 216508 kb
Host smart-1fa08921-68b3-4acf-8fc7-2eb38d4c8527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124398660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4124398660
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2382276359
Short name T877
Test name
Test status
Simulation time 12724874 ps
CPU time 0.69 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:27:23 PM PDT 24
Peak memory 205448 kb
Host smart-6908adf5-459f-4878-b153-f508af7392bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382276359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2382276359
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4024080005
Short name T338
Test name
Test status
Simulation time 124566689 ps
CPU time 0.78 seconds
Started May 16 01:27:02 PM PDT 24
Finished May 16 01:27:25 PM PDT 24
Peak memory 205864 kb
Host smart-c6cfef56-ee25-495a-87a0-af16bf760b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024080005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4024080005
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2706657448
Short name T953
Test name
Test status
Simulation time 230572450 ps
CPU time 2.73 seconds
Started May 16 01:26:56 PM PDT 24
Finished May 16 01:27:15 PM PDT 24
Peak memory 224576 kb
Host smart-9cc2bc93-fb6e-4aa3-b5cd-2aa0943565e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706657448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2706657448
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3094935984
Short name T703
Test name
Test status
Simulation time 44049698 ps
CPU time 0.75 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:27:23 PM PDT 24
Peak memory 205400 kb
Host smart-11b93ca6-f419-466b-ae57-b7909fd3ab63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094935984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3094935984
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.426515274
Short name T655
Test name
Test status
Simulation time 554140441 ps
CPU time 6.09 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:31 PM PDT 24
Peak memory 233992 kb
Host smart-5ad359d5-77dd-48de-9e4e-bd4dae0471eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426515274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.426515274
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2101429014
Short name T704
Test name
Test status
Simulation time 69981870 ps
CPU time 0.79 seconds
Started May 16 01:26:56 PM PDT 24
Finished May 16 01:27:14 PM PDT 24
Peak memory 206472 kb
Host smart-a50c00a2-f728-4e07-b42e-8ce8a9370e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101429014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2101429014
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2751141540
Short name T137
Test name
Test status
Simulation time 97143326632 ps
CPU time 185.22 seconds
Started May 16 01:27:06 PM PDT 24
Finished May 16 01:30:33 PM PDT 24
Peak memory 251464 kb
Host smart-8df25115-ea88-4910-b89c-f902f18c1cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751141540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2751141540
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2681627955
Short name T849
Test name
Test status
Simulation time 34145020554 ps
CPU time 143.09 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:29:49 PM PDT 24
Peak memory 241152 kb
Host smart-2238d91b-5c9a-406a-b7ea-0fb5ddaa17ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681627955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2681627955
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1915664125
Short name T291
Test name
Test status
Simulation time 6874775202 ps
CPU time 31.48 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:56 PM PDT 24
Peak memory 232828 kb
Host smart-2b26058c-1240-4961-ac91-833bbf75d093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915664125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1915664125
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1825541310
Short name T124
Test name
Test status
Simulation time 268831309 ps
CPU time 2.72 seconds
Started May 16 01:27:02 PM PDT 24
Finished May 16 01:27:27 PM PDT 24
Peak memory 224516 kb
Host smart-77b82457-d05a-4cde-8059-f2e83bd4a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825541310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1825541310
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3005085932
Short name T522
Test name
Test status
Simulation time 2447628422 ps
CPU time 18.49 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:46 PM PDT 24
Peak memory 234136 kb
Host smart-21f69d76-3389-4c8c-9362-7b2cb1494739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005085932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3005085932
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2613675759
Short name T385
Test name
Test status
Simulation time 15365658 ps
CPU time 0.98 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:27:23 PM PDT 24
Peak memory 217972 kb
Host smart-6dfad412-2497-41df-89a9-ab37e66cd1f4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613675759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2613675759
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.294701744
Short name T273
Test name
Test status
Simulation time 1593782733 ps
CPU time 4.68 seconds
Started May 16 01:26:59 PM PDT 24
Finished May 16 01:27:24 PM PDT 24
Peak memory 233304 kb
Host smart-fb20ff1a-9049-42db-adb1-bd1948f5dac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294701744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.294701744
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.285021490
Short name T944
Test name
Test status
Simulation time 14041911156 ps
CPU time 6.33 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:32 PM PDT 24
Peak memory 233428 kb
Host smart-c22ef28b-2a7b-48e3-a8c6-56a07aeca3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285021490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.285021490
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3324452347
Short name T554
Test name
Test status
Simulation time 1671490871 ps
CPU time 18.77 seconds
Started May 16 01:26:57 PM PDT 24
Finished May 16 01:27:34 PM PDT 24
Peak memory 222252 kb
Host smart-d5691824-6542-4c8e-8b74-d20413ff3b09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3324452347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3324452347
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.230638417
Short name T431
Test name
Test status
Simulation time 1361401394 ps
CPU time 16.7 seconds
Started May 16 01:26:54 PM PDT 24
Finished May 16 01:27:28 PM PDT 24
Peak memory 219540 kb
Host smart-30454b13-05c9-45c4-b8bb-5069435cc54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230638417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.230638417
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.595315351
Short name T345
Test name
Test status
Simulation time 5998751708 ps
CPU time 5.73 seconds
Started May 16 01:26:57 PM PDT 24
Finished May 16 01:27:21 PM PDT 24
Peak memory 216544 kb
Host smart-757720ac-4766-4fa9-926c-047c7daa85b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595315351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.595315351
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1352357510
Short name T369
Test name
Test status
Simulation time 59452449 ps
CPU time 1.2 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:26 PM PDT 24
Peak memory 216356 kb
Host smart-08410460-d013-43bb-82b0-63878a3d3919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352357510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1352357510
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2628716398
Short name T866
Test name
Test status
Simulation time 57505718 ps
CPU time 0.71 seconds
Started May 16 01:26:58 PM PDT 24
Finished May 16 01:27:18 PM PDT 24
Peak memory 205752 kb
Host smart-f704df17-ad64-4b9b-b7bd-d1915ba6975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628716398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2628716398
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1974087912
Short name T406
Test name
Test status
Simulation time 46638912713 ps
CPU time 31.21 seconds
Started May 16 01:26:59 PM PDT 24
Finished May 16 01:27:50 PM PDT 24
Peak memory 236356 kb
Host smart-004e56f4-9cc2-4de8-b9ad-e7a38abf00fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974087912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1974087912
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2057279835
Short name T695
Test name
Test status
Simulation time 23649603 ps
CPU time 0.77 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:26 PM PDT 24
Peak memory 204744 kb
Host smart-d55fa162-4eb5-4b75-b725-2d44333359cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057279835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2057279835
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2473376659
Short name T423
Test name
Test status
Simulation time 404767938 ps
CPU time 5.54 seconds
Started May 16 01:27:00 PM PDT 24
Finished May 16 01:27:26 PM PDT 24
Peak memory 218564 kb
Host smart-9ae53032-bd62-43bb-ac78-c9aaa65808c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473376659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2473376659
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.883234050
Short name T543
Test name
Test status
Simulation time 61866988 ps
CPU time 0.82 seconds
Started May 16 01:27:02 PM PDT 24
Finished May 16 01:27:25 PM PDT 24
Peak memory 206824 kb
Host smart-43c30ce7-80d1-41ef-94f1-d59a67ea2412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883234050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.883234050
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1501037591
Short name T376
Test name
Test status
Simulation time 50371951941 ps
CPU time 151.47 seconds
Started May 16 01:26:59 PM PDT 24
Finished May 16 01:29:50 PM PDT 24
Peak memory 241048 kb
Host smart-2131c38e-e0c4-4206-bb47-0e568d17406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501037591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1501037591
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1752393145
Short name T39
Test name
Test status
Simulation time 40673229031 ps
CPU time 65.71 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:28:29 PM PDT 24
Peak memory 254200 kb
Host smart-1cb76b64-16a0-4906-b51a-5d12ce6de6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752393145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1752393145
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2067547913
Short name T27
Test name
Test status
Simulation time 19813243083 ps
CPU time 109.04 seconds
Started May 16 01:27:07 PM PDT 24
Finished May 16 01:29:18 PM PDT 24
Peak memory 251772 kb
Host smart-89361281-480a-4d9c-9471-e02e4d840f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067547913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2067547913
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3475082866
Short name T780
Test name
Test status
Simulation time 2032209239 ps
CPU time 37.24 seconds
Started May 16 01:26:56 PM PDT 24
Finished May 16 01:27:51 PM PDT 24
Peak memory 232772 kb
Host smart-70e9be3c-7a1b-42ab-97f2-3d426df754fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475082866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3475082866
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3496214484
Short name T557
Test name
Test status
Simulation time 143886445 ps
CPU time 4.11 seconds
Started May 16 01:27:02 PM PDT 24
Finished May 16 01:27:29 PM PDT 24
Peak memory 219576 kb
Host smart-eb08b121-f741-41cf-b4bc-af3774558a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496214484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3496214484
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2618561311
Short name T811
Test name
Test status
Simulation time 2066401400 ps
CPU time 9.78 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:37 PM PDT 24
Peak memory 234980 kb
Host smart-aec959ad-2449-4e88-9fc1-30fa77e6b152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618561311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2618561311
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.647799899
Short name T578
Test name
Test status
Simulation time 24821865 ps
CPU time 1.05 seconds
Started May 16 01:27:00 PM PDT 24
Finished May 16 01:27:22 PM PDT 24
Peak memory 217972 kb
Host smart-28400228-004c-4da7-9734-54073a074b0e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647799899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.647799899
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1402734002
Short name T375
Test name
Test status
Simulation time 28872471 ps
CPU time 2.12 seconds
Started May 16 01:26:58 PM PDT 24
Finished May 16 01:27:20 PM PDT 24
Peak memory 216108 kb
Host smart-c78f3657-47c0-41d6-a7de-78b4937ca71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402734002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1402734002
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3485992956
Short name T879
Test name
Test status
Simulation time 225692197 ps
CPU time 2.87 seconds
Started May 16 01:26:59 PM PDT 24
Finished May 16 01:27:21 PM PDT 24
Peak memory 234280 kb
Host smart-467e8bef-594e-48d3-a6cf-e725de38c07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485992956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3485992956
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3903639379
Short name T509
Test name
Test status
Simulation time 139446827 ps
CPU time 3.67 seconds
Started May 16 01:26:58 PM PDT 24
Finished May 16 01:27:21 PM PDT 24
Peak memory 219296 kb
Host smart-fc5cf1f2-1340-4950-9a0d-e9208f1ba997
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3903639379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3903639379
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1300069227
Short name T788
Test name
Test status
Simulation time 41137383 ps
CPU time 0.93 seconds
Started May 16 01:26:57 PM PDT 24
Finished May 16 01:27:15 PM PDT 24
Peak memory 206456 kb
Host smart-c767cf90-0eb1-4456-8ce9-78cf840e1a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300069227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1300069227
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1855189572
Short name T302
Test name
Test status
Simulation time 3119885582 ps
CPU time 2.83 seconds
Started May 16 01:27:00 PM PDT 24
Finished May 16 01:27:24 PM PDT 24
Peak memory 216592 kb
Host smart-4c9642db-d14f-42ee-8938-4f98a62b778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855189572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1855189572
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3683851886
Short name T733
Test name
Test status
Simulation time 4175090466 ps
CPU time 10.63 seconds
Started May 16 01:26:57 PM PDT 24
Finished May 16 01:27:24 PM PDT 24
Peak memory 217320 kb
Host smart-9a7e2408-1081-4032-bd1b-1051805ae3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683851886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3683851886
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.668121599
Short name T665
Test name
Test status
Simulation time 2413696523 ps
CPU time 2.46 seconds
Started May 16 01:26:58 PM PDT 24
Finished May 16 01:27:20 PM PDT 24
Peak memory 216796 kb
Host smart-4bec5cbd-f7e4-4d1f-8b39-1924237f41f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668121599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.668121599
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1069855909
Short name T585
Test name
Test status
Simulation time 46239548 ps
CPU time 0.71 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:27:23 PM PDT 24
Peak memory 205820 kb
Host smart-83a56163-431f-4312-b402-a5f6a035bfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069855909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1069855909
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3432677754
Short name T194
Test name
Test status
Simulation time 245929250 ps
CPU time 5.96 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:31 PM PDT 24
Peak memory 217344 kb
Host smart-627f4a5f-8b98-4aef-a921-98e57368dd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432677754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3432677754
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3203293922
Short name T61
Test name
Test status
Simulation time 18038754 ps
CPU time 0.7 seconds
Started May 16 01:27:04 PM PDT 24
Finished May 16 01:27:27 PM PDT 24
Peak memory 205704 kb
Host smart-ccfbd34e-38c6-4f1d-9273-a91a0c526ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203293922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3203293922
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.804438334
Short name T786
Test name
Test status
Simulation time 904222482 ps
CPU time 4.7 seconds
Started May 16 01:27:02 PM PDT 24
Finished May 16 01:27:29 PM PDT 24
Peak memory 237100 kb
Host smart-8c793081-c3fe-4879-b2cf-b61707d1a06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804438334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.804438334
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1904554249
Short name T72
Test name
Test status
Simulation time 38145616 ps
CPU time 0.74 seconds
Started May 16 01:27:02 PM PDT 24
Finished May 16 01:27:25 PM PDT 24
Peak memory 205436 kb
Host smart-481568b3-4014-457f-bc70-56ee050ef3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904554249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1904554249
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2315400033
Short name T920
Test name
Test status
Simulation time 8438025548 ps
CPU time 46.35 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:28:10 PM PDT 24
Peak memory 250552 kb
Host smart-9ae32ae6-d89c-41e9-95fb-bce7f4f55e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315400033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2315400033
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3446009347
Short name T298
Test name
Test status
Simulation time 1840926160 ps
CPU time 16.87 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:43 PM PDT 24
Peak memory 217348 kb
Host smart-6530789c-8323-4d96-818d-ed6a9b029d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446009347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3446009347
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2475722653
Short name T416
Test name
Test status
Simulation time 1516036306 ps
CPU time 15.81 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:27:39 PM PDT 24
Peak memory 240928 kb
Host smart-7ccd75a5-8d05-474f-91fa-423041ef19d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475722653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2475722653
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1617099309
Short name T561
Test name
Test status
Simulation time 33698165 ps
CPU time 2.36 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:27 PM PDT 24
Peak memory 221416 kb
Host smart-2dfc0d2f-cf47-4332-aa2b-8da84bede129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617099309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1617099309
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1995315647
Short name T352
Test name
Test status
Simulation time 225274431 ps
CPU time 1.93 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:27 PM PDT 24
Peak memory 216116 kb
Host smart-8dbf2c1a-ea4d-40c4-aa98-7f0a0a8970d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995315647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1995315647
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2736047893
Short name T752
Test name
Test status
Simulation time 17150322 ps
CPU time 1.01 seconds
Started May 16 01:26:58 PM PDT 24
Finished May 16 01:27:18 PM PDT 24
Peak memory 216648 kb
Host smart-fbad1285-a9a8-4c3e-ad39-f5678df465b1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736047893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2736047893
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3368111007
Short name T732
Test name
Test status
Simulation time 3998655291 ps
CPU time 14.43 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:39 PM PDT 24
Peak memory 233848 kb
Host smart-c08b6821-96c7-432b-9672-07a91cb78588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368111007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3368111007
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.116196112
Short name T814
Test name
Test status
Simulation time 3551930312 ps
CPU time 7.32 seconds
Started May 16 01:27:06 PM PDT 24
Finished May 16 01:27:35 PM PDT 24
Peak memory 235208 kb
Host smart-e4bc6b01-efc2-4c1b-9c8b-aa32933618ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116196112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.116196112
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.949286167
Short name T494
Test name
Test status
Simulation time 2505191134 ps
CPU time 8.89 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:34 PM PDT 24
Peak memory 221460 kb
Host smart-04ab2986-4525-410f-bd10-b145d108bdf3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=949286167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.949286167
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1770298636
Short name T903
Test name
Test status
Simulation time 4348523117 ps
CPU time 22.86 seconds
Started May 16 01:26:58 PM PDT 24
Finished May 16 01:27:39 PM PDT 24
Peak memory 216556 kb
Host smart-9ae4f876-0da9-40ed-b0af-97679403e58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770298636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1770298636
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.412448768
Short name T342
Test name
Test status
Simulation time 89047018 ps
CPU time 1.31 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:27:24 PM PDT 24
Peak memory 207752 kb
Host smart-f7f82c76-0c6b-40a7-b074-44c53aef5fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412448768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.412448768
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.103985178
Short name T142
Test name
Test status
Simulation time 114931813 ps
CPU time 1.71 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:29 PM PDT 24
Peak memory 216356 kb
Host smart-1a232e68-e3bf-4d3b-97b6-6a1d1bf36de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103985178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.103985178
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1824534932
Short name T789
Test name
Test status
Simulation time 518693419 ps
CPU time 0.99 seconds
Started May 16 01:26:59 PM PDT 24
Finished May 16 01:27:20 PM PDT 24
Peak memory 206892 kb
Host smart-d39e0160-0746-4049-86b0-7542dd3efc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824534932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1824534932
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.21117074
Short name T793
Test name
Test status
Simulation time 4332594103 ps
CPU time 5.62 seconds
Started May 16 01:27:02 PM PDT 24
Finished May 16 01:27:30 PM PDT 24
Peak memory 233820 kb
Host smart-f3b8b185-0dea-4234-bf86-3396fbd56f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21117074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.21117074
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1967267496
Short name T942
Test name
Test status
Simulation time 10877768 ps
CPU time 0.69 seconds
Started May 16 01:27:04 PM PDT 24
Finished May 16 01:27:27 PM PDT 24
Peak memory 205756 kb
Host smart-f847fa7b-9eca-4a0e-8969-660eefe240a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967267496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1967267496
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3424615733
Short name T712
Test name
Test status
Simulation time 115518784 ps
CPU time 2.45 seconds
Started May 16 01:27:04 PM PDT 24
Finished May 16 01:27:29 PM PDT 24
Peak memory 218560 kb
Host smart-fa3098ab-b13b-4cd9-804a-4b57bd5538bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424615733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3424615733
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2767776640
Short name T428
Test name
Test status
Simulation time 15147880 ps
CPU time 0.8 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:25 PM PDT 24
Peak memory 205428 kb
Host smart-15f98efc-e7e4-42fe-b50b-7bd0c55b5c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767776640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2767776640
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3817375450
Short name T941
Test name
Test status
Simulation time 24564457083 ps
CPU time 171.84 seconds
Started May 16 01:27:06 PM PDT 24
Finished May 16 01:30:20 PM PDT 24
Peak memory 249236 kb
Host smart-e44ef9b5-3eca-45d3-9887-a06af36fac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817375450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3817375450
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3172786356
Short name T621
Test name
Test status
Simulation time 74906074 ps
CPU time 3.6 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:31 PM PDT 24
Peak memory 232760 kb
Host smart-283524c0-b14a-40d6-ba87-4fe9eda6493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172786356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3172786356
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3606508270
Short name T769
Test name
Test status
Simulation time 59599971 ps
CPU time 2.52 seconds
Started May 16 01:27:12 PM PDT 24
Finished May 16 01:27:37 PM PDT 24
Peak memory 221212 kb
Host smart-f5bdb31a-54f1-43c9-9b3e-e9400928d846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606508270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3606508270
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1324125743
Short name T323
Test name
Test status
Simulation time 132370191 ps
CPU time 1.06 seconds
Started May 16 01:27:09 PM PDT 24
Finished May 16 01:27:31 PM PDT 24
Peak memory 217976 kb
Host smart-ac27255a-86d1-405e-9b84-e023d1229f78
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324125743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1324125743
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.824443524
Short name T35
Test name
Test status
Simulation time 24019265021 ps
CPU time 15.93 seconds
Started May 16 01:27:06 PM PDT 24
Finished May 16 01:27:44 PM PDT 24
Peak memory 232888 kb
Host smart-ee9af772-8231-49e8-8081-66b40bc3117e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824443524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.824443524
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1711856248
Short name T331
Test name
Test status
Simulation time 59096029 ps
CPU time 2.27 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:30 PM PDT 24
Peak memory 220788 kb
Host smart-fdb6bb54-a5a0-40e7-ba0e-28fa4b9bc107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711856248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1711856248
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3532894789
Short name T155
Test name
Test status
Simulation time 2174823733 ps
CPU time 8.03 seconds
Started May 16 01:27:02 PM PDT 24
Finished May 16 01:27:33 PM PDT 24
Peak memory 222516 kb
Host smart-084aaf3f-7ad6-406f-a88a-aa0ab2e4b932
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3532894789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3532894789
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1762858862
Short name T148
Test name
Test status
Simulation time 12759352437 ps
CPU time 184.78 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:30:30 PM PDT 24
Peak memory 257088 kb
Host smart-11894c90-5a7a-42dc-88ff-73210cddd9d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762858862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1762858862
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1890063286
Short name T843
Test name
Test status
Simulation time 1748636847 ps
CPU time 13.48 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:49 PM PDT 24
Peak memory 216496 kb
Host smart-a44e55bb-c2d0-473a-820e-250f4d25b40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890063286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1890063286
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.383223806
Short name T340
Test name
Test status
Simulation time 28767852 ps
CPU time 0.69 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:28 PM PDT 24
Peak memory 205604 kb
Host smart-b9255589-c363-49fd-9f4c-c22ec6cb7a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383223806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.383223806
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1021786924
Short name T251
Test name
Test status
Simulation time 113625452 ps
CPU time 2.04 seconds
Started May 16 01:27:08 PM PDT 24
Finished May 16 01:27:32 PM PDT 24
Peak memory 216392 kb
Host smart-e6b4f2fc-7c0a-4df3-90dc-a4878de7bfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021786924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1021786924
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3906153926
Short name T735
Test name
Test status
Simulation time 135061553 ps
CPU time 1.02 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:36 PM PDT 24
Peak memory 205836 kb
Host smart-3b0fb527-c2b9-4da5-9ccc-50b7136b5a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906153926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3906153926
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2855780896
Short name T971
Test name
Test status
Simulation time 1718230465 ps
CPU time 4.58 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:32 PM PDT 24
Peak memory 219348 kb
Host smart-c83c107b-092d-4608-a735-f46ffafd3ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855780896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2855780896
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.709752461
Short name T966
Test name
Test status
Simulation time 32353054 ps
CPU time 0.69 seconds
Started May 16 01:27:12 PM PDT 24
Finished May 16 01:27:35 PM PDT 24
Peak memory 204608 kb
Host smart-08a3b127-922f-4424-be64-f3405b8b19d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709752461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.709752461
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.457495846
Short name T861
Test name
Test status
Simulation time 16289953276 ps
CPU time 22.36 seconds
Started May 16 01:27:12 PM PDT 24
Finished May 16 01:27:57 PM PDT 24
Peak memory 224616 kb
Host smart-34e2f6f1-eed0-416d-b99c-984d34c4eb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457495846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.457495846
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3234796897
Short name T690
Test name
Test status
Simulation time 17644635 ps
CPU time 0.77 seconds
Started May 16 01:27:09 PM PDT 24
Finished May 16 01:27:31 PM PDT 24
Peak memory 205432 kb
Host smart-10731478-55e5-4961-acce-bc2b1c47ccde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234796897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3234796897
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.550920056
Short name T461
Test name
Test status
Simulation time 31677877 ps
CPU time 0.73 seconds
Started May 16 01:27:11 PM PDT 24
Finished May 16 01:27:34 PM PDT 24
Peak memory 215956 kb
Host smart-4cc49e4d-e8bc-4f03-8705-18cd78e0a320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550920056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.550920056
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1671196636
Short name T223
Test name
Test status
Simulation time 332337225878 ps
CPU time 271.62 seconds
Started May 16 01:27:12 PM PDT 24
Finished May 16 01:32:06 PM PDT 24
Peak memory 253520 kb
Host smart-1748579b-06ce-4591-b4d5-aa223056e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671196636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1671196636
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3585843017
Short name T741
Test name
Test status
Simulation time 63807568220 ps
CPU time 297.54 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:32:23 PM PDT 24
Peak memory 249392 kb
Host smart-7fa4e075-1bb9-4735-859c-3c2418cfca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585843017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3585843017
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3357005445
Short name T829
Test name
Test status
Simulation time 691892547 ps
CPU time 2.88 seconds
Started May 16 01:27:07 PM PDT 24
Finished May 16 01:27:32 PM PDT 24
Peak memory 216844 kb
Host smart-549bf23a-54c5-4d2b-a0e5-6630b8cf9ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357005445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3357005445
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1258658010
Short name T892
Test name
Test status
Simulation time 542417843 ps
CPU time 10.46 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:38 PM PDT 24
Peak memory 224524 kb
Host smart-daca6ea4-4bdc-44f5-b9e9-dd52ccc904e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258658010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1258658010
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2248802306
Short name T318
Test name
Test status
Simulation time 30249429 ps
CPU time 1.05 seconds
Started May 16 01:27:03 PM PDT 24
Finished May 16 01:27:26 PM PDT 24
Peak memory 217984 kb
Host smart-eff3149c-f48c-42de-9b00-79547f5e7c87
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248802306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2248802306
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1828877773
Short name T245
Test name
Test status
Simulation time 1661196374 ps
CPU time 7.6 seconds
Started May 16 01:27:06 PM PDT 24
Finished May 16 01:27:36 PM PDT 24
Peak memory 218648 kb
Host smart-c6f8c753-2d1b-402c-9283-d3e6e4de06e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828877773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1828877773
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.860910487
Short name T195
Test name
Test status
Simulation time 2264288458 ps
CPU time 5.38 seconds
Started May 16 01:27:06 PM PDT 24
Finished May 16 01:27:33 PM PDT 24
Peak memory 237276 kb
Host smart-ddd0ded7-6943-49bc-89f1-6ae16ba54003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860910487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.860910487
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.982968306
Short name T671
Test name
Test status
Simulation time 745521691 ps
CPU time 10.42 seconds
Started May 16 01:27:12 PM PDT 24
Finished May 16 01:27:45 PM PDT 24
Peak memory 222892 kb
Host smart-c735fbb3-d8bd-40e3-ab23-2c76f14f1a04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=982968306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.982968306
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2291185241
Short name T657
Test name
Test status
Simulation time 151714308 ps
CPU time 0.94 seconds
Started May 16 01:27:09 PM PDT 24
Finished May 16 01:27:31 PM PDT 24
Peak memory 205612 kb
Host smart-290f1858-134b-4b80-9ba8-015eeb89a78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291185241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2291185241
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.309193842
Short name T705
Test name
Test status
Simulation time 2340471510 ps
CPU time 7.91 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:44 PM PDT 24
Peak memory 219388 kb
Host smart-7824fecf-d7e3-4be7-87e6-702ff0aa884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309193842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.309193842
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1878678294
Short name T645
Test name
Test status
Simulation time 2753513382 ps
CPU time 5.45 seconds
Started May 16 01:27:05 PM PDT 24
Finished May 16 01:27:33 PM PDT 24
Peak memory 216424 kb
Host smart-cd03c2a8-0e67-484b-8aae-dfd49d85a3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878678294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1878678294
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.234363626
Short name T924
Test name
Test status
Simulation time 183042035 ps
CPU time 3.14 seconds
Started May 16 01:27:09 PM PDT 24
Finished May 16 01:27:34 PM PDT 24
Peak memory 216320 kb
Host smart-ce29726b-c284-41f5-bcea-7f4e3392a0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234363626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.234363626
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.221600967
Short name T75
Test name
Test status
Simulation time 35558491 ps
CPU time 0.85 seconds
Started May 16 01:27:09 PM PDT 24
Finished May 16 01:27:31 PM PDT 24
Peak memory 206888 kb
Host smart-44223dea-9a13-4141-add8-7836928b1434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221600967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.221600967
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.755715906
Short name T911
Test name
Test status
Simulation time 2782578884 ps
CPU time 6.76 seconds
Started May 16 01:27:04 PM PDT 24
Finished May 16 01:27:33 PM PDT 24
Peak memory 232864 kb
Host smart-f1b22cfc-307c-4c80-a1a2-cb158a9b6986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755715906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.755715906
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3014600139
Short name T353
Test name
Test status
Simulation time 56545834 ps
CPU time 0.73 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:40 PM PDT 24
Peak memory 205708 kb
Host smart-9154519f-ec0b-4bbe-bc82-de4f191faa2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014600139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3014600139
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2197591044
Short name T191
Test name
Test status
Simulation time 1508540323 ps
CPU time 8.1 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:47 PM PDT 24
Peak memory 234424 kb
Host smart-9488f556-a119-4142-9e71-1b844418fe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197591044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2197591044
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2278656574
Short name T760
Test name
Test status
Simulation time 30798817 ps
CPU time 0.79 seconds
Started May 16 01:27:11 PM PDT 24
Finished May 16 01:27:33 PM PDT 24
Peak memory 206680 kb
Host smart-18b01fcc-2eb7-4327-b00f-5e34cbff8668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278656574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2278656574
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4272712652
Short name T468
Test name
Test status
Simulation time 7908420282 ps
CPU time 76.74 seconds
Started May 16 01:27:06 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 249276 kb
Host smart-fe90438a-bcaf-4d5f-9ebc-0151399cc92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272712652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4272712652
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1502178525
Short name T445
Test name
Test status
Simulation time 92328908964 ps
CPU time 394.89 seconds
Started May 16 01:27:06 PM PDT 24
Finished May 16 01:34:03 PM PDT 24
Peak memory 265784 kb
Host smart-88571f21-5f18-4500-b9f9-af94a1f1c1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502178525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1502178525
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1869261212
Short name T139
Test name
Test status
Simulation time 581580719 ps
CPU time 11.67 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:47 PM PDT 24
Peak memory 237612 kb
Host smart-2941e52c-62c1-4e16-b118-5847f53b4ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869261212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1869261212
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.483125128
Short name T528
Test name
Test status
Simulation time 1394605985 ps
CPU time 12.94 seconds
Started May 16 01:27:04 PM PDT 24
Finished May 16 01:27:39 PM PDT 24
Peak memory 219516 kb
Host smart-e70b325d-3557-4e99-988e-c529a4dc883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483125128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.483125128
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2189482675
Short name T184
Test name
Test status
Simulation time 4095499318 ps
CPU time 23.4 seconds
Started May 16 01:27:12 PM PDT 24
Finished May 16 01:27:58 PM PDT 24
Peak memory 241012 kb
Host smart-d1ed93ac-afa5-427b-a2b4-4bbc66483143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189482675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2189482675
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1188592354
Short name T672
Test name
Test status
Simulation time 52007019 ps
CPU time 1.07 seconds
Started May 16 01:27:12 PM PDT 24
Finished May 16 01:27:35 PM PDT 24
Peak memory 216700 kb
Host smart-a3351d90-9493-4b45-86a8-6a1eb18403a0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188592354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1188592354
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2356221093
Short name T929
Test name
Test status
Simulation time 32879714 ps
CPU time 2.07 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:37 PM PDT 24
Peak memory 216096 kb
Host smart-e7409f31-0f11-4457-b2b7-fa252b0d98fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356221093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2356221093
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.702781969
Short name T596
Test name
Test status
Simulation time 7736616627 ps
CPU time 13.36 seconds
Started May 16 01:27:11 PM PDT 24
Finished May 16 01:27:46 PM PDT 24
Peak memory 233672 kb
Host smart-4b020b3b-96aa-42bb-9c52-e33d3a237873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702781969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.702781969
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3169444932
Short name T538
Test name
Test status
Simulation time 563777064 ps
CPU time 7.43 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:46 PM PDT 24
Peak memory 219928 kb
Host smart-1a37971d-973c-4bf7-a0e3-26c39c92900a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3169444932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3169444932
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4243486661
Short name T169
Test name
Test status
Simulation time 27181391327 ps
CPU time 124.31 seconds
Started May 16 01:27:15 PM PDT 24
Finished May 16 01:29:42 PM PDT 24
Peak memory 250548 kb
Host smart-f78d61e5-28c1-4128-a1ca-3edb719d14d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243486661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4243486661
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2748419551
Short name T553
Test name
Test status
Simulation time 22734092235 ps
CPU time 23.22 seconds
Started May 16 01:27:10 PM PDT 24
Finished May 16 01:27:54 PM PDT 24
Peak memory 220816 kb
Host smart-9f4f69e9-63d8-4dda-a48c-83754ee5fdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748419551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2748419551
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3891157557
Short name T326
Test name
Test status
Simulation time 13928053810 ps
CPU time 9.36 seconds
Started May 16 01:27:15 PM PDT 24
Finished May 16 01:27:48 PM PDT 24
Peak memory 216496 kb
Host smart-0b9c0a34-1b31-4960-8036-8cb66e58d539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891157557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3891157557
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3355631017
Short name T500
Test name
Test status
Simulation time 126389935 ps
CPU time 1.67 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:37 PM PDT 24
Peak memory 216284 kb
Host smart-341c11ce-ab0c-4c36-9722-275699673639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355631017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3355631017
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3355500928
Short name T731
Test name
Test status
Simulation time 33004507 ps
CPU time 0.84 seconds
Started May 16 01:27:14 PM PDT 24
Finished May 16 01:27:37 PM PDT 24
Peak memory 205796 kb
Host smart-e04b3d72-9cd6-4c80-9b6b-15710d5d631d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355500928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3355500928
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1533331274
Short name T729
Test name
Test status
Simulation time 1741915012 ps
CPU time 3.58 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:42 PM PDT 24
Peak memory 233772 kb
Host smart-4e1f2f22-7606-4a94-b5d3-e0c3a9a037fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533331274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1533331274
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1184424855
Short name T766
Test name
Test status
Simulation time 35131910 ps
CPU time 0.7 seconds
Started May 16 01:27:15 PM PDT 24
Finished May 16 01:27:38 PM PDT 24
Peak memory 205396 kb
Host smart-33aa0da3-a496-4cc8-bf9b-59377e256c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184424855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1184424855
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1642177495
Short name T740
Test name
Test status
Simulation time 984134550 ps
CPU time 8.82 seconds
Started May 16 01:27:15 PM PDT 24
Finished May 16 01:27:47 PM PDT 24
Peak memory 234236 kb
Host smart-746ea417-b93c-4553-b035-68352c023fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642177495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1642177495
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4186797143
Short name T449
Test name
Test status
Simulation time 15306866 ps
CPU time 0.76 seconds
Started May 16 01:27:15 PM PDT 24
Finished May 16 01:27:38 PM PDT 24
Peak memory 206472 kb
Host smart-c6aae055-5180-4990-ab06-34896b934a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186797143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4186797143
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3068865018
Short name T641
Test name
Test status
Simulation time 13040782756 ps
CPU time 60.64 seconds
Started May 16 01:27:12 PM PDT 24
Finished May 16 01:28:35 PM PDT 24
Peak memory 241052 kb
Host smart-2afe82a9-b23d-42b8-93c5-4145d842e0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068865018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3068865018
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3788700833
Short name T290
Test name
Test status
Simulation time 3235732427 ps
CPU time 10.52 seconds
Started May 16 01:27:17 PM PDT 24
Finished May 16 01:27:49 PM PDT 24
Peak memory 224512 kb
Host smart-34199764-36ad-4688-ac85-deae6db6dc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788700833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3788700833
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.87044468
Short name T371
Test name
Test status
Simulation time 263489531 ps
CPU time 4.99 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:44 PM PDT 24
Peak memory 235128 kb
Host smart-cc7779d2-8a78-40e2-a74d-73a22a7c743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87044468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.87044468
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4081265346
Short name T333
Test name
Test status
Simulation time 1010183669 ps
CPU time 5.04 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:43 PM PDT 24
Peak memory 221876 kb
Host smart-9c39c8fe-2abc-4cdc-bdda-8511988292f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081265346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4081265346
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4235361514
Short name T407
Test name
Test status
Simulation time 35380142 ps
CPU time 1.05 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:37 PM PDT 24
Peak memory 216744 kb
Host smart-ba0dd3b5-0d0d-4934-ad1a-b42a6d883122
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235361514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4235361514
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2997516774
Short name T524
Test name
Test status
Simulation time 1515613589 ps
CPU time 4.84 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:41 PM PDT 24
Peak memory 224552 kb
Host smart-22714feb-49de-4a42-93a2-72c5850a8a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997516774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2997516774
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1613325640
Short name T206
Test name
Test status
Simulation time 3712769139 ps
CPU time 11.76 seconds
Started May 16 01:27:19 PM PDT 24
Finished May 16 01:27:53 PM PDT 24
Peak memory 233816 kb
Host smart-8a88255b-5abd-4d89-af3b-bf5593ceb9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613325640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1613325640
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.962270478
Short name T546
Test name
Test status
Simulation time 5398829410 ps
CPU time 5.5 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:41 PM PDT 24
Peak memory 218992 kb
Host smart-d8e84e9f-4ecc-4744-9e9f-c8187971659d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=962270478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.962270478
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1953475700
Short name T863
Test name
Test status
Simulation time 791199815 ps
CPU time 4.43 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:43 PM PDT 24
Peak memory 216436 kb
Host smart-c66c6e00-0e11-46c5-b4f3-96bdffa3b7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953475700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1953475700
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2732570043
Short name T343
Test name
Test status
Simulation time 14033467 ps
CPU time 0.7 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:40 PM PDT 24
Peak memory 205536 kb
Host smart-6ebaf96a-5fdc-49fb-bda4-f51e1632a630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732570043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2732570043
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3925627454
Short name T365
Test name
Test status
Simulation time 159042274 ps
CPU time 3.18 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:39 PM PDT 24
Peak memory 216444 kb
Host smart-a72be6fd-088a-4288-ac18-ca420785c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925627454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3925627454
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4281041871
Short name T629
Test name
Test status
Simulation time 48470390 ps
CPU time 0.7 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:36 PM PDT 24
Peak memory 205836 kb
Host smart-2026aa0f-d944-486d-8e1d-0e061ec45a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281041871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4281041871
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3403419813
Short name T745
Test name
Test status
Simulation time 3386741757 ps
CPU time 9.64 seconds
Started May 16 01:27:19 PM PDT 24
Finished May 16 01:27:51 PM PDT 24
Peak memory 234440 kb
Host smart-5a093450-f690-48f9-909f-1b1d6c5acb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403419813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3403419813
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1150349410
Short name T536
Test name
Test status
Simulation time 13645331 ps
CPU time 0.74 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:40 PM PDT 24
Peak memory 205360 kb
Host smart-ad680147-075e-407d-9bc6-a9aeb75de22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150349410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1150349410
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1009783517
Short name T904
Test name
Test status
Simulation time 65182801 ps
CPU time 2.26 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:41 PM PDT 24
Peak memory 234436 kb
Host smart-dc7420e9-7439-4ce6-862d-9d68ddcbc7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009783517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1009783517
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2797300806
Short name T791
Test name
Test status
Simulation time 16763662 ps
CPU time 0.8 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:36 PM PDT 24
Peak memory 206468 kb
Host smart-171d5e36-e4f0-428e-a1f0-1288ab406898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797300806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2797300806
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2174290151
Short name T876
Test name
Test status
Simulation time 148476442 ps
CPU time 0.79 seconds
Started May 16 01:27:15 PM PDT 24
Finished May 16 01:27:38 PM PDT 24
Peak memory 215948 kb
Host smart-19e5f637-2cea-48e1-b8a7-19f4f331b03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174290151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2174290151
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4208799323
Short name T507
Test name
Test status
Simulation time 18219687 ps
CPU time 0.79 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:39 PM PDT 24
Peak memory 216816 kb
Host smart-69b1c364-c123-4387-b41b-15e1fea04550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208799323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4208799323
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.326006175
Short name T480
Test name
Test status
Simulation time 3831167345 ps
CPU time 14.63 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:50 PM PDT 24
Peak memory 232984 kb
Host smart-580b7ed6-615f-4bfe-8275-ad86e93b5934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326006175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.326006175
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2665407832
Short name T898
Test name
Test status
Simulation time 360680621 ps
CPU time 3.04 seconds
Started May 16 01:27:14 PM PDT 24
Finished May 16 01:27:40 PM PDT 24
Peak memory 224552 kb
Host smart-9f8c3000-0a4d-488d-a837-e19e22697afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665407832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2665407832
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2418180189
Short name T674
Test name
Test status
Simulation time 18348735978 ps
CPU time 12.2 seconds
Started May 16 01:27:14 PM PDT 24
Finished May 16 01:27:49 PM PDT 24
Peak memory 233944 kb
Host smart-4089e44d-8fb0-499f-a43e-2e84d8da01fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418180189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2418180189
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2308836999
Short name T618
Test name
Test status
Simulation time 13085844041 ps
CPU time 36.4 seconds
Started May 16 01:27:15 PM PDT 24
Finished May 16 01:28:14 PM PDT 24
Peak memory 233948 kb
Host smart-7c47a959-1411-44d8-818f-b65d3fe426bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308836999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2308836999
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1666942694
Short name T540
Test name
Test status
Simulation time 29768815 ps
CPU time 1.05 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:40 PM PDT 24
Peak memory 217912 kb
Host smart-f28d5ff1-067b-4d10-ae9b-972c32cba9e1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666942694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1666942694
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.239484593
Short name T714
Test name
Test status
Simulation time 29819506955 ps
CPU time 21.27 seconds
Started May 16 01:27:15 PM PDT 24
Finished May 16 01:27:59 PM PDT 24
Peak memory 238444 kb
Host smart-35f315d7-191c-4f57-a2fe-a38bec25294d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239484593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.239484593
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1823637824
Short name T308
Test name
Test status
Simulation time 218933594 ps
CPU time 2.18 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:41 PM PDT 24
Peak memory 221480 kb
Host smart-8092c182-469d-4bc4-9d0a-4c6d6c6ff3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823637824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1823637824
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3094474427
Short name T685
Test name
Test status
Simulation time 187545245 ps
CPU time 3.98 seconds
Started May 16 01:27:14 PM PDT 24
Finished May 16 01:27:41 PM PDT 24
Peak memory 221772 kb
Host smart-3af14a30-2a17-4dd4-9a25-51e3e0c9e466
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3094474427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3094474427
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4095447111
Short name T918
Test name
Test status
Simulation time 32329913245 ps
CPU time 280.75 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:32:19 PM PDT 24
Peak memory 254860 kb
Host smart-9ebe84e9-13fd-41e8-b235-39447721f340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095447111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4095447111
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3651138822
Short name T835
Test name
Test status
Simulation time 4153341877 ps
CPU time 6.57 seconds
Started May 16 01:27:14 PM PDT 24
Finished May 16 01:27:43 PM PDT 24
Peak memory 216544 kb
Host smart-d8e4b880-aca4-43aa-a17c-70be4cf3cebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651138822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3651138822
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3141991806
Short name T772
Test name
Test status
Simulation time 3774645078 ps
CPU time 5.17 seconds
Started May 16 01:27:14 PM PDT 24
Finished May 16 01:27:42 PM PDT 24
Peak memory 216492 kb
Host smart-0994d9ad-e20e-4226-8816-5a1e059a84c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141991806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3141991806
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.125337177
Short name T564
Test name
Test status
Simulation time 279423395 ps
CPU time 5.13 seconds
Started May 16 01:27:14 PM PDT 24
Finished May 16 01:27:42 PM PDT 24
Peak memory 216520 kb
Host smart-a88bcbe8-6036-47af-b3fc-90a80b0640e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125337177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.125337177
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.34291061
Short name T1
Test name
Test status
Simulation time 118612343 ps
CPU time 0.86 seconds
Started May 16 01:27:13 PM PDT 24
Finished May 16 01:27:37 PM PDT 24
Peak memory 205916 kb
Host smart-f245cb62-3394-4bcf-b27b-67b7e7553abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34291061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.34291061
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1366726124
Short name T417
Test name
Test status
Simulation time 327669546 ps
CPU time 2.52 seconds
Started May 16 01:27:14 PM PDT 24
Finished May 16 01:27:39 PM PDT 24
Peak memory 232660 kb
Host smart-07f1f42b-d152-4e07-9ed5-27965e262fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366726124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1366726124
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3237677230
Short name T410
Test name
Test status
Simulation time 83620342 ps
CPU time 0.72 seconds
Started May 16 01:27:24 PM PDT 24
Finished May 16 01:27:46 PM PDT 24
Peak memory 205308 kb
Host smart-69d2948f-4f2a-4fcf-bd81-7576f7292f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237677230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3237677230
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.627623182
Short name T531
Test name
Test status
Simulation time 112353268 ps
CPU time 2.15 seconds
Started May 16 01:27:24 PM PDT 24
Finished May 16 01:27:48 PM PDT 24
Peak memory 216108 kb
Host smart-f29291a7-f2bb-46a2-a720-4c71a2f4fcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627623182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.627623182
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3087160584
Short name T73
Test name
Test status
Simulation time 15599129 ps
CPU time 0.76 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:40 PM PDT 24
Peak memory 206432 kb
Host smart-76dbbff8-6382-4cfa-8daf-276585eb982b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087160584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3087160584
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2618839781
Short name T434
Test name
Test status
Simulation time 6365399710 ps
CPU time 46.6 seconds
Started May 16 01:27:38 PM PDT 24
Finished May 16 01:28:43 PM PDT 24
Peak memory 249384 kb
Host smart-3af6e5ec-1280-4b62-8796-9e56880b3471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618839781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2618839781
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2452290927
Short name T790
Test name
Test status
Simulation time 17616223226 ps
CPU time 33.34 seconds
Started May 16 01:27:22 PM PDT 24
Finished May 16 01:28:17 PM PDT 24
Peak memory 224716 kb
Host smart-72c74b7c-9d85-4205-874b-d8f5e2939ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452290927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2452290927
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2887413818
Short name T53
Test name
Test status
Simulation time 5109953423 ps
CPU time 61.3 seconds
Started May 16 01:27:32 PM PDT 24
Finished May 16 01:28:52 PM PDT 24
Peak memory 240212 kb
Host smart-05455b06-0a02-48b2-ae6c-373b12f6e438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887413818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2887413818
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3434892272
Short name T264
Test name
Test status
Simulation time 1236255808 ps
CPU time 13.3 seconds
Started May 16 01:27:25 PM PDT 24
Finished May 16 01:27:59 PM PDT 24
Peak memory 219660 kb
Host smart-3102df4a-c909-4f5a-ad39-c452a6636aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434892272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3434892272
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1728722925
Short name T269
Test name
Test status
Simulation time 2154120641 ps
CPU time 26.44 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:28:22 PM PDT 24
Peak memory 218628 kb
Host smart-a4c515bd-6909-4d4f-8969-b8cd44e5c551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728722925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1728722925
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.921047474
Short name T414
Test name
Test status
Simulation time 309772392 ps
CPU time 1.09 seconds
Started May 16 01:27:18 PM PDT 24
Finished May 16 01:27:41 PM PDT 24
Peak memory 216732 kb
Host smart-e413d771-d168-4dcf-89d8-de82cf1c7d62
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921047474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.921047474
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1209645272
Short name T510
Test name
Test status
Simulation time 1053659973 ps
CPU time 4.7 seconds
Started May 16 01:27:31 PM PDT 24
Finished May 16 01:27:56 PM PDT 24
Peak memory 224556 kb
Host smart-0df0696a-26fa-4545-b71f-97f42b508947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209645272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1209645272
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3211047044
Short name T435
Test name
Test status
Simulation time 28638550435 ps
CPU time 12.84 seconds
Started May 16 01:27:20 PM PDT 24
Finished May 16 01:27:54 PM PDT 24
Peak memory 233932 kb
Host smart-88e8198c-3132-46c6-817e-133bb7b0f940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211047044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3211047044
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1109414361
Short name T173
Test name
Test status
Simulation time 2541616096 ps
CPU time 6.43 seconds
Started May 16 01:27:30 PM PDT 24
Finished May 16 01:27:56 PM PDT 24
Peak memory 222988 kb
Host smart-f9f691f8-632b-4366-ae18-8e3de8b1f9b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1109414361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1109414361
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.845282482
Short name T850
Test name
Test status
Simulation time 49430389063 ps
CPU time 121.59 seconds
Started May 16 01:27:24 PM PDT 24
Finished May 16 01:29:47 PM PDT 24
Peak memory 232964 kb
Host smart-15fdfb3f-7606-4a81-8d61-b3918057ce86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845282482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.845282482
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4031941076
Short name T571
Test name
Test status
Simulation time 689237655 ps
CPU time 3.31 seconds
Started May 16 01:27:17 PM PDT 24
Finished May 16 01:27:42 PM PDT 24
Peak memory 216460 kb
Host smart-6352873b-af64-4f35-a721-699daa6e5cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031941076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4031941076
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2170007996
Short name T19
Test name
Test status
Simulation time 12165869626 ps
CPU time 8.51 seconds
Started May 16 01:27:16 PM PDT 24
Finished May 16 01:27:47 PM PDT 24
Peak memory 216516 kb
Host smart-6351c127-2907-4846-aff9-64466b5a7f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170007996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2170007996
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.472557555
Short name T518
Test name
Test status
Simulation time 42952774 ps
CPU time 0.97 seconds
Started May 16 01:27:15 PM PDT 24
Finished May 16 01:27:38 PM PDT 24
Peak memory 207944 kb
Host smart-a3ea3b1e-7085-404f-bd0a-71af90dd7204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472557555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.472557555
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3467759808
Short name T925
Test name
Test status
Simulation time 95373981 ps
CPU time 0.97 seconds
Started May 16 01:27:20 PM PDT 24
Finished May 16 01:27:42 PM PDT 24
Peak memory 205820 kb
Host smart-c063b300-fc4f-4674-b3b9-fd6d81e9c597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467759808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3467759808
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.276271876
Short name T457
Test name
Test status
Simulation time 695274703 ps
CPU time 4.21 seconds
Started May 16 01:27:23 PM PDT 24
Finished May 16 01:27:49 PM PDT 24
Peak memory 219044 kb
Host smart-dacc7f31-4961-4285-89dc-4545c7a12603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276271876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.276271876
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.105065350
Short name T577
Test name
Test status
Simulation time 19464613 ps
CPU time 0.74 seconds
Started May 16 01:26:27 PM PDT 24
Finished May 16 01:26:44 PM PDT 24
Peak memory 205352 kb
Host smart-48427260-d88f-425e-ae28-4ed7ef7c618b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105065350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.105065350
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.556768182
Short name T490
Test name
Test status
Simulation time 692033632 ps
CPU time 4.59 seconds
Started May 16 01:26:37 PM PDT 24
Finished May 16 01:26:56 PM PDT 24
Peak memory 224564 kb
Host smart-ca5d0010-b5e5-4876-afce-dd5fdd77dec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556768182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.556768182
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3463538164
Short name T807
Test name
Test status
Simulation time 22859881 ps
CPU time 0.8 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:50 PM PDT 24
Peak memory 205456 kb
Host smart-7dce3d12-91e4-494a-8211-41afd26d785d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463538164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3463538164
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2936850988
Short name T943
Test name
Test status
Simulation time 10799879 ps
CPU time 0.73 seconds
Started May 16 01:26:37 PM PDT 24
Finished May 16 01:26:53 PM PDT 24
Peak memory 215892 kb
Host smart-77f3f7ee-4add-476d-b622-08cd709c4683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936850988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2936850988
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3119759813
Short name T46
Test name
Test status
Simulation time 37078822508 ps
CPU time 346.85 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:32:37 PM PDT 24
Peak memory 254640 kb
Host smart-98fc2df7-34a2-4672-9aa0-df6a8ea53d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119759813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3119759813
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1255919889
Short name T301
Test name
Test status
Simulation time 7934332059 ps
CPU time 36.54 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:27:26 PM PDT 24
Peak memory 224768 kb
Host smart-76430058-692e-41ff-8ead-af13063135af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255919889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1255919889
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3600813762
Short name T547
Test name
Test status
Simulation time 224910762 ps
CPU time 8.85 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:26:59 PM PDT 24
Peak memory 232752 kb
Host smart-afabcc3d-0186-4932-9868-f2e74c271340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600813762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3600813762
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.237940154
Short name T123
Test name
Test status
Simulation time 120809244 ps
CPU time 3.54 seconds
Started May 16 01:26:33 PM PDT 24
Finished May 16 01:26:51 PM PDT 24
Peak memory 233828 kb
Host smart-23718112-245b-4bbb-be27-2424a816ca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237940154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.237940154
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.4094495855
Short name T475
Test name
Test status
Simulation time 21420072526 ps
CPU time 58.41 seconds
Started May 16 01:26:30 PM PDT 24
Finished May 16 01:27:44 PM PDT 24
Peak memory 247520 kb
Host smart-df3159a3-0cea-4477-8330-30cad1b5ec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094495855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4094495855
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2126100849
Short name T26
Test name
Test status
Simulation time 146341947 ps
CPU time 1.04 seconds
Started May 16 01:26:26 PM PDT 24
Finished May 16 01:26:44 PM PDT 24
Peak memory 217984 kb
Host smart-955f25dc-835a-4100-a4d7-fe7cbfbc152f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126100849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2126100849
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2305332534
Short name T260
Test name
Test status
Simulation time 21482521057 ps
CPU time 12.22 seconds
Started May 16 01:26:30 PM PDT 24
Finished May 16 01:26:58 PM PDT 24
Peak memory 228176 kb
Host smart-d7491149-4c26-470e-ad6b-c8bf29e69f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305332534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2305332534
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.656687059
Short name T818
Test name
Test status
Simulation time 24380435648 ps
CPU time 8.8 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:59 PM PDT 24
Peak memory 233684 kb
Host smart-aa5b0adc-a625-48a0-9063-21ab929cb753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656687059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.656687059
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2809739746
Short name T699
Test name
Test status
Simulation time 193382951 ps
CPU time 4.48 seconds
Started May 16 01:26:28 PM PDT 24
Finished May 16 01:26:49 PM PDT 24
Peak memory 222240 kb
Host smart-d6b50a22-11b1-40cf-af00-eec27b8bfbc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2809739746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2809739746
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3297525497
Short name T67
Test name
Test status
Simulation time 144877262 ps
CPU time 1.16 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:26:52 PM PDT 24
Peak memory 235076 kb
Host smart-8c00f49e-4e43-4f0c-a31e-c8bf29d23e80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297525497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3297525497
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1247073337
Short name T398
Test name
Test status
Simulation time 318303349 ps
CPU time 1.23 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:51 PM PDT 24
Peak memory 206760 kb
Host smart-bfcb0f3d-33ec-4184-a7fc-78866e8c7e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247073337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1247073337
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.222230746
Short name T300
Test name
Test status
Simulation time 7861092244 ps
CPU time 24.12 seconds
Started May 16 01:26:36 PM PDT 24
Finished May 16 01:27:15 PM PDT 24
Peak memory 216548 kb
Host smart-6d613194-3103-4d2e-9e6b-d115c9a80dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222230746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.222230746
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3252840888
Short name T649
Test name
Test status
Simulation time 42225644993 ps
CPU time 14.56 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:27:04 PM PDT 24
Peak memory 216532 kb
Host smart-fdb4cc5f-a42a-4808-8fde-f68e1c883733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252840888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3252840888
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1103634410
Short name T388
Test name
Test status
Simulation time 82891292 ps
CPU time 0.95 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:04 PM PDT 24
Peak memory 206860 kb
Host smart-8a839640-3e64-49f3-bf9b-a7b391a81328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103634410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1103634410
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3813801049
Short name T327
Test name
Test status
Simulation time 200636142 ps
CPU time 1.02 seconds
Started May 16 01:26:28 PM PDT 24
Finished May 16 01:26:45 PM PDT 24
Peak memory 206200 kb
Host smart-9e625e14-164b-4cdc-a397-84714d785981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813801049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3813801049
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2424629403
Short name T498
Test name
Test status
Simulation time 2489338151 ps
CPU time 11.14 seconds
Started May 16 01:26:29 PM PDT 24
Finished May 16 01:26:57 PM PDT 24
Peak memory 232836 kb
Host smart-07480a58-9fa8-45b1-b3a5-4c5c6feb4e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424629403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2424629403
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1277425145
Short name T961
Test name
Test status
Simulation time 24816564 ps
CPU time 0.72 seconds
Started May 16 01:27:25 PM PDT 24
Finished May 16 01:27:46 PM PDT 24
Peak memory 205312 kb
Host smart-abfa0549-e5a1-4906-b9e8-c9a28dd1a515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277425145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1277425145
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1365312904
Short name T140
Test name
Test status
Simulation time 73244524 ps
CPU time 2.19 seconds
Started May 16 01:27:31 PM PDT 24
Finished May 16 01:27:53 PM PDT 24
Peak memory 216136 kb
Host smart-c3ef5cfc-8727-4e79-a426-970ed3972abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365312904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1365312904
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.339915354
Short name T443
Test name
Test status
Simulation time 49591612 ps
CPU time 0.76 seconds
Started May 16 01:27:27 PM PDT 24
Finished May 16 01:27:48 PM PDT 24
Peak memory 206796 kb
Host smart-e7212019-bf75-4914-9f6c-c0decb941b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339915354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.339915354
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2164894055
Short name T219
Test name
Test status
Simulation time 30250399852 ps
CPU time 94.85 seconds
Started May 16 01:27:24 PM PDT 24
Finished May 16 01:29:19 PM PDT 24
Peak memory 253912 kb
Host smart-47da927d-e3f7-45d1-81a3-9d92de44f4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164894055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2164894055
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2324303398
Short name T268
Test name
Test status
Simulation time 8506161182 ps
CPU time 114.48 seconds
Started May 16 01:27:26 PM PDT 24
Finished May 16 01:29:41 PM PDT 24
Peak memory 249452 kb
Host smart-f4c7d93e-2af1-48f0-8401-15527365cee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324303398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2324303398
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2951089329
Short name T919
Test name
Test status
Simulation time 1095925972 ps
CPU time 23.83 seconds
Started May 16 01:27:26 PM PDT 24
Finished May 16 01:28:10 PM PDT 24
Peak memory 255260 kb
Host smart-4e5ecf8b-272d-4800-ad58-d44f2ca8029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951089329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2951089329
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.250461697
Short name T679
Test name
Test status
Simulation time 2693448841 ps
CPU time 33.21 seconds
Started May 16 01:27:30 PM PDT 24
Finished May 16 01:28:23 PM PDT 24
Peak memory 224652 kb
Host smart-b35830e9-9b70-4020-b570-69f4e635fb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250461697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.250461697
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3007069040
Short name T773
Test name
Test status
Simulation time 40455881 ps
CPU time 2.55 seconds
Started May 16 01:27:31 PM PDT 24
Finished May 16 01:27:53 PM PDT 24
Peak memory 232780 kb
Host smart-5176b34c-3386-46e1-9911-4a47a5c95a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007069040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3007069040
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2717179234
Short name T739
Test name
Test status
Simulation time 1419795341 ps
CPU time 7.88 seconds
Started May 16 01:27:31 PM PDT 24
Finished May 16 01:27:59 PM PDT 24
Peak memory 238956 kb
Host smart-d89730d3-d34c-4a28-a15d-cb57e8e02707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717179234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2717179234
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.758946308
Short name T580
Test name
Test status
Simulation time 255950621 ps
CPU time 2.73 seconds
Started May 16 01:27:36 PM PDT 24
Finished May 16 01:27:58 PM PDT 24
Peak memory 216760 kb
Host smart-29b69af8-1111-4ffc-8307-390fa79045e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758946308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.758946308
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2923669460
Short name T181
Test name
Test status
Simulation time 1129394031 ps
CPU time 6.03 seconds
Started May 16 01:27:22 PM PDT 24
Finished May 16 01:27:50 PM PDT 24
Peak memory 224524 kb
Host smart-546d435a-6d62-4125-8b5e-33d023dc29b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923669460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2923669460
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3737813486
Short name T584
Test name
Test status
Simulation time 2079190686 ps
CPU time 8.52 seconds
Started May 16 01:27:25 PM PDT 24
Finished May 16 01:27:55 PM PDT 24
Peak memory 223100 kb
Host smart-e89350df-b6d6-448f-8985-fe9044d2d080
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3737813486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3737813486
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1724224074
Short name T783
Test name
Test status
Simulation time 2536845912 ps
CPU time 25.98 seconds
Started May 16 01:27:25 PM PDT 24
Finished May 16 01:28:12 PM PDT 24
Peak memory 224732 kb
Host smart-89cad857-30a3-45ff-b58b-98f0e9e5308c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724224074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1724224074
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.832175499
Short name T599
Test name
Test status
Simulation time 1452050584 ps
CPU time 14.47 seconds
Started May 16 01:27:25 PM PDT 24
Finished May 16 01:28:00 PM PDT 24
Peak memory 216408 kb
Host smart-ab50afcc-adf1-40be-869c-06ab059ce864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832175499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.832175499
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2673698289
Short name T623
Test name
Test status
Simulation time 5572214246 ps
CPU time 9.14 seconds
Started May 16 01:27:24 PM PDT 24
Finished May 16 01:27:54 PM PDT 24
Peak memory 216512 kb
Host smart-ba7139d6-5f29-4f02-a20a-e67702edcf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673698289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2673698289
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1040842469
Short name T421
Test name
Test status
Simulation time 37785912 ps
CPU time 1.56 seconds
Started May 16 01:27:24 PM PDT 24
Finished May 16 01:27:47 PM PDT 24
Peak memory 207864 kb
Host smart-0c364429-432e-4690-964c-bf5f76925295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040842469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1040842469
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.856734011
Short name T759
Test name
Test status
Simulation time 181062010 ps
CPU time 0.86 seconds
Started May 16 01:27:24 PM PDT 24
Finished May 16 01:27:46 PM PDT 24
Peak memory 206836 kb
Host smart-05a593a6-618b-4c74-a7db-a8119bf8bcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856734011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.856734011
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2473168484
Short name T640
Test name
Test status
Simulation time 464121542 ps
CPU time 7.59 seconds
Started May 16 01:27:24 PM PDT 24
Finished May 16 01:27:53 PM PDT 24
Peak memory 228196 kb
Host smart-dd02b9e5-109e-4bf3-9da4-d54a00ddb244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473168484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2473168484
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1236537644
Short name T681
Test name
Test status
Simulation time 24016963 ps
CPU time 0.71 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:27:56 PM PDT 24
Peak memory 205372 kb
Host smart-3f3728b9-9b29-4126-8091-da5796a3b1b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236537644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1236537644
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4117347646
Short name T654
Test name
Test status
Simulation time 74391633 ps
CPU time 3.02 seconds
Started May 16 01:27:30 PM PDT 24
Finished May 16 01:27:52 PM PDT 24
Peak memory 233176 kb
Host smart-3e62d77c-6487-4189-8bb6-1622c3926f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117347646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4117347646
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.382560257
Short name T447
Test name
Test status
Simulation time 39819276 ps
CPU time 0.75 seconds
Started May 16 01:27:23 PM PDT 24
Finished May 16 01:27:45 PM PDT 24
Peak memory 205436 kb
Host smart-b057b84e-1356-461c-92f6-b775af2b9f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382560257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.382560257
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1669250108
Short name T865
Test name
Test status
Simulation time 116205254074 ps
CPU time 202.27 seconds
Started May 16 01:27:36 PM PDT 24
Finished May 16 01:31:18 PM PDT 24
Peak memory 257440 kb
Host smart-4400c146-6dde-40f3-ba5c-cf9e5fd88d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669250108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1669250108
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3925044489
Short name T706
Test name
Test status
Simulation time 9734560323 ps
CPU time 41.1 seconds
Started May 16 01:27:28 PM PDT 24
Finished May 16 01:28:29 PM PDT 24
Peak memory 249408 kb
Host smart-7c30cd5e-be64-4ec3-929f-3bfddd94d8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925044489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3925044489
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2190491493
Short name T610
Test name
Test status
Simulation time 516763744 ps
CPU time 14.05 seconds
Started May 16 01:27:24 PM PDT 24
Finished May 16 01:27:59 PM PDT 24
Peak memory 240912 kb
Host smart-ed3349dd-89d7-44a6-9507-eed93e16a1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190491493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2190491493
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4186675464
Short name T266
Test name
Test status
Simulation time 436385876 ps
CPU time 6.49 seconds
Started May 16 01:27:28 PM PDT 24
Finished May 16 01:27:55 PM PDT 24
Peak memory 233800 kb
Host smart-6da33514-8b43-447d-9091-8f824e8034ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186675464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4186675464
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3751053111
Short name T900
Test name
Test status
Simulation time 277822302 ps
CPU time 2.28 seconds
Started May 16 01:27:26 PM PDT 24
Finished May 16 01:27:48 PM PDT 24
Peak memory 216140 kb
Host smart-a58d2cbd-6df6-405a-a8da-9bf9c517f57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751053111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3751053111
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2995526297
Short name T287
Test name
Test status
Simulation time 318289791 ps
CPU time 2.4 seconds
Started May 16 01:27:38 PM PDT 24
Finished May 16 01:27:58 PM PDT 24
Peak memory 218600 kb
Host smart-04f0a84b-2810-4ce7-aa0a-d11409933552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995526297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2995526297
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1126906964
Short name T56
Test name
Test status
Simulation time 255113994 ps
CPU time 2.54 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:27:58 PM PDT 24
Peak memory 233436 kb
Host smart-35c2a50f-6bcb-4767-bc93-5a8802c01542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126906964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1126906964
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.233393388
Short name T424
Test name
Test status
Simulation time 881161508 ps
CPU time 11.14 seconds
Started May 16 01:27:23 PM PDT 24
Finished May 16 01:27:56 PM PDT 24
Peak memory 223104 kb
Host smart-2c767252-7e86-4224-a6a0-ecb2b1acf19d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=233393388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.233393388
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2910107322
Short name T430
Test name
Test status
Simulation time 36173071 ps
CPU time 0.9 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:27:57 PM PDT 24
Peak memory 205544 kb
Host smart-eb306fdc-235d-43bb-aa95-e2bfd27c8d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910107322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2910107322
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3675014290
Short name T859
Test name
Test status
Simulation time 5061180102 ps
CPU time 18.43 seconds
Started May 16 01:27:24 PM PDT 24
Finished May 16 01:28:04 PM PDT 24
Peak memory 216496 kb
Host smart-f7e49fe4-afe8-4de6-bed4-0f42c0871451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675014290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3675014290
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4273983719
Short name T533
Test name
Test status
Simulation time 7694259507 ps
CPU time 6.44 seconds
Started May 16 01:27:25 PM PDT 24
Finished May 16 01:27:53 PM PDT 24
Peak memory 216480 kb
Host smart-a82f9da3-6057-457d-bd5a-f0589599fd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273983719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4273983719
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.466272411
Short name T419
Test name
Test status
Simulation time 67565930 ps
CPU time 1.37 seconds
Started May 16 01:27:26 PM PDT 24
Finished May 16 01:27:48 PM PDT 24
Peak memory 216276 kb
Host smart-0be97fdd-6ad5-41dd-a9b7-3edd2dcdd055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466272411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.466272411
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1438842480
Short name T833
Test name
Test status
Simulation time 226095641 ps
CPU time 0.86 seconds
Started May 16 01:27:31 PM PDT 24
Finished May 16 01:27:52 PM PDT 24
Peak memory 205808 kb
Host smart-b1873edf-fa0b-4b35-aea0-5b4c9fe503c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438842480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1438842480
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.700752625
Short name T210
Test name
Test status
Simulation time 489689121 ps
CPU time 2.46 seconds
Started May 16 01:27:27 PM PDT 24
Finished May 16 01:27:49 PM PDT 24
Peak memory 235272 kb
Host smart-07eadebc-f509-499d-945d-8f19ebbc719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700752625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.700752625
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.4112062109
Short name T50
Test name
Test status
Simulation time 143069726 ps
CPU time 2.17 seconds
Started May 16 01:27:40 PM PDT 24
Finished May 16 01:28:01 PM PDT 24
Peak memory 218572 kb
Host smart-ea429157-824e-4582-8462-f671ce180b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112062109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4112062109
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3629954614
Short name T931
Test name
Test status
Simulation time 136230698 ps
CPU time 0.75 seconds
Started May 16 01:27:27 PM PDT 24
Finished May 16 01:27:49 PM PDT 24
Peak memory 206364 kb
Host smart-5e91cc24-8956-43b2-8d42-64d062c1d68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629954614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3629954614
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1462064735
Short name T77
Test name
Test status
Simulation time 72384463828 ps
CPU time 109.45 seconds
Started May 16 01:27:39 PM PDT 24
Finished May 16 01:29:47 PM PDT 24
Peak memory 255424 kb
Host smart-dfdf3116-f311-4fce-8af7-ceb4900a53f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462064735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1462064735
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3682451206
Short name T969
Test name
Test status
Simulation time 8440681820 ps
CPU time 67.92 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:29:04 PM PDT 24
Peak memory 252336 kb
Host smart-5da11f6c-73ed-4b44-aa04-3cfa288139f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682451206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3682451206
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3478286054
Short name T159
Test name
Test status
Simulation time 1329866833 ps
CPU time 17.54 seconds
Started May 16 01:27:39 PM PDT 24
Finished May 16 01:28:15 PM PDT 24
Peak memory 224400 kb
Host smart-9fbdbaa8-0b5c-4f67-852f-65bd1debb87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478286054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3478286054
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2239463578
Short name T778
Test name
Test status
Simulation time 3689940730 ps
CPU time 16.93 seconds
Started May 16 01:27:39 PM PDT 24
Finished May 16 01:28:15 PM PDT 24
Peak memory 219664 kb
Host smart-ed81a739-71ee-4d55-b7d6-9ee25dde185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239463578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2239463578
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.712997217
Short name T505
Test name
Test status
Simulation time 8111866361 ps
CPU time 73.58 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:29:09 PM PDT 24
Peak memory 237568 kb
Host smart-f701c50c-a957-482b-8dec-f0421c93d04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712997217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.712997217
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3561019248
Short name T218
Test name
Test status
Simulation time 1321337149 ps
CPU time 4.27 seconds
Started May 16 01:27:41 PM PDT 24
Finished May 16 01:28:03 PM PDT 24
Peak memory 233272 kb
Host smart-76d9a998-f496-4ff9-a081-fe8d5d806ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561019248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3561019248
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3685255864
Short name T11
Test name
Test status
Simulation time 10190024697 ps
CPU time 20.63 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:28:16 PM PDT 24
Peak memory 236724 kb
Host smart-9eb67e4e-62fa-454a-90b9-9e6d6cb9ccb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685255864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3685255864
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3201465246
Short name T502
Test name
Test status
Simulation time 252633884 ps
CPU time 3.83 seconds
Started May 16 01:27:34 PM PDT 24
Finished May 16 01:27:57 PM PDT 24
Peak memory 220312 kb
Host smart-9c3b48ef-8539-40b5-bedd-292b56ee2fb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3201465246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3201465246
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1797093907
Short name T48
Test name
Test status
Simulation time 83047326079 ps
CPU time 330.32 seconds
Started May 16 01:27:40 PM PDT 24
Finished May 16 01:33:29 PM PDT 24
Peak memory 286876 kb
Host smart-a094ae56-fc53-4018-bb29-20e1b4ff726e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797093907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1797093907
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.605804505
Short name T799
Test name
Test status
Simulation time 1455083837 ps
CPU time 7.44 seconds
Started May 16 01:27:36 PM PDT 24
Finished May 16 01:28:02 PM PDT 24
Peak memory 216356 kb
Host smart-9455f7aa-6344-4c92-ade5-0e53dbb2a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605804505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.605804505
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.131092295
Short name T756
Test name
Test status
Simulation time 1977524972 ps
CPU time 10 seconds
Started May 16 01:27:23 PM PDT 24
Finished May 16 01:27:54 PM PDT 24
Peak memory 216364 kb
Host smart-10f8c008-bb02-4629-96d8-af815e14ca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131092295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.131092295
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4191728102
Short name T491
Test name
Test status
Simulation time 300731452 ps
CPU time 8.13 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:28:04 PM PDT 24
Peak memory 217736 kb
Host smart-3c33016d-b782-48a7-8cf6-bed8b79d3bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191728102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4191728102
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3559525349
Short name T143
Test name
Test status
Simulation time 108399674 ps
CPU time 0.84 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:27:57 PM PDT 24
Peak memory 205816 kb
Host smart-42355386-be5a-42c4-9059-576cfdd8b294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559525349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3559525349
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2491090463
Short name T207
Test name
Test status
Simulation time 19119489561 ps
CPU time 15.79 seconds
Started May 16 01:27:40 PM PDT 24
Finished May 16 01:28:14 PM PDT 24
Peak memory 234300 kb
Host smart-5e5a11a9-a3ec-4528-a19b-cd48bae9470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491090463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2491090463
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.947092187
Short name T511
Test name
Test status
Simulation time 15122842 ps
CPU time 0.75 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:27:57 PM PDT 24
Peak memory 205356 kb
Host smart-6eec24a3-5ef9-4460-b63b-9da4c755a214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947092187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.947092187
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2903165064
Short name T798
Test name
Test status
Simulation time 139996570 ps
CPU time 3.85 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:28:00 PM PDT 24
Peak memory 233736 kb
Host smart-c116ce1e-1df2-4ef8-ad8e-e14949318d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903165064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2903165064
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.829456330
Short name T455
Test name
Test status
Simulation time 20212270 ps
CPU time 0.8 seconds
Started May 16 01:27:39 PM PDT 24
Finished May 16 01:27:58 PM PDT 24
Peak memory 206348 kb
Host smart-409a1b0b-0a37-4160-a102-3ce9e3f18248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829456330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.829456330
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.937419379
Short name T874
Test name
Test status
Simulation time 2452824123 ps
CPU time 41.68 seconds
Started May 16 01:27:35 PM PDT 24
Finished May 16 01:28:36 PM PDT 24
Peak memory 249252 kb
Host smart-f33ffd22-ac2a-4f5d-b30d-ba0744172176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937419379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.937419379
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4264578940
Short name T503
Test name
Test status
Simulation time 153480897010 ps
CPU time 364.71 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:34:00 PM PDT 24
Peak memory 249408 kb
Host smart-1ce4da45-f8ef-4c69-9cad-1d612c7885e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264578940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4264578940
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.887856690
Short name T390
Test name
Test status
Simulation time 4260932307 ps
CPU time 51.1 seconds
Started May 16 01:27:35 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 232880 kb
Host smart-4cc02782-8ce3-490e-a81d-6172970142ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887856690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.887856690
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3302750062
Short name T777
Test name
Test status
Simulation time 1358963583 ps
CPU time 8.41 seconds
Started May 16 01:27:36 PM PDT 24
Finished May 16 01:28:03 PM PDT 24
Peak memory 218560 kb
Host smart-6c84e687-33ea-4e77-9f99-d4b0f2944c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302750062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3302750062
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1027289285
Short name T634
Test name
Test status
Simulation time 951596106 ps
CPU time 9.88 seconds
Started May 16 01:27:41 PM PDT 24
Finished May 16 01:28:10 PM PDT 24
Peak memory 230748 kb
Host smart-c8b02b68-d474-4d58-bd96-487591ae8772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027289285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1027289285
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.35426680
Short name T794
Test name
Test status
Simulation time 7779752878 ps
CPU time 13.08 seconds
Started May 16 01:27:36 PM PDT 24
Finished May 16 01:28:08 PM PDT 24
Peak memory 224108 kb
Host smart-eb08b47a-7fcb-4e4b-81c0-a0bd2e88a0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35426680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.35426680
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4229472883
Short name T597
Test name
Test status
Simulation time 7124740831 ps
CPU time 21 seconds
Started May 16 01:27:37 PM PDT 24
Finished May 16 01:28:16 PM PDT 24
Peak memory 233832 kb
Host smart-65fb7af1-149a-4315-a3c3-97f897549a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229472883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4229472883
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1992402267
Short name T436
Test name
Test status
Simulation time 5633566823 ps
CPU time 15.05 seconds
Started May 16 01:27:36 PM PDT 24
Finished May 16 01:28:10 PM PDT 24
Peak memory 222672 kb
Host smart-5f8022a2-046e-4586-adc5-7bdfcc435001
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1992402267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1992402267
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3350602869
Short name T175
Test name
Test status
Simulation time 4617300493 ps
CPU time 35.51 seconds
Started May 16 01:27:40 PM PDT 24
Finished May 16 01:28:34 PM PDT 24
Peak memory 237948 kb
Host smart-0f645d36-0676-4fa6-9336-7910b75a96bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350602869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3350602869
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3701364759
Short name T569
Test name
Test status
Simulation time 4608826117 ps
CPU time 13.29 seconds
Started May 16 01:27:39 PM PDT 24
Finished May 16 01:28:11 PM PDT 24
Peak memory 216500 kb
Host smart-f0ea81d0-09b5-4af5-b16b-4dc6934c062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701364759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3701364759
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2521025891
Short name T364
Test name
Test status
Simulation time 5987102877 ps
CPU time 14.92 seconds
Started May 16 01:27:39 PM PDT 24
Finished May 16 01:28:12 PM PDT 24
Peak memory 216480 kb
Host smart-510f2154-8157-497b-9451-1bce012ee1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521025891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2521025891
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2346528054
Short name T828
Test name
Test status
Simulation time 69365228 ps
CPU time 0.81 seconds
Started May 16 01:27:36 PM PDT 24
Finished May 16 01:27:56 PM PDT 24
Peak memory 205860 kb
Host smart-e74d2082-5d0a-4d73-be94-ce083472a4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346528054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2346528054
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3870760067
Short name T716
Test name
Test status
Simulation time 59570953 ps
CPU time 0.86 seconds
Started May 16 01:27:36 PM PDT 24
Finished May 16 01:27:56 PM PDT 24
Peak memory 205824 kb
Host smart-5ef2ec0e-0601-4530-bb2c-31015faa046d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870760067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3870760067
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2982323371
Short name T607
Test name
Test status
Simulation time 2347215887 ps
CPU time 4.49 seconds
Started May 16 01:27:39 PM PDT 24
Finished May 16 01:28:02 PM PDT 24
Peak memory 224672 kb
Host smart-b3a8b854-05d5-42dc-8da9-858d6ec58d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982323371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2982323371
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4183271484
Short name T960
Test name
Test status
Simulation time 21941018 ps
CPU time 0.72 seconds
Started May 16 01:27:48 PM PDT 24
Finished May 16 01:28:06 PM PDT 24
Peak memory 205372 kb
Host smart-60ae9d88-8b78-4e2b-ab85-0c15d3b05915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183271484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4183271484
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3591151276
Short name T329
Test name
Test status
Simulation time 189992943 ps
CPU time 4.66 seconds
Started May 16 01:27:44 PM PDT 24
Finished May 16 01:28:07 PM PDT 24
Peak memory 219456 kb
Host smart-fbfb728d-22ee-4393-b66c-a74e715b312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591151276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3591151276
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3734129452
Short name T887
Test name
Test status
Simulation time 22164765 ps
CPU time 0.78 seconds
Started May 16 01:27:35 PM PDT 24
Finished May 16 01:27:55 PM PDT 24
Peak memory 205464 kb
Host smart-aaddd68a-10c4-4721-836a-984d3d4db03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734129452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3734129452
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1142493200
Short name T937
Test name
Test status
Simulation time 66760693 ps
CPU time 0.74 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:28:06 PM PDT 24
Peak memory 215980 kb
Host smart-6be04b41-90bc-4fc3-a5df-296f1f81ebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142493200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1142493200
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.263725874
Short name T541
Test name
Test status
Simulation time 21936457222 ps
CPU time 105.58 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:29:51 PM PDT 24
Peak memory 249400 kb
Host smart-47aed8a2-9937-4081-916e-ac2b06946a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263725874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.263725874
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4240107852
Short name T177
Test name
Test status
Simulation time 86431106689 ps
CPU time 375.02 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:34:21 PM PDT 24
Peak memory 249408 kb
Host smart-9120f93f-3948-4281-ba23-c9482bf5f751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240107852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4240107852
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2006488074
Short name T933
Test name
Test status
Simulation time 927385247 ps
CPU time 4.44 seconds
Started May 16 01:27:43 PM PDT 24
Finished May 16 01:28:06 PM PDT 24
Peak memory 232764 kb
Host smart-1c2d9316-0e67-40e5-b2a0-787f3d549961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006488074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2006488074
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4208785967
Short name T727
Test name
Test status
Simulation time 1866991360 ps
CPU time 7.67 seconds
Started May 16 01:27:35 PM PDT 24
Finished May 16 01:28:02 PM PDT 24
Peak memory 219560 kb
Host smart-c375e18d-ee70-446f-88db-75b71f682ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208785967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4208785967
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1411601941
Short name T812
Test name
Test status
Simulation time 528629517 ps
CPU time 14.01 seconds
Started May 16 01:27:48 PM PDT 24
Finished May 16 01:28:20 PM PDT 24
Peak memory 240484 kb
Host smart-206d472a-00f5-4ecb-8a17-f92d0f4d94a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411601941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1411601941
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3005854548
Short name T420
Test name
Test status
Simulation time 4916905014 ps
CPU time 16.74 seconds
Started May 16 01:27:40 PM PDT 24
Finished May 16 01:28:15 PM PDT 24
Peak memory 228784 kb
Host smart-41162d4f-a05a-4eb2-b30c-c73ffb9a37b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005854548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3005854548
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1520683217
Short name T908
Test name
Test status
Simulation time 354794563 ps
CPU time 4 seconds
Started May 16 01:27:38 PM PDT 24
Finished May 16 01:28:00 PM PDT 24
Peak memory 233080 kb
Host smart-dd2b1d22-3cf5-4006-ad53-b70c9764ea82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520683217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1520683217
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4198031968
Short name T896
Test name
Test status
Simulation time 3600851320 ps
CPU time 8.64 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:28:14 PM PDT 24
Peak memory 219200 kb
Host smart-4e04b444-37ca-409d-94e3-da6c68e77c85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4198031968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4198031968
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.654195443
Short name T890
Test name
Test status
Simulation time 6772843896 ps
CPU time 16.79 seconds
Started May 16 01:27:39 PM PDT 24
Finished May 16 01:28:15 PM PDT 24
Peak memory 216552 kb
Host smart-45945721-0a1a-4513-8432-4dc89c671fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654195443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.654195443
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4248705585
Short name T539
Test name
Test status
Simulation time 5521358196 ps
CPU time 15.94 seconds
Started May 16 01:27:41 PM PDT 24
Finished May 16 01:28:15 PM PDT 24
Peak memory 216100 kb
Host smart-49f0e466-dd48-482b-8858-e9cb1a98515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248705585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4248705585
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1847265011
Short name T402
Test name
Test status
Simulation time 169850194 ps
CPU time 1.62 seconds
Started May 16 01:27:38 PM PDT 24
Finished May 16 01:27:58 PM PDT 24
Peak memory 216460 kb
Host smart-88c3d8a9-4861-4e8a-806b-197dcba2e227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847265011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1847265011
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1066702148
Short name T647
Test name
Test status
Simulation time 148723673 ps
CPU time 0.98 seconds
Started May 16 01:27:36 PM PDT 24
Finished May 16 01:27:56 PM PDT 24
Peak memory 206848 kb
Host smart-081b9d08-e094-46e3-bfc5-51b5e2d542bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066702148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1066702148
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.780579242
Short name T758
Test name
Test status
Simulation time 577611780 ps
CPU time 9.53 seconds
Started May 16 01:27:46 PM PDT 24
Finished May 16 01:28:13 PM PDT 24
Peak memory 232620 kb
Host smart-53274cff-0317-4520-8ca4-a182859b7392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780579242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.780579242
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4273284672
Short name T895
Test name
Test status
Simulation time 25006758 ps
CPU time 0.73 seconds
Started May 16 01:27:49 PM PDT 24
Finished May 16 01:28:07 PM PDT 24
Peak memory 205348 kb
Host smart-fa9a7d01-e69d-4ec0-b2bf-7dd85e7a791b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273284672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4273284672
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2002955593
Short name T955
Test name
Test status
Simulation time 607043070 ps
CPU time 8.78 seconds
Started May 16 01:27:48 PM PDT 24
Finished May 16 01:28:15 PM PDT 24
Peak memory 220692 kb
Host smart-f27813db-112d-4465-ac08-20793b7e1be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002955593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2002955593
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.378532338
Short name T379
Test name
Test status
Simulation time 29816228 ps
CPU time 0.78 seconds
Started May 16 01:27:44 PM PDT 24
Finished May 16 01:28:03 PM PDT 24
Peak memory 206696 kb
Host smart-98e2d352-a1ea-4306-878c-6ccde2dee452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378532338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.378532338
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.458506651
Short name T644
Test name
Test status
Simulation time 54573411456 ps
CPU time 107.12 seconds
Started May 16 01:27:45 PM PDT 24
Finished May 16 01:29:50 PM PDT 24
Peak memory 253424 kb
Host smart-964e7fa3-eb8f-4e49-b384-8b917edf96b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458506651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.458506651
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1693280318
Short name T934
Test name
Test status
Simulation time 323936046806 ps
CPU time 154.43 seconds
Started May 16 01:27:52 PM PDT 24
Finished May 16 01:30:43 PM PDT 24
Peak memory 252412 kb
Host smart-5a530b27-00ab-435b-bec7-5ef41fd6fab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693280318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1693280318
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3978087011
Short name T613
Test name
Test status
Simulation time 5480444707 ps
CPU time 65.44 seconds
Started May 16 01:27:46 PM PDT 24
Finished May 16 01:29:09 PM PDT 24
Peak memory 240716 kb
Host smart-3d7768cf-3050-40c0-bdd2-651e877ebc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978087011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3978087011
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1214615831
Short name T922
Test name
Test status
Simulation time 265459464 ps
CPU time 3.75 seconds
Started May 16 01:27:45 PM PDT 24
Finished May 16 01:28:07 PM PDT 24
Peak memory 224532 kb
Host smart-a834fdd2-b75a-4a2c-a7c9-782aecf00fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214615831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1214615831
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2197772234
Short name T869
Test name
Test status
Simulation time 7576139087 ps
CPU time 22.49 seconds
Started May 16 01:27:52 PM PDT 24
Finished May 16 01:28:32 PM PDT 24
Peak memory 219504 kb
Host smart-971c78b2-3334-4098-8f6c-318542d52c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197772234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2197772234
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3134496353
Short name T935
Test name
Test status
Simulation time 604465120 ps
CPU time 8.59 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:28:13 PM PDT 24
Peak memory 218388 kb
Host smart-1b1629cc-3d4a-46c1-98a2-564d1f929038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134496353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3134496353
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2108657856
Short name T230
Test name
Test status
Simulation time 706295552 ps
CPU time 7.35 seconds
Started May 16 01:27:45 PM PDT 24
Finished May 16 01:28:10 PM PDT 24
Peak memory 240284 kb
Host smart-c4837941-06bb-46e2-9b9d-7d879ce68204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108657856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2108657856
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1601235983
Short name T283
Test name
Test status
Simulation time 13498588628 ps
CPU time 13.8 seconds
Started May 16 01:27:48 PM PDT 24
Finished May 16 01:28:20 PM PDT 24
Peak memory 238884 kb
Host smart-de97a75b-4a77-40a9-942f-08139193fa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601235983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1601235983
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3477251634
Short name T697
Test name
Test status
Simulation time 4263638353 ps
CPU time 9.15 seconds
Started May 16 01:27:44 PM PDT 24
Finished May 16 01:28:11 PM PDT 24
Peak memory 219264 kb
Host smart-c0854dde-b2e6-427c-9b4e-ef2920578c8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3477251634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3477251634
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1149405113
Short name T556
Test name
Test status
Simulation time 47968145194 ps
CPU time 433.46 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:35:19 PM PDT 24
Peak memory 270256 kb
Host smart-320f0f93-8d64-4ae3-8c12-0abd7de09dee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149405113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1149405113
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3126529634
Short name T784
Test name
Test status
Simulation time 19781376008 ps
CPU time 32.69 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:28:38 PM PDT 24
Peak memory 216544 kb
Host smart-c8b624bd-b089-4e40-874a-798dd06a6ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126529634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3126529634
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1319315796
Short name T779
Test name
Test status
Simulation time 3368109189 ps
CPU time 3.21 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:28:08 PM PDT 24
Peak memory 216524 kb
Host smart-dd11cb6b-0636-4ff7-a958-c52649d834e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319315796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1319315796
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3975273400
Short name T662
Test name
Test status
Simulation time 44687207 ps
CPU time 0.7 seconds
Started May 16 01:27:48 PM PDT 24
Finished May 16 01:28:06 PM PDT 24
Peak memory 205504 kb
Host smart-ba0ca171-bf4f-43dd-98cb-dcff1a50d49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975273400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3975273400
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1155716093
Short name T615
Test name
Test status
Simulation time 11273076 ps
CPU time 0.78 seconds
Started May 16 01:27:45 PM PDT 24
Finished May 16 01:28:04 PM PDT 24
Peak memory 205508 kb
Host smart-7a4a6a97-101f-4a17-af33-c9114b224169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155716093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1155716093
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3087024114
Short name T824
Test name
Test status
Simulation time 249057408 ps
CPU time 3.81 seconds
Started May 16 01:27:46 PM PDT 24
Finished May 16 01:28:08 PM PDT 24
Peak memory 235432 kb
Host smart-d43fd006-e814-478e-900b-6e5a12fe5994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087024114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3087024114
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3370087506
Short name T488
Test name
Test status
Simulation time 37161166 ps
CPU time 0.69 seconds
Started May 16 01:27:54 PM PDT 24
Finished May 16 01:28:11 PM PDT 24
Peak memory 205372 kb
Host smart-0de29b58-892c-4400-b39d-90705f63a4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370087506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3370087506
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.383964918
Short name T725
Test name
Test status
Simulation time 1098266517 ps
CPU time 5.52 seconds
Started May 16 01:27:49 PM PDT 24
Finished May 16 01:28:12 PM PDT 24
Peak memory 219580 kb
Host smart-9498cbb4-d72c-46bc-aded-f930c3ff8892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383964918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.383964918
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1539280511
Short name T344
Test name
Test status
Simulation time 17213894 ps
CPU time 0.78 seconds
Started May 16 01:27:49 PM PDT 24
Finished May 16 01:28:07 PM PDT 24
Peak memory 205772 kb
Host smart-589407d5-582b-47b0-919c-4f583795a0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539280511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1539280511
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.818669004
Short name T190
Test name
Test status
Simulation time 220011616503 ps
CPU time 225.64 seconds
Started May 16 01:27:48 PM PDT 24
Finished May 16 01:31:52 PM PDT 24
Peak memory 251920 kb
Host smart-0b5727fe-41e3-4681-8c92-19eb9d61dabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818669004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.818669004
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3637571500
Short name T279
Test name
Test status
Simulation time 25139368466 ps
CPU time 111.41 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:29:57 PM PDT 24
Peak memory 252812 kb
Host smart-74ca92e4-8ca8-47f0-878a-55090c8237bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637571500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3637571500
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.884810776
Short name T687
Test name
Test status
Simulation time 1485674953 ps
CPU time 13.48 seconds
Started May 16 01:27:48 PM PDT 24
Finished May 16 01:28:20 PM PDT 24
Peak memory 217376 kb
Host smart-ce1590b6-f0cd-42c6-88cb-7934b5a416df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884810776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.884810776
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.27795129
Short name T12
Test name
Test status
Simulation time 1278479888 ps
CPU time 23.03 seconds
Started May 16 01:27:46 PM PDT 24
Finished May 16 01:28:26 PM PDT 24
Peak memory 249140 kb
Host smart-4f7ad417-468b-4949-baea-f69418057090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27795129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.27795129
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4209626438
Short name T205
Test name
Test status
Simulation time 408664649 ps
CPU time 6.11 seconds
Started May 16 01:27:49 PM PDT 24
Finished May 16 01:28:12 PM PDT 24
Peak memory 233856 kb
Host smart-47544eee-6a8d-4d20-a400-182ea1933506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209626438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4209626438
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2869532367
Short name T897
Test name
Test status
Simulation time 1056066899 ps
CPU time 14.77 seconds
Started May 16 01:27:44 PM PDT 24
Finished May 16 01:28:17 PM PDT 24
Peak memory 246820 kb
Host smart-eaddcfbc-e6e5-4aa9-b362-f086bf508279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869532367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2869532367
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1975306449
Short name T581
Test name
Test status
Simulation time 281934721 ps
CPU time 2.32 seconds
Started May 16 01:27:49 PM PDT 24
Finished May 16 01:28:09 PM PDT 24
Peak memory 216116 kb
Host smart-36e8c8ee-870d-4553-880c-82dbe431d6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975306449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1975306449
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.83686975
Short name T891
Test name
Test status
Simulation time 2541544129 ps
CPU time 10.23 seconds
Started May 16 01:27:46 PM PDT 24
Finished May 16 01:28:14 PM PDT 24
Peak memory 224632 kb
Host smart-422e6fb9-f0ac-4e11-8cf8-7ad5241c6f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83686975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.83686975
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2249214340
Short name T677
Test name
Test status
Simulation time 5913930539 ps
CPU time 26.51 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:28:31 PM PDT 24
Peak memory 220772 kb
Host smart-04a84a9c-d9f5-4d7f-bd1c-c0e775e72cc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2249214340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2249214340
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.647525843
Short name T534
Test name
Test status
Simulation time 40853576866 ps
CPU time 48.59 seconds
Started May 16 01:27:46 PM PDT 24
Finished May 16 01:28:52 PM PDT 24
Peak memory 216552 kb
Host smart-a75d1a0d-a316-4aea-9f4a-ac6e62ea59a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647525843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.647525843
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2039225409
Short name T713
Test name
Test status
Simulation time 4669337057 ps
CPU time 7.67 seconds
Started May 16 01:27:43 PM PDT 24
Finished May 16 01:28:09 PM PDT 24
Peak memory 216444 kb
Host smart-0265a4cc-daaf-4f3e-85fd-43b7cab59cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039225409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2039225409
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1691133530
Short name T482
Test name
Test status
Simulation time 58036615 ps
CPU time 1.78 seconds
Started May 16 01:27:48 PM PDT 24
Finished May 16 01:28:08 PM PDT 24
Peak memory 216376 kb
Host smart-c309a2a4-f0cf-4fce-93d9-1a9ac9fc04b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691133530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1691133530
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4157341716
Short name T764
Test name
Test status
Simulation time 120211157 ps
CPU time 0.89 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:28:06 PM PDT 24
Peak memory 205832 kb
Host smart-0c2f7b46-4e95-449e-8e62-b849871a6fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157341716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4157341716
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3509585180
Short name T962
Test name
Test status
Simulation time 2554634997 ps
CPU time 12.2 seconds
Started May 16 01:27:49 PM PDT 24
Finished May 16 01:28:19 PM PDT 24
Peak memory 235684 kb
Host smart-138b1371-7477-4450-b883-ac631d0245e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509585180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3509585180
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1542268741
Short name T590
Test name
Test status
Simulation time 50070734 ps
CPU time 0.74 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:13 PM PDT 24
Peak memory 205392 kb
Host smart-07a7a2bb-caa3-4589-8024-65dff288ac19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542268741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1542268741
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4193520078
Short name T484
Test name
Test status
Simulation time 139700677 ps
CPU time 3.09 seconds
Started May 16 01:27:48 PM PDT 24
Finished May 16 01:28:09 PM PDT 24
Peak memory 233128 kb
Host smart-198dae5e-a15a-40a7-aa3c-a615e5f45639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193520078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4193520078
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1038460759
Short name T921
Test name
Test status
Simulation time 56034185 ps
CPU time 0.77 seconds
Started May 16 01:27:52 PM PDT 24
Finished May 16 01:28:10 PM PDT 24
Peak memory 206408 kb
Host smart-57a372cb-840a-423a-88fd-456d34e94c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038460759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1038460759
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.176977115
Short name T632
Test name
Test status
Simulation time 1277294276 ps
CPU time 22.09 seconds
Started May 16 01:27:58 PM PDT 24
Finished May 16 01:28:36 PM PDT 24
Peak memory 240940 kb
Host smart-52f804bf-1c9b-438c-a65a-14a5e638ef28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176977115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.176977115
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3884268064
Short name T304
Test name
Test status
Simulation time 18522487960 ps
CPU time 26.55 seconds
Started May 16 01:27:55 PM PDT 24
Finished May 16 01:28:38 PM PDT 24
Peak memory 217504 kb
Host smart-8c2209a3-9351-45f5-9c42-98ae9ff795ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884268064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3884268064
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1996064181
Short name T85
Test name
Test status
Simulation time 22964719258 ps
CPU time 110.94 seconds
Started May 16 01:28:00 PM PDT 24
Finished May 16 01:30:07 PM PDT 24
Peak memory 254388 kb
Host smart-9c343f3c-2f29-4838-a590-10571bc8333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996064181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1996064181
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2191421892
Short name T362
Test name
Test status
Simulation time 616737589 ps
CPU time 11.79 seconds
Started May 16 01:27:47 PM PDT 24
Finished May 16 01:28:17 PM PDT 24
Peak memory 240888 kb
Host smart-57ce3c10-8610-4ce8-a114-4a7237f4079a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191421892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2191421892
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2685070460
Short name T579
Test name
Test status
Simulation time 9031869977 ps
CPU time 24.96 seconds
Started May 16 01:27:48 PM PDT 24
Finished May 16 01:28:31 PM PDT 24
Peak memory 219160 kb
Host smart-dd37ecf0-9318-43cf-a5b5-6d4eb490ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685070460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2685070460
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4226751865
Short name T750
Test name
Test status
Simulation time 2500486100 ps
CPU time 27.64 seconds
Started May 16 01:27:51 PM PDT 24
Finished May 16 01:28:35 PM PDT 24
Peak memory 227128 kb
Host smart-85323463-e292-4abf-959c-7762e9f69e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226751865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4226751865
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.80963220
Short name T54
Test name
Test status
Simulation time 8876606328 ps
CPU time 25.35 seconds
Started May 16 01:27:50 PM PDT 24
Finished May 16 01:28:32 PM PDT 24
Peak memory 240556 kb
Host smart-4332eb47-a2d9-46a0-ae53-d1f2fd912a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80963220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.80963220
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3248952283
Short name T450
Test name
Test status
Simulation time 5425401145 ps
CPU time 19.67 seconds
Started May 16 01:27:49 PM PDT 24
Finished May 16 01:28:26 PM PDT 24
Peak memory 235272 kb
Host smart-440e22e7-b551-450d-87c6-c6f08fca84aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248952283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3248952283
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1955558542
Short name T530
Test name
Test status
Simulation time 7825439300 ps
CPU time 9.92 seconds
Started May 16 01:27:57 PM PDT 24
Finished May 16 01:28:23 PM PDT 24
Peak memory 220228 kb
Host smart-ab8d28b1-e027-4ce9-b056-490ab7a3d5d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1955558542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1955558542
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.959458273
Short name T7
Test name
Test status
Simulation time 23613618 ps
CPU time 0.74 seconds
Started May 16 01:27:49 PM PDT 24
Finished May 16 01:28:07 PM PDT 24
Peak memory 205556 kb
Host smart-5fbcb1c0-3154-42c9-bc03-9f211285c07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959458273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.959458273
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2928216455
Short name T446
Test name
Test status
Simulation time 7720171908 ps
CPU time 17.96 seconds
Started May 16 01:27:54 PM PDT 24
Finished May 16 01:28:29 PM PDT 24
Peak memory 216496 kb
Host smart-46547041-7fd1-44d8-ba8d-84f7a1a02c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928216455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2928216455
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1130921135
Short name T506
Test name
Test status
Simulation time 12229820 ps
CPU time 0.68 seconds
Started May 16 01:27:53 PM PDT 24
Finished May 16 01:28:11 PM PDT 24
Peak memory 205496 kb
Host smart-e294861c-76e9-458e-9240-d10ccb5b02ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130921135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1130921135
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2744497950
Short name T463
Test name
Test status
Simulation time 16979238 ps
CPU time 0.73 seconds
Started May 16 01:27:53 PM PDT 24
Finished May 16 01:28:11 PM PDT 24
Peak memory 205836 kb
Host smart-5c9a329c-0850-4dc7-b7fb-4e84b21f7c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744497950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2744497950
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2932736750
Short name T940
Test name
Test status
Simulation time 12647598573 ps
CPU time 12.91 seconds
Started May 16 01:27:50 PM PDT 24
Finished May 16 01:28:20 PM PDT 24
Peak memory 232852 kb
Host smart-baf94d53-8a0d-40cb-a1c9-db63754335fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932736750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2932736750
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1491643559
Short name T493
Test name
Test status
Simulation time 13622684 ps
CPU time 0.7 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:13 PM PDT 24
Peak memory 204728 kb
Host smart-11e36feb-91bf-4f8e-9724-201bb461a19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491643559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1491643559
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3881333474
Short name T770
Test name
Test status
Simulation time 1519197779 ps
CPU time 5.98 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:18 PM PDT 24
Peak memory 234364 kb
Host smart-9650fed8-607d-4edf-86da-73fde336d66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881333474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3881333474
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4277014570
Short name T415
Test name
Test status
Simulation time 49587870 ps
CPU time 0.75 seconds
Started May 16 01:27:58 PM PDT 24
Finished May 16 01:28:14 PM PDT 24
Peak memory 205384 kb
Host smart-fa330d0d-8db2-4bf7-8fc8-2cb263f8de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277014570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4277014570
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3138003843
Short name T213
Test name
Test status
Simulation time 66964898469 ps
CPU time 435.15 seconds
Started May 16 01:28:01 PM PDT 24
Finished May 16 01:35:32 PM PDT 24
Peak memory 256664 kb
Host smart-b0d4553b-31d0-4c03-88eb-1cb2adb986d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138003843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3138003843
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4263381588
Short name T974
Test name
Test status
Simulation time 5423853955 ps
CPU time 104.03 seconds
Started May 16 01:27:54 PM PDT 24
Finished May 16 01:29:55 PM PDT 24
Peak memory 267496 kb
Host smart-270fef80-7be7-44bb-aa42-07dee3e0292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263381588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4263381588
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2343019052
Short name T24
Test name
Test status
Simulation time 18097586781 ps
CPU time 179 seconds
Started May 16 01:28:00 PM PDT 24
Finished May 16 01:31:16 PM PDT 24
Peak memory 251448 kb
Host smart-2274f6c5-0676-4d10-a226-993e53ef31df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343019052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2343019052
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1691254516
Short name T567
Test name
Test status
Simulation time 53140555 ps
CPU time 3.17 seconds
Started May 16 01:28:01 PM PDT 24
Finished May 16 01:28:20 PM PDT 24
Peak memory 232716 kb
Host smart-3bceb826-14b9-4e51-91da-1dc936a8ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691254516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1691254516
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2310502445
Short name T573
Test name
Test status
Simulation time 525450455 ps
CPU time 6 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:19 PM PDT 24
Peak memory 219548 kb
Host smart-d5d4e92d-8792-4380-874e-4a86ceec3dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310502445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2310502445
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1651673846
Short name T351
Test name
Test status
Simulation time 7120424296 ps
CPU time 74.89 seconds
Started May 16 01:28:00 PM PDT 24
Finished May 16 01:29:31 PM PDT 24
Peak memory 249008 kb
Host smart-35d5c789-7719-4905-9c3a-a8a390780f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651673846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1651673846
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.279536195
Short name T529
Test name
Test status
Simulation time 296358975 ps
CPU time 3.27 seconds
Started May 16 01:27:57 PM PDT 24
Finished May 16 01:28:17 PM PDT 24
Peak memory 218456 kb
Host smart-6bfe04ce-0ebd-454d-8820-bf77eaef4fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279536195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.279536195
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4147877119
Short name T744
Test name
Test status
Simulation time 33256308 ps
CPU time 2.28 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:15 PM PDT 24
Peak memory 221424 kb
Host smart-22444492-2fb1-493d-ae9c-90a31ae13c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147877119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4147877119
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2038219101
Short name T862
Test name
Test status
Simulation time 342365353 ps
CPU time 6.65 seconds
Started May 16 01:27:54 PM PDT 24
Finished May 16 01:28:18 PM PDT 24
Peak memory 219780 kb
Host smart-d2fd6afd-a21d-4296-b7ae-b8ef70244312
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2038219101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2038219101
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2411856212
Short name T149
Test name
Test status
Simulation time 9429185642 ps
CPU time 75.47 seconds
Started May 16 01:28:00 PM PDT 24
Finished May 16 01:29:32 PM PDT 24
Peak memory 244872 kb
Host smart-cc3ec7ae-b4b6-474f-bc8f-8ba9a334696f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411856212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2411856212
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2115618046
Short name T909
Test name
Test status
Simulation time 6822711534 ps
CPU time 34.76 seconds
Started May 16 01:27:55 PM PDT 24
Finished May 16 01:28:46 PM PDT 24
Peak memory 216568 kb
Host smart-71873f92-9b2a-4b2f-9f44-b9ed96a1e78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115618046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2115618046
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2112313577
Short name T566
Test name
Test status
Simulation time 1916433232 ps
CPU time 9.07 seconds
Started May 16 01:27:54 PM PDT 24
Finished May 16 01:28:20 PM PDT 24
Peak memory 216368 kb
Host smart-b6fd0c01-14dc-4b5d-8603-0ab115d43437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112313577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2112313577
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1289757128
Short name T51
Test name
Test status
Simulation time 18656838 ps
CPU time 0.83 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:13 PM PDT 24
Peak memory 206556 kb
Host smart-9ce2c757-5a7b-4c4f-ae28-359b102516d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289757128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1289757128
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1525626177
Short name T42
Test name
Test status
Simulation time 56911125 ps
CPU time 0.73 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:13 PM PDT 24
Peak memory 205856 kb
Host smart-8835094f-a210-4840-8075-210ef25bcf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525626177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1525626177
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2993998011
Short name T274
Test name
Test status
Simulation time 3032002889 ps
CPU time 13.23 seconds
Started May 16 01:27:58 PM PDT 24
Finished May 16 01:28:27 PM PDT 24
Peak memory 236740 kb
Host smart-c31a969f-20e6-4718-bbe2-24dfdbe5d2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993998011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2993998011
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2953575448
Short name T58
Test name
Test status
Simulation time 23951715 ps
CPU time 0.76 seconds
Started May 16 01:28:08 PM PDT 24
Finished May 16 01:28:25 PM PDT 24
Peak memory 205352 kb
Host smart-b0d4d69b-cc0d-4d65-aeae-8be628170a9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953575448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2953575448
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2415018463
Short name T363
Test name
Test status
Simulation time 18083103178 ps
CPU time 12.49 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:25 PM PDT 24
Peak memory 234416 kb
Host smart-9f1abdcd-f0d1-419b-b5e1-f3cc777b8a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415018463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2415018463
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2421636050
Short name T635
Test name
Test status
Simulation time 14211728 ps
CPU time 0.74 seconds
Started May 16 01:28:01 PM PDT 24
Finished May 16 01:28:18 PM PDT 24
Peak memory 206804 kb
Host smart-8431c5ee-1876-449d-bf9a-8bafa9abc36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421636050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2421636050
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1249313411
Short name T473
Test name
Test status
Simulation time 65841323031 ps
CPU time 223.79 seconds
Started May 16 01:27:57 PM PDT 24
Finished May 16 01:31:57 PM PDT 24
Peak memory 249904 kb
Host smart-9d65e52d-a7dd-4b37-a4df-3ac8629e64ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249313411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1249313411
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3437059552
Short name T411
Test name
Test status
Simulation time 2779646102 ps
CPU time 26.38 seconds
Started May 16 01:27:57 PM PDT 24
Finished May 16 01:28:39 PM PDT 24
Peak memory 217584 kb
Host smart-68221b8d-8823-40cf-b558-4a503fd4c3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437059552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3437059552
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2566912083
Short name T193
Test name
Test status
Simulation time 156900736578 ps
CPU time 444.47 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:35:37 PM PDT 24
Peak memory 265740 kb
Host smart-84a063b8-f7fa-48f2-ad34-9a2e6af550bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566912083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2566912083
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3449135563
Short name T297
Test name
Test status
Simulation time 576673815 ps
CPU time 4.43 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:17 PM PDT 24
Peak memory 224452 kb
Host smart-8e770374-4186-4f04-a2d4-5fb5e258ea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449135563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3449135563
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.281159641
Short name T429
Test name
Test status
Simulation time 7090108593 ps
CPU time 7.9 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:21 PM PDT 24
Peak memory 234080 kb
Host smart-6d2d1dcd-8d29-41c1-9ac8-8b6684241b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281159641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.281159641
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3247660578
Short name T186
Test name
Test status
Simulation time 16088930066 ps
CPU time 54.61 seconds
Started May 16 01:27:57 PM PDT 24
Finished May 16 01:29:08 PM PDT 24
Peak memory 237488 kb
Host smart-b6c06176-8bac-4329-8065-e7e3189f3283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247660578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3247660578
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.757994272
Short name T249
Test name
Test status
Simulation time 2024111743 ps
CPU time 11.09 seconds
Started May 16 01:27:55 PM PDT 24
Finished May 16 01:28:22 PM PDT 24
Peak memory 227932 kb
Host smart-33a84695-76d2-41af-af83-b859bb567cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757994272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.757994272
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.229771175
Short name T884
Test name
Test status
Simulation time 532995407 ps
CPU time 6.61 seconds
Started May 16 01:27:55 PM PDT 24
Finished May 16 01:28:18 PM PDT 24
Peak memory 233280 kb
Host smart-f16950bc-aee0-43d0-98bf-1192f2c3eb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229771175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.229771175
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.35013577
Short name T49
Test name
Test status
Simulation time 2120379614 ps
CPU time 13.71 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:26 PM PDT 24
Peak memory 223108 kb
Host smart-cee23e6b-51af-4a4e-bc3a-812c5522cf69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=35013577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direc
t.35013577
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1461419214
Short name T166
Test name
Test status
Simulation time 9277975835 ps
CPU time 27.09 seconds
Started May 16 01:28:04 PM PDT 24
Finished May 16 01:28:46 PM PDT 24
Peak memory 241120 kb
Host smart-287a491d-b4a4-4c12-a840-21bcf1a3fff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461419214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1461419214
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3256049455
Short name T10
Test name
Test status
Simulation time 28758233267 ps
CPU time 26.83 seconds
Started May 16 01:28:00 PM PDT 24
Finished May 16 01:28:43 PM PDT 24
Peak memory 216332 kb
Host smart-4c39cc93-9a71-45b1-bec4-34f49d47688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256049455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3256049455
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2548307323
Short name T841
Test name
Test status
Simulation time 1679329453 ps
CPU time 6.42 seconds
Started May 16 01:27:55 PM PDT 24
Finished May 16 01:28:18 PM PDT 24
Peak memory 216364 kb
Host smart-90e5c88d-e887-42b1-a415-ac665727d9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548307323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2548307323
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.848225040
Short name T856
Test name
Test status
Simulation time 130004304 ps
CPU time 2.94 seconds
Started May 16 01:27:57 PM PDT 24
Finished May 16 01:28:16 PM PDT 24
Peak memory 216340 kb
Host smart-0910e644-ee47-4043-be9c-cda8e6015b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848225040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.848225040
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.4096758495
Short name T94
Test name
Test status
Simulation time 63928510 ps
CPU time 0.85 seconds
Started May 16 01:27:55 PM PDT 24
Finished May 16 01:28:13 PM PDT 24
Peak memory 205836 kb
Host smart-b6226a40-ce9e-4c1d-8ade-fe9da64a7afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096758495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.4096758495
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3154030837
Short name T280
Test name
Test status
Simulation time 1090259347 ps
CPU time 5.25 seconds
Started May 16 01:27:56 PM PDT 24
Finished May 16 01:28:17 PM PDT 24
Peak memory 218876 kb
Host smart-e78003e5-2a49-4724-814b-74763f99fd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154030837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3154030837
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.202210271
Short name T901
Test name
Test status
Simulation time 14723611 ps
CPU time 0.71 seconds
Started May 16 01:26:29 PM PDT 24
Finished May 16 01:26:46 PM PDT 24
Peak memory 204792 kb
Host smart-de5973ad-e5d2-4a1c-8ad5-b7aa3aca4e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202210271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.202210271
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1925546859
Short name T775
Test name
Test status
Simulation time 202602753 ps
CPU time 3.56 seconds
Started May 16 01:26:43 PM PDT 24
Finished May 16 01:27:00 PM PDT 24
Peak memory 218768 kb
Host smart-5fe15e8c-9a87-471f-a3c3-14dccb6f64d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925546859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1925546859
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1175181669
Short name T393
Test name
Test status
Simulation time 18566960 ps
CPU time 0.8 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:26:51 PM PDT 24
Peak memory 206740 kb
Host smart-a40f83d1-1bdf-4301-a01a-6d578ff09c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175181669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1175181669
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1651615728
Short name T227
Test name
Test status
Simulation time 15057241053 ps
CPU time 24.86 seconds
Started May 16 01:26:26 PM PDT 24
Finished May 16 01:27:08 PM PDT 24
Peak memory 221456 kb
Host smart-55cd62d0-7571-4db4-9fe5-903e6b7f29a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651615728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1651615728
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3946486931
Short name T792
Test name
Test status
Simulation time 130205506209 ps
CPU time 357.25 seconds
Started May 16 01:26:33 PM PDT 24
Finished May 16 01:32:45 PM PDT 24
Peak memory 256240 kb
Host smart-2b5c76a7-8476-4ad9-8c09-359d436d2c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946486931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3946486931
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.220584147
Short name T242
Test name
Test status
Simulation time 3484996674 ps
CPU time 42.61 seconds
Started May 16 01:26:26 PM PDT 24
Finished May 16 01:27:25 PM PDT 24
Peak memory 249376 kb
Host smart-8ad6e9c8-841c-468b-b450-ee5caba64899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220584147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
220584147
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.947792475
Short name T572
Test name
Test status
Simulation time 13958396194 ps
CPU time 41.62 seconds
Started May 16 01:26:43 PM PDT 24
Finished May 16 01:27:38 PM PDT 24
Peak memory 249296 kb
Host smart-3194a98d-4959-4124-bb8e-a37e331a75ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947792475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.947792475
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1223189909
Short name T372
Test name
Test status
Simulation time 2868097902 ps
CPU time 3.91 seconds
Started May 16 01:26:33 PM PDT 24
Finished May 16 01:26:52 PM PDT 24
Peak memory 218012 kb
Host smart-af180433-57c9-4bdd-bc0c-759770204d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223189909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1223189909
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3121759373
Short name T310
Test name
Test status
Simulation time 98598123 ps
CPU time 2.14 seconds
Started May 16 01:26:33 PM PDT 24
Finished May 16 01:26:50 PM PDT 24
Peak memory 218040 kb
Host smart-70715a86-9562-49fb-bcb3-e8fe4e80f753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121759373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3121759373
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.557981451
Short name T964
Test name
Test status
Simulation time 51974326 ps
CPU time 1.11 seconds
Started May 16 01:26:30 PM PDT 24
Finished May 16 01:26:47 PM PDT 24
Peak memory 216700 kb
Host smart-91391f91-a26a-45fa-95b9-d496b89e2158
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557981451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.557981451
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.4201729049
Short name T916
Test name
Test status
Simulation time 4562671153 ps
CPU time 6.32 seconds
Started May 16 01:26:45 PM PDT 24
Finished May 16 01:27:05 PM PDT 24
Peak memory 233988 kb
Host smart-66d3798f-63d9-48b7-aff0-74bcbc950be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201729049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.4201729049
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2573550066
Short name T336
Test name
Test status
Simulation time 1476128617 ps
CPU time 5.37 seconds
Started May 16 01:26:42 PM PDT 24
Finished May 16 01:27:01 PM PDT 24
Peak memory 219876 kb
Host smart-b88cef12-d25f-481e-a3c5-2a8e572b6119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573550066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2573550066
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1873979292
Short name T669
Test name
Test status
Simulation time 839319512 ps
CPU time 4.1 seconds
Started May 16 01:26:28 PM PDT 24
Finished May 16 01:26:48 PM PDT 24
Peak memory 220248 kb
Host smart-880dc9d2-491a-47ae-80f8-6f60d5e97e65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1873979292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1873979292
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2526742795
Short name T70
Test name
Test status
Simulation time 144515841 ps
CPU time 0.98 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:50 PM PDT 24
Peak memory 235080 kb
Host smart-e64a90d3-57fb-4601-9645-286d1365040e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526742795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2526742795
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2206349828
Short name T153
Test name
Test status
Simulation time 163457212 ps
CPU time 0.95 seconds
Started May 16 01:26:26 PM PDT 24
Finished May 16 01:26:44 PM PDT 24
Peak memory 206516 kb
Host smart-38d747a2-2f16-4e4c-b306-18b963f07291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206349828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2206349828
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1294935558
Short name T141
Test name
Test status
Simulation time 12100745281 ps
CPU time 34.23 seconds
Started May 16 01:26:37 PM PDT 24
Finished May 16 01:27:26 PM PDT 24
Peak memory 216468 kb
Host smart-8b351d39-c8ed-45ee-9054-a94f63bb7398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294935558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1294935558
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1760750338
Short name T306
Test name
Test status
Simulation time 2072664534 ps
CPU time 5.4 seconds
Started May 16 01:26:32 PM PDT 24
Finished May 16 01:26:52 PM PDT 24
Peak memory 216404 kb
Host smart-1f745445-968c-4a2e-acb7-f0289fc9f70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760750338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1760750338
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3592829057
Short name T558
Test name
Test status
Simulation time 31000312 ps
CPU time 1.04 seconds
Started May 16 01:26:32 PM PDT 24
Finished May 16 01:26:48 PM PDT 24
Peak memory 206648 kb
Host smart-1b5547c6-8f99-4e3c-8e57-9512d3e443c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592829057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3592829057
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.4027176569
Short name T383
Test name
Test status
Simulation time 92001248 ps
CPU time 0.77 seconds
Started May 16 01:26:27 PM PDT 24
Finished May 16 01:26:44 PM PDT 24
Peak memory 205928 kb
Host smart-0055df47-45fb-4b4c-80ad-4aecd61d21da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027176569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.4027176569
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2217245715
Short name T870
Test name
Test status
Simulation time 13477094052 ps
CPU time 15.59 seconds
Started May 16 01:26:36 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 232880 kb
Host smart-55f71a3e-c7b5-48fc-8302-73d93b6c6ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217245715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2217245715
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3199443441
Short name T315
Test name
Test status
Simulation time 12397575 ps
CPU time 0.72 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:23 PM PDT 24
Peak memory 204760 kb
Host smart-626d5afa-5f2a-4ff1-bb93-56506547368c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199443441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3199443441
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2840714950
Short name T816
Test name
Test status
Simulation time 970238406 ps
CPU time 12.08 seconds
Started May 16 01:28:08 PM PDT 24
Finished May 16 01:28:36 PM PDT 24
Peak memory 219924 kb
Host smart-9c4b04f7-4ab1-4a22-b94a-b1778b877b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840714950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2840714950
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1953979574
Short name T356
Test name
Test status
Simulation time 42324153 ps
CPU time 0.78 seconds
Started May 16 01:28:07 PM PDT 24
Finished May 16 01:28:24 PM PDT 24
Peak memory 206460 kb
Host smart-5450b2b0-3924-418a-b2af-be11ac3da77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953979574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1953979574
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3502234105
Short name T616
Test name
Test status
Simulation time 24738595250 ps
CPU time 111.31 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:30:13 PM PDT 24
Peak memory 250432 kb
Host smart-2d5fa93b-e1aa-4f0c-aa85-34bb41eebd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502234105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3502234105
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.909202398
Short name T923
Test name
Test status
Simulation time 303578958099 ps
CPU time 722.28 seconds
Started May 16 01:28:08 PM PDT 24
Finished May 16 01:40:26 PM PDT 24
Peak memory 261088 kb
Host smart-d1ca49e3-275d-4f5e-84ac-21f221954e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909202398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.909202398
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2856233891
Short name T550
Test name
Test status
Simulation time 22625573428 ps
CPU time 60.61 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:29:22 PM PDT 24
Peak memory 249420 kb
Host smart-76037c52-572b-48b9-b02e-fa8e03653e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856233891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2856233891
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2665682576
Short name T378
Test name
Test status
Simulation time 532882916 ps
CPU time 11.04 seconds
Started May 16 01:28:04 PM PDT 24
Finished May 16 01:28:30 PM PDT 24
Peak memory 224424 kb
Host smart-97753b9f-b109-4f2c-acd4-556a09cf1f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665682576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2665682576
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.43841734
Short name T736
Test name
Test status
Simulation time 613244638 ps
CPU time 6.36 seconds
Started May 16 01:28:02 PM PDT 24
Finished May 16 01:28:24 PM PDT 24
Peak memory 232744 kb
Host smart-f0e8cab1-816e-4b6f-98da-eadbeca05767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43841734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.43841734
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1584961576
Short name T663
Test name
Test status
Simulation time 537769420 ps
CPU time 5.58 seconds
Started May 16 01:28:09 PM PDT 24
Finished May 16 01:28:30 PM PDT 24
Peak memory 233516 kb
Host smart-b8ee3a54-cfda-43a9-8f01-2839d6dd832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584961576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1584961576
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1246839716
Short name T608
Test name
Test status
Simulation time 571172944 ps
CPU time 4.81 seconds
Started May 16 01:28:07 PM PDT 24
Finished May 16 01:28:27 PM PDT 24
Peak memory 224532 kb
Host smart-dfaa22fa-2ef8-4f40-9239-a9d1265558f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246839716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1246839716
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3931365129
Short name T763
Test name
Test status
Simulation time 226322751 ps
CPU time 4.91 seconds
Started May 16 01:28:04 PM PDT 24
Finished May 16 01:28:24 PM PDT 24
Peak memory 235456 kb
Host smart-98fee34f-6178-4c8f-86b1-cc3f92719c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931365129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3931365129
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1005066684
Short name T710
Test name
Test status
Simulation time 2214302433 ps
CPU time 6.56 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:28 PM PDT 24
Peak memory 219348 kb
Host smart-6099055d-14f8-4d3c-8264-06788551cd64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1005066684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1005066684
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2412303180
Short name T337
Test name
Test status
Simulation time 2186205951 ps
CPU time 9.21 seconds
Started May 16 01:28:04 PM PDT 24
Finished May 16 01:28:28 PM PDT 24
Peak memory 216572 kb
Host smart-afdf5942-0a0b-45d2-b7b5-6284bb6228df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412303180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2412303180
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1887847337
Short name T483
Test name
Test status
Simulation time 1832106733 ps
CPU time 7.9 seconds
Started May 16 01:28:07 PM PDT 24
Finished May 16 01:28:31 PM PDT 24
Peak memory 216364 kb
Host smart-67435ed5-44b5-4983-b013-31e629e3fa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887847337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1887847337
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2159860737
Short name T361
Test name
Test status
Simulation time 35380084 ps
CPU time 0.72 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:23 PM PDT 24
Peak memory 205848 kb
Host smart-75f67b11-8767-4323-803d-2ebaa5d2e951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159860737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2159860737
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1474826660
Short name T568
Test name
Test status
Simulation time 87961906 ps
CPU time 0.97 seconds
Started May 16 01:28:05 PM PDT 24
Finished May 16 01:28:21 PM PDT 24
Peak memory 205796 kb
Host smart-15f53066-42de-41eb-8106-c09af3de23ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474826660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1474826660
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2766879399
Short name T686
Test name
Test status
Simulation time 1323781123 ps
CPU time 5.18 seconds
Started May 16 01:28:07 PM PDT 24
Finished May 16 01:28:27 PM PDT 24
Peak memory 219052 kb
Host smart-89c65163-9a9e-47d7-a390-5fc8d0afc5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766879399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2766879399
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3457277505
Short name T956
Test name
Test status
Simulation time 12829365 ps
CPU time 0.72 seconds
Started May 16 01:28:09 PM PDT 24
Finished May 16 01:28:25 PM PDT 24
Peak memory 205732 kb
Host smart-e1344921-1d74-4afa-9745-99c8060b99e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457277505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3457277505
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1095050971
Short name T726
Test name
Test status
Simulation time 144020715 ps
CPU time 3.37 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:24 PM PDT 24
Peak memory 218788 kb
Host smart-3016d8ba-b735-43d7-a15b-171d44d8c39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095050971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1095050971
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3549801359
Short name T650
Test name
Test status
Simulation time 148370364 ps
CPU time 0.84 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:22 PM PDT 24
Peak memory 206492 kb
Host smart-18463860-efdb-481a-a4f6-eeca98b1c148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549801359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3549801359
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3513620554
Short name T366
Test name
Test status
Simulation time 443600031 ps
CPU time 8.68 seconds
Started May 16 01:28:05 PM PDT 24
Finished May 16 01:28:30 PM PDT 24
Peak memory 235992 kb
Host smart-e264d8e8-f9a3-4ee8-805e-5b086560133f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513620554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3513620554
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.179917905
Short name T708
Test name
Test status
Simulation time 35486367871 ps
CPU time 128.95 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:30:30 PM PDT 24
Peak memory 254016 kb
Host smart-f2c4e6f5-b7f6-4fa3-afe2-ec407f23995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179917905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.179917905
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1531278696
Short name T261
Test name
Test status
Simulation time 75159297488 ps
CPU time 742.82 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:40:45 PM PDT 24
Peak memory 253876 kb
Host smart-770af380-b2a6-4253-919f-f176024c9e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531278696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1531278696
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.191835637
Short name T499
Test name
Test status
Simulation time 868775174 ps
CPU time 7.04 seconds
Started May 16 01:28:04 PM PDT 24
Finished May 16 01:28:26 PM PDT 24
Peak memory 224584 kb
Host smart-3b97b55d-18f9-4edc-a696-475fe3c263f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191835637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.191835637
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2740492164
Short name T947
Test name
Test status
Simulation time 4425977070 ps
CPU time 17.49 seconds
Started May 16 01:28:05 PM PDT 24
Finished May 16 01:28:38 PM PDT 24
Peak memory 218928 kb
Host smart-276534d1-93f1-4118-97b9-3874357573f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740492164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2740492164
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.561226514
Short name T626
Test name
Test status
Simulation time 109571674 ps
CPU time 2.46 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:24 PM PDT 24
Peak memory 221444 kb
Host smart-a1ce70e4-fa7d-4ab8-9520-e72df18f68a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561226514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.561226514
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.870373133
Short name T196
Test name
Test status
Simulation time 346706901 ps
CPU time 2.43 seconds
Started May 16 01:28:05 PM PDT 24
Finished May 16 01:28:23 PM PDT 24
Peak memory 218624 kb
Host smart-3855ff19-6746-42eb-9a75-375f8ab2bb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870373133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.870373133
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.645781928
Short name T258
Test name
Test status
Simulation time 6664046847 ps
CPU time 4.72 seconds
Started May 16 01:28:05 PM PDT 24
Finished May 16 01:28:25 PM PDT 24
Peak memory 233860 kb
Host smart-3f8e1ec9-4aeb-4d54-8bc6-b64e895cb39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645781928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.645781928
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.81870540
Short name T625
Test name
Test status
Simulation time 215794545 ps
CPU time 4.22 seconds
Started May 16 01:28:07 PM PDT 24
Finished May 16 01:28:27 PM PDT 24
Peak memory 218972 kb
Host smart-799431d8-2a6f-4b47-876a-a62f52a0071b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=81870540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direc
t.81870540
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.170068475
Short name T871
Test name
Test status
Simulation time 290331112 ps
CPU time 1.29 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:23 PM PDT 24
Peak memory 206872 kb
Host smart-852486cf-c32f-472e-a4db-4ebadf184767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170068475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.170068475
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3622371689
Short name T328
Test name
Test status
Simulation time 13081180 ps
CPU time 0.72 seconds
Started May 16 01:28:07 PM PDT 24
Finished May 16 01:28:24 PM PDT 24
Peak memory 205564 kb
Host smart-fbfc7d91-3b6e-4f86-9494-12ac8dcb1f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622371689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3622371689
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4239735677
Short name T803
Test name
Test status
Simulation time 2829715372 ps
CPU time 8.02 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:29 PM PDT 24
Peak memory 216380 kb
Host smart-24c5848e-8e4d-4a0c-9a35-4a90f485a3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239735677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4239735677
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3866909570
Short name T440
Test name
Test status
Simulation time 36342401 ps
CPU time 0.87 seconds
Started May 16 01:28:07 PM PDT 24
Finished May 16 01:28:23 PM PDT 24
Peak memory 205808 kb
Host smart-6ed48b68-98c1-4073-badc-5dded849b8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866909570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3866909570
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1528401820
Short name T617
Test name
Test status
Simulation time 54557878 ps
CPU time 0.88 seconds
Started May 16 01:28:05 PM PDT 24
Finished May 16 01:28:22 PM PDT 24
Peak memory 206860 kb
Host smart-2a0137bc-ea2e-406b-a738-f6d34472448b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528401820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1528401820
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3939803115
Short name T724
Test name
Test status
Simulation time 592452507 ps
CPU time 6.9 seconds
Started May 16 01:28:05 PM PDT 24
Finished May 16 01:28:27 PM PDT 24
Peak memory 235040 kb
Host smart-2b9cfb50-bd27-4af1-8f66-38496dc5e75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939803115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3939803115
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1225019000
Short name T957
Test name
Test status
Simulation time 15037626 ps
CPU time 0.76 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:28:30 PM PDT 24
Peak memory 205404 kb
Host smart-c6997ab6-c517-46d4-b486-693cd4c6de9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225019000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1225019000
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1183753141
Short name T822
Test name
Test status
Simulation time 387869635 ps
CPU time 5.45 seconds
Started May 16 01:28:09 PM PDT 24
Finished May 16 01:28:30 PM PDT 24
Peak memory 233804 kb
Host smart-da8582f8-5b25-40c3-8d2a-1006cde56583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183753141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1183753141
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3755349598
Short name T74
Test name
Test status
Simulation time 42633649 ps
CPU time 0.77 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:23 PM PDT 24
Peak memory 206384 kb
Host smart-2b232067-6ce6-429d-b82e-e1803e57994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755349598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3755349598
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.373107462
Short name T236
Test name
Test status
Simulation time 2563476907 ps
CPU time 15.73 seconds
Started May 16 01:28:04 PM PDT 24
Finished May 16 01:28:35 PM PDT 24
Peak memory 232864 kb
Host smart-468d932a-9983-41b8-8b9e-bca8863cdfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373107462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.373107462
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.860961405
Short name T696
Test name
Test status
Simulation time 4588165118 ps
CPU time 96.73 seconds
Started May 16 01:28:19 PM PDT 24
Finished May 16 01:30:10 PM PDT 24
Peak memory 251192 kb
Host smart-40de7fcb-e02a-466c-b957-02401a3d2cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860961405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.860961405
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1310254184
Short name T682
Test name
Test status
Simulation time 16961298640 ps
CPU time 168.83 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:31:19 PM PDT 24
Peak memory 250488 kb
Host smart-9347915b-a46b-495a-99ec-94ccbb4ddca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310254184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1310254184
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1317855282
Short name T160
Test name
Test status
Simulation time 1827067947 ps
CPU time 28.84 seconds
Started May 16 01:28:07 PM PDT 24
Finished May 16 01:28:52 PM PDT 24
Peak memory 232688 kb
Host smart-a9345c76-e1af-404b-9cd0-21bf769f21bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317855282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1317855282
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1707290845
Short name T688
Test name
Test status
Simulation time 106932715 ps
CPU time 1.9 seconds
Started May 16 01:28:09 PM PDT 24
Finished May 16 01:28:26 PM PDT 24
Peak memory 216132 kb
Host smart-b16aa75a-c3b3-41e0-adb6-ee69ba80ba3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707290845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1707290845
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.303767655
Short name T885
Test name
Test status
Simulation time 2016583362 ps
CPU time 6.94 seconds
Started May 16 01:28:10 PM PDT 24
Finished May 16 01:28:32 PM PDT 24
Peak memory 218500 kb
Host smart-294b2dd7-791f-48aa-ba4f-08c6872a6182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303767655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.303767655
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.658211419
Short name T639
Test name
Test status
Simulation time 7507896028 ps
CPU time 14.83 seconds
Started May 16 01:28:10 PM PDT 24
Finished May 16 01:28:40 PM PDT 24
Peak memory 236696 kb
Host smart-a70631fe-a777-41cd-9da2-37da543acf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658211419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.658211419
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.144998081
Short name T486
Test name
Test status
Simulation time 152778374 ps
CPU time 3.75 seconds
Started May 16 01:28:10 PM PDT 24
Finished May 16 01:28:29 PM PDT 24
Peak memory 219676 kb
Host smart-fcad310d-df1d-487f-bcc3-54b4309888db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144998081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.144998081
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.170388919
Short name T819
Test name
Test status
Simulation time 10974555864 ps
CPU time 13.25 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:34 PM PDT 24
Peak memory 220808 kb
Host smart-3c439282-9d87-4c97-becb-55a33f654b69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=170388919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.170388919
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3445085912
Short name T150
Test name
Test status
Simulation time 223186841053 ps
CPU time 297.56 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:33:28 PM PDT 24
Peak memory 273580 kb
Host smart-a6ef970f-ede6-46b3-b39c-6e0e09014534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445085912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3445085912
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2839128528
Short name T846
Test name
Test status
Simulation time 6724012984 ps
CPU time 12.19 seconds
Started May 16 01:28:10 PM PDT 24
Finished May 16 01:28:37 PM PDT 24
Peak memory 216600 kb
Host smart-ec1bca53-3e67-44d6-9111-8c83f6eff2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839128528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2839128528
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.448126529
Short name T357
Test name
Test status
Simulation time 409366675 ps
CPU time 1.57 seconds
Started May 16 01:28:10 PM PDT 24
Finished May 16 01:28:27 PM PDT 24
Peak memory 207956 kb
Host smart-810a013e-1ffd-4d10-afc8-46ccae7bf0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448126529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.448126529
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2479388669
Short name T341
Test name
Test status
Simulation time 35336563 ps
CPU time 0.93 seconds
Started May 16 01:28:10 PM PDT 24
Finished May 16 01:28:26 PM PDT 24
Peak memory 206876 kb
Host smart-72e5183d-1c06-487c-b7b5-698177f0d302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479388669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2479388669
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.997048619
Short name T332
Test name
Test status
Simulation time 72258201 ps
CPU time 0.87 seconds
Started May 16 01:28:06 PM PDT 24
Finished May 16 01:28:22 PM PDT 24
Peak memory 205836 kb
Host smart-967ef5f3-9639-4e8d-8d8b-93d9a6a2925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997048619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.997048619
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3881433699
Short name T551
Test name
Test status
Simulation time 19625768933 ps
CPU time 17.2 seconds
Started May 16 01:28:10 PM PDT 24
Finished May 16 01:28:42 PM PDT 24
Peak memory 219288 kb
Host smart-24389a3c-a178-4656-8a8b-f9b4f3b421b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881433699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3881433699
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1793224387
Short name T330
Test name
Test status
Simulation time 73519309 ps
CPU time 0.71 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:28:30 PM PDT 24
Peak memory 205348 kb
Host smart-14aaa70c-061d-46b2-8ae5-202630587107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793224387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1793224387
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4082719745
Short name T95
Test name
Test status
Simulation time 1086789608 ps
CPU time 10.97 seconds
Started May 16 01:28:14 PM PDT 24
Finished May 16 01:28:38 PM PDT 24
Peak memory 218868 kb
Host smart-17f85eab-9a4b-4b81-b6c5-5d4d2ad62319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082719745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4082719745
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.666078815
Short name T652
Test name
Test status
Simulation time 25958986 ps
CPU time 0.8 seconds
Started May 16 01:28:19 PM PDT 24
Finished May 16 01:28:34 PM PDT 24
Peak memory 206368 kb
Host smart-67fd8973-431d-489b-8081-31d455ae8c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666078815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.666078815
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2234243140
Short name T82
Test name
Test status
Simulation time 72794276093 ps
CPU time 257.13 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:32:47 PM PDT 24
Peak memory 257420 kb
Host smart-688041fa-241c-45cb-808a-33bb341e3d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234243140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2234243140
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.287733821
Short name T214
Test name
Test status
Simulation time 100550796545 ps
CPU time 261.93 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:32:52 PM PDT 24
Peak memory 255028 kb
Host smart-27a5e80f-b192-4263-a79a-52554a34cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287733821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.287733821
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3205129356
Short name T276
Test name
Test status
Simulation time 10880964441 ps
CPU time 88.61 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:29:58 PM PDT 24
Peak memory 251760 kb
Host smart-6bbe12e8-1682-47dc-8437-5abac225778f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205129356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3205129356
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3392697707
Short name T295
Test name
Test status
Simulation time 338237892 ps
CPU time 10.79 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:28:41 PM PDT 24
Peak memory 224540 kb
Host smart-7b725aab-9322-4af0-b62e-eebb8f9dc95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392697707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3392697707
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2336892080
Short name T715
Test name
Test status
Simulation time 479033882 ps
CPU time 2.09 seconds
Started May 16 01:28:14 PM PDT 24
Finished May 16 01:28:30 PM PDT 24
Peak memory 216148 kb
Host smart-8de2d19d-18ea-49b7-8c67-c02c9bbe9e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336892080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2336892080
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.563137989
Short name T642
Test name
Test status
Simulation time 3244066443 ps
CPU time 15.25 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:28:44 PM PDT 24
Peak memory 233172 kb
Host smart-4796e34a-f1d7-4060-8559-7ec272d7db05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563137989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.563137989
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3122046943
Short name T110
Test name
Test status
Simulation time 3217583599 ps
CPU time 10.29 seconds
Started May 16 01:28:15 PM PDT 24
Finished May 16 01:28:38 PM PDT 24
Peak memory 224664 kb
Host smart-c51d92b7-0475-4d3a-bcc4-be62f770c601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122046943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3122046943
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3078163169
Short name T836
Test name
Test status
Simulation time 11312575880 ps
CPU time 10.97 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:28:41 PM PDT 24
Peak memory 235428 kb
Host smart-64c8ab88-d3a0-406d-bca2-cbed9811cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078163169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3078163169
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3450963667
Short name T855
Test name
Test status
Simulation time 988768818 ps
CPU time 5.88 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:28:35 PM PDT 24
Peak memory 222268 kb
Host smart-690fc9ac-9be2-418a-80c7-8ce85a0fc02b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3450963667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3450963667
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1507607381
Short name T460
Test name
Test status
Simulation time 16105687826 ps
CPU time 128.28 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:30:37 PM PDT 24
Peak memory 249380 kb
Host smart-78e90f2f-43c9-4870-8573-b180a2fe7c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507607381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1507607381
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2751682939
Short name T600
Test name
Test status
Simulation time 10427354343 ps
CPU time 26.85 seconds
Started May 16 01:28:14 PM PDT 24
Finished May 16 01:28:54 PM PDT 24
Peak memory 216500 kb
Host smart-1ae3649c-b0ba-4e46-8b65-f6ee75b88c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751682939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2751682939
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2362542864
Short name T734
Test name
Test status
Simulation time 1826403058 ps
CPU time 10.23 seconds
Started May 16 01:28:15 PM PDT 24
Finished May 16 01:28:38 PM PDT 24
Peak memory 216400 kb
Host smart-cdff74e8-6544-439b-a388-64115c775848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362542864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2362542864
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3881429264
Short name T667
Test name
Test status
Simulation time 554820359 ps
CPU time 8.77 seconds
Started May 16 01:28:18 PM PDT 24
Finished May 16 01:28:40 PM PDT 24
Peak memory 217796 kb
Host smart-c6f41b15-e93a-46ab-b6f9-496744132bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881429264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3881429264
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2505683218
Short name T442
Test name
Test status
Simulation time 37608707 ps
CPU time 0.81 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:28:31 PM PDT 24
Peak memory 205852 kb
Host smart-a1397ecf-e362-4d7b-bf4c-b1e705bad9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505683218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2505683218
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.190659192
Short name T620
Test name
Test status
Simulation time 10721438737 ps
CPU time 31.87 seconds
Started May 16 01:28:14 PM PDT 24
Finished May 16 01:28:59 PM PDT 24
Peak memory 218320 kb
Host smart-eb8251b9-5bcf-4f0d-bbe7-df2d82b40bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190659192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.190659192
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4258729825
Short name T532
Test name
Test status
Simulation time 39480851 ps
CPU time 0.72 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:28:30 PM PDT 24
Peak memory 204744 kb
Host smart-867b267b-c81a-4784-bbcc-cb8d6ac9cb1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258729825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4258729825
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3346785447
Short name T582
Test name
Test status
Simulation time 243859172 ps
CPU time 5.58 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:28:36 PM PDT 24
Peak memory 234460 kb
Host smart-6d2ad395-9bee-4c60-b003-f3dba60cddce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346785447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3346785447
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.55897845
Short name T408
Test name
Test status
Simulation time 49696382 ps
CPU time 0.75 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:28:31 PM PDT 24
Peak memory 205340 kb
Host smart-d5e077cd-23ce-4fb6-9f35-ec800673810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55897845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.55897845
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3655627214
Short name T241
Test name
Test status
Simulation time 8290127318 ps
CPU time 51.11 seconds
Started May 16 01:28:22 PM PDT 24
Finished May 16 01:29:25 PM PDT 24
Peak memory 250884 kb
Host smart-4ca35d20-a925-4441-9f34-f57ce2939680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655627214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3655627214
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2161318567
Short name T21
Test name
Test status
Simulation time 6621702359 ps
CPU time 32.52 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:29:02 PM PDT 24
Peak memory 224784 kb
Host smart-3274242d-53cc-4d11-aa9e-af22cd48c130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161318567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2161318567
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3987368948
Short name T748
Test name
Test status
Simulation time 15005690134 ps
CPU time 108.78 seconds
Started May 16 01:28:14 PM PDT 24
Finished May 16 01:30:16 PM PDT 24
Peak memory 247972 kb
Host smart-f5c5d240-26ee-4dcf-b089-7bce92acb29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987368948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3987368948
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.419065484
Short name T512
Test name
Test status
Simulation time 2368427867 ps
CPU time 42.81 seconds
Started May 16 01:28:13 PM PDT 24
Finished May 16 01:29:10 PM PDT 24
Peak memory 232908 kb
Host smart-94083cb9-e459-4c5a-9540-c2336b438efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419065484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.419065484
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1699363782
Short name T673
Test name
Test status
Simulation time 1337444286 ps
CPU time 6.56 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:28:35 PM PDT 24
Peak memory 233436 kb
Host smart-20635dfe-2f00-4c8a-b67c-dcc13b120123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699363782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1699363782
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.591565823
Short name T851
Test name
Test status
Simulation time 1202363948 ps
CPU time 10.6 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:28:41 PM PDT 24
Peak memory 218544 kb
Host smart-aef1a075-d88d-4ece-aa53-bdc7a8974402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591565823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.591565823
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2912260353
Short name T664
Test name
Test status
Simulation time 2697273224 ps
CPU time 8.49 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:28:38 PM PDT 24
Peak memory 224608 kb
Host smart-7c0e1daa-941b-407d-a3c2-951fe81b1192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912260353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2912260353
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.80189958
Short name T767
Test name
Test status
Simulation time 21884653959 ps
CPU time 15.26 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 220776 kb
Host smart-8f4daf22-ecfa-4ff2-a47d-680d268fe657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80189958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.80189958
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1171709278
Short name T13
Test name
Test status
Simulation time 467663472 ps
CPU time 7.92 seconds
Started May 16 01:28:19 PM PDT 24
Finished May 16 01:28:41 PM PDT 24
Peak memory 221652 kb
Host smart-7818c722-3ce7-4db4-8ebb-9876fa3d2e28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1171709278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1171709278
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3561498945
Short name T963
Test name
Test status
Simulation time 476070398 ps
CPU time 3.34 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:28:33 PM PDT 24
Peak memory 222532 kb
Host smart-8dd26fc9-b485-4aee-b724-521469003c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561498945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3561498945
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3355789936
Short name T889
Test name
Test status
Simulation time 8334334694 ps
CPU time 26.69 seconds
Started May 16 01:28:15 PM PDT 24
Finished May 16 01:28:55 PM PDT 24
Peak memory 216516 kb
Host smart-b69d9ae0-8b57-4c98-841c-bc5cd4aa2d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355789936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3355789936
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1614758991
Short name T347
Test name
Test status
Simulation time 2955887181 ps
CPU time 10.5 seconds
Started May 16 01:28:21 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 216560 kb
Host smart-9de88ac4-4189-489c-8f33-fd30013fc34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614758991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1614758991
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3042087300
Short name T145
Test name
Test status
Simulation time 204724701 ps
CPU time 9.88 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:28:39 PM PDT 24
Peak memory 216620 kb
Host smart-c9fa2656-3b84-4b81-bdbd-3f3bf42f9363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042087300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3042087300
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3077828012
Short name T939
Test name
Test status
Simulation time 64332001 ps
CPU time 0.84 seconds
Started May 16 01:28:21 PM PDT 24
Finished May 16 01:28:35 PM PDT 24
Peak memory 205824 kb
Host smart-7a436c23-16a5-4b30-829c-882af19b6dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077828012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3077828012
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2303937568
Short name T717
Test name
Test status
Simulation time 4974672510 ps
CPU time 10.2 seconds
Started May 16 01:28:19 PM PDT 24
Finished May 16 01:28:43 PM PDT 24
Peak memory 239928 kb
Host smart-dcce7553-ce09-4ad4-bb66-fa42a0290606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303937568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2303937568
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4112809365
Short name T478
Test name
Test status
Simulation time 18344460 ps
CPU time 0.72 seconds
Started May 16 01:28:30 PM PDT 24
Finished May 16 01:28:43 PM PDT 24
Peak memory 205352 kb
Host smart-8efcde9f-834b-473f-b762-d8b9019b704b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112809365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4112809365
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1196706860
Short name T548
Test name
Test status
Simulation time 109728477 ps
CPU time 2.44 seconds
Started May 16 01:28:19 PM PDT 24
Finished May 16 01:28:35 PM PDT 24
Peak memory 216180 kb
Host smart-c0acfaa1-3a65-4804-b592-e731da78417c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196706860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1196706860
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2105656690
Short name T905
Test name
Test status
Simulation time 13350349 ps
CPU time 0.73 seconds
Started May 16 01:28:19 PM PDT 24
Finished May 16 01:28:34 PM PDT 24
Peak memory 206460 kb
Host smart-5bb29149-029e-4902-b8bc-3e92ce17c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105656690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2105656690
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1098832615
Short name T232
Test name
Test status
Simulation time 40941876213 ps
CPU time 132.55 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:30:56 PM PDT 24
Peak memory 253364 kb
Host smart-93dd75eb-ba75-49b5-b24d-6d82af237f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098832615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1098832615
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.262837268
Short name T288
Test name
Test status
Simulation time 114586612722 ps
CPU time 202.35 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:32:04 PM PDT 24
Peak memory 250264 kb
Host smart-fe290c86-3cc5-4fb4-89a2-2d324000f6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262837268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.262837268
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3806417216
Short name T246
Test name
Test status
Simulation time 9688145080 ps
CPU time 96.52 seconds
Started May 16 01:28:28 PM PDT 24
Finished May 16 01:30:16 PM PDT 24
Peak memory 250256 kb
Host smart-5d2b72ac-66b9-4075-aa9c-5eec501cb9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806417216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3806417216
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.709050665
Short name T451
Test name
Test status
Simulation time 1243385597 ps
CPU time 9.78 seconds
Started May 16 01:28:22 PM PDT 24
Finished May 16 01:28:44 PM PDT 24
Peak memory 224560 kb
Host smart-5be46b20-265b-46dc-80e4-beb547187cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709050665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.709050665
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3057279190
Short name T754
Test name
Test status
Simulation time 228711588 ps
CPU time 5.73 seconds
Started May 16 01:28:18 PM PDT 24
Finished May 16 01:28:37 PM PDT 24
Peak memory 233780 kb
Host smart-e9b07a87-fa31-4215-b907-7ba2897fb201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057279190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3057279190
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.702899030
Short name T263
Test name
Test status
Simulation time 9881549533 ps
CPU time 92.28 seconds
Started May 16 01:28:18 PM PDT 24
Finished May 16 01:30:04 PM PDT 24
Peak memory 233980 kb
Host smart-1be63e77-8a98-46f1-b5e4-2ba3c8f64dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702899030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.702899030
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3036220957
Short name T910
Test name
Test status
Simulation time 634276199 ps
CPU time 5.69 seconds
Started May 16 01:28:19 PM PDT 24
Finished May 16 01:28:39 PM PDT 24
Peak memory 224512 kb
Host smart-8af0e421-1c84-476c-8f01-36af2c2cac92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036220957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3036220957
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2918818639
Short name T427
Test name
Test status
Simulation time 361244903 ps
CPU time 5.47 seconds
Started May 16 01:28:19 PM PDT 24
Finished May 16 01:28:38 PM PDT 24
Peak memory 229456 kb
Host smart-b6aea20b-0732-448c-af71-6d1f429cfe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918818639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2918818639
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1585714879
Short name T456
Test name
Test status
Simulation time 2045955502 ps
CPU time 17.03 seconds
Started May 16 01:28:18 PM PDT 24
Finished May 16 01:28:49 PM PDT 24
Peak memory 222220 kb
Host smart-1db63664-71bb-415a-8e8c-ddd9679cb341
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1585714879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1585714879
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.337300980
Short name T91
Test name
Test status
Simulation time 31409877910 ps
CPU time 175.86 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:31:37 PM PDT 24
Peak memory 273960 kb
Host smart-ab533ac9-9ddf-4580-bfdb-000911dc36aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337300980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.337300980
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.281466866
Short name T576
Test name
Test status
Simulation time 10855345085 ps
CPU time 46.81 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:29:17 PM PDT 24
Peak memory 216516 kb
Host smart-193e3562-3a14-4388-af24-40230372a672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281466866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.281466866
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1147460829
Short name T670
Test name
Test status
Simulation time 3811986855 ps
CPU time 3.32 seconds
Started May 16 01:28:17 PM PDT 24
Finished May 16 01:28:34 PM PDT 24
Peak memory 207712 kb
Host smart-e812f6f3-5003-4831-8ddc-1ab3bd3314ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147460829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1147460829
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2594996741
Short name T636
Test name
Test status
Simulation time 79453465 ps
CPU time 0.89 seconds
Started May 16 01:28:18 PM PDT 24
Finished May 16 01:28:32 PM PDT 24
Peak memory 207332 kb
Host smart-4b5b1ff6-297c-4b04-afce-ce21f1ecffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594996741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2594996741
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2012079035
Short name T604
Test name
Test status
Simulation time 160972966 ps
CPU time 0.83 seconds
Started May 16 01:28:16 PM PDT 24
Finished May 16 01:28:31 PM PDT 24
Peak memory 205824 kb
Host smart-b5081151-b04b-4253-ba80-57e4cba90068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012079035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2012079035
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1022289948
Short name T810
Test name
Test status
Simulation time 275234977 ps
CPU time 6.36 seconds
Started May 16 01:28:19 PM PDT 24
Finished May 16 01:28:39 PM PDT 24
Peak memory 239248 kb
Host smart-2c1b2af9-d4d2-4de6-85d8-20d0f698c7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022289948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1022289948
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.963505776
Short name T489
Test name
Test status
Simulation time 14571540 ps
CPU time 0.74 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 205572 kb
Host smart-ac680b97-99a2-480f-8728-7bf98f4b3ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963505776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.963505776
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2997659236
Short name T391
Test name
Test status
Simulation time 98083116 ps
CPU time 1.96 seconds
Started May 16 01:28:28 PM PDT 24
Finished May 16 01:28:43 PM PDT 24
Peak memory 216124 kb
Host smart-6b8e2967-9e4d-41fd-82f1-f6369bec7445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997659236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2997659236
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1611512668
Short name T633
Test name
Test status
Simulation time 72427795 ps
CPU time 0.8 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:42 PM PDT 24
Peak memory 206472 kb
Host smart-d04c77c8-1c96-4d03-b656-9f9b918a30ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611512668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1611512668
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2523730294
Short name T513
Test name
Test status
Simulation time 1351826819 ps
CPU time 8.38 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:52 PM PDT 24
Peak memory 224564 kb
Host smart-5727fec2-4a1c-478e-86fe-d3774e7baffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523730294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2523730294
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1312696892
Short name T248
Test name
Test status
Simulation time 228964608372 ps
CPU time 361.91 seconds
Started May 16 01:28:27 PM PDT 24
Finished May 16 01:34:41 PM PDT 24
Peak memory 257228 kb
Host smart-84d6ab83-7105-43f5-9ef6-f2f49a9a3531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312696892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1312696892
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1443561058
Short name T271
Test name
Test status
Simulation time 102386631298 ps
CPU time 191.42 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:31:53 PM PDT 24
Peak memory 250440 kb
Host smart-dd78c671-2f05-467d-9102-77fa70389076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443561058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1443561058
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.453152436
Short name T749
Test name
Test status
Simulation time 234986459 ps
CPU time 7.84 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:52 PM PDT 24
Peak memory 240972 kb
Host smart-cb5c7b0f-50ab-4cc1-ae6b-d3ac33ef0614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453152436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.453152436
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1148325878
Short name T802
Test name
Test status
Simulation time 1832872108 ps
CPU time 6.22 seconds
Started May 16 01:28:28 PM PDT 24
Finished May 16 01:28:46 PM PDT 24
Peak memory 224492 kb
Host smart-fdff0d4a-9202-4df2-af2c-a63ffee44ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148325878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1148325878
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.119151106
Short name T270
Test name
Test status
Simulation time 27271292096 ps
CPU time 29.89 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:29:14 PM PDT 24
Peak memory 237188 kb
Host smart-56ff129f-dd73-4d30-8b74-731e1494e2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119151106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.119151106
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3932107017
Short name T970
Test name
Test status
Simulation time 4351686214 ps
CPU time 13.72 seconds
Started May 16 01:28:27 PM PDT 24
Finished May 16 01:28:53 PM PDT 24
Peak memory 224564 kb
Host smart-300dcbb2-5366-44c2-b97e-3fbda66f858b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932107017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3932107017
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1416036085
Short name T200
Test name
Test status
Simulation time 5049765523 ps
CPU time 5.92 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:50 PM PDT 24
Peak memory 233464 kb
Host smart-74cee32d-6e95-4ccb-a615-c346e83d5cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416036085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1416036085
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2658297817
Short name T156
Test name
Test status
Simulation time 379503066 ps
CPU time 4.07 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:46 PM PDT 24
Peak memory 218812 kb
Host smart-83b9a6f5-c9a5-4253-9111-0b69f588945c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2658297817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2658297817
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.961115103
Short name T747
Test name
Test status
Simulation time 42265514 ps
CPU time 0.92 seconds
Started May 16 01:28:28 PM PDT 24
Finished May 16 01:28:41 PM PDT 24
Peak memory 206860 kb
Host smart-03391f99-b969-425c-81ae-d34f8e3fd3f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961115103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.961115103
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3906287004
Short name T755
Test name
Test status
Simulation time 17455474 ps
CPU time 0.75 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:42 PM PDT 24
Peak memory 205560 kb
Host smart-0b4ad08f-bf54-4d86-ae0a-4f8934980c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906287004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3906287004
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3462404035
Short name T857
Test name
Test status
Simulation time 908324063 ps
CPU time 5.14 seconds
Started May 16 01:28:27 PM PDT 24
Finished May 16 01:28:44 PM PDT 24
Peak memory 216460 kb
Host smart-9acca610-2b5e-4c95-9baa-39d6004e4f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462404035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3462404035
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1025002166
Short name T172
Test name
Test status
Simulation time 1227188480 ps
CPU time 6.23 seconds
Started May 16 01:28:28 PM PDT 24
Finished May 16 01:28:47 PM PDT 24
Peak memory 216480 kb
Host smart-b86b95f4-df52-418c-980a-c5cf8b99b3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025002166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1025002166
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2421939484
Short name T339
Test name
Test status
Simulation time 55063035 ps
CPU time 0.7 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:44 PM PDT 24
Peak memory 205472 kb
Host smart-710097f6-45a6-4c04-8e4d-93b807656317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421939484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2421939484
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4215703176
Short name T738
Test name
Test status
Simulation time 12659645383 ps
CPU time 12.28 seconds
Started May 16 01:28:28 PM PDT 24
Finished May 16 01:28:52 PM PDT 24
Peak memory 234236 kb
Host smart-91da6b19-3f4d-4d8c-9e00-59ed51eadc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215703176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4215703176
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3442587317
Short name T668
Test name
Test status
Simulation time 23665746 ps
CPU time 0.71 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 205368 kb
Host smart-e2bbbf41-cb5f-4050-890a-b1824ae7047f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442587317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3442587317
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2507026515
Short name T109
Test name
Test status
Simulation time 59251847 ps
CPU time 2.27 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:44 PM PDT 24
Peak memory 221132 kb
Host smart-5d90a0ff-8888-4ce4-a512-5374d5afbb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507026515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2507026515
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3002641016
Short name T776
Test name
Test status
Simulation time 40105310 ps
CPU time 0.85 seconds
Started May 16 01:28:31 PM PDT 24
Finished May 16 01:28:44 PM PDT 24
Peak memory 206776 kb
Host smart-e3726079-c107-4a87-99fa-332ed8caee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002641016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3002641016
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3742507539
Short name T33
Test name
Test status
Simulation time 37738560041 ps
CPU time 274.26 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:33:18 PM PDT 24
Peak memory 252800 kb
Host smart-7ba47ec5-984f-4f58-8e1f-8bcd7b4cd013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742507539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3742507539
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.54124351
Short name T222
Test name
Test status
Simulation time 28322675411 ps
CPU time 303.33 seconds
Started May 16 01:28:34 PM PDT 24
Finished May 16 01:33:49 PM PDT 24
Peak memory 271992 kb
Host smart-8eacf22b-5d03-430c-8c87-254b846f00b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54124351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.54124351
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1098789158
Short name T247
Test name
Test status
Simulation time 124341890669 ps
CPU time 392.02 seconds
Started May 16 01:28:28 PM PDT 24
Finished May 16 01:35:12 PM PDT 24
Peak memory 257580 kb
Host smart-20cfffa5-cd51-4e9c-a100-aa915c40f3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098789158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1098789158
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2639339163
Short name T743
Test name
Test status
Simulation time 3788489187 ps
CPU time 45.74 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:29:30 PM PDT 24
Peak memory 232720 kb
Host smart-67c32ccd-00a4-445d-9aaa-676ee73f6851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639339163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2639339163
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2923907662
Short name T915
Test name
Test status
Simulation time 2690111731 ps
CPU time 4.88 seconds
Started May 16 01:28:27 PM PDT 24
Finished May 16 01:28:44 PM PDT 24
Peak memory 219564 kb
Host smart-e553e306-d0ee-434e-85b6-1f1436455b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923907662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2923907662
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.9621521
Short name T348
Test name
Test status
Simulation time 333606619 ps
CPU time 2.48 seconds
Started May 16 01:28:30 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 221516 kb
Host smart-b471f7bd-8264-47fc-a57f-0848c92852de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9621521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.9621521
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4051281679
Short name T381
Test name
Test status
Simulation time 208462422 ps
CPU time 4.73 seconds
Started May 16 01:28:31 PM PDT 24
Finished May 16 01:28:48 PM PDT 24
Peak memory 237452 kb
Host smart-5c6c20dd-5aec-4d41-aa95-5ef5fd1f3d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051281679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4051281679
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2545396654
Short name T880
Test name
Test status
Simulation time 1573164567 ps
CPU time 4.55 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:49 PM PDT 24
Peak memory 233700 kb
Host smart-90d75393-ed77-4ac8-b457-b9c6e5ff6339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545396654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2545396654
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1895181444
Short name T481
Test name
Test status
Simulation time 3559080823 ps
CPU time 11.03 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:53 PM PDT 24
Peak memory 223180 kb
Host smart-c33f8309-1138-4a69-9a05-e847fea50ad9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1895181444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1895181444
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1711696954
Short name T64
Test name
Test status
Simulation time 89183251 ps
CPU time 0.93 seconds
Started May 16 01:28:27 PM PDT 24
Finished May 16 01:28:40 PM PDT 24
Peak memory 205524 kb
Host smart-f2ee9de5-9388-4055-b469-b947489a83d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711696954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1711696954
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1313627635
Short name T462
Test name
Test status
Simulation time 3921955671 ps
CPU time 8.28 seconds
Started May 16 01:28:28 PM PDT 24
Finished May 16 01:28:48 PM PDT 24
Peak memory 216864 kb
Host smart-f8167747-063c-4567-8b14-f2cbb451042d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313627635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1313627635
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1735956349
Short name T52
Test name
Test status
Simulation time 854086288 ps
CPU time 6.24 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:48 PM PDT 24
Peak memory 216340 kb
Host smart-d99fb088-53b0-4e2f-b720-30cbac07b074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735956349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1735956349
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.4197386291
Short name T401
Test name
Test status
Simulation time 1869625044 ps
CPU time 3.38 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 216388 kb
Host smart-7f9bb4bb-8ab5-479f-a64b-f5ccac9b4512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197386291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4197386291
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2109066823
Short name T418
Test name
Test status
Simulation time 19580593 ps
CPU time 0.69 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:42 PM PDT 24
Peak memory 205496 kb
Host smart-2c183854-92b0-4428-9d25-85b55bffc35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109066823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2109066823
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2329018189
Short name T718
Test name
Test status
Simulation time 11403016164 ps
CPU time 20.68 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:29:02 PM PDT 24
Peak memory 240736 kb
Host smart-bb975dab-d76e-4224-9379-79a2ea45dd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329018189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2329018189
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.261054748
Short name T675
Test name
Test status
Simulation time 39996954 ps
CPU time 0.79 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 204780 kb
Host smart-3042e61e-583c-4ecf-b692-eefbdd9ac859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261054748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.261054748
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1284522624
Short name T380
Test name
Test status
Simulation time 644970171 ps
CPU time 4.22 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:48 PM PDT 24
Peak memory 233512 kb
Host smart-e65ffae8-005c-4f9a-9d18-4aec02f3bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284522624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1284522624
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2794984859
Short name T22
Test name
Test status
Simulation time 25570060 ps
CPU time 0.76 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:42 PM PDT 24
Peak memory 206788 kb
Host smart-a29e97c7-8385-4276-b257-45d694b5c95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794984859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2794984859
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3760697967
Short name T545
Test name
Test status
Simulation time 3768602344 ps
CPU time 20.53 seconds
Started May 16 01:28:27 PM PDT 24
Finished May 16 01:28:59 PM PDT 24
Peak memory 237728 kb
Host smart-3ccd83e7-c3a4-4fc4-a8ef-8dd6de2f1e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760697967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3760697967
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1409514946
Short name T504
Test name
Test status
Simulation time 6829799998 ps
CPU time 11.58 seconds
Started May 16 01:28:34 PM PDT 24
Finished May 16 01:28:58 PM PDT 24
Peak memory 217512 kb
Host smart-d3cb11d6-9dea-4490-a898-d5f06561171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409514946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1409514946
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2776805128
Short name T294
Test name
Test status
Simulation time 1020615106 ps
CPU time 15.11 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:59 PM PDT 24
Peak memory 232640 kb
Host smart-1b989b27-e704-4436-8a09-521437fb7383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776805128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2776805128
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.34177772
Short name T400
Test name
Test status
Simulation time 552607533 ps
CPU time 6.52 seconds
Started May 16 01:28:27 PM PDT 24
Finished May 16 01:28:46 PM PDT 24
Peak memory 233484 kb
Host smart-2181d982-0dcd-49cf-8bcc-54118b42ee18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34177772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.34177772
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2550109366
Short name T936
Test name
Test status
Simulation time 52723836 ps
CPU time 2.68 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:44 PM PDT 24
Peak memory 232752 kb
Host smart-17189a8f-5188-4d48-b594-100476659024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550109366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2550109366
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3336564806
Short name T259
Test name
Test status
Simulation time 606110910 ps
CPU time 6.03 seconds
Started May 16 01:28:33 PM PDT 24
Finished May 16 01:28:51 PM PDT 24
Peak memory 233384 kb
Host smart-7da99a6f-e50f-44d3-989d-2ae1afde6e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336564806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3336564806
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2623459006
Short name T198
Test name
Test status
Simulation time 2540370641 ps
CPU time 9.48 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:53 PM PDT 24
Peak memory 233964 kb
Host smart-5727801e-bdf9-404c-b102-c68c5b530f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623459006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2623459006
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4240551950
Short name T350
Test name
Test status
Simulation time 1439894443 ps
CPU time 7.35 seconds
Started May 16 01:28:34 PM PDT 24
Finished May 16 01:28:53 PM PDT 24
Peak memory 219304 kb
Host smart-b7a9f7d5-0338-4b0e-949f-29f6ed667a36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4240551950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4240551950
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1733851704
Short name T694
Test name
Test status
Simulation time 53214003233 ps
CPU time 430.07 seconds
Started May 16 01:28:31 PM PDT 24
Finished May 16 01:35:53 PM PDT 24
Peak memory 251416 kb
Host smart-2ad25b87-dd23-4c8a-b88d-98142e12df2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733851704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1733851704
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.57240633
Short name T92
Test name
Test status
Simulation time 2725204622 ps
CPU time 22.8 seconds
Started May 16 01:28:33 PM PDT 24
Finished May 16 01:29:07 PM PDT 24
Peak memory 216492 kb
Host smart-ef8f321f-b8b1-4b94-8803-3d692932da5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57240633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.57240633
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3898439628
Short name T762
Test name
Test status
Simulation time 2938162239 ps
CPU time 11.94 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:56 PM PDT 24
Peak memory 216572 kb
Host smart-6cc70b0d-d378-43d0-ad25-8eeb6d2644a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898439628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3898439628
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.267104545
Short name T387
Test name
Test status
Simulation time 58162232 ps
CPU time 1.16 seconds
Started May 16 01:28:29 PM PDT 24
Finished May 16 01:28:43 PM PDT 24
Peak memory 207924 kb
Host smart-a3f26621-0989-4ea0-9e88-aec9ca013a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267104545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.267104545
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3387979154
Short name T448
Test name
Test status
Simulation time 827328144 ps
CPU time 1 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 206768 kb
Host smart-a204266f-1ca6-4da1-8302-a8d8c1a22aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387979154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3387979154
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.156111768
Short name T868
Test name
Test status
Simulation time 1069007124 ps
CPU time 3.93 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:48 PM PDT 24
Peak memory 218788 kb
Host smart-4717dc8a-927f-4ca2-93fa-721617134122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156111768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.156111768
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.399468088
Short name T720
Test name
Test status
Simulation time 62230995 ps
CPU time 0.72 seconds
Started May 16 01:28:45 PM PDT 24
Finished May 16 01:28:58 PM PDT 24
Peak memory 205368 kb
Host smart-87b7649e-4ae4-42a4-a2c3-02cf46a80c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399468088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.399468088
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1555637759
Short name T860
Test name
Test status
Simulation time 2745566648 ps
CPU time 11.31 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:29:04 PM PDT 24
Peak memory 220700 kb
Host smart-8c95d48e-91aa-4561-a2f9-b536ea8b5564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555637759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1555637759
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2919218892
Short name T307
Test name
Test status
Simulation time 17280632 ps
CPU time 0.81 seconds
Started May 16 01:28:34 PM PDT 24
Finished May 16 01:28:48 PM PDT 24
Peak memory 205424 kb
Host smart-76616cd9-6a52-42d8-86d8-def070511361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919218892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2919218892
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3713560861
Short name T852
Test name
Test status
Simulation time 15304844518 ps
CPU time 59.56 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:29:52 PM PDT 24
Peak memory 240196 kb
Host smart-661df975-dab1-4169-8128-f6177a25ee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713560861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3713560861
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.319288698
Short name T275
Test name
Test status
Simulation time 32361116058 ps
CPU time 87.83 seconds
Started May 16 01:28:42 PM PDT 24
Finished May 16 01:30:22 PM PDT 24
Peak memory 250392 kb
Host smart-64ce7df0-b256-4eb9-9511-33ae12fa6772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319288698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.319288698
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3769790916
Short name T559
Test name
Test status
Simulation time 356247595 ps
CPU time 2.86 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:28:56 PM PDT 24
Peak memory 232672 kb
Host smart-7f593807-d7bb-4021-9c4d-68aa65f33106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769790916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3769790916
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3618179068
Short name T800
Test name
Test status
Simulation time 203020920 ps
CPU time 2.62 seconds
Started May 16 01:28:38 PM PDT 24
Finished May 16 01:28:54 PM PDT 24
Peak memory 218576 kb
Host smart-b8092ea7-6e57-4dce-80c1-782a3e7e2f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618179068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3618179068
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2142518804
Short name T189
Test name
Test status
Simulation time 55765139524 ps
CPU time 85.94 seconds
Started May 16 01:28:39 PM PDT 24
Finished May 16 01:30:18 PM PDT 24
Peak memory 240560 kb
Host smart-abb6776f-dde7-4dbd-be72-7ecbbc0451b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142518804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2142518804
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3408269947
Short name T588
Test name
Test status
Simulation time 361472772 ps
CPU time 2.54 seconds
Started May 16 01:28:33 PM PDT 24
Finished May 16 01:28:47 PM PDT 24
Peak memory 224548 kb
Host smart-3f30b626-8a10-4f35-8d22-28bf1e8c5c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408269947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3408269947
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.388902622
Short name T698
Test name
Test status
Simulation time 7096407995 ps
CPU time 9.64 seconds
Started May 16 01:28:31 PM PDT 24
Finished May 16 01:28:53 PM PDT 24
Peak memory 235516 kb
Host smart-97f616c4-d9b7-4e1c-bb79-a01d1a2898aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388902622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.388902622
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.867351870
Short name T38
Test name
Test status
Simulation time 3330199879 ps
CPU time 8.55 seconds
Started May 16 01:28:39 PM PDT 24
Finished May 16 01:29:00 PM PDT 24
Peak memory 223172 kb
Host smart-6c52d0c4-d281-409f-99b8-c8e8d382117a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=867351870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.867351870
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2527867821
Short name T692
Test name
Test status
Simulation time 27141111540 ps
CPU time 29.81 seconds
Started May 16 01:28:35 PM PDT 24
Finished May 16 01:29:17 PM PDT 24
Peak memory 216500 kb
Host smart-a46fb09b-f841-46a9-84b6-1255a304ce35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527867821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2527867821
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1093249581
Short name T683
Test name
Test status
Simulation time 359759363 ps
CPU time 2.18 seconds
Started May 16 01:28:34 PM PDT 24
Finished May 16 01:28:49 PM PDT 24
Peak memory 216352 kb
Host smart-424b21a1-d452-4dce-9adc-90c1c46b70a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093249581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1093249581
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2557753650
Short name T305
Test name
Test status
Simulation time 111468441 ps
CPU time 1.02 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 207912 kb
Host smart-25f8a0b4-1d59-4c58-b0c7-7020472a56f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557753650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2557753650
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3935483296
Short name T395
Test name
Test status
Simulation time 42229244 ps
CPU time 0.85 seconds
Started May 16 01:28:32 PM PDT 24
Finished May 16 01:28:45 PM PDT 24
Peak memory 205856 kb
Host smart-708cc397-4956-446e-9a11-3eb723406f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935483296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3935483296
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2870871696
Short name T204
Test name
Test status
Simulation time 2550367914 ps
CPU time 6.85 seconds
Started May 16 01:28:39 PM PDT 24
Finished May 16 01:28:58 PM PDT 24
Peak memory 217448 kb
Host smart-3165e5ed-4b44-44e3-b9ba-0a1b01d67cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870871696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2870871696
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4243645897
Short name T804
Test name
Test status
Simulation time 21876636 ps
CPU time 0.75 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:50 PM PDT 24
Peak memory 205364 kb
Host smart-c635ae08-7bec-44f5-832a-40a80b712e6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243645897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
243645897
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2605939196
Short name T737
Test name
Test status
Simulation time 424240145 ps
CPU time 2.28 seconds
Started May 16 01:26:33 PM PDT 24
Finished May 16 01:26:51 PM PDT 24
Peak memory 217836 kb
Host smart-5a38e435-b58c-4442-a1c7-6670ae8c32c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605939196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2605939196
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2878789028
Short name T707
Test name
Test status
Simulation time 14175673 ps
CPU time 0.75 seconds
Started May 16 01:26:45 PM PDT 24
Finished May 16 01:26:59 PM PDT 24
Peak memory 206432 kb
Host smart-e03e3b5e-7247-4101-9f86-43140de8cfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878789028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2878789028
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.41622415
Short name T949
Test name
Test status
Simulation time 87750612562 ps
CPU time 610.76 seconds
Started May 16 01:26:43 PM PDT 24
Finished May 16 01:37:08 PM PDT 24
Peak memory 264640 kb
Host smart-e8302a90-97ef-4d57-966e-1ef69e538e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41622415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.41622415
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3954245419
Short name T40
Test name
Test status
Simulation time 1615184160 ps
CPU time 2.34 seconds
Started May 16 01:26:50 PM PDT 24
Finished May 16 01:27:09 PM PDT 24
Peak memory 217800 kb
Host smart-1cd47951-bab6-4edb-9d81-4a967707e865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954245419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3954245419
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3575108418
Short name T867
Test name
Test status
Simulation time 4703953973 ps
CPU time 21.64 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:27:12 PM PDT 24
Peak memory 217464 kb
Host smart-6e207987-f415-4ba1-8916-075e0b9757bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575108418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3575108418
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2219366771
Short name T292
Test name
Test status
Simulation time 1401745754 ps
CPU time 17.66 seconds
Started May 16 01:26:37 PM PDT 24
Finished May 16 01:27:10 PM PDT 24
Peak memory 232220 kb
Host smart-1829d628-883e-449e-9d84-b18965ab47c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219366771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2219366771
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3769731407
Short name T471
Test name
Test status
Simulation time 2471955267 ps
CPU time 7.25 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:11 PM PDT 24
Peak memory 217424 kb
Host smart-07dc4654-54ee-426f-91e7-350eb3fe5b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769731407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3769731407
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.92165381
Short name T262
Test name
Test status
Simulation time 995675937 ps
CPU time 9.39 seconds
Started May 16 01:26:36 PM PDT 24
Finished May 16 01:27:00 PM PDT 24
Peak memory 240912 kb
Host smart-740fcf6a-5f13-41d7-a928-ac6e2e15b588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92165381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.92165381
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.437689428
Short name T854
Test name
Test status
Simulation time 30309953 ps
CPU time 1.04 seconds
Started May 16 01:26:26 PM PDT 24
Finished May 16 01:26:44 PM PDT 24
Peak memory 217960 kb
Host smart-a1adbcfa-56b4-4a64-845e-cf78aaea4306
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437689428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.437689428
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.120752733
Short name T215
Test name
Test status
Simulation time 18160451544 ps
CPU time 15.2 seconds
Started May 16 01:26:46 PM PDT 24
Finished May 16 01:27:15 PM PDT 24
Peak memory 234004 kb
Host smart-66701ff4-7ea8-4a8e-ab71-afaf7a883a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120752733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
120752733
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3847995420
Short name T479
Test name
Test status
Simulation time 1463267884 ps
CPU time 2.73 seconds
Started May 16 01:26:51 PM PDT 24
Finished May 16 01:27:10 PM PDT 24
Peak memory 218720 kb
Host smart-e2c9b78e-afb2-446e-ac2d-21fe33b8ea0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847995420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3847995420
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2518553433
Short name T565
Test name
Test status
Simulation time 4163868942 ps
CPU time 11.27 seconds
Started May 16 01:26:37 PM PDT 24
Finished May 16 01:27:03 PM PDT 24
Peak memory 219796 kb
Host smart-03183d00-819e-42fb-ae6d-e096f4e4b68f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2518553433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2518553433
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4199519758
Short name T68
Test name
Test status
Simulation time 58035096 ps
CPU time 1.07 seconds
Started May 16 01:26:37 PM PDT 24
Finished May 16 01:26:53 PM PDT 24
Peak memory 235292 kb
Host smart-fb92ea2e-6bc4-4eaa-a2ac-6afe903d77e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199519758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4199519758
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1069075529
Short name T562
Test name
Test status
Simulation time 4338351062 ps
CPU time 52.35 seconds
Started May 16 01:26:33 PM PDT 24
Finished May 16 01:27:40 PM PDT 24
Peak memory 235720 kb
Host smart-0b727225-d11c-41b9-92c8-210ba0c87d3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069075529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1069075529
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.653894529
Short name T659
Test name
Test status
Simulation time 47062692667 ps
CPU time 61.56 seconds
Started May 16 01:26:38 PM PDT 24
Finished May 16 01:27:55 PM PDT 24
Peak memory 216592 kb
Host smart-1b5d48a5-c490-4ce9-b4d3-a21b7ff69f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653894529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.653894529
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3588367740
Short name T827
Test name
Test status
Simulation time 2200279229 ps
CPU time 4.85 seconds
Started May 16 01:26:29 PM PDT 24
Finished May 16 01:26:50 PM PDT 24
Peak memory 216492 kb
Host smart-476a5c22-de2b-46a6-862a-c36fe96ddea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588367740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3588367740
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2431701305
Short name T535
Test name
Test status
Simulation time 817712293 ps
CPU time 9.43 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:26:59 PM PDT 24
Peak memory 216452 kb
Host smart-fd4d72b2-6add-4389-9724-adf876e1b348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431701305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2431701305
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.641882317
Short name T722
Test name
Test status
Simulation time 74698196 ps
CPU time 0.86 seconds
Started May 16 01:26:44 PM PDT 24
Finished May 16 01:26:59 PM PDT 24
Peak memory 205836 kb
Host smart-76ab8173-e7a3-4325-9178-e61e367e60ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641882317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.641882317
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4292473591
Short name T453
Test name
Test status
Simulation time 84586429 ps
CPU time 2.54 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:52 PM PDT 24
Peak memory 221088 kb
Host smart-7a70ab63-9c07-42ca-b854-3ad4c7ca84c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292473591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4292473591
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.870911875
Short name T893
Test name
Test status
Simulation time 94290551 ps
CPU time 0.74 seconds
Started May 16 01:28:41 PM PDT 24
Finished May 16 01:28:54 PM PDT 24
Peak memory 204792 kb
Host smart-8d10d44a-32bf-450d-9887-a85b5da5188f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870911875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.870911875
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1008519280
Short name T79
Test name
Test status
Simulation time 4187970185 ps
CPU time 12.88 seconds
Started May 16 01:28:45 PM PDT 24
Finished May 16 01:29:10 PM PDT 24
Peak memory 234532 kb
Host smart-07c28b62-c5c6-42eb-baa1-38d05510ba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008519280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1008519280
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1939212789
Short name T373
Test name
Test status
Simulation time 16430982 ps
CPU time 0.74 seconds
Started May 16 01:28:39 PM PDT 24
Finished May 16 01:28:53 PM PDT 24
Peak memory 205416 kb
Host smart-099465a8-da6e-47e3-ad5b-acb36c5d8d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939212789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1939212789
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.142502503
Short name T787
Test name
Test status
Simulation time 448001969243 ps
CPU time 229.44 seconds
Started May 16 01:28:42 PM PDT 24
Finished May 16 01:32:44 PM PDT 24
Peak memory 249612 kb
Host smart-3ae33bbd-d514-4d1c-8ae9-35cdce942740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142502503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.142502503
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.627303584
Short name T526
Test name
Test status
Simulation time 17033284370 ps
CPU time 86.48 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:30:19 PM PDT 24
Peak memory 237192 kb
Host smart-8e3c128a-c597-4631-8fd6-339ef351e622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627303584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.627303584
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2888802890
Short name T826
Test name
Test status
Simulation time 872020691 ps
CPU time 5.68 seconds
Started May 16 01:28:38 PM PDT 24
Finished May 16 01:28:57 PM PDT 24
Peak memory 232760 kb
Host smart-68f92f39-3bc4-4300-ae24-15f8f533db60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888802890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2888802890
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.379052962
Short name T15
Test name
Test status
Simulation time 551925822 ps
CPU time 4.97 seconds
Started May 16 01:28:39 PM PDT 24
Finished May 16 01:28:56 PM PDT 24
Peak memory 218800 kb
Host smart-cae7e09d-926d-4dcd-a2f8-b5913f5bbe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379052962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.379052962
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.296021249
Short name T265
Test name
Test status
Simulation time 2154008549 ps
CPU time 7.54 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:29:00 PM PDT 24
Peak memory 234588 kb
Host smart-ae782f5a-b61d-4683-ac28-30fc6250bcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296021249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.296021249
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4235935208
Short name T549
Test name
Test status
Simulation time 55220902 ps
CPU time 2.34 seconds
Started May 16 01:28:44 PM PDT 24
Finished May 16 01:28:58 PM PDT 24
Peak memory 221220 kb
Host smart-ae4a7140-c305-4508-9860-691bb5e6e84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235935208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4235935208
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1075424347
Short name T477
Test name
Test status
Simulation time 6465668254 ps
CPU time 6.86 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:29:00 PM PDT 24
Peak memory 232912 kb
Host smart-c2447682-d356-4963-a1f8-df690ab98eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075424347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1075424347
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2591700212
Short name T808
Test name
Test status
Simulation time 1454003266 ps
CPU time 8.53 seconds
Started May 16 01:28:42 PM PDT 24
Finished May 16 01:29:03 PM PDT 24
Peak memory 218984 kb
Host smart-17cf9a25-11d6-46b7-8467-6c2b0b318c34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2591700212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2591700212
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3808393324
Short name T813
Test name
Test status
Simulation time 53777242 ps
CPU time 1.16 seconds
Started May 16 01:28:41 PM PDT 24
Finished May 16 01:28:54 PM PDT 24
Peak memory 215368 kb
Host smart-003bcd95-e3bd-4e19-87f6-069a9f5b1780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808393324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3808393324
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2734901792
Short name T349
Test name
Test status
Simulation time 313838236 ps
CPU time 2.39 seconds
Started May 16 01:28:46 PM PDT 24
Finished May 16 01:29:00 PM PDT 24
Peak memory 216464 kb
Host smart-b0109642-dc54-4e32-84f1-ff0e39762363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734901792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2734901792
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2744852436
Short name T902
Test name
Test status
Simulation time 20950742276 ps
CPU time 14.1 seconds
Started May 16 01:28:39 PM PDT 24
Finished May 16 01:29:05 PM PDT 24
Peak memory 217604 kb
Host smart-b63962e8-d134-4cbb-8a12-209c0932e3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744852436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2744852436
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4161182975
Short name T676
Test name
Test status
Simulation time 53080242 ps
CPU time 0.95 seconds
Started May 16 01:28:44 PM PDT 24
Finished May 16 01:28:57 PM PDT 24
Peak memory 206976 kb
Host smart-37c0b8ad-38dc-45b9-b549-f138800c4d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161182975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4161182975
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1996865224
Short name T309
Test name
Test status
Simulation time 15125388 ps
CPU time 0.76 seconds
Started May 16 01:28:38 PM PDT 24
Finished May 16 01:28:52 PM PDT 24
Peak memory 205476 kb
Host smart-81dcad89-28c8-4385-9bfa-67f0f7aa7976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996865224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1996865224
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.453060731
Short name T519
Test name
Test status
Simulation time 567408751 ps
CPU time 2.05 seconds
Started May 16 01:28:38 PM PDT 24
Finished May 16 01:28:52 PM PDT 24
Peak memory 207908 kb
Host smart-168a214f-5bdd-46ff-95d4-d6813dd68278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453060731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.453060731
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2140822114
Short name T312
Test name
Test status
Simulation time 33311117 ps
CPU time 0.71 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:28:54 PM PDT 24
Peak memory 204740 kb
Host smart-9d46486a-0fcd-40f0-b140-6ce5a47ebb40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140822114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2140822114
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.336780890
Short name T771
Test name
Test status
Simulation time 2708976165 ps
CPU time 9.39 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:29:02 PM PDT 24
Peak memory 232888 kb
Host smart-95440d93-1040-4261-8ab3-012f3e0c0bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336780890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.336780890
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.117449472
Short name T319
Test name
Test status
Simulation time 18516657 ps
CPU time 0.79 seconds
Started May 16 01:28:47 PM PDT 24
Finished May 16 01:28:59 PM PDT 24
Peak memory 205396 kb
Host smart-8a590d5c-cd52-4f90-8033-a0aa745b6cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117449472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.117449472
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1571015786
Short name T55
Test name
Test status
Simulation time 25426212211 ps
CPU time 114.66 seconds
Started May 16 01:28:45 PM PDT 24
Finished May 16 01:30:51 PM PDT 24
Peak memory 250244 kb
Host smart-4ffe99a3-9f46-4d61-8330-3fdae77cb6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571015786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1571015786
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.570121826
Short name T945
Test name
Test status
Simulation time 5688670632 ps
CPU time 4.89 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:28:57 PM PDT 24
Peak memory 217764 kb
Host smart-64fec8dc-701a-4bb1-9a24-ce75729c510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570121826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.570121826
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3131522508
Short name T136
Test name
Test status
Simulation time 41582214344 ps
CPU time 199.26 seconds
Started May 16 01:28:42 PM PDT 24
Finished May 16 01:32:14 PM PDT 24
Peak memory 254476 kb
Host smart-bce9fb0a-d7fb-456b-a09d-3740f1efea75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131522508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3131522508
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.286528965
Short name T444
Test name
Test status
Simulation time 134289286 ps
CPU time 4.01 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:28:57 PM PDT 24
Peak memory 232792 kb
Host smart-b422f516-8fd0-4629-8b27-d5e6d6ce7f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286528965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.286528965
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3856062344
Short name T106
Test name
Test status
Simulation time 1008484699 ps
CPU time 5.74 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:28:58 PM PDT 24
Peak memory 224404 kb
Host smart-26246506-023e-40bf-b957-f3379ae87add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856062344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3856062344
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2751134637
Short name T289
Test name
Test status
Simulation time 3365676978 ps
CPU time 19.95 seconds
Started May 16 01:28:42 PM PDT 24
Finished May 16 01:29:15 PM PDT 24
Peak memory 240860 kb
Host smart-207acf9a-3a59-4bf7-b582-2d701a5c9bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751134637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2751134637
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1094910816
Short name T225
Test name
Test status
Simulation time 12523514828 ps
CPU time 9.66 seconds
Started May 16 01:28:42 PM PDT 24
Finished May 16 01:29:04 PM PDT 24
Peak memory 218092 kb
Host smart-98372f15-a8c1-4c03-b916-b48b9c355cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094910816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1094910816
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3661308363
Short name T932
Test name
Test status
Simulation time 2039463702 ps
CPU time 5.47 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:28:58 PM PDT 24
Peak memory 226868 kb
Host smart-27442ae6-8db7-4c56-b924-0fa5109deb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661308363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3661308363
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.192605499
Short name T368
Test name
Test status
Simulation time 636101283 ps
CPU time 3.9 seconds
Started May 16 01:28:42 PM PDT 24
Finished May 16 01:28:58 PM PDT 24
Peak memory 219188 kb
Host smart-0560b184-564d-4345-bf0f-2b3df76eeced
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=192605499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.192605499
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4015832401
Short name T603
Test name
Test status
Simulation time 120587907 ps
CPU time 1.14 seconds
Started May 16 01:28:40 PM PDT 24
Finished May 16 01:28:54 PM PDT 24
Peak memory 215360 kb
Host smart-68224e77-cb75-4859-b7b6-dfd3f1a280f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015832401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4015832401
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1086150408
Short name T426
Test name
Test status
Simulation time 764258383 ps
CPU time 12.17 seconds
Started May 16 01:28:42 PM PDT 24
Finished May 16 01:29:06 PM PDT 24
Peak memory 219296 kb
Host smart-ab19d637-da01-4303-bcdb-16cd9c6ce480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086150408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1086150408
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3789915805
Short name T958
Test name
Test status
Simulation time 22157146253 ps
CPU time 17.87 seconds
Started May 16 01:28:41 PM PDT 24
Finished May 16 01:29:11 PM PDT 24
Peak memory 216516 kb
Host smart-f2198326-0060-4350-b33c-b0bb0c41d469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789915805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3789915805
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2763296508
Short name T967
Test name
Test status
Simulation time 100416020 ps
CPU time 1.55 seconds
Started May 16 01:28:42 PM PDT 24
Finished May 16 01:28:55 PM PDT 24
Peak memory 216372 kb
Host smart-2127b72d-edf9-482b-93f5-8b16439362f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763296508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2763296508
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3155592929
Short name T555
Test name
Test status
Simulation time 239239614 ps
CPU time 0.78 seconds
Started May 16 01:28:46 PM PDT 24
Finished May 16 01:28:58 PM PDT 24
Peak memory 205732 kb
Host smart-c57e6d71-226d-47db-9f6d-10d26059f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155592929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3155592929
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2624603113
Short name T43
Test name
Test status
Simulation time 6631321144 ps
CPU time 10.43 seconds
Started May 16 01:28:41 PM PDT 24
Finished May 16 01:29:03 PM PDT 24
Peak memory 234488 kb
Host smart-c2c4ce25-2116-48fc-bf49-82346ee75a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624603113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2624603113
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4180416460
Short name T611
Test name
Test status
Simulation time 49019155 ps
CPU time 0.73 seconds
Started May 16 01:28:49 PM PDT 24
Finished May 16 01:29:02 PM PDT 24
Peak memory 204760 kb
Host smart-40f62180-10fe-49a3-b617-9a48103d5ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180416460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4180416460
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4003557329
Short name T832
Test name
Test status
Simulation time 106546896 ps
CPU time 2.58 seconds
Started May 16 01:28:48 PM PDT 24
Finished May 16 01:29:02 PM PDT 24
Peak memory 233260 kb
Host smart-a2e7a107-3a1c-4595-84ec-cfd4e655ffc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003557329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4003557329
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.479193272
Short name T20
Test name
Test status
Simulation time 18427680 ps
CPU time 0.77 seconds
Started May 16 01:28:46 PM PDT 24
Finished May 16 01:28:59 PM PDT 24
Peak memory 206788 kb
Host smart-336f34ff-5e41-495e-88b1-93637b9bc014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479193272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.479193272
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3462498330
Short name T761
Test name
Test status
Simulation time 823885394 ps
CPU time 6.71 seconds
Started May 16 01:28:46 PM PDT 24
Finished May 16 01:29:05 PM PDT 24
Peak memory 217348 kb
Host smart-bcdaa211-5269-445e-98e0-fe02a8335a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462498330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3462498330
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2223669184
Short name T386
Test name
Test status
Simulation time 24255266969 ps
CPU time 92.57 seconds
Started May 16 01:28:43 PM PDT 24
Finished May 16 01:30:28 PM PDT 24
Peak memory 265684 kb
Host smart-f7e2d373-b0fd-48bc-a3f7-daa1236f6959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223669184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2223669184
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.136491087
Short name T296
Test name
Test status
Simulation time 2085113210 ps
CPU time 13.76 seconds
Started May 16 01:28:43 PM PDT 24
Finished May 16 01:29:09 PM PDT 24
Peak memory 249164 kb
Host smart-225ac09e-c217-4b23-bb98-54064ee10d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136491087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.136491087
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1809642976
Short name T661
Test name
Test status
Simulation time 1637710391 ps
CPU time 18.72 seconds
Started May 16 01:28:46 PM PDT 24
Finished May 16 01:29:16 PM PDT 24
Peak memory 224508 kb
Host smart-e40fafad-4912-42a6-922a-a6cdbe90c6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809642976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1809642976
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2843951109
Short name T108
Test name
Test status
Simulation time 13162923208 ps
CPU time 98.76 seconds
Started May 16 01:28:42 PM PDT 24
Finished May 16 01:30:33 PM PDT 24
Peak memory 229756 kb
Host smart-ec94fdbc-c44f-4a26-9253-ee7f87f2c70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843951109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2843951109
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2970983577
Short name T286
Test name
Test status
Simulation time 633960377 ps
CPU time 3.59 seconds
Started May 16 01:28:45 PM PDT 24
Finished May 16 01:29:01 PM PDT 24
Peak memory 224512 kb
Host smart-722a12dc-42e8-4d9e-8261-a798ccc61b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970983577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2970983577
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1195133142
Short name T952
Test name
Test status
Simulation time 217843662 ps
CPU time 4.45 seconds
Started May 16 01:28:47 PM PDT 24
Finished May 16 01:29:04 PM PDT 24
Peak memory 233448 kb
Host smart-081959f2-bb62-4107-a5a8-32ee343c39b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195133142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1195133142
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2502291655
Short name T830
Test name
Test status
Simulation time 919611402 ps
CPU time 7.51 seconds
Started May 16 01:28:47 PM PDT 24
Finished May 16 01:29:07 PM PDT 24
Peak memory 220528 kb
Host smart-49579855-09df-4c55-826f-f17d5220120f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2502291655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2502291655
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1851911004
Short name T171
Test name
Test status
Simulation time 443253504924 ps
CPU time 717.16 seconds
Started May 16 01:28:52 PM PDT 24
Finished May 16 01:41:02 PM PDT 24
Peak memory 285324 kb
Host smart-eceffbca-a964-4fdd-bce3-8bb6795acea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851911004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1851911004
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1865948334
Short name T643
Test name
Test status
Simulation time 21641589389 ps
CPU time 14.99 seconds
Started May 16 01:28:45 PM PDT 24
Finished May 16 01:29:12 PM PDT 24
Peak memory 216552 kb
Host smart-2e547a92-26c4-4158-963c-122ed108301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865948334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1865948334
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.420374973
Short name T848
Test name
Test status
Simulation time 10313478709 ps
CPU time 16.16 seconds
Started May 16 01:28:47 PM PDT 24
Finished May 16 01:29:15 PM PDT 24
Peak memory 216472 kb
Host smart-9a193ae4-a2ad-4985-b191-c6147c68ba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420374973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.420374973
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3151167136
Short name T914
Test name
Test status
Simulation time 164368950 ps
CPU time 1.1 seconds
Started May 16 01:28:46 PM PDT 24
Finished May 16 01:28:59 PM PDT 24
Peak memory 207932 kb
Host smart-181e4217-c802-4924-9a7b-e7c1aa41e363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151167136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3151167136
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1707838542
Short name T317
Test name
Test status
Simulation time 106743454 ps
CPU time 0.88 seconds
Started May 16 01:28:45 PM PDT 24
Finished May 16 01:28:58 PM PDT 24
Peak memory 206096 kb
Host smart-9b8bf477-f9c4-40b3-a7ba-5a72cc9ef6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707838542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1707838542
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1044840776
Short name T470
Test name
Test status
Simulation time 5202684810 ps
CPU time 6.67 seconds
Started May 16 01:28:46 PM PDT 24
Finished May 16 01:29:04 PM PDT 24
Peak memory 219928 kb
Host smart-e78c0619-2f80-40d7-a843-8f28df9696a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044840776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1044840776
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2375756440
Short name T437
Test name
Test status
Simulation time 10414838 ps
CPU time 0.69 seconds
Started May 16 01:28:53 PM PDT 24
Finished May 16 01:29:06 PM PDT 24
Peak memory 204672 kb
Host smart-dad049dc-6c76-4d74-a363-0a97e7f50c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375756440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2375756440
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3718798877
Short name T454
Test name
Test status
Simulation time 307170089 ps
CPU time 3.37 seconds
Started May 16 01:28:51 PM PDT 24
Finished May 16 01:29:07 PM PDT 24
Peak memory 218368 kb
Host smart-e6767ef9-c622-4b99-aae8-015ed2e475d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718798877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3718798877
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3195259578
Short name T501
Test name
Test status
Simulation time 45729179 ps
CPU time 0.74 seconds
Started May 16 01:28:52 PM PDT 24
Finished May 16 01:29:05 PM PDT 24
Peak memory 205376 kb
Host smart-6f7c03b7-cec0-4077-b982-d83fbc658add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195259578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3195259578
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.193099973
Short name T185
Test name
Test status
Simulation time 475379258966 ps
CPU time 218.92 seconds
Started May 16 01:28:49 PM PDT 24
Finished May 16 01:32:40 PM PDT 24
Peak memory 257432 kb
Host smart-c489a137-af49-4806-99ce-1f74f578bdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193099973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.193099973
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2023092958
Short name T37
Test name
Test status
Simulation time 6915142672 ps
CPU time 38.77 seconds
Started May 16 01:28:54 PM PDT 24
Finished May 16 01:29:45 PM PDT 24
Peak memory 249396 kb
Host smart-237e77c8-627d-4cca-9445-8be0f3fc6106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023092958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2023092958
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2807466731
Short name T693
Test name
Test status
Simulation time 514264538 ps
CPU time 6.44 seconds
Started May 16 01:28:52 PM PDT 24
Finished May 16 01:29:11 PM PDT 24
Peak memory 232648 kb
Host smart-5df21f58-e413-4fba-afd3-bfac6b0f7464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807466731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2807466731
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.598668385
Short name T782
Test name
Test status
Simulation time 7856087414 ps
CPU time 15.9 seconds
Started May 16 01:28:52 PM PDT 24
Finished May 16 01:29:20 PM PDT 24
Peak memory 234364 kb
Host smart-4518bfa4-5d67-440f-990c-b8f83d68452e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598668385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.598668385
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1275251092
Short name T796
Test name
Test status
Simulation time 9853246584 ps
CPU time 15.72 seconds
Started May 16 01:28:51 PM PDT 24
Finished May 16 01:29:19 PM PDT 24
Peak memory 222832 kb
Host smart-8efc3678-10bf-4f8e-a023-e9a39ba32430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275251092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1275251092
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1769217067
Short name T346
Test name
Test status
Simulation time 141688669 ps
CPU time 2.57 seconds
Started May 16 01:28:48 PM PDT 24
Finished May 16 01:29:03 PM PDT 24
Peak memory 221344 kb
Host smart-1aca6412-09aa-458d-9d33-e7868862fc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769217067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1769217067
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.725523303
Short name T527
Test name
Test status
Simulation time 780438778 ps
CPU time 3.32 seconds
Started May 16 01:28:52 PM PDT 24
Finished May 16 01:29:08 PM PDT 24
Peak memory 224528 kb
Host smart-68d163de-c546-46ce-a480-f06d9fbf41b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725523303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.725523303
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2435460523
Short name T157
Test name
Test status
Simulation time 82474278 ps
CPU time 3.95 seconds
Started May 16 01:28:49 PM PDT 24
Finished May 16 01:29:05 PM PDT 24
Peak memory 222992 kb
Host smart-f5cd0eff-462a-4ac1-86ac-69ec85edf8b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2435460523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2435460523
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3268550438
Short name T303
Test name
Test status
Simulation time 7749445864 ps
CPU time 45.44 seconds
Started May 16 01:28:54 PM PDT 24
Finished May 16 01:29:51 PM PDT 24
Peak memory 216500 kb
Host smart-1889d3df-64b4-4f23-8b8a-5ac5bd595c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268550438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3268550438
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3372985946
Short name T591
Test name
Test status
Simulation time 1507832745 ps
CPU time 1.98 seconds
Started May 16 01:28:53 PM PDT 24
Finished May 16 01:29:07 PM PDT 24
Peak memory 207592 kb
Host smart-7180ae3d-2869-4b50-a6e1-84a4473d0277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372985946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3372985946
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3185436265
Short name T472
Test name
Test status
Simulation time 20591672 ps
CPU time 0.71 seconds
Started May 16 01:28:50 PM PDT 24
Finished May 16 01:29:03 PM PDT 24
Peak memory 205416 kb
Host smart-a73df418-91cf-401b-adce-fc0aa34b8bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185436265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3185436265
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.531589902
Short name T515
Test name
Test status
Simulation time 25888584 ps
CPU time 0.78 seconds
Started May 16 01:28:52 PM PDT 24
Finished May 16 01:29:05 PM PDT 24
Peak memory 205892 kb
Host smart-a1d1a633-9374-4355-818a-fa67e3096a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531589902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.531589902
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3679496487
Short name T821
Test name
Test status
Simulation time 5570906826 ps
CPU time 8.61 seconds
Started May 16 01:28:52 PM PDT 24
Finished May 16 01:29:13 PM PDT 24
Peak memory 218628 kb
Host smart-b7ef5ee2-f581-4f80-ad04-87ae98764d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679496487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3679496487
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.794321941
Short name T594
Test name
Test status
Simulation time 46409518 ps
CPU time 0.76 seconds
Started May 16 01:28:50 PM PDT 24
Finished May 16 01:29:04 PM PDT 24
Peak memory 205476 kb
Host smart-0295b49a-2f23-4fe6-a4b3-de430f905721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794321941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.794321941
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3056163695
Short name T680
Test name
Test status
Simulation time 34598616 ps
CPU time 2.05 seconds
Started May 16 01:28:50 PM PDT 24
Finished May 16 01:29:05 PM PDT 24
Peak memory 218472 kb
Host smart-22586660-b656-4cc5-b797-e09a2d8174eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056163695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3056163695
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1319451565
Short name T521
Test name
Test status
Simulation time 78681124 ps
CPU time 0.77 seconds
Started May 16 01:28:54 PM PDT 24
Finished May 16 01:29:06 PM PDT 24
Peak memory 206488 kb
Host smart-08ca44eb-6459-4e1a-abcb-cfb9511c4f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319451565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1319451565
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2292788019
Short name T602
Test name
Test status
Simulation time 30745486739 ps
CPU time 116.66 seconds
Started May 16 01:28:49 PM PDT 24
Finished May 16 01:30:58 PM PDT 24
Peak memory 251200 kb
Host smart-0e7853e8-514a-493a-b2d2-a17e34db579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292788019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2292788019
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.300110544
Short name T801
Test name
Test status
Simulation time 15526733752 ps
CPU time 88.42 seconds
Started May 16 01:28:52 PM PDT 24
Finished May 16 01:30:33 PM PDT 24
Peak memory 254048 kb
Host smart-350dd66f-f2cb-4d28-b424-1dc751c30dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300110544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.300110544
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4134809568
Short name T179
Test name
Test status
Simulation time 2809395652 ps
CPU time 54.59 seconds
Started May 16 01:28:53 PM PDT 24
Finished May 16 01:30:00 PM PDT 24
Peak memory 249408 kb
Host smart-a97c20c3-a0f0-438b-91af-525147f43c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134809568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4134809568
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1690534354
Short name T806
Test name
Test status
Simulation time 1912855519 ps
CPU time 24.96 seconds
Started May 16 01:28:54 PM PDT 24
Finished May 16 01:29:31 PM PDT 24
Peak memory 240940 kb
Host smart-19e8aa74-29d7-41f5-bee0-98fa7456b54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690534354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1690534354
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.458300930
Short name T950
Test name
Test status
Simulation time 662581166 ps
CPU time 3.56 seconds
Started May 16 01:28:49 PM PDT 24
Finished May 16 01:29:05 PM PDT 24
Peak memory 233720 kb
Host smart-24665a7a-3a6e-45c0-be66-fe78c58a70a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458300930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.458300930
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3295469990
Short name T107
Test name
Test status
Simulation time 293715626 ps
CPU time 2.74 seconds
Started May 16 01:28:55 PM PDT 24
Finished May 16 01:29:09 PM PDT 24
Peak memory 234136 kb
Host smart-d852b264-70b3-4939-a342-ac303fccd32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295469990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3295469990
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2122175038
Short name T837
Test name
Test status
Simulation time 134159775 ps
CPU time 2.18 seconds
Started May 16 01:28:51 PM PDT 24
Finished May 16 01:29:06 PM PDT 24
Peak memory 215824 kb
Host smart-dbbd5967-a7df-44c0-9131-dd9e0d43572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122175038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2122175038
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4157440738
Short name T954
Test name
Test status
Simulation time 22123023662 ps
CPU time 19.84 seconds
Started May 16 01:28:50 PM PDT 24
Finished May 16 01:29:22 PM PDT 24
Peak memory 216948 kb
Host smart-2c332256-71bb-4148-b10e-34423eb42855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157440738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4157440738
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1755047054
Short name T753
Test name
Test status
Simulation time 380907010 ps
CPU time 6.05 seconds
Started May 16 01:28:49 PM PDT 24
Finished May 16 01:29:07 PM PDT 24
Peak memory 218896 kb
Host smart-f2899509-8ef3-4ed0-8bfc-2b217ac2dc5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1755047054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1755047054
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1650737483
Short name T168
Test name
Test status
Simulation time 5582116904 ps
CPU time 106.13 seconds
Started May 16 01:28:50 PM PDT 24
Finished May 16 01:30:49 PM PDT 24
Peak memory 270388 kb
Host smart-94b995f4-2e3d-473f-b58e-153f4209da9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650737483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1650737483
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.761813258
Short name T630
Test name
Test status
Simulation time 14884778289 ps
CPU time 22.97 seconds
Started May 16 01:28:51 PM PDT 24
Finished May 16 01:29:27 PM PDT 24
Peak memory 216444 kb
Host smart-b5a6313f-10a0-41e7-8284-9b0c137cc7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761813258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.761813258
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4030413514
Short name T93
Test name
Test status
Simulation time 4623463957 ps
CPU time 13.91 seconds
Started May 16 01:28:52 PM PDT 24
Finished May 16 01:29:19 PM PDT 24
Peak memory 216472 kb
Host smart-8dc53520-7c36-4088-b6c3-1dc08cc455e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030413514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4030413514
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1162625172
Short name T517
Test name
Test status
Simulation time 140370356 ps
CPU time 0.95 seconds
Started May 16 01:28:50 PM PDT 24
Finished May 16 01:29:04 PM PDT 24
Peak memory 206568 kb
Host smart-383c965c-9947-4d34-9d27-2f92e6f791db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162625172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1162625172
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2328781413
Short name T765
Test name
Test status
Simulation time 37154761 ps
CPU time 0.87 seconds
Started May 16 01:28:54 PM PDT 24
Finished May 16 01:29:07 PM PDT 24
Peak memory 206856 kb
Host smart-2d651c34-5835-42f2-bb2a-d30381e24f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328781413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2328781413
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2919697872
Short name T382
Test name
Test status
Simulation time 159488929 ps
CPU time 2.71 seconds
Started May 16 01:28:48 PM PDT 24
Finished May 16 01:29:03 PM PDT 24
Peak memory 234104 kb
Host smart-d217ca1c-a441-4c42-a21a-78a1dc8c52b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919697872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2919697872
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1564922360
Short name T374
Test name
Test status
Simulation time 35848916 ps
CPU time 0.73 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:29:17 PM PDT 24
Peak memory 205276 kb
Host smart-92d88094-6f16-4c22-88dd-8b6a69351c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564922360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1564922360
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2045205720
Short name T666
Test name
Test status
Simulation time 435421116 ps
CPU time 3.56 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:29:19 PM PDT 24
Peak memory 234416 kb
Host smart-81792375-9f21-4cca-805f-bdf6b24927b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045205720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2045205720
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.820758467
Short name T899
Test name
Test status
Simulation time 16722069 ps
CPU time 0.8 seconds
Started May 16 01:28:50 PM PDT 24
Finished May 16 01:29:04 PM PDT 24
Peak memory 206420 kb
Host smart-eece7a84-4076-453d-b621-b0f61accfb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820758467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.820758467
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3470634320
Short name T469
Test name
Test status
Simulation time 31209583260 ps
CPU time 67.41 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:30:23 PM PDT 24
Peak memory 252524 kb
Host smart-0f7dcd30-2b28-4b68-8670-f03fa11b3bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470634320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3470634320
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.24088289
Short name T299
Test name
Test status
Simulation time 2587033169 ps
CPU time 26.35 seconds
Started May 16 01:29:09 PM PDT 24
Finished May 16 01:29:45 PM PDT 24
Peak memory 224784 kb
Host smart-56396054-dbca-4791-afae-415af8725ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24088289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.24088289
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1014438830
Short name T237
Test name
Test status
Simulation time 47305279327 ps
CPU time 111.33 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:31:07 PM PDT 24
Peak memory 241104 kb
Host smart-ee43e37e-cb0d-4e7b-90d4-3d075a3863dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014438830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1014438830
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4185772230
Short name T678
Test name
Test status
Simulation time 183013824 ps
CPU time 7.49 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:25 PM PDT 24
Peak memory 249108 kb
Host smart-39f589c5-0fe8-4398-bdbf-cedddeeb2358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185772230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4185772230
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1222424965
Short name T278
Test name
Test status
Simulation time 262551186 ps
CPU time 2.86 seconds
Started May 16 01:29:05 PM PDT 24
Finished May 16 01:29:18 PM PDT 24
Peak memory 217892 kb
Host smart-9075a463-d418-4301-b9dd-5160b52c1e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222424965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1222424965
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.853538011
Short name T624
Test name
Test status
Simulation time 5313050651 ps
CPU time 21.14 seconds
Started May 16 01:29:09 PM PDT 24
Finished May 16 01:29:40 PM PDT 24
Peak memory 239548 kb
Host smart-28ba80ec-9947-40d3-bc75-9f05052744b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853538011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.853538011
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.851057306
Short name T847
Test name
Test status
Simulation time 16766599003 ps
CPU time 20.18 seconds
Started May 16 01:29:05 PM PDT 24
Finished May 16 01:29:34 PM PDT 24
Peak memory 233420 kb
Host smart-53652a23-161d-4f17-be78-4d19a2edc00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851057306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.851057306
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3120617302
Short name T325
Test name
Test status
Simulation time 134043362 ps
CPU time 2.36 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:29:18 PM PDT 24
Peak memory 220964 kb
Host smart-bfa67bb8-4599-4f32-9a07-abb0f1c1259b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120617302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3120617302
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.541841862
Short name T355
Test name
Test status
Simulation time 1806777604 ps
CPU time 7.6 seconds
Started May 16 01:29:05 PM PDT 24
Finished May 16 01:29:23 PM PDT 24
Peak memory 220208 kb
Host smart-3f66373d-5afb-4750-b16d-bde6e9021d9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=541841862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.541841862
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2647992660
Short name T238
Test name
Test status
Simulation time 8786349101 ps
CPU time 109.41 seconds
Started May 16 01:29:09 PM PDT 24
Finished May 16 01:31:09 PM PDT 24
Peak memory 257604 kb
Host smart-2689f027-64ff-4c21-8fc7-b40d788b99a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647992660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2647992660
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2471743527
Short name T324
Test name
Test status
Simulation time 6006248936 ps
CPU time 10.24 seconds
Started May 16 01:28:52 PM PDT 24
Finished May 16 01:29:15 PM PDT 24
Peak memory 220060 kb
Host smart-9cea65fa-7fdd-4479-972f-17d4369ec25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471743527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2471743527
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.744168928
Short name T834
Test name
Test status
Simulation time 542970265 ps
CPU time 4.43 seconds
Started May 16 01:28:51 PM PDT 24
Finished May 16 01:29:08 PM PDT 24
Peak memory 216380 kb
Host smart-2c16eb64-97ef-4fac-be2e-1b2fd27c3937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744168928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.744168928
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3506858932
Short name T881
Test name
Test status
Simulation time 109299009 ps
CPU time 1.17 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:29:17 PM PDT 24
Peak memory 207960 kb
Host smart-3c4218cb-7771-4d5a-99e4-69be152b434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506858932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3506858932
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1768050988
Short name T912
Test name
Test status
Simulation time 169126041 ps
CPU time 0.84 seconds
Started May 16 01:28:50 PM PDT 24
Finished May 16 01:29:03 PM PDT 24
Peak memory 206812 kb
Host smart-0762e280-ba40-4c16-9171-34cb2a58eda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768050988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1768050988
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.801508156
Short name T587
Test name
Test status
Simulation time 4169973479 ps
CPU time 14.83 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:29:31 PM PDT 24
Peak memory 229344 kb
Host smart-0af89091-568d-4a63-a9ea-0757e2119aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801508156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.801508156
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1024212889
Short name T60
Test name
Test status
Simulation time 40898302 ps
CPU time 0.7 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:29:17 PM PDT 24
Peak memory 205756 kb
Host smart-3e5d152a-738d-49a9-84ff-963a7107bb56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024212889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1024212889
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4274980534
Short name T335
Test name
Test status
Simulation time 1196852778 ps
CPU time 4.37 seconds
Started May 16 01:29:05 PM PDT 24
Finished May 16 01:29:19 PM PDT 24
Peak memory 236192 kb
Host smart-88579a0b-c6e6-4346-bad9-1974a7ed1652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274980534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4274980534
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1681314154
Short name T637
Test name
Test status
Simulation time 32132265 ps
CPU time 0.76 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:18 PM PDT 24
Peak memory 205732 kb
Host smart-3c274ef6-d218-4b4b-b39b-91447575034c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681314154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1681314154
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2941826556
Short name T968
Test name
Test status
Simulation time 23999898524 ps
CPU time 104.01 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:31:00 PM PDT 24
Peak memory 255688 kb
Host smart-6cba2556-1305-4936-afd1-ab86e9f5e95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941826556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2941826556
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1606393583
Short name T844
Test name
Test status
Simulation time 330452371 ps
CPU time 3.23 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:21 PM PDT 24
Peak memory 217352 kb
Host smart-c82a369d-fcaf-440f-baf1-b0dce277e506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606393583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1606393583
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1662736286
Short name T31
Test name
Test status
Simulation time 156571622675 ps
CPU time 267 seconds
Started May 16 01:29:09 PM PDT 24
Finished May 16 01:33:46 PM PDT 24
Peak memory 256496 kb
Host smart-786f703f-3083-4a21-9e7b-786759398d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662736286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1662736286
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4196174705
Short name T795
Test name
Test status
Simulation time 4841647511 ps
CPU time 18.97 seconds
Started May 16 01:29:05 PM PDT 24
Finished May 16 01:29:34 PM PDT 24
Peak memory 232856 kb
Host smart-396e4906-8fa3-4d21-bbe5-c0530e119536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196174705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4196174705
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.659501041
Short name T396
Test name
Test status
Simulation time 860703270 ps
CPU time 8.63 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:29:25 PM PDT 24
Peak memory 224492 kb
Host smart-b4a1a95a-2190-478d-8b73-4721cd594784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659501041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.659501041
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1904450126
Short name T845
Test name
Test status
Simulation time 3353971290 ps
CPU time 37.68 seconds
Started May 16 01:29:05 PM PDT 24
Finished May 16 01:29:53 PM PDT 24
Peak memory 230268 kb
Host smart-5dc958db-7621-49b1-994d-aee694e3cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904450126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1904450126
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.4080363235
Short name T570
Test name
Test status
Simulation time 8598167080 ps
CPU time 8.35 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:29:25 PM PDT 24
Peak memory 217268 kb
Host smart-741be377-1e6c-4819-8153-241f62795eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080363235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.4080363235
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.953243046
Short name T284
Test name
Test status
Simulation time 524190297 ps
CPU time 4.33 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:22 PM PDT 24
Peak memory 233344 kb
Host smart-f43b7c85-5eca-4db1-9cf3-917939095c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953243046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.953243046
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3768401813
Short name T2
Test name
Test status
Simulation time 722269770 ps
CPU time 8.55 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:29:24 PM PDT 24
Peak memory 218796 kb
Host smart-660b3cb2-8959-45c9-9f02-c027c5f6a719
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3768401813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3768401813
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3719444617
Short name T820
Test name
Test status
Simulation time 94779016 ps
CPU time 1.05 seconds
Started May 16 01:29:05 PM PDT 24
Finished May 16 01:29:16 PM PDT 24
Peak memory 205436 kb
Host smart-6ab01b48-7ff9-479a-aa9d-87e7cd0e8d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719444617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3719444617
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.901787319
Short name T946
Test name
Test status
Simulation time 9044473069 ps
CPU time 44.61 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:30:01 PM PDT 24
Peak memory 216404 kb
Host smart-7ab45d56-1e9f-4df1-b8dc-747dbe60a743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901787319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.901787319
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2383118422
Short name T702
Test name
Test status
Simulation time 15164164 ps
CPU time 0.7 seconds
Started May 16 01:29:05 PM PDT 24
Finished May 16 01:29:15 PM PDT 24
Peak memory 205592 kb
Host smart-6c65d5db-c621-4c35-aec9-69570e8bbe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383118422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2383118422
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1665099266
Short name T938
Test name
Test status
Simulation time 34229739 ps
CPU time 1.35 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:19 PM PDT 24
Peak memory 216292 kb
Host smart-17770987-5c3e-4575-b087-282f88872ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665099266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1665099266
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4052451505
Short name T334
Test name
Test status
Simulation time 167326711 ps
CPU time 0.91 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:29:16 PM PDT 24
Peak memory 206840 kb
Host smart-3ab7374a-54bb-4581-bb6c-24c30b3d0dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052451505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4052451505
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2263191014
Short name T285
Test name
Test status
Simulation time 1069223184 ps
CPU time 8.3 seconds
Started May 16 01:29:05 PM PDT 24
Finished May 16 01:29:23 PM PDT 24
Peak memory 234588 kb
Host smart-a3964852-f644-4d4f-8091-df028d42809b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263191014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2263191014
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4108500014
Short name T438
Test name
Test status
Simulation time 82738525 ps
CPU time 0.72 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:18 PM PDT 24
Peak memory 205388 kb
Host smart-122bfcf5-3453-458d-ba70-c39e02781447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108500014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4108500014
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.714884092
Short name T495
Test name
Test status
Simulation time 2172936848 ps
CPU time 19.66 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:29:37 PM PDT 24
Peak memory 219868 kb
Host smart-78af554b-e9fd-4e60-ac28-76fba7e86788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714884092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.714884092
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2126353396
Short name T144
Test name
Test status
Simulation time 42010380 ps
CPU time 0.77 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:29:18 PM PDT 24
Peak memory 206724 kb
Host smart-a0f9f00f-0b12-4823-981c-eb787f6c868b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126353396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2126353396
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3458693988
Short name T211
Test name
Test status
Simulation time 242515137108 ps
CPU time 432.09 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:36:28 PM PDT 24
Peak memory 265512 kb
Host smart-a4d6dfae-daf1-4f06-aee2-6c306b79105c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458693988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3458693988
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2344100123
Short name T47
Test name
Test status
Simulation time 22163441034 ps
CPU time 255.66 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:33:33 PM PDT 24
Peak memory 249412 kb
Host smart-91963697-e63a-4687-8ac3-ce9b29c333d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344100123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2344100123
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3545046761
Short name T476
Test name
Test status
Simulation time 53026291493 ps
CPU time 92.66 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:30:49 PM PDT 24
Peak memory 241196 kb
Host smart-7f5e88a2-e857-4e58-bd61-ca1fab4372f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545046761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3545046761
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.395076931
Short name T817
Test name
Test status
Simulation time 273469414 ps
CPU time 6.29 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:29:22 PM PDT 24
Peak memory 224536 kb
Host smart-ef19300f-b0c0-4608-a203-31c2332cf48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395076931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.395076931
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3365432544
Short name T187
Test name
Test status
Simulation time 139270381 ps
CPU time 4.78 seconds
Started May 16 01:29:09 PM PDT 24
Finished May 16 01:29:24 PM PDT 24
Peak memory 219660 kb
Host smart-672b3eac-9522-4312-ae3a-685de9cc8214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365432544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3365432544
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1655601872
Short name T439
Test name
Test status
Simulation time 4632968203 ps
CPU time 24.32 seconds
Started May 16 01:29:09 PM PDT 24
Finished May 16 01:29:43 PM PDT 24
Peak memory 219816 kb
Host smart-c430184e-07c3-4707-a1df-f0fec966dbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655601872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1655601872
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.929420800
Short name T496
Test name
Test status
Simulation time 4120700349 ps
CPU time 14.36 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:29:31 PM PDT 24
Peak memory 233900 kb
Host smart-6fbccdd2-3e6d-463c-a109-19d759b0396e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929420800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.929420800
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1666957590
Short name T313
Test name
Test status
Simulation time 55969307 ps
CPU time 2.06 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:29:18 PM PDT 24
Peak memory 216148 kb
Host smart-47088dd3-47e1-4496-8d6a-1b9188776310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666957590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1666957590
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2118771124
Short name T723
Test name
Test status
Simulation time 857027563 ps
CPU time 13.15 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:29:29 PM PDT 24
Peak memory 220672 kb
Host smart-8ac48edf-f617-4826-80cd-7f6cbdde44b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2118771124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2118771124
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3029701726
Short name T730
Test name
Test status
Simulation time 188257950 ps
CPU time 0.96 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:29:18 PM PDT 24
Peak memory 206604 kb
Host smart-ffed9dea-7868-466d-a7c1-167f86009898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029701726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3029701726
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.575033397
Short name T853
Test name
Test status
Simulation time 4508443834 ps
CPU time 29.12 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:47 PM PDT 24
Peak memory 216480 kb
Host smart-9e3120e0-563e-4880-99fc-a82a355d46d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575033397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.575033397
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3165385707
Short name T709
Test name
Test status
Simulation time 22095457637 ps
CPU time 18.46 seconds
Started May 16 01:29:04 PM PDT 24
Finished May 16 01:29:32 PM PDT 24
Peak memory 216484 kb
Host smart-d1f5587a-9f1b-4166-a46e-34fe3b502e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165385707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3165385707
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2755085960
Short name T314
Test name
Test status
Simulation time 75048412 ps
CPU time 1.12 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:29:17 PM PDT 24
Peak memory 207832 kb
Host smart-810de5fa-746b-4246-90ca-ddf395dce1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755085960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2755085960
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.771112003
Short name T432
Test name
Test status
Simulation time 24582664 ps
CPU time 0.71 seconds
Started May 16 01:29:07 PM PDT 24
Finished May 16 01:29:18 PM PDT 24
Peak memory 205496 kb
Host smart-83d7e760-7a28-47a4-b7d0-b4572cfb13e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771112003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.771112003
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3079336763
Short name T751
Test name
Test status
Simulation time 140771825 ps
CPU time 3.74 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:22 PM PDT 24
Peak memory 218876 kb
Host smart-188d14b1-9a3e-4828-b768-6902d24e2f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079336763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3079336763
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1377735118
Short name T660
Test name
Test status
Simulation time 11675588 ps
CPU time 0.72 seconds
Started May 16 01:29:21 PM PDT 24
Finished May 16 01:29:34 PM PDT 24
Peak memory 205388 kb
Host smart-299d46f3-9829-4fa7-aa48-a1c4b2ae70a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377735118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1377735118
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1408295306
Short name T97
Test name
Test status
Simulation time 525466399 ps
CPU time 2.53 seconds
Started May 16 01:29:10 PM PDT 24
Finished May 16 01:29:22 PM PDT 24
Peak memory 218752 kb
Host smart-925ce4a7-1e0a-42ee-af19-fb61cddcbed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408295306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1408295306
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.352267555
Short name T17
Test name
Test status
Simulation time 59130737 ps
CPU time 0.76 seconds
Started May 16 01:29:13 PM PDT 24
Finished May 16 01:29:24 PM PDT 24
Peak memory 205696 kb
Host smart-8f4bed13-c6af-457f-95ad-bedc10cee421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352267555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.352267555
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.473083896
Short name T805
Test name
Test status
Simulation time 97365037718 ps
CPU time 186.2 seconds
Started May 16 01:29:18 PM PDT 24
Finished May 16 01:32:36 PM PDT 24
Peak memory 255128 kb
Host smart-e94eb40f-1131-457f-85ba-5ed0cae3a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473083896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.473083896
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1451854546
Short name T197
Test name
Test status
Simulation time 3905192977 ps
CPU time 81.3 seconds
Started May 16 01:29:20 PM PDT 24
Finished May 16 01:30:54 PM PDT 24
Peak memory 249416 kb
Host smart-59244054-4fd5-4695-8cce-8dad087c6499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451854546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1451854546
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3074626320
Short name T41
Test name
Test status
Simulation time 63523266346 ps
CPU time 306.35 seconds
Started May 16 01:29:21 PM PDT 24
Finished May 16 01:34:40 PM PDT 24
Peak memory 252816 kb
Host smart-873ba16a-3767-4b53-af59-caa3ce0d7836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074626320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3074626320
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2854007007
Short name T514
Test name
Test status
Simulation time 181843190 ps
CPU time 3.28 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:22 PM PDT 24
Peak memory 234052 kb
Host smart-f249deec-1adf-48a9-b1fe-3038466a29d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854007007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2854007007
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.593673213
Short name T209
Test name
Test status
Simulation time 207116475 ps
CPU time 5.78 seconds
Started May 16 01:29:10 PM PDT 24
Finished May 16 01:29:25 PM PDT 24
Peak memory 233272 kb
Host smart-745835bf-576f-4b48-b959-148ad85f328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593673213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.593673213
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3206862060
Short name T202
Test name
Test status
Simulation time 12906548345 ps
CPU time 61.31 seconds
Started May 16 01:29:09 PM PDT 24
Finished May 16 01:30:21 PM PDT 24
Peak memory 239040 kb
Host smart-e337d7dd-550b-4e64-9dd0-bfa0d7a923ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206862060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3206862060
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3034927218
Short name T243
Test name
Test status
Simulation time 2277794829 ps
CPU time 10.13 seconds
Started May 16 01:29:09 PM PDT 24
Finished May 16 01:29:29 PM PDT 24
Peak memory 219920 kb
Host smart-7ff2c1c2-d9e6-4017-bde8-be56e306dd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034927218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3034927218
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3228366526
Short name T622
Test name
Test status
Simulation time 739808221 ps
CPU time 3.34 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:21 PM PDT 24
Peak memory 233700 kb
Host smart-cefd3bba-4b6c-496f-bdcf-d0efaafa3c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228366526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3228366526
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1338756961
Short name T768
Test name
Test status
Simulation time 129436078 ps
CPU time 3.75 seconds
Started May 16 01:29:09 PM PDT 24
Finished May 16 01:29:23 PM PDT 24
Peak memory 223076 kb
Host smart-31338ced-1977-4786-9310-d8f986fe2dc8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1338756961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1338756961
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.956432185
Short name T797
Test name
Test status
Simulation time 493336786624 ps
CPU time 548.47 seconds
Started May 16 01:29:16 PM PDT 24
Finished May 16 01:38:37 PM PDT 24
Peak memory 273960 kb
Host smart-4cd93912-2675-44fe-89ee-04c927b1d880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956432185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.956432185
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3839246340
Short name T392
Test name
Test status
Simulation time 1638834845 ps
CPU time 2.96 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:21 PM PDT 24
Peak memory 216364 kb
Host smart-c7538dde-0926-422e-aca8-23343c4f6230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839246340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3839246340
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.4290165904
Short name T441
Test name
Test status
Simulation time 1688652788 ps
CPU time 6.77 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:25 PM PDT 24
Peak memory 216236 kb
Host smart-d01ccfcb-7faa-42e9-b21d-bac7bd7facdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290165904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4290165904
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.393651831
Short name T593
Test name
Test status
Simulation time 423414378 ps
CPU time 2.21 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:20 PM PDT 24
Peak memory 216440 kb
Host smart-5e6f1b11-8218-4a86-ada9-9f9a2086a938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393651831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.393651831
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3402787168
Short name T360
Test name
Test status
Simulation time 125504131 ps
CPU time 0.77 seconds
Started May 16 01:29:08 PM PDT 24
Finished May 16 01:29:18 PM PDT 24
Peak memory 205824 kb
Host smart-5f5e550f-0853-4db1-a542-74c48ae0f9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402787168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3402787168
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.360707033
Short name T188
Test name
Test status
Simulation time 716626850 ps
CPU time 9.04 seconds
Started May 16 01:29:06 PM PDT 24
Finished May 16 01:29:25 PM PDT 24
Peak memory 240908 kb
Host smart-a1005e13-8cab-4a82-8b63-a25231fac688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360707033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.360707033
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3731931378
Short name T311
Test name
Test status
Simulation time 15252731 ps
CPU time 0.71 seconds
Started May 16 01:29:18 PM PDT 24
Finished May 16 01:29:31 PM PDT 24
Peak memory 205356 kb
Host smart-bb4fc76a-1a28-4ff3-a104-c35189ff56a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731931378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3731931378
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1630083300
Short name T589
Test name
Test status
Simulation time 121855738 ps
CPU time 3.19 seconds
Started May 16 01:29:26 PM PDT 24
Finished May 16 01:29:41 PM PDT 24
Peak memory 232736 kb
Host smart-a0eb5b4a-1a77-49e4-a96d-8e2730591fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630083300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1630083300
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1572416588
Short name T397
Test name
Test status
Simulation time 32717244 ps
CPU time 0.76 seconds
Started May 16 01:29:17 PM PDT 24
Finished May 16 01:29:31 PM PDT 24
Peak memory 206500 kb
Host smart-d02e94b2-85c0-4618-b37b-fd87be72ac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572416588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1572416588
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1097472996
Short name T282
Test name
Test status
Simulation time 48024211901 ps
CPU time 163.24 seconds
Started May 16 01:29:18 PM PDT 24
Finished May 16 01:32:13 PM PDT 24
Peak memory 237212 kb
Host smart-f0115fc1-7026-45d7-9eb9-6e806d985785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097472996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1097472996
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3424315639
Short name T138
Test name
Test status
Simulation time 2397630318 ps
CPU time 17.5 seconds
Started May 16 01:29:25 PM PDT 24
Finished May 16 01:29:54 PM PDT 24
Peak memory 239600 kb
Host smart-ab688071-36f1-4869-87f8-34e9096444f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424315639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3424315639
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.328498775
Short name T235
Test name
Test status
Simulation time 105087919126 ps
CPU time 191.71 seconds
Started May 16 01:29:16 PM PDT 24
Finished May 16 01:32:40 PM PDT 24
Peak memory 249328 kb
Host smart-c8c57563-a0ec-4d98-8bba-5eaa3d3f1b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328498775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.328498775
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3073646093
Short name T888
Test name
Test status
Simulation time 880253750 ps
CPU time 3.79 seconds
Started May 16 01:29:18 PM PDT 24
Finished May 16 01:29:34 PM PDT 24
Peak memory 233680 kb
Host smart-008bd50f-38c4-45d1-8de3-de8a354543fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073646093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3073646093
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.148265573
Short name T951
Test name
Test status
Simulation time 208422312 ps
CPU time 2.37 seconds
Started May 16 01:29:18 PM PDT 24
Finished May 16 01:29:32 PM PDT 24
Peak memory 216152 kb
Host smart-6d76d6db-e691-48fe-ad84-60bbb03e382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148265573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.148265573
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3036391335
Short name T658
Test name
Test status
Simulation time 1200560276 ps
CPU time 4.75 seconds
Started May 16 01:29:18 PM PDT 24
Finished May 16 01:29:35 PM PDT 24
Peak memory 216920 kb
Host smart-2c5689a2-2f3a-4c62-bd63-1bf8e269d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036391335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3036391335
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.161979385
Short name T36
Test name
Test status
Simulation time 5579963548 ps
CPU time 6.51 seconds
Started May 16 01:29:19 PM PDT 24
Finished May 16 01:29:37 PM PDT 24
Peak memory 218084 kb
Host smart-ec0d09c8-f9fb-4757-ba8c-e1d56775da85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161979385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.161979385
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1639295823
Short name T928
Test name
Test status
Simulation time 598753979 ps
CPU time 5.27 seconds
Started May 16 01:29:18 PM PDT 24
Finished May 16 01:29:36 PM PDT 24
Peak memory 218824 kb
Host smart-8e1aa935-3155-4fb2-b5ab-48f144a76b31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1639295823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1639295823
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1404159425
Short name T228
Test name
Test status
Simulation time 76008763207 ps
CPU time 706.15 seconds
Started May 16 01:29:21 PM PDT 24
Finished May 16 01:41:19 PM PDT 24
Peak memory 253436 kb
Host smart-20b6f16f-520d-4940-9d3e-fec4fd80d42c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404159425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1404159425
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2616949742
Short name T384
Test name
Test status
Simulation time 1550022252 ps
CPU time 5.23 seconds
Started May 16 01:29:17 PM PDT 24
Finished May 16 01:29:35 PM PDT 24
Peak memory 216348 kb
Host smart-5072d79b-e95d-4a22-908b-fec8c1c8893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616949742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2616949742
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3681523695
Short name T875
Test name
Test status
Simulation time 5410361109 ps
CPU time 15.43 seconds
Started May 16 01:29:23 PM PDT 24
Finished May 16 01:29:51 PM PDT 24
Peak memory 216500 kb
Host smart-3e5dc194-dfbb-47e8-9488-6a033e871838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681523695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3681523695
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2458700252
Short name T689
Test name
Test status
Simulation time 126281365 ps
CPU time 2.08 seconds
Started May 16 01:29:20 PM PDT 24
Finished May 16 01:29:35 PM PDT 24
Peak memory 216368 kb
Host smart-8ad0e73f-246e-4202-9d74-102be4ffa8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458700252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2458700252
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.147706852
Short name T781
Test name
Test status
Simulation time 214525212 ps
CPU time 0.91 seconds
Started May 16 01:29:19 PM PDT 24
Finished May 16 01:29:32 PM PDT 24
Peak memory 205824 kb
Host smart-21806a30-1535-4775-9031-84a31c396af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147706852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.147706852
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3301200468
Short name T544
Test name
Test status
Simulation time 494975698 ps
CPU time 5.67 seconds
Started May 16 01:29:19 PM PDT 24
Finished May 16 01:29:36 PM PDT 24
Peak memory 218852 kb
Host smart-74fa2899-ac2e-4381-8531-492b1b47024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301200468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3301200468
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.984948482
Short name T653
Test name
Test status
Simulation time 45819194 ps
CPU time 0.73 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:50 PM PDT 24
Peak memory 205400 kb
Host smart-c6ef4c0f-940e-4cb0-abfb-3ae4600aaa0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984948482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.984948482
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1926680129
Short name T823
Test name
Test status
Simulation time 903571913 ps
CPU time 9.24 seconds
Started May 16 01:26:40 PM PDT 24
Finished May 16 01:27:04 PM PDT 24
Peak memory 220036 kb
Host smart-6d85a6c7-b758-4ed0-95bd-421714c2cd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926680129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1926680129
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.928531073
Short name T973
Test name
Test status
Simulation time 23572019 ps
CPU time 0.76 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:05 PM PDT 24
Peak memory 206716 kb
Host smart-aeec3199-1e0d-414d-a329-ff56f70408aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928531073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.928531073
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2227111635
Short name T180
Test name
Test status
Simulation time 12763609364 ps
CPU time 56.57 seconds
Started May 16 01:26:33 PM PDT 24
Finished May 16 01:27:45 PM PDT 24
Peak memory 251004 kb
Host smart-4ea30ce1-3015-4b2c-b82d-5474e27a3766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227111635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2227111635
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3998729954
Short name T646
Test name
Test status
Simulation time 41300648795 ps
CPU time 197.83 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:30:07 PM PDT 24
Peak memory 249368 kb
Host smart-5f9b5cfa-77be-48e3-9f29-e3d7a9b40f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998729954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3998729954
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3974703730
Short name T147
Test name
Test status
Simulation time 3934421152 ps
CPU time 58.91 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:27:49 PM PDT 24
Peak memory 249784 kb
Host smart-594bf9b5-3085-49ba-986c-1d860479cbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974703730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3974703730
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1922725804
Short name T864
Test name
Test status
Simulation time 1384540463 ps
CPU time 7.25 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:26:57 PM PDT 24
Peak memory 224568 kb
Host smart-359b7387-c636-49b8-9389-758aa852ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922725804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1922725804
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.998319117
Short name T574
Test name
Test status
Simulation time 1056495335 ps
CPU time 9.21 seconds
Started May 16 01:26:38 PM PDT 24
Finished May 16 01:27:01 PM PDT 24
Peak memory 233896 kb
Host smart-e1c2e3cf-ed3e-4d4b-ad46-8a06336d68c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998319117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.998319117
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1527450029
Short name T815
Test name
Test status
Simulation time 1558751395 ps
CPU time 3.78 seconds
Started May 16 01:26:45 PM PDT 24
Finished May 16 01:27:02 PM PDT 24
Peak memory 238160 kb
Host smart-37f16e17-58b5-4b40-8d91-efa34aa79ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527450029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1527450029
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2538187440
Short name T721
Test name
Test status
Simulation time 29153471 ps
CPU time 1.07 seconds
Started May 16 01:26:45 PM PDT 24
Finished May 16 01:27:00 PM PDT 24
Peak memory 216700 kb
Host smart-dd5d7464-155c-4b78-b9cf-6272cb00f92a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538187440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2538187440
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2354542307
Short name T728
Test name
Test status
Simulation time 378670271 ps
CPU time 3.72 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:53 PM PDT 24
Peak memory 224500 kb
Host smart-ddfe07ab-9701-4066-892a-614b5e20cc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354542307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2354542307
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2495978895
Short name T926
Test name
Test status
Simulation time 3188519317 ps
CPU time 12.78 seconds
Started May 16 01:26:33 PM PDT 24
Finished May 16 01:27:01 PM PDT 24
Peak memory 229792 kb
Host smart-b1ff3b87-d528-46b5-9d97-185329a2de78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495978895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2495978895
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.812527960
Short name T586
Test name
Test status
Simulation time 635507673 ps
CPU time 3.78 seconds
Started May 16 01:26:38 PM PDT 24
Finished May 16 01:26:56 PM PDT 24
Peak memory 220380 kb
Host smart-f98a7c55-03ac-468b-b945-1ce822de2ed9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=812527960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.812527960
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2122012799
Short name T711
Test name
Test status
Simulation time 15529699798 ps
CPU time 61.88 seconds
Started May 16 01:26:37 PM PDT 24
Finished May 16 01:27:54 PM PDT 24
Peak memory 249344 kb
Host smart-ec4da94a-2306-45a8-b20f-d6421f3e30f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122012799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2122012799
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3453213775
Short name T742
Test name
Test status
Simulation time 6598131543 ps
CPU time 11.69 seconds
Started May 16 01:26:47 PM PDT 24
Finished May 16 01:27:14 PM PDT 24
Peak memory 216468 kb
Host smart-d45588b1-6bd7-476f-aa5a-ba772940767f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453213775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3453213775
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2520443164
Short name T605
Test name
Test status
Simulation time 7527222728 ps
CPU time 6.58 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:26:57 PM PDT 24
Peak memory 216548 kb
Host smart-f18b3088-ea0d-4377-9989-832e7835b592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520443164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2520443164
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2718289523
Short name T405
Test name
Test status
Simulation time 60651941 ps
CPU time 0.85 seconds
Started May 16 01:26:36 PM PDT 24
Finished May 16 01:26:52 PM PDT 24
Peak memory 207200 kb
Host smart-46218ea6-4a25-4c18-8a3b-aca6d861da24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718289523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2718289523
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1040892984
Short name T71
Test name
Test status
Simulation time 165230332 ps
CPU time 0.89 seconds
Started May 16 01:26:32 PM PDT 24
Finished May 16 01:26:48 PM PDT 24
Peak memory 205840 kb
Host smart-b115fbf3-f229-4722-b5cd-2ecfebfed322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040892984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1040892984
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.487798528
Short name T972
Test name
Test status
Simulation time 112345691 ps
CPU time 2.51 seconds
Started May 16 01:26:44 PM PDT 24
Finished May 16 01:27:00 PM PDT 24
Peak memory 212912 kb
Host smart-85068b55-218e-4c17-bb2f-6856abdfd2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487798528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.487798528
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.392678227
Short name T872
Test name
Test status
Simulation time 30490256 ps
CPU time 0.73 seconds
Started May 16 01:26:44 PM PDT 24
Finished May 16 01:26:58 PM PDT 24
Peak memory 205368 kb
Host smart-a526dd5d-6f0b-4503-b36b-7d2a073084b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392678227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.392678227
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1096979863
Short name T873
Test name
Test status
Simulation time 2890383197 ps
CPU time 20.32 seconds
Started May 16 01:26:53 PM PDT 24
Finished May 16 01:27:30 PM PDT 24
Peak memory 221692 kb
Host smart-6d60a2a6-e936-4523-8b6c-c37ba2fb2c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096979863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1096979863
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1246318232
Short name T516
Test name
Test status
Simulation time 49019528 ps
CPU time 0.74 seconds
Started May 16 01:26:50 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 205308 kb
Host smart-6ddb20be-2c03-4083-8e89-73fb0920474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246318232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1246318232
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1739322152
Short name T221
Test name
Test status
Simulation time 6418479434 ps
CPU time 76.5 seconds
Started May 16 01:26:47 PM PDT 24
Finished May 16 01:28:18 PM PDT 24
Peak memory 249268 kb
Host smart-2c26bf68-0bc6-4663-8c07-8ef705ea8feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739322152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1739322152
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.128641836
Short name T57
Test name
Test status
Simulation time 36237397938 ps
CPU time 83.6 seconds
Started May 16 01:26:51 PM PDT 24
Finished May 16 01:28:31 PM PDT 24
Peak memory 249560 kb
Host smart-15bae299-7156-46aa-8361-2045be2d015e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128641836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.128641836
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2695391902
Short name T542
Test name
Test status
Simulation time 13999185907 ps
CPU time 115.66 seconds
Started May 16 01:26:53 PM PDT 24
Finished May 16 01:29:06 PM PDT 24
Peak memory 250864 kb
Host smart-03a5ee08-cbc3-49f1-8eff-d681b3b89737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695391902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2695391902
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3381244052
Short name T656
Test name
Test status
Simulation time 290109601 ps
CPU time 2.52 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 224540 kb
Host smart-31bfbbfb-ae55-4ac9-b7ae-3b0e832d2225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381244052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3381244052
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2647084827
Short name T14
Test name
Test status
Simulation time 103036024 ps
CPU time 3.68 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:07 PM PDT 24
Peak memory 219600 kb
Host smart-c5f345bb-9bb6-4475-90ea-3ceeb16cc312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647084827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2647084827
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1936152065
Short name T322
Test name
Test status
Simulation time 34817620 ps
CPU time 2.44 seconds
Started May 16 01:26:53 PM PDT 24
Finished May 16 01:27:13 PM PDT 24
Peak memory 221592 kb
Host smart-4b52420d-987f-433f-bfd7-4da669043e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936152065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1936152065
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2528321434
Short name T840
Test name
Test status
Simulation time 46771830 ps
CPU time 1.03 seconds
Started May 16 01:26:42 PM PDT 24
Finished May 16 01:26:57 PM PDT 24
Peak memory 216728 kb
Host smart-4dd27396-15e5-447c-93d6-a051867c618b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528321434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2528321434
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1528897826
Short name T267
Test name
Test status
Simulation time 186981240 ps
CPU time 3.54 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:26:54 PM PDT 24
Peak memory 233684 kb
Host smart-d9b6236a-5c28-4e4f-a509-f9320ce64940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528897826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1528897826
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3573756653
Short name T281
Test name
Test status
Simulation time 3886776515 ps
CPU time 7.46 seconds
Started May 16 01:26:54 PM PDT 24
Finished May 16 01:27:18 PM PDT 24
Peak memory 235032 kb
Host smart-2cccc860-a8fd-49ba-a789-7cbc60ccf452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573756653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3573756653
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3089243082
Short name T399
Test name
Test status
Simulation time 392629152 ps
CPU time 4.25 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:08 PM PDT 24
Peak memory 223012 kb
Host smart-d9d532e0-bf9f-4581-96a8-3bbdcfb26c96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3089243082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3089243082
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3501803674
Short name T882
Test name
Test status
Simulation time 3970541394 ps
CPU time 15.35 seconds
Started May 16 01:26:47 PM PDT 24
Finished May 16 01:27:17 PM PDT 24
Peak memory 217688 kb
Host smart-733279bd-5072-41ef-8545-0b7ecd8a2c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501803674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3501803674
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.73158441
Short name T508
Test name
Test status
Simulation time 1771255514 ps
CPU time 6.36 seconds
Started May 16 01:26:34 PM PDT 24
Finished May 16 01:26:56 PM PDT 24
Peak memory 216364 kb
Host smart-9b13546b-b743-46ba-84c1-cfc26da690b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73158441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.73158441
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1861635605
Short name T497
Test name
Test status
Simulation time 41471654 ps
CPU time 2.62 seconds
Started May 16 01:26:35 PM PDT 24
Finished May 16 01:26:53 PM PDT 24
Peak memory 216384 kb
Host smart-1d14a31c-2c82-4001-9b37-33d6b126bcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861635605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1861635605
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.195305608
Short name T316
Test name
Test status
Simulation time 314246839 ps
CPU time 0.81 seconds
Started May 16 01:26:39 PM PDT 24
Finished May 16 01:26:55 PM PDT 24
Peak memory 205812 kb
Host smart-aa9e1662-8705-48ad-b1d5-b124ebfe31ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195305608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.195305608
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.869404337
Short name T201
Test name
Test status
Simulation time 2191757621 ps
CPU time 9.49 seconds
Started May 16 01:26:55 PM PDT 24
Finished May 16 01:27:21 PM PDT 24
Peak memory 233928 kb
Host smart-a518cba9-f708-4400-a7f6-fadb62f74a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869404337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.869404337
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.250056932
Short name T560
Test name
Test status
Simulation time 79517332 ps
CPU time 0.73 seconds
Started May 16 01:26:46 PM PDT 24
Finished May 16 01:27:01 PM PDT 24
Peak memory 204856 kb
Host smart-498ed059-06d3-4604-bbb6-f332d0028d7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250056932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.250056932
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3831330459
Short name T563
Test name
Test status
Simulation time 9235214073 ps
CPU time 25.49 seconds
Started May 16 01:26:57 PM PDT 24
Finished May 16 01:27:39 PM PDT 24
Peak memory 233976 kb
Host smart-28f51a79-9f57-467c-bfe0-c584f1a854d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831330459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3831330459
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.956872217
Short name T487
Test name
Test status
Simulation time 48768134 ps
CPU time 0.76 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:05 PM PDT 24
Peak memory 206684 kb
Host smart-a0f68171-b3de-4a8b-90d5-7c1e1fc6fe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956872217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.956872217
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3106145890
Short name T583
Test name
Test status
Simulation time 83868045149 ps
CPU time 164.18 seconds
Started May 16 01:26:50 PM PDT 24
Finished May 16 01:29:49 PM PDT 24
Peak memory 249304 kb
Host smart-b5abb2b1-b28f-43f8-84da-0f8334485ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106145890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3106145890
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1016148650
Short name T146
Test name
Test status
Simulation time 13703053734 ps
CPU time 71.29 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:28:15 PM PDT 24
Peak memory 249388 kb
Host smart-1d55d60a-0dd6-4f1b-86c9-79e0f7b5f7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016148650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1016148650
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2647907569
Short name T277
Test name
Test status
Simulation time 9319516760 ps
CPU time 141.32 seconds
Started May 16 01:26:55 PM PDT 24
Finished May 16 01:29:33 PM PDT 24
Peak memory 256156 kb
Host smart-e1222b62-0a88-42f8-a6a9-414162896998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647907569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2647907569
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.826624648
Short name T631
Test name
Test status
Simulation time 12337473757 ps
CPU time 12.24 seconds
Started May 16 01:26:52 PM PDT 24
Finished May 16 01:27:21 PM PDT 24
Peak memory 234936 kb
Host smart-70e6b5f8-d390-4c6c-ba00-ebf5a0e4c36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826624648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.826624648
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4017015782
Short name T878
Test name
Test status
Simulation time 72451284 ps
CPU time 2.2 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 216120 kb
Host smart-13b573a1-9804-4652-a188-fa98ac0f5702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017015782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4017015782
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.4265812362
Short name T619
Test name
Test status
Simulation time 13833624214 ps
CPU time 37.82 seconds
Started May 16 01:26:50 PM PDT 24
Finished May 16 01:27:43 PM PDT 24
Peak memory 248736 kb
Host smart-e5820ca0-4a65-48e4-9575-0b8274d83914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265812362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.4265812362
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2406600215
Short name T467
Test name
Test status
Simulation time 47256878 ps
CPU time 1.1 seconds
Started May 16 01:26:47 PM PDT 24
Finished May 16 01:27:02 PM PDT 24
Peak memory 216736 kb
Host smart-754e1dc1-2584-432c-9ebc-8d99c44c1528
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406600215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2406600215
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2907235296
Short name T638
Test name
Test status
Simulation time 1589374161 ps
CPU time 2.58 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 216876 kb
Host smart-f2e1efd9-6b1b-4aa4-82bc-06401b4df430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907235296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2907235296
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.828973233
Short name T930
Test name
Test status
Simulation time 4885890248 ps
CPU time 8.13 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:12 PM PDT 24
Peak memory 217988 kb
Host smart-41f83921-7aff-45e7-8f25-b92fd1787294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828973233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.828973233
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2628327293
Short name T394
Test name
Test status
Simulation time 586832947 ps
CPU time 3.06 seconds
Started May 16 01:26:56 PM PDT 24
Finished May 16 01:27:17 PM PDT 24
Peak memory 218740 kb
Host smart-4e8fe00f-f239-4eac-b8b1-545950d2768d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2628327293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2628327293
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1678110786
Short name T627
Test name
Test status
Simulation time 56402434 ps
CPU time 1.16 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:04 PM PDT 24
Peak memory 207128 kb
Host smart-4bd0fdbe-9a5a-425c-97b8-3e1d66bdfb3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678110786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1678110786
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4273254349
Short name T452
Test name
Test status
Simulation time 8809720891 ps
CPU time 10.89 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:15 PM PDT 24
Peak memory 216464 kb
Host smart-ef7033b6-3b28-4852-b5dc-349f2c0dc6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273254349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4273254349
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1180085039
Short name T422
Test name
Test status
Simulation time 895703342 ps
CPU time 5.52 seconds
Started May 16 01:26:50 PM PDT 24
Finished May 16 01:27:12 PM PDT 24
Peak memory 216316 kb
Host smart-f7f24b3e-b2db-4e3b-a159-74d9d135a74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180085039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1180085039
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1353458723
Short name T612
Test name
Test status
Simulation time 104056863 ps
CPU time 0.88 seconds
Started May 16 01:26:51 PM PDT 24
Finished May 16 01:27:08 PM PDT 24
Peak memory 206668 kb
Host smart-ca853ec4-0840-49d6-be99-f7ff03ecf726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353458723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1353458723
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3087713567
Short name T886
Test name
Test status
Simulation time 61541160 ps
CPU time 0.71 seconds
Started May 16 01:26:50 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 205720 kb
Host smart-322be3b6-45c3-4180-86d8-ac8aeecd0a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087713567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3087713567
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3291574530
Short name T3
Test name
Test status
Simulation time 741765034 ps
CPU time 11.87 seconds
Started May 16 01:26:59 PM PDT 24
Finished May 16 01:27:31 PM PDT 24
Peak memory 219028 kb
Host smart-e1a67313-5080-439f-856e-dd93ec230ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291574530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3291574530
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3481325440
Short name T59
Test name
Test status
Simulation time 15072806 ps
CPU time 0.8 seconds
Started May 16 01:26:57 PM PDT 24
Finished May 16 01:27:16 PM PDT 24
Peak memory 205392 kb
Host smart-61912009-bc5c-4e6d-983e-b5f20a16d55e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481325440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
481325440
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1498255409
Short name T700
Test name
Test status
Simulation time 156294196 ps
CPU time 2.62 seconds
Started May 16 01:26:54 PM PDT 24
Finished May 16 01:27:14 PM PDT 24
Peak memory 218408 kb
Host smart-85fb9d19-0730-4043-96a7-8981d64d83cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498255409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1498255409
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2264810690
Short name T525
Test name
Test status
Simulation time 15811248 ps
CPU time 0.76 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 206448 kb
Host smart-d3838df6-22db-44e3-a08c-a7bb0a22c5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264810690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2264810690
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3904301694
Short name T229
Test name
Test status
Simulation time 50746930280 ps
CPU time 88.04 seconds
Started May 16 01:26:53 PM PDT 24
Finished May 16 01:28:38 PM PDT 24
Peak memory 249280 kb
Host smart-c14c9850-4fda-434e-bc7a-8c7e0dbcfb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904301694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3904301694
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.4268222603
Short name T907
Test name
Test status
Simulation time 179866493 ps
CPU time 2.28 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:05 PM PDT 24
Peak memory 217368 kb
Host smart-7877a706-6c55-4db5-adab-69398466ccf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268222603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.4268222603
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4293329299
Short name T377
Test name
Test status
Simulation time 37839818173 ps
CPU time 148.96 seconds
Started May 16 01:26:47 PM PDT 24
Finished May 16 01:29:31 PM PDT 24
Peak memory 249800 kb
Host smart-b597a7a5-3b10-4824-add2-48b95c3696b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293329299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4293329299
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3431261176
Short name T809
Test name
Test status
Simulation time 622536884 ps
CPU time 11.31 seconds
Started May 16 01:26:53 PM PDT 24
Finished May 16 01:27:21 PM PDT 24
Peak memory 224520 kb
Host smart-a2bcd73a-dce1-4ce1-a5d2-3ef2c565a0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431261176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3431261176
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2207311028
Short name T575
Test name
Test status
Simulation time 178418495 ps
CPU time 4.47 seconds
Started May 16 01:26:47 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 217760 kb
Host smart-c38fa5e4-453d-40f9-9b58-c2303655a967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207311028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2207311028
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1909848625
Short name T6
Test name
Test status
Simulation time 3588633609 ps
CPU time 7.61 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:12 PM PDT 24
Peak memory 233876 kb
Host smart-9a41a0c7-8550-4ea4-9a91-f2a7458055b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909848625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1909848625
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1836022411
Short name T948
Test name
Test status
Simulation time 14851929 ps
CPU time 0.98 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 217888 kb
Host smart-871fb600-6246-4c83-b0b5-d24545178756
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836022411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1836022411
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.945010224
Short name T959
Test name
Test status
Simulation time 1041936477 ps
CPU time 5.21 seconds
Started May 16 01:26:55 PM PDT 24
Finished May 16 01:27:17 PM PDT 24
Peak memory 233712 kb
Host smart-d94bb57a-7ba9-4080-ba10-532c35570f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945010224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
945010224
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1369883351
Short name T839
Test name
Test status
Simulation time 616243790 ps
CPU time 4.56 seconds
Started May 16 01:26:47 PM PDT 24
Finished May 16 01:27:06 PM PDT 24
Peak memory 216928 kb
Host smart-207c66df-4c00-4501-85f1-96431ac7e19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369883351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1369883351
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1198321000
Short name T520
Test name
Test status
Simulation time 1599871673 ps
CPU time 6.84 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:10 PM PDT 24
Peak memory 222964 kb
Host smart-d19baa8a-b22a-4487-92d4-3484e11c43b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1198321000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1198321000
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.41486002
Short name T425
Test name
Test status
Simulation time 5542252210 ps
CPU time 57.4 seconds
Started May 16 01:26:47 PM PDT 24
Finished May 16 01:28:00 PM PDT 24
Peak memory 249276 kb
Host smart-bc1588a4-cca0-4803-8279-f5b2289f8cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41486002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_
all.41486002
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.395129280
Short name T367
Test name
Test status
Simulation time 4651485059 ps
CPU time 26.82 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:32 PM PDT 24
Peak memory 216568 kb
Host smart-eac26eae-17e1-4ebc-9a48-3c9b799df049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395129280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.395129280
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2652199122
Short name T458
Test name
Test status
Simulation time 2558384030 ps
CPU time 1.85 seconds
Started May 16 01:26:58 PM PDT 24
Finished May 16 01:27:18 PM PDT 24
Peak memory 207512 kb
Host smart-0a807771-c89d-4ff1-b69f-143ee9c309fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652199122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2652199122
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3308848236
Short name T413
Test name
Test status
Simulation time 20699401 ps
CPU time 0.76 seconds
Started May 16 01:26:52 PM PDT 24
Finished May 16 01:27:08 PM PDT 24
Peak memory 205864 kb
Host smart-dd7617ee-e391-4978-940f-693ecd0eba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308848236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3308848236
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2420834663
Short name T409
Test name
Test status
Simulation time 118418141 ps
CPU time 0.77 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:05 PM PDT 24
Peak memory 205844 kb
Host smart-c71bcaa8-ec4b-4c20-b6d3-37fee26587ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420834663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2420834663
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.187709334
Short name T825
Test name
Test status
Simulation time 2098600403 ps
CPU time 5.66 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:10 PM PDT 24
Peak memory 233856 kb
Host smart-c67fed19-caa5-44f1-8f95-c9f2e80f303b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187709334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.187709334
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1200650307
Short name T883
Test name
Test status
Simulation time 58501456 ps
CPU time 0.71 seconds
Started May 16 01:26:59 PM PDT 24
Finished May 16 01:27:19 PM PDT 24
Peak memory 205356 kb
Host smart-21f5c3cd-bd6e-4102-a538-dbc79cc069b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200650307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
200650307
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.271049571
Short name T474
Test name
Test status
Simulation time 124561991 ps
CPU time 2.75 seconds
Started May 16 01:26:45 PM PDT 24
Finished May 16 01:27:02 PM PDT 24
Peak memory 233260 kb
Host smart-d22661d7-1333-4850-8499-2f0973845b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271049571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.271049571
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1292887409
Short name T404
Test name
Test status
Simulation time 24020974 ps
CPU time 0.74 seconds
Started May 16 01:26:52 PM PDT 24
Finished May 16 01:27:08 PM PDT 24
Peak memory 205508 kb
Host smart-7e1c939e-e067-4302-93cb-3e42e447fcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292887409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1292887409
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3205679349
Short name T76
Test name
Test status
Simulation time 3010888735 ps
CPU time 20.48 seconds
Started May 16 01:26:58 PM PDT 24
Finished May 16 01:27:39 PM PDT 24
Peak memory 254252 kb
Host smart-08a788b8-f2ae-4e17-9f28-e388f5da7df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205679349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3205679349
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1172955398
Short name T234
Test name
Test status
Simulation time 4235903978 ps
CPU time 56.27 seconds
Started May 16 01:27:01 PM PDT 24
Finished May 16 01:28:19 PM PDT 24
Peak memory 250988 kb
Host smart-e1339e4f-d64b-4225-87c1-638014c3f7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172955398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1172955398
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3123651476
Short name T199
Test name
Test status
Simulation time 9855323126 ps
CPU time 153.09 seconds
Started May 16 01:27:02 PM PDT 24
Finished May 16 01:29:58 PM PDT 24
Peak memory 249428 kb
Host smart-8152cd8a-15e8-49f6-88f3-33b3ace5f83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123651476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3123651476
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2930562452
Short name T78
Test name
Test status
Simulation time 1035901322 ps
CPU time 5.9 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:09 PM PDT 24
Peak memory 233608 kb
Host smart-11f32afb-9b76-417c-bd8c-96f2249fd971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930562452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2930562452
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3088453975
Short name T757
Test name
Test status
Simulation time 9600356118 ps
CPU time 16.76 seconds
Started May 16 01:26:48 PM PDT 24
Finished May 16 01:27:20 PM PDT 24
Peak memory 219588 kb
Host smart-412e2354-9052-4a0a-80e0-a242aee8bd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088453975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3088453975
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2236897526
Short name T606
Test name
Test status
Simulation time 8493587313 ps
CPU time 69.51 seconds
Started May 16 01:26:47 PM PDT 24
Finished May 16 01:28:11 PM PDT 24
Peak memory 232824 kb
Host smart-859f3f15-938c-4a0f-b68a-1fc2d3e67170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236897526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2236897526
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3448097008
Short name T25
Test name
Test status
Simulation time 17866021 ps
CPU time 1.04 seconds
Started May 16 01:26:47 PM PDT 24
Finished May 16 01:27:04 PM PDT 24
Peak memory 216752 kb
Host smart-fa4ee26b-85a5-4cff-af0a-564f4e03d878
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448097008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3448097008
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1947823508
Short name T203
Test name
Test status
Simulation time 2492189392 ps
CPU time 5.04 seconds
Started May 16 01:26:45 PM PDT 24
Finished May 16 01:27:04 PM PDT 24
Peak memory 218768 kb
Host smart-c31adc9b-5515-4a00-8294-7332c756f9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947823508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1947823508
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1108373323
Short name T894
Test name
Test status
Simulation time 1833482301 ps
CPU time 4.72 seconds
Started May 16 01:26:58 PM PDT 24
Finished May 16 01:27:22 PM PDT 24
Peak memory 233648 kb
Host smart-29b6cb49-1210-48b2-a9b8-3b6bad56d939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108373323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1108373323
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.396064721
Short name T158
Test name
Test status
Simulation time 1125506843 ps
CPU time 8.05 seconds
Started May 16 01:26:57 PM PDT 24
Finished May 16 01:27:22 PM PDT 24
Peak memory 219912 kb
Host smart-a3710d83-b242-4a5f-91a6-35d388a6552c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=396064721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.396064721
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.627142814
Short name T831
Test name
Test status
Simulation time 3765799221 ps
CPU time 16.35 seconds
Started May 16 01:26:45 PM PDT 24
Finished May 16 01:27:15 PM PDT 24
Peak memory 216564 kb
Host smart-7391a065-a302-4c07-8ec5-27c84ff89653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627142814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.627142814
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2098488123
Short name T354
Test name
Test status
Simulation time 73837381845 ps
CPU time 16.96 seconds
Started May 16 01:26:49 PM PDT 24
Finished May 16 01:27:21 PM PDT 24
Peak memory 216448 kb
Host smart-63aea183-9f1c-48e0-8671-dc65aa8df4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098488123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2098488123
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3132248953
Short name T651
Test name
Test status
Simulation time 11321305 ps
CPU time 0.72 seconds
Started May 16 01:26:46 PM PDT 24
Finished May 16 01:27:01 PM PDT 24
Peak memory 205536 kb
Host smart-667f1d81-423f-4a24-b50f-afa304e15d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132248953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3132248953
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1169413415
Short name T906
Test name
Test status
Simulation time 190646704 ps
CPU time 0.87 seconds
Started May 16 01:26:52 PM PDT 24
Finished May 16 01:27:09 PM PDT 24
Peak memory 205824 kb
Host smart-2a0be783-cca9-4bfd-9573-c6b39b6e6ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169413415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1169413415
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1083344669
Short name T785
Test name
Test status
Simulation time 643473970 ps
CPU time 7.58 seconds
Started May 16 01:26:46 PM PDT 24
Finished May 16 01:27:08 PM PDT 24
Peak memory 230264 kb
Host smart-c77f9b6c-765a-480e-97ae-d5664ba191ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083344669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1083344669
Directory /workspace/9.spi_device_upload/latest
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