Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.62	93.89	84.31	96.94		87.50	95.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	91.62	93.89	84.31	96.94		87.50	95.45

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.62	93.89	84.31	96.94		87.50	95.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.60	98.35	94.20	98.61	89.36	97.23	95.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	96.74	100.00	87.80		100.00	95.92	100.00
u_csb_buf	100.00	100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_cmd_end	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_drop	97.92	100.00	91.67			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_p2s	85.98	100.00	71.43			72.50	100.00
u_passthrough	89.62	92.20	89.22		75.00	91.67	100.00
u_read_en_pipe_stg1	100.00	100.00				100.00
u_read_en_pipe_stg2	100.00	100.00				100.00
u_read_intercept_pipe_stg1	100.00	100.00				100.00
u_read_intercept_pipe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00
u_readcmd	89.30	93.62	90.32		87.50	84.15	90.91
u_reg	99.64	99.53	99.33	100.00		99.35	100.00
u_rst_spi_out_sync	100.00	100.00				100.00
u_s2p	89.38	100.00	78.57			78.95	100.00
u_scanmode_sync	100.00						100.00
u_spi_tpm	92.81	99.28	85.25		91.67	95.68	92.16
u_spid_addr_4b	86.34	97.59	77.78			95.00	75.00
u_spid_csb_sync	96.97	100.00	100.00			90.91
u_spid_dpram	95.45	100.00	81.82			100.00	100.00
u_spid_status	99.11	100.00	97.83			98.63	100.00
u_sys_csb_syncd	100.00	100.00				100.00
u_sys_sram_arbiter	89.65	100.00	76.47			96.43	85.71
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	71.44	81.97	59.19			63.33	81.25
u_tlul2sram_ingress	86.61	88.11	73.90			84.44	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_tpm_rst_out_sync	100.00	100.00				100.00
u_upload	90.79	98.60	71.95		100.00	94.12	89.29

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		229	215	93.89
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
ALWAYS	538	4	4	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	563	1	1	100.00
ALWAYS	568	0	0
ALWAYS	568	2	2	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
ALWAYS	582	0	0
ALWAYS	582	12	12	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
ALWAYS	809	3	3	100.00
ALWAYS	815	8	8	100.00
ALWAYS	853	9	9	100.00
ALWAYS	877	24	24	100.00
CONT_ASSIGN	945	1	1	100.00
CONT_ASSIGN	946	1	1	100.00
ALWAYS	1009	7	4	57.14
ALWAYS	1022	13	13	100.00
ALWAYS	1059	3	3	100.00
CONT_ASSIGN	1196	1	1	100.00
CONT_ASSIGN	1199	1	1	100.00
CONT_ASSIGN	1203	1	1	100.00
CONT_ASSIGN	1204	1	1	100.00
CONT_ASSIGN	1205	1	1	100.00
CONT_ASSIGN	1207	1	1	100.00
CONT_ASSIGN	1208	1	1	100.00
CONT_ASSIGN	1211	1	1	100.00
CONT_ASSIGN	1258	1	0	0.00
CONT_ASSIGN	1289	1	0	0.00
CONT_ASSIGN	1372	1	1	100.00
CONT_ASSIGN	1373	1	1	100.00
CONT_ASSIGN	1374	1	1	100.00
CONT_ASSIGN	1375	1	1	100.00
CONT_ASSIGN	1376	1	1	100.00
CONT_ASSIGN	1378	1	1	100.00
CONT_ASSIGN	1382	1	1	100.00
CONT_ASSIGN	1389	1	1	100.00
CONT_ASSIGN	1390	1	1	100.00
CONT_ASSIGN	1392	1	1	100.00
CONT_ASSIGN	1396	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00
CONT_ASSIGN	1405	1	1	100.00
CONT_ASSIGN	1408	1	1	100.00
CONT_ASSIGN	1411	1	1	100.00
CONT_ASSIGN	1418	1	1	100.00
CONT_ASSIGN	1419	1	1	100.00
CONT_ASSIGN	1458	1	1	100.00
CONT_ASSIGN	1561	1	0	0.00
CONT_ASSIGN	1569	1	1	100.00
CONT_ASSIGN	1570	1	1	100.00
CONT_ASSIGN	1571	1	1	100.00
CONT_ASSIGN	1572	1	1	100.00
CONT_ASSIGN	1573	1	1	100.00
CONT_ASSIGN	1576	1	1	100.00
CONT_ASSIGN	1583	1	1	100.00
CONT_ASSIGN	1590	1	1	100.00
CONT_ASSIGN	1590	1	1	100.00
CONT_ASSIGN	1590	1	1	100.00
CONT_ASSIGN	1590	1	1	100.00
CONT_ASSIGN	1590	1	1	100.00
CONT_ASSIGN	1593	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1595	1	1	100.00
CONT_ASSIGN	1596	1	1	100.00
CONT_ASSIGN	1597	1	1	100.00
CONT_ASSIGN	1598	1	1	100.00
CONT_ASSIGN	1600	1	1	100.00
CONT_ASSIGN	1604	1	1	100.00
CONT_ASSIGN	1606	1	1	100.00
CONT_ASSIGN	1607	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1616	1	1	100.00
CONT_ASSIGN	1617	1	1	100.00
CONT_ASSIGN	1626	1	1	100.00
CONT_ASSIGN	1627	1	1	100.00
CONT_ASSIGN	1628	1	1	100.00
CONT_ASSIGN	1629	1	1	100.00
CONT_ASSIGN	1692	1	1	100.00
CONT_ASSIGN	1694	1	1	100.00
ALWAYS	1699	4	4	100.00
ALWAYS	1708	0	0
ALWAYS	1708	9	9	100.00
CONT_ASSIGN	1725	1	1	100.00
CONT_ASSIGN	1725	1	1	100.00
CONT_ASSIGN	1725	1	1	100.00
CONT_ASSIGN	1725	1	1	100.00
CONT_ASSIGN	1725	1	1	100.00
CONT_ASSIGN	1726	1	1	100.00
CONT_ASSIGN	1726	1	1	100.00
CONT_ASSIGN	1726	1	0	0.00
CONT_ASSIGN	1726	1	0	0.00
CONT_ASSIGN	1726	1	0	0.00
CONT_ASSIGN	1727	1	1	100.00
CONT_ASSIGN	1727	1	1	100.00
CONT_ASSIGN	1727	1	0	0.00
CONT_ASSIGN	1727	1	0	0.00
CONT_ASSIGN	1727	1	1	100.00
CONT_ASSIGN	1728	1	1	100.00
CONT_ASSIGN	1728	1	1	100.00
CONT_ASSIGN	1728	1	0	0.00
CONT_ASSIGN	1728	1	0	0.00
CONT_ASSIGN	1728	1	0	0.00
CONT_ASSIGN	1730	1	1	100.00
CONT_ASSIGN	1730	1	1	100.00
CONT_ASSIGN	1730	1	1	100.00
CONT_ASSIGN	1730	1	1	100.00
CONT_ASSIGN	1730	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1773	1	1	100.00
CONT_ASSIGN	1775	1	1	100.00
CONT_ASSIGN	1776	1	1	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1778	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1781	1	1	100.00
CONT_ASSIGN	1782	1	1	100.00
CONT_ASSIGN	1783	1	1	100.00
CONT_ASSIGN	1839	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
173	1	1
308	1	1
371	1	1
372	1	1
375	1	1
376	1	1
378	1	1
393	1	1
526	1	1
533	1	1
535	1	1
538	1	1
539	1	1
540	1	1
541	1	1
			MISSING_ELSE
546	1	1
552	1	1
553	1	1
558	1	1
559	1	1
563	1	1
568	1	1
569	1	1
573	1	1
574	1	1
582	1	1
583	1	1
602	1	1
603	1	1
607	1	1
608	1	1
610	1	1
611	1	1
613	1	1
614	1	1
616	1	1
617	1	1
646	1	1
647	1	1
648	1	1
709	1	1
809	2	2
810	1	1
815	1	1
817	1	1
818	1	1
825	1	1
829	1	1
830	1	1
834	1	1
835	1	1
853	1	1
855	1	1
860	1	1
866	1	1
867	1	1
868	1	1
869	1	1
870	1	1
871	1	1
			MISSING_ELSE
877	1	1
878	1	1
879	1	1
880	1	1
882	1	1
884	1	1
886	1	1
888	1	1
892	1	1
894	1	1
895	1	1
896	1	1
899	1	1
901	1	1
902	1	1
903	1	1
908	1	1
910	1	1
911	1	1
912	1	1
916	1	1
918	1	1
919	1	1
920	1	1
945	1	1
946	1	1
1009	1	1
1010	0	1
1011	0	1
1012	0	1
1014	1	1
1015	1	1
1016	1	1
1022	1	1
1023	1	1
1025	1	1
1027	1	1
1028	1	1
1032	1	1
1034	1	1
1035	1	1
1039	1	1
1040	1	1
1041	1	1
1043	1	1
1044	1	1
1059	2	2
1060	1	1
1196	1	1
1199	1	1
1203	1	1
1204	1	1
1205	1	1
1207	1	1
1208	1	1
1211	1	1
1258	0	1
1289	0	1
1372	1	1
1373	1	1
1374	1	1
1375	1	1
1376	1	1
1378	1	1
1382	1	1
1389	1	1
1390	1	1
1392	1	1
1396	1	1
1399	1	1
1402	1	1
1405	1	1
1408	1	1
1411	1	1
1418	1	1
1419	1	1
1458	1	1
1561	0	1
1569	1	1
1570	1	1
1571	1	1
1572	1	1
1573	1	1
1576	1	1
1583	1	1
1590	5	5
1593	1	1
1594	1	1
1595	1	1
1596	1	1
1597	1	1
1598	1	1
1600	1	1
1604	1	1
1606	1	1
1607	1	1
1614	1	1
1616	1	1
1617	1	1
1626	1	1
1627	1	1
1628	1	1
1629	1	1
1692	1	1
1694	1	1
1699	1	1
1700	1	1
1701	1	1
1702	1	1
			MISSING_ELSE
1708	1	1
1709	1	1
1711	1	1
1714	1	1
1715	1	1
1716	1	1
1717	1	1
1719	1	1
1720	1	1
1725	5	5
1726	2	5
1727	3	5
1728	2	5
1730	5	5
1731	5	5
1732	5	5
1773	1	1
1775	1	1
1776	1	1
1777	1	1
1778	1	1
1779	1	1
1781	1	1
1782	1	1
1783	1	1
1839	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       701
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       726
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T8

 LINE       839
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       866
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       866
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       866
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       866
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       1025
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T8,T50,T51
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       1196
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       1207
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T10

 LINE       1208
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       1418
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       1419
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1583
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

 LINE       1701
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1701
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1701
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1773
 EXPRESSION (tpm_rst_in_n | rst_spi_in_n)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T8

 LINE       1839
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T52

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	59	54	91.53
Total Bits	458	444	96.94
Total Bits 0->1	229	222	96.94
Total Bits 1->0	229	222	96.94

Ports	59	54	91.53
Port Bits	458	444	96.94
Port Bits 0->1	229	222	96.94
Port Bits 1->0	229	222	96.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T53,T54	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T6	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T4,T52	Yes	T1,T4,T52	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T4,T52	Yes	T1,T4,T52	OUTPUT
cio_sck_i	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
cio_csb_i	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
cio_sd_o[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
cio_tpm_csb_i	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T2,*T3,*T5	Yes	T2,T3,T5	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T2,T3,T12	Yes	T2,T3,T5	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T8,T53,T27	Yes	T8,T53,T27	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T8,T53,T27	Yes	T8,T53,T27	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T8,T53,T27	Yes	T8,T53,T27	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T8,T53,T55	Yes	T8,T53,T55	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T8,T53,T27	Yes	T8,T53,T27	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T8,T53,T27	Yes	T8,T53,T27	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T8,T53,T27	Yes	T8,T53,T27	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T8,T53,T27	Yes	T8,T53,T27	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T56	Yes	T56	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T56	Yes	T56	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T56	Yes	T56	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T56	Yes	T56	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T56	Yes	T56	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T56	Yes	T56	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T56	Yes	T56	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T56	Yes	T56	INPUT
sck_monitor_o	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		32	28	87.50
IF	538	3	3	100.00
IF	809	2	2	100.00
CASE	825	4	4	100.00
IF	866	3	3	100.00
CASE	882	7	5	71.43
IF	1009	2	1	50.00
IF	1025	5	4	80.00
IF	1059	2	2	100.00
IF	1701	2	2	100.00
IF	1711	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	538	if ((!rst_ni))
-2-:	540	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	809	if ((!rst_spi_out_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	825	case (cmd_dp_sel)
-2-:	839	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T2,T3,T5
DpUpload	-	Covered	T2,T3,T8
default	1	Covered	T2,T3,T8
default	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	866	if (((!sck_csb) && ((spi_mode == FlashMode) || (spi_mode == PassThrough))))
-2-:	869	if (cfg_tpm_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T5
0	1	Covered	T2,T3,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	882	case (spi_mode)
-2-:	884	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T2,T3,T5
FlashMode PassThrough	DpReadStatus	Covered	T2,T3,T8
FlashMode PassThrough	DpReadJEDEC	Covered	T2,T8,T10
FlashMode PassThrough	DpUpload	Covered	T2,T3,T8
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	1009	if (cmd_read_pipeline_sel)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1025	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	1032	case (spi_mode)
-3-:	1039	if (intercept_en_out)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T8
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T2,T3,T12
0	PassThrough	0	Covered	T2,T3,T5
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1059	if ((!rst_spi_out_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	1701	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1711	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	21	95.45
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	21	95.45

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	423181611	423098462	0	0
CioSdoEnOKnown	423181611	423098462	0	0
CioSdoEnOffWhenInactive	423181611	423098462	0	0
FpvSecCmRegWeOnehotCheck_A	423181611	80	0	0
InterceptLevel_M	129467528	0	0	0
IntrReadbufFlipOKnown	423181611	423098462	0	0
IntrReadbufWatermarkOKnown	423181611	423098462	0	0
IntrTpmHeaderNotEmptyOKnown	423181611	423098462	0	0
IntrTpmRdfifoCmdEndOKnown	423181611	423098462	0	0
IntrTpmRdfifoDropOKnown	423181611	423098462	0	0
IntrUploadCmdfifoNotEmptyOKnown	423181611	423098462	0	0
IntrUploadPayloadNotEmptyOKnown	423181611	423098462	0	0
IntrUploadPayloadOverflowOKnown	423181611	423098462	0	0
PayloadStartIdxWidthMatch_A	926	926	0	0
SpiModeKnown_A	423181611	423098462	0	0
TpmEnableWhenTpmCsbIdle_M	423181611	344	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	423181611	1702736	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	423181611	156078	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	423181611	1985	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	423181611	1491	0	0
g_sram_connect[4].ReqAlwaysAccepted_A	423181611	188526	0	0
scanmodeKnown	423181611	423181611	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	80	0	0
T21	2625	0	0	0
T25	171549	0	0	0
T54	3552	10	0	0
T57	0	10	0	0
T58	0	10	0	0
T59	0	30	0	0
T60	0	20	0	0
T61	920	0	0	0
T62	637310	0	0	0
T63	148393	0	0	0
T64	45755	0	0	0
T65	895610	0	0	0
T66	604272	0	0	0
T67	939	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	129467528	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

IntrTpmRdfifoCmdEndOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

IntrTpmRdfifoDropOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	344	0	0
T2	178611	1	0	0
T3	117346	1	0	0
T4	923	0	0	0
T5	20698	0	0	0
T6	96714	0	0	0
T7	93764	0	0	0
T8	447173	2	0	0
T9	418352	1	0	0
T10	275880	1	0	0
T11	124822	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T68	0	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	1702736	0	0
T2	178611	4992	0	0
T3	117346	832	0	0
T4	923	0	0	0
T5	20698	832	0	0
T6	96714	832	0	0
T7	93764	832	0	0
T8	447173	7488	0	0
T9	418352	0	0	0
T10	275880	9152	0	0
T11	124822	832	0	0
T12	0	1664	0	0
T13	0	832	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	156078	0	0
T2	178611	1064	0	0
T3	117346	619	0	0
T4	923	0	0	0
T5	20698	0	0	0
T6	96714	0	0	0
T7	93764	0	0	0
T8	447173	937	0	0
T9	418352	0	0	0
T10	275880	423	0	0
T11	124822	0	0	0
T12	0	635	0	0
T13	0	64	0	0
T15	0	446	0	0
T16	0	835	0	0
T17	0	13	0	0
T23	0	425	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	1985	0	0
T2	178611	7	0	0
T3	117346	1	0	0
T4	923	0	0	0
T5	20698	0	0	0
T6	96714	0	0	0
T7	93764	0	0	0
T8	447173	11	0	0
T9	418352	0	0	0
T10	275880	22	0	0
T11	124822	0	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T24	0	14	0	0
T36	0	4	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	1491	0	0
T2	178611	6	0	0
T3	117346	0	0	0
T4	923	0	0	0
T5	20698	0	0	0
T6	96714	0	0	0
T7	93764	0	0	0
T8	447173	7	0	0
T9	418352	0	0	0
T10	275880	18	0	0
T11	124822	0	0	0
T13	0	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T22	0	21	0	0
T24	0	7	0	0
T36	0	4	0	0
T69	0	6	0	0

g_sram_connect[4].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	188526	0	0
T2	178611	1205	0	0
T3	117346	897	0	0
T4	923	0	0	0
T5	20698	0	0	0
T6	96714	0	0	0
T7	93764	0	0	0
T8	447173	1084	0	0
T9	418352	0	0	0
T10	275880	141	0	0
T11	124822	0	0	0
T12	0	803	0	0
T15	0	689	0	0
T16	0	1320	0	0
T17	0	10	0	0
T23	0	770	0	0
T24	0	1229	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423181611	0	0
T1	951	951	0	0
T2	178611	178611	0	0
T3	117346	117346	0	0
T4	923	923	0	0
T5	20698	20698	0	0
T6	96714	96714	0	0
T7	93764	93764	0	0
T8	447173	447173	0	0
T9	418352	418352	0	0
T10	275880	275880	0	0