Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
3854 |
0 |
0 |
T86 |
4496 |
2 |
0 |
0 |
T87 |
4049 |
21 |
0 |
0 |
T88 |
2977 |
93 |
0 |
0 |
T89 |
3659 |
3 |
0 |
0 |
T90 |
91714 |
3 |
0 |
0 |
T91 |
10400 |
202 |
0 |
0 |
T92 |
64637 |
4 |
0 |
0 |
T93 |
10338 |
1 |
0 |
0 |
T94 |
8345 |
3 |
0 |
0 |
T97 |
13534 |
143 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2334 |
0 |
0 |
T73 |
1821 |
1 |
0 |
0 |
T90 |
91714 |
66 |
0 |
0 |
T92 |
64637 |
41 |
0 |
0 |
T104 |
89806 |
86 |
0 |
0 |
T109 |
10797 |
9 |
0 |
0 |
T110 |
180393 |
452 |
0 |
0 |
T141 |
18300 |
64 |
0 |
0 |
T142 |
13852 |
62 |
0 |
0 |
T143 |
64010 |
48 |
0 |
0 |
T144 |
4345 |
3 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2233 |
0 |
0 |
T90 |
91714 |
83 |
0 |
0 |
T92 |
64637 |
67 |
0 |
0 |
T104 |
89806 |
33 |
0 |
0 |
T109 |
10797 |
16 |
0 |
0 |
T110 |
180393 |
433 |
0 |
0 |
T141 |
18300 |
90 |
0 |
0 |
T142 |
13852 |
71 |
0 |
0 |
T143 |
64010 |
36 |
0 |
0 |
T144 |
4345 |
4 |
0 |
0 |
T145 |
13809 |
50 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2607 |
0 |
0 |
T90 |
91714 |
107 |
0 |
0 |
T92 |
64637 |
57 |
0 |
0 |
T104 |
89806 |
127 |
0 |
0 |
T109 |
10797 |
28 |
0 |
0 |
T110 |
180393 |
395 |
0 |
0 |
T141 |
18300 |
49 |
0 |
0 |
T142 |
13852 |
44 |
0 |
0 |
T143 |
64010 |
72 |
0 |
0 |
T144 |
4345 |
10 |
0 |
0 |
T145 |
13809 |
34 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
12495 |
0 |
0 |
T90 |
91714 |
865 |
0 |
0 |
T92 |
64637 |
375 |
0 |
0 |
T104 |
89806 |
1337 |
0 |
0 |
T109 |
10797 |
150 |
0 |
0 |
T110 |
180393 |
431 |
0 |
0 |
T141 |
18300 |
59 |
0 |
0 |
T142 |
13852 |
35 |
0 |
0 |
T143 |
64010 |
383 |
0 |
0 |
T144 |
4345 |
154 |
0 |
0 |
T145 |
13809 |
42 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
11556 |
0 |
0 |
T90 |
91714 |
1192 |
0 |
0 |
T92 |
64637 |
756 |
0 |
0 |
T104 |
89806 |
1274 |
0 |
0 |
T109 |
10797 |
243 |
0 |
0 |
T110 |
180393 |
491 |
0 |
0 |
T141 |
18300 |
63 |
0 |
0 |
T142 |
13852 |
54 |
0 |
0 |
T143 |
64010 |
832 |
0 |
0 |
T144 |
4345 |
3 |
0 |
0 |
T145 |
13809 |
36 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
12635 |
0 |
0 |
T90 |
91714 |
821 |
0 |
0 |
T92 |
64637 |
736 |
0 |
0 |
T104 |
89806 |
891 |
0 |
0 |
T109 |
10797 |
246 |
0 |
0 |
T110 |
180393 |
406 |
0 |
0 |
T141 |
18300 |
70 |
0 |
0 |
T142 |
13852 |
51 |
0 |
0 |
T143 |
64010 |
802 |
0 |
0 |
T144 |
4345 |
114 |
0 |
0 |
T145 |
13809 |
76 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
12022 |
0 |
0 |
T90 |
91714 |
1286 |
0 |
0 |
T92 |
64637 |
695 |
0 |
0 |
T104 |
89806 |
1030 |
0 |
0 |
T109 |
10797 |
226 |
0 |
0 |
T110 |
180393 |
459 |
0 |
0 |
T141 |
18300 |
41 |
0 |
0 |
T142 |
13852 |
28 |
0 |
0 |
T143 |
64010 |
687 |
0 |
0 |
T144 |
4345 |
97 |
0 |
0 |
T145 |
13809 |
57 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
11774 |
0 |
0 |
T90 |
91714 |
1027 |
0 |
0 |
T92 |
64637 |
749 |
0 |
0 |
T104 |
89806 |
684 |
0 |
0 |
T109 |
10797 |
345 |
0 |
0 |
T110 |
180393 |
490 |
0 |
0 |
T141 |
18300 |
50 |
0 |
0 |
T142 |
13852 |
58 |
0 |
0 |
T143 |
64010 |
771 |
0 |
0 |
T144 |
4345 |
132 |
0 |
0 |
T145 |
13809 |
88 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
11639 |
0 |
0 |
T90 |
91714 |
927 |
0 |
0 |
T92 |
64637 |
886 |
0 |
0 |
T104 |
89806 |
1060 |
0 |
0 |
T109 |
10797 |
260 |
0 |
0 |
T110 |
180393 |
469 |
0 |
0 |
T141 |
18300 |
65 |
0 |
0 |
T142 |
13852 |
68 |
0 |
0 |
T143 |
64010 |
661 |
0 |
0 |
T144 |
4345 |
8 |
0 |
0 |
T145 |
13809 |
53 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
11079 |
0 |
0 |
T73 |
1821 |
2 |
0 |
0 |
T90 |
91714 |
1019 |
0 |
0 |
T92 |
64637 |
903 |
0 |
0 |
T104 |
89806 |
806 |
0 |
0 |
T109 |
10797 |
144 |
0 |
0 |
T110 |
180393 |
465 |
0 |
0 |
T141 |
18300 |
44 |
0 |
0 |
T142 |
13852 |
59 |
0 |
0 |
T143 |
64010 |
617 |
0 |
0 |
T144 |
4345 |
9 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
10836 |
0 |
0 |
T90 |
91714 |
1056 |
0 |
0 |
T92 |
64637 |
626 |
0 |
0 |
T104 |
89806 |
802 |
0 |
0 |
T109 |
10797 |
22 |
0 |
0 |
T110 |
180393 |
434 |
0 |
0 |
T141 |
18300 |
55 |
0 |
0 |
T142 |
13852 |
30 |
0 |
0 |
T143 |
64010 |
873 |
0 |
0 |
T144 |
4345 |
4 |
0 |
0 |
T145 |
13809 |
63 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6326 |
0 |
0 |
T90 |
91714 |
426 |
0 |
0 |
T92 |
64637 |
327 |
0 |
0 |
T104 |
89806 |
444 |
0 |
0 |
T109 |
10797 |
44 |
0 |
0 |
T110 |
180393 |
443 |
0 |
0 |
T141 |
18300 |
61 |
0 |
0 |
T142 |
13852 |
13 |
0 |
0 |
T143 |
64010 |
421 |
0 |
0 |
T144 |
4345 |
50 |
0 |
0 |
T145 |
13809 |
82 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6545 |
0 |
0 |
T73 |
1821 |
9 |
0 |
0 |
T90 |
91714 |
471 |
0 |
0 |
T92 |
64637 |
330 |
0 |
0 |
T104 |
89806 |
423 |
0 |
0 |
T109 |
10797 |
112 |
0 |
0 |
T110 |
180393 |
478 |
0 |
0 |
T141 |
18300 |
84 |
0 |
0 |
T142 |
13852 |
59 |
0 |
0 |
T143 |
64010 |
311 |
0 |
0 |
T144 |
4345 |
54 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
5480 |
0 |
0 |
T90 |
91714 |
390 |
0 |
0 |
T92 |
64637 |
208 |
0 |
0 |
T104 |
89806 |
354 |
0 |
0 |
T109 |
10797 |
58 |
0 |
0 |
T110 |
180393 |
459 |
0 |
0 |
T141 |
18300 |
82 |
0 |
0 |
T142 |
13852 |
19 |
0 |
0 |
T143 |
64010 |
213 |
0 |
0 |
T144 |
4345 |
2 |
0 |
0 |
T145 |
13809 |
39 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6072 |
0 |
0 |
T73 |
1821 |
1 |
0 |
0 |
T90 |
91714 |
528 |
0 |
0 |
T92 |
64637 |
389 |
0 |
0 |
T104 |
89806 |
434 |
0 |
0 |
T109 |
10797 |
99 |
0 |
0 |
T110 |
180393 |
434 |
0 |
0 |
T141 |
18300 |
56 |
0 |
0 |
T142 |
13852 |
41 |
0 |
0 |
T143 |
64010 |
326 |
0 |
0 |
T144 |
4345 |
24 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6314 |
0 |
0 |
T90 |
91714 |
310 |
0 |
0 |
T92 |
64637 |
266 |
0 |
0 |
T104 |
89806 |
457 |
0 |
0 |
T109 |
10797 |
113 |
0 |
0 |
T110 |
180393 |
441 |
0 |
0 |
T141 |
18300 |
51 |
0 |
0 |
T142 |
13852 |
14 |
0 |
0 |
T143 |
64010 |
386 |
0 |
0 |
T144 |
4345 |
36 |
0 |
0 |
T145 |
13809 |
4 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6381 |
0 |
0 |
T73 |
1821 |
1 |
0 |
0 |
T90 |
91714 |
576 |
0 |
0 |
T92 |
64637 |
353 |
0 |
0 |
T104 |
89806 |
554 |
0 |
0 |
T109 |
10797 |
39 |
0 |
0 |
T110 |
180393 |
441 |
0 |
0 |
T141 |
18300 |
77 |
0 |
0 |
T142 |
13852 |
54 |
0 |
0 |
T143 |
64010 |
231 |
0 |
0 |
T144 |
4345 |
46 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6122 |
0 |
0 |
T73 |
1821 |
6 |
0 |
0 |
T90 |
91714 |
618 |
0 |
0 |
T92 |
64637 |
196 |
0 |
0 |
T104 |
89806 |
519 |
0 |
0 |
T109 |
10797 |
170 |
0 |
0 |
T110 |
180393 |
506 |
0 |
0 |
T141 |
18300 |
72 |
0 |
0 |
T142 |
13852 |
39 |
0 |
0 |
T143 |
64010 |
192 |
0 |
0 |
T144 |
4345 |
9 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6236 |
0 |
0 |
T90 |
91714 |
391 |
0 |
0 |
T92 |
64637 |
319 |
0 |
0 |
T104 |
89806 |
615 |
0 |
0 |
T109 |
10797 |
69 |
0 |
0 |
T110 |
180393 |
446 |
0 |
0 |
T141 |
18300 |
47 |
0 |
0 |
T142 |
13852 |
59 |
0 |
0 |
T143 |
64010 |
236 |
0 |
0 |
T144 |
4345 |
49 |
0 |
0 |
T145 |
13809 |
82 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
5146 |
0 |
0 |
T90 |
91714 |
280 |
0 |
0 |
T92 |
64637 |
229 |
0 |
0 |
T104 |
89806 |
543 |
0 |
0 |
T109 |
10797 |
55 |
0 |
0 |
T110 |
180393 |
488 |
0 |
0 |
T141 |
18300 |
64 |
0 |
0 |
T142 |
13852 |
34 |
0 |
0 |
T143 |
64010 |
187 |
0 |
0 |
T144 |
4345 |
5 |
0 |
0 |
T145 |
13809 |
16 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6358 |
0 |
0 |
T90 |
91714 |
574 |
0 |
0 |
T92 |
64637 |
278 |
0 |
0 |
T104 |
89806 |
497 |
0 |
0 |
T109 |
10797 |
109 |
0 |
0 |
T110 |
180393 |
391 |
0 |
0 |
T141 |
18300 |
124 |
0 |
0 |
T142 |
13852 |
21 |
0 |
0 |
T143 |
64010 |
365 |
0 |
0 |
T144 |
4345 |
4 |
0 |
0 |
T145 |
13809 |
47 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
5837 |
0 |
0 |
T90 |
91714 |
429 |
0 |
0 |
T92 |
64637 |
264 |
0 |
0 |
T104 |
89806 |
423 |
0 |
0 |
T109 |
10797 |
58 |
0 |
0 |
T110 |
180393 |
435 |
0 |
0 |
T141 |
18300 |
57 |
0 |
0 |
T142 |
13852 |
61 |
0 |
0 |
T143 |
64010 |
219 |
0 |
0 |
T144 |
4345 |
2 |
0 |
0 |
T145 |
13809 |
56 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6237 |
0 |
0 |
T90 |
91714 |
638 |
0 |
0 |
T92 |
64637 |
301 |
0 |
0 |
T104 |
89806 |
416 |
0 |
0 |
T109 |
10797 |
89 |
0 |
0 |
T110 |
180393 |
403 |
0 |
0 |
T141 |
18300 |
35 |
0 |
0 |
T142 |
13852 |
57 |
0 |
0 |
T143 |
64010 |
336 |
0 |
0 |
T144 |
4345 |
49 |
0 |
0 |
T145 |
13809 |
31 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
5881 |
0 |
0 |
T73 |
1821 |
2 |
0 |
0 |
T90 |
91714 |
531 |
0 |
0 |
T92 |
64637 |
254 |
0 |
0 |
T104 |
89806 |
434 |
0 |
0 |
T109 |
10797 |
11 |
0 |
0 |
T110 |
180393 |
409 |
0 |
0 |
T141 |
18300 |
73 |
0 |
0 |
T142 |
13852 |
40 |
0 |
0 |
T143 |
64010 |
337 |
0 |
0 |
T144 |
4345 |
3 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6198 |
0 |
0 |
T73 |
1821 |
5 |
0 |
0 |
T90 |
91714 |
437 |
0 |
0 |
T92 |
64637 |
188 |
0 |
0 |
T104 |
89806 |
386 |
0 |
0 |
T109 |
10797 |
161 |
0 |
0 |
T110 |
180393 |
484 |
0 |
0 |
T141 |
18300 |
86 |
0 |
0 |
T142 |
13852 |
52 |
0 |
0 |
T143 |
64010 |
316 |
0 |
0 |
T144 |
4345 |
65 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
5893 |
0 |
0 |
T73 |
1821 |
4 |
0 |
0 |
T90 |
91714 |
453 |
0 |
0 |
T92 |
64637 |
242 |
0 |
0 |
T104 |
89806 |
409 |
0 |
0 |
T109 |
10797 |
111 |
0 |
0 |
T110 |
180393 |
448 |
0 |
0 |
T141 |
18300 |
30 |
0 |
0 |
T142 |
13852 |
26 |
0 |
0 |
T143 |
64010 |
315 |
0 |
0 |
T145 |
13809 |
53 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
5956 |
0 |
0 |
T73 |
1821 |
1 |
0 |
0 |
T90 |
91714 |
522 |
0 |
0 |
T92 |
64637 |
438 |
0 |
0 |
T104 |
89806 |
571 |
0 |
0 |
T109 |
10797 |
13 |
0 |
0 |
T110 |
180393 |
432 |
0 |
0 |
T141 |
18300 |
32 |
0 |
0 |
T142 |
13852 |
54 |
0 |
0 |
T143 |
64010 |
243 |
0 |
0 |
T144 |
4345 |
52 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6471 |
0 |
0 |
T90 |
91714 |
427 |
0 |
0 |
T92 |
64637 |
464 |
0 |
0 |
T104 |
89806 |
576 |
0 |
0 |
T109 |
10797 |
70 |
0 |
0 |
T110 |
180393 |
473 |
0 |
0 |
T141 |
18300 |
37 |
0 |
0 |
T142 |
13852 |
68 |
0 |
0 |
T143 |
64010 |
305 |
0 |
0 |
T144 |
4345 |
59 |
0 |
0 |
T145 |
13809 |
108 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6290 |
0 |
0 |
T73 |
1821 |
5 |
0 |
0 |
T90 |
91714 |
522 |
0 |
0 |
T92 |
64637 |
200 |
0 |
0 |
T104 |
89806 |
420 |
0 |
0 |
T109 |
10797 |
1 |
0 |
0 |
T110 |
180393 |
445 |
0 |
0 |
T141 |
18300 |
94 |
0 |
0 |
T142 |
13852 |
10 |
0 |
0 |
T143 |
64010 |
154 |
0 |
0 |
T144 |
4345 |
41 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
5693 |
0 |
0 |
T73 |
1821 |
9 |
0 |
0 |
T90 |
91714 |
519 |
0 |
0 |
T92 |
64637 |
189 |
0 |
0 |
T104 |
89806 |
218 |
0 |
0 |
T109 |
10797 |
139 |
0 |
0 |
T110 |
180393 |
453 |
0 |
0 |
T141 |
18300 |
43 |
0 |
0 |
T142 |
13852 |
71 |
0 |
0 |
T143 |
64010 |
376 |
0 |
0 |
T144 |
4345 |
48 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
5937 |
0 |
0 |
T73 |
1821 |
6 |
0 |
0 |
T90 |
91714 |
429 |
0 |
0 |
T92 |
64637 |
283 |
0 |
0 |
T104 |
89806 |
375 |
0 |
0 |
T109 |
10797 |
93 |
0 |
0 |
T110 |
180393 |
459 |
0 |
0 |
T141 |
18300 |
89 |
0 |
0 |
T142 |
13852 |
57 |
0 |
0 |
T143 |
64010 |
194 |
0 |
0 |
T144 |
4345 |
1 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6224 |
0 |
0 |
T90 |
91714 |
432 |
0 |
0 |
T92 |
64637 |
225 |
0 |
0 |
T104 |
89806 |
477 |
0 |
0 |
T109 |
10797 |
11 |
0 |
0 |
T110 |
180393 |
494 |
0 |
0 |
T141 |
18300 |
62 |
0 |
0 |
T142 |
13852 |
86 |
0 |
0 |
T143 |
64010 |
281 |
0 |
0 |
T144 |
4345 |
9 |
0 |
0 |
T145 |
13809 |
30 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6026 |
0 |
0 |
T90 |
91714 |
403 |
0 |
0 |
T92 |
64637 |
270 |
0 |
0 |
T104 |
89806 |
439 |
0 |
0 |
T109 |
10797 |
126 |
0 |
0 |
T110 |
180393 |
495 |
0 |
0 |
T141 |
18300 |
70 |
0 |
0 |
T142 |
13852 |
39 |
0 |
0 |
T143 |
64010 |
202 |
0 |
0 |
T144 |
4345 |
30 |
0 |
0 |
T145 |
13809 |
90 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
5805 |
0 |
0 |
T90 |
91714 |
517 |
0 |
0 |
T92 |
64637 |
160 |
0 |
0 |
T104 |
89806 |
615 |
0 |
0 |
T109 |
10797 |
82 |
0 |
0 |
T110 |
180393 |
412 |
0 |
0 |
T141 |
18300 |
32 |
0 |
0 |
T142 |
13852 |
39 |
0 |
0 |
T143 |
64010 |
374 |
0 |
0 |
T144 |
4345 |
56 |
0 |
0 |
T145 |
13809 |
33 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
6375 |
0 |
0 |
T90 |
91714 |
442 |
0 |
0 |
T92 |
64637 |
350 |
0 |
0 |
T104 |
89806 |
511 |
0 |
0 |
T109 |
10797 |
54 |
0 |
0 |
T110 |
180393 |
445 |
0 |
0 |
T141 |
18300 |
59 |
0 |
0 |
T142 |
13852 |
43 |
0 |
0 |
T143 |
64010 |
249 |
0 |
0 |
T144 |
4345 |
5 |
0 |
0 |
T145 |
13809 |
22 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2662 |
0 |
0 |
T90 |
91714 |
88 |
0 |
0 |
T92 |
64637 |
77 |
0 |
0 |
T104 |
89806 |
80 |
0 |
0 |
T109 |
10797 |
22 |
0 |
0 |
T110 |
180393 |
482 |
0 |
0 |
T141 |
18300 |
99 |
0 |
0 |
T142 |
13852 |
43 |
0 |
0 |
T143 |
64010 |
63 |
0 |
0 |
T144 |
4345 |
3 |
0 |
0 |
T145 |
13809 |
17 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2600 |
0 |
0 |
T90 |
91714 |
119 |
0 |
0 |
T92 |
64637 |
59 |
0 |
0 |
T104 |
89806 |
115 |
0 |
0 |
T109 |
10797 |
2 |
0 |
0 |
T110 |
180393 |
369 |
0 |
0 |
T141 |
18300 |
75 |
0 |
0 |
T142 |
13852 |
71 |
0 |
0 |
T143 |
64010 |
79 |
0 |
0 |
T144 |
4345 |
10 |
0 |
0 |
T145 |
13809 |
25 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2493 |
0 |
0 |
T73 |
1821 |
3 |
0 |
0 |
T90 |
91714 |
100 |
0 |
0 |
T92 |
64637 |
42 |
0 |
0 |
T104 |
89806 |
69 |
0 |
0 |
T109 |
10797 |
10 |
0 |
0 |
T110 |
180393 |
449 |
0 |
0 |
T141 |
18300 |
108 |
0 |
0 |
T142 |
13852 |
26 |
0 |
0 |
T143 |
64010 |
67 |
0 |
0 |
T144 |
4345 |
10 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2663 |
0 |
0 |
T73 |
1821 |
6 |
0 |
0 |
T90 |
91714 |
82 |
0 |
0 |
T92 |
64637 |
68 |
0 |
0 |
T104 |
89806 |
94 |
0 |
0 |
T109 |
10797 |
11 |
0 |
0 |
T110 |
180393 |
422 |
0 |
0 |
T141 |
18300 |
111 |
0 |
0 |
T142 |
13852 |
50 |
0 |
0 |
T143 |
64010 |
83 |
0 |
0 |
T144 |
4345 |
4 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
3484 |
0 |
0 |
T73 |
1821 |
4 |
0 |
0 |
T90 |
91714 |
160 |
0 |
0 |
T92 |
64637 |
147 |
0 |
0 |
T104 |
89806 |
120 |
0 |
0 |
T109 |
10797 |
22 |
0 |
0 |
T110 |
180393 |
443 |
0 |
0 |
T141 |
18300 |
49 |
0 |
0 |
T142 |
13852 |
49 |
0 |
0 |
T143 |
64010 |
120 |
0 |
0 |
T144 |
4345 |
10 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
4930 |
0 |
0 |
T8 |
447173 |
23 |
0 |
0 |
T9 |
418352 |
0 |
0 |
0 |
T10 |
275880 |
0 |
0 |
0 |
T11 |
124822 |
0 |
0 |
0 |
T12 |
335030 |
0 |
0 |
0 |
T13 |
9703 |
0 |
0 |
0 |
T33 |
110176 |
0 |
0 |
0 |
T35 |
374217 |
0 |
0 |
0 |
T68 |
958 |
0 |
0 |
0 |
T83 |
18800 |
0 |
0 |
0 |
T133 |
0 |
43 |
0 |
0 |
T146 |
0 |
13 |
0 |
0 |
T147 |
0 |
13 |
0 |
0 |
T148 |
0 |
22 |
0 |
0 |
T149 |
0 |
20 |
0 |
0 |
T150 |
0 |
35 |
0 |
0 |
T151 |
0 |
17 |
0 |
0 |
T152 |
0 |
11 |
0 |
0 |
T153 |
0 |
15 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2563 |
0 |
0 |
T90 |
91714 |
134 |
0 |
0 |
T92 |
64637 |
45 |
0 |
0 |
T104 |
89806 |
82 |
0 |
0 |
T109 |
10797 |
21 |
0 |
0 |
T110 |
180393 |
446 |
0 |
0 |
T141 |
18300 |
65 |
0 |
0 |
T142 |
13852 |
55 |
0 |
0 |
T143 |
64010 |
56 |
0 |
0 |
T144 |
4345 |
7 |
0 |
0 |
T145 |
13809 |
68 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2568 |
0 |
0 |
T90 |
91714 |
73 |
0 |
0 |
T92 |
64637 |
31 |
0 |
0 |
T104 |
89806 |
114 |
0 |
0 |
T109 |
10797 |
15 |
0 |
0 |
T110 |
180393 |
404 |
0 |
0 |
T141 |
18300 |
93 |
0 |
0 |
T142 |
13852 |
76 |
0 |
0 |
T143 |
64010 |
85 |
0 |
0 |
T144 |
4345 |
5 |
0 |
0 |
T145 |
13809 |
21 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2221 |
0 |
0 |
T90 |
91714 |
68 |
0 |
0 |
T92 |
64637 |
39 |
0 |
0 |
T104 |
89806 |
90 |
0 |
0 |
T109 |
10797 |
8 |
0 |
0 |
T110 |
180393 |
461 |
0 |
0 |
T141 |
18300 |
27 |
0 |
0 |
T142 |
13852 |
29 |
0 |
0 |
T143 |
64010 |
32 |
0 |
0 |
T144 |
4345 |
7 |
0 |
0 |
T145 |
13809 |
59 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2061 |
0 |
0 |
T73 |
1821 |
1 |
0 |
0 |
T90 |
91714 |
77 |
0 |
0 |
T92 |
64637 |
19 |
0 |
0 |
T104 |
89806 |
57 |
0 |
0 |
T109 |
10797 |
8 |
0 |
0 |
T110 |
180393 |
389 |
0 |
0 |
T141 |
18300 |
97 |
0 |
0 |
T142 |
13852 |
19 |
0 |
0 |
T143 |
64010 |
40 |
0 |
0 |
T144 |
4345 |
5 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2206 |
0 |
0 |
T90 |
91714 |
61 |
0 |
0 |
T92 |
64637 |
55 |
0 |
0 |
T104 |
89806 |
53 |
0 |
0 |
T109 |
10797 |
15 |
0 |
0 |
T110 |
180393 |
457 |
0 |
0 |
T141 |
18300 |
66 |
0 |
0 |
T142 |
13852 |
42 |
0 |
0 |
T143 |
64010 |
30 |
0 |
0 |
T145 |
13809 |
32 |
0 |
0 |
T154 |
22772 |
104 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2199 |
0 |
0 |
T73 |
1821 |
1 |
0 |
0 |
T90 |
91714 |
37 |
0 |
0 |
T92 |
64637 |
23 |
0 |
0 |
T104 |
89806 |
73 |
0 |
0 |
T109 |
10797 |
15 |
0 |
0 |
T110 |
180393 |
462 |
0 |
0 |
T141 |
18300 |
99 |
0 |
0 |
T142 |
13852 |
73 |
0 |
0 |
T143 |
64010 |
61 |
0 |
0 |
T144 |
4345 |
3 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
3141 |
0 |
0 |
T73 |
1821 |
7 |
0 |
0 |
T90 |
91714 |
156 |
0 |
0 |
T92 |
64637 |
63 |
0 |
0 |
T104 |
89806 |
113 |
0 |
0 |
T109 |
10797 |
44 |
0 |
0 |
T110 |
180393 |
485 |
0 |
0 |
T141 |
18300 |
41 |
0 |
0 |
T142 |
13852 |
21 |
0 |
0 |
T143 |
64010 |
94 |
0 |
0 |
T144 |
4345 |
5 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2123 |
0 |
0 |
T90 |
91714 |
62 |
0 |
0 |
T92 |
64637 |
40 |
0 |
0 |
T104 |
89806 |
79 |
0 |
0 |
T109 |
10797 |
9 |
0 |
0 |
T110 |
180393 |
442 |
0 |
0 |
T141 |
18300 |
86 |
0 |
0 |
T142 |
13852 |
30 |
0 |
0 |
T143 |
64010 |
41 |
0 |
0 |
T144 |
4345 |
2 |
0 |
0 |
T145 |
13809 |
25 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
3686 |
0 |
0 |
T73 |
1821 |
8 |
0 |
0 |
T90 |
91714 |
175 |
0 |
0 |
T92 |
64637 |
135 |
0 |
0 |
T104 |
89806 |
203 |
0 |
0 |
T109 |
10797 |
60 |
0 |
0 |
T110 |
180393 |
458 |
0 |
0 |
T141 |
18300 |
34 |
0 |
0 |
T142 |
13852 |
77 |
0 |
0 |
T143 |
64010 |
134 |
0 |
0 |
T144 |
4345 |
6 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2390 |
0 |
0 |
T90 |
91714 |
83 |
0 |
0 |
T92 |
64637 |
49 |
0 |
0 |
T104 |
89806 |
87 |
0 |
0 |
T109 |
10797 |
13 |
0 |
0 |
T110 |
180393 |
446 |
0 |
0 |
T141 |
18300 |
54 |
0 |
0 |
T142 |
13852 |
41 |
0 |
0 |
T143 |
64010 |
88 |
0 |
0 |
T144 |
4345 |
1 |
0 |
0 |
T145 |
13809 |
26 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2236 |
0 |
0 |
T90 |
91714 |
72 |
0 |
0 |
T92 |
64637 |
62 |
0 |
0 |
T104 |
89806 |
38 |
0 |
0 |
T109 |
10797 |
15 |
0 |
0 |
T110 |
180393 |
486 |
0 |
0 |
T141 |
18300 |
64 |
0 |
0 |
T142 |
13852 |
53 |
0 |
0 |
T143 |
64010 |
45 |
0 |
0 |
T144 |
4345 |
8 |
0 |
0 |
T145 |
13809 |
28 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2129 |
0 |
0 |
T73 |
1821 |
1 |
0 |
0 |
T90 |
91714 |
52 |
0 |
0 |
T92 |
64637 |
44 |
0 |
0 |
T104 |
89806 |
59 |
0 |
0 |
T109 |
10797 |
2 |
0 |
0 |
T110 |
180393 |
410 |
0 |
0 |
T141 |
18300 |
66 |
0 |
0 |
T142 |
13852 |
35 |
0 |
0 |
T143 |
64010 |
42 |
0 |
0 |
T144 |
4345 |
5 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2275 |
0 |
0 |
T73 |
1821 |
2 |
0 |
0 |
T90 |
91714 |
77 |
0 |
0 |
T92 |
64637 |
44 |
0 |
0 |
T104 |
89806 |
66 |
0 |
0 |
T109 |
10797 |
19 |
0 |
0 |
T110 |
180393 |
437 |
0 |
0 |
T141 |
18300 |
78 |
0 |
0 |
T142 |
13852 |
16 |
0 |
0 |
T143 |
64010 |
33 |
0 |
0 |
T144 |
4345 |
9 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2222 |
0 |
0 |
T73 |
1821 |
1 |
0 |
0 |
T90 |
91714 |
49 |
0 |
0 |
T92 |
64637 |
29 |
0 |
0 |
T104 |
89806 |
72 |
0 |
0 |
T109 |
10797 |
17 |
0 |
0 |
T110 |
180393 |
418 |
0 |
0 |
T141 |
18300 |
89 |
0 |
0 |
T142 |
13852 |
38 |
0 |
0 |
T143 |
64010 |
46 |
0 |
0 |
T144 |
4345 |
4 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2214 |
0 |
0 |
T90 |
91714 |
78 |
0 |
0 |
T92 |
64637 |
66 |
0 |
0 |
T104 |
89806 |
28 |
0 |
0 |
T109 |
10797 |
16 |
0 |
0 |
T110 |
180393 |
451 |
0 |
0 |
T141 |
18300 |
92 |
0 |
0 |
T142 |
13852 |
52 |
0 |
0 |
T143 |
64010 |
46 |
0 |
0 |
T144 |
4345 |
4 |
0 |
0 |
T145 |
13809 |
11 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
425541073 |
2213 |
0 |
0 |
T90 |
91714 |
43 |
0 |
0 |
T92 |
64637 |
36 |
0 |
0 |
T104 |
89806 |
73 |
0 |
0 |
T109 |
10797 |
9 |
0 |
0 |
T110 |
180393 |
462 |
0 |
0 |
T141 |
18300 |
86 |
0 |
0 |
T142 |
13852 |
17 |
0 |
0 |
T143 |
64010 |
45 |
0 |
0 |
T145 |
13809 |
63 |
0 |
0 |
T154 |
22772 |
112 |
0 |
0 |