Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3918743	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4030401

1

T1

36

T2

58

T3

4857

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4631857	1			T1	1		T2	587		T3	7847
values[0x0]	1659334	1			T1	20		T2	25		T3	448
values[0x1]	1657953	1			T1	23		T2	28		T3	446

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2773155	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5175989

1

T1

40

T2

251

T3

5619

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29168	1			T3	14		T4	3		T7	2
valid_sources[0x01]	29258	1			T1	1		T3	60		T4	2
valid_sources[0x02]	31134	1			T2	4		T3	24		T4	2
valid_sources[0x03]	31551	1			T2	9		T3	47		T4	3
valid_sources[0x04]	28466	1			T2	4		T3	23		T4	2
valid_sources[0x05]	31018	1			T2	5		T3	19		T4	7
valid_sources[0x06]	28575	1			T2	2		T3	35		T4	2
valid_sources[0x07]	29896	1			T2	4		T3	105		T4	3
valid_sources[0x08]	30227	1			T3	23		T4	7		T7	2
valid_sources[0x09]	28701	1			T1	1		T2	1		T3	31
valid_sources[0x0a]	29130	1			T2	1		T3	67		T4	2
valid_sources[0x0b]	31279	1			T3	29		T4	2		T7	7
valid_sources[0x0c]	29237	1			T2	5		T3	50		T4	4
valid_sources[0x0d]	30384	1			T2	1		T3	55		T4	3
valid_sources[0x0e]	33616	1			T1	2		T2	3		T3	90
valid_sources[0x0f]	28881	1			T3	15		T4	1		T7	3
valid_sources[0x10]	29964	1			T3	14		T4	3		T7	2
valid_sources[0x11]	32034	1			T2	2		T3	14		T4	7
valid_sources[0x12]	29386	1			T2	1		T3	16		T4	3
valid_sources[0x13]	29747	1			T2	3		T3	16		T4	1
valid_sources[0x14]	28297	1			T2	4		T3	10		T4	2
valid_sources[0x15]	29605	1			T2	1		T3	9		T4	1
valid_sources[0x16]	31050	1			T2	6		T3	14		T4	3
valid_sources[0x17]	32454	1			T2	1		T3	81		T4	7
valid_sources[0x18]	32951	1			T3	20		T4	3		T7	3
valid_sources[0x19]	33745	1			T3	26		T4	8		T7	4
valid_sources[0x1a]	31980	1			T3	95		T4	1		T7	11
valid_sources[0x1b]	29384	1			T2	3		T3	50		T4	2
valid_sources[0x1c]	32670	1			T3	22		T4	5		T7	3
valid_sources[0x1d]	31622	1			T2	1		T3	37		T4	5
valid_sources[0x1e]	31499	1			T2	3		T3	23		T4	3
valid_sources[0x1f]	29241	1			T2	6		T4	7		T8	10
valid_sources[0x20]	29004	1			T2	6		T3	50		T4	2
valid_sources[0x21]	28485	1			T1	1		T3	1		T4	6
valid_sources[0x22]	29731	1			T2	2		T3	34		T4	2
valid_sources[0x23]	32939	1			T1	2		T2	5		T3	39
valid_sources[0x24]	30563	1			T2	1		T3	43		T4	3
valid_sources[0x25]	30952	1			T3	16		T4	3		T7	5
valid_sources[0x26]	30008	1			T2	1		T3	13		T4	2
valid_sources[0x27]	29573	1			T2	2		T3	30		T4	6
valid_sources[0x28]	30391	1			T1	2		T2	4		T3	93
valid_sources[0x29]	29688	1			T2	2		T3	11		T4	8
valid_sources[0x2a]	35117	1			T2	1		T3	47		T4	2
valid_sources[0x2b]	37605	1			T2	5		T3	9		T4	5
valid_sources[0x2c]	31911	1			T2	5		T3	15		T4	4
valid_sources[0x2d]	29365	1			T3	12		T4	2		T7	3
valid_sources[0x2e]	29806	1			T2	2		T3	30		T4	4
valid_sources[0x2f]	28553	1			T2	8		T3	101		T4	3
valid_sources[0x30]	39357	1			T3	51		T4	3		T7	2
valid_sources[0x31]	27983	1			T2	6		T3	26		T4	3
valid_sources[0x32]	28064	1			T2	3		T3	20		T4	7
valid_sources[0x33]	37216	1			T2	1		T3	63		T4	8
valid_sources[0x34]	28909	1			T2	2		T3	18		T4	5
valid_sources[0x35]	30237	1			T1	2		T2	8		T3	25
valid_sources[0x36]	34133	1			T2	1		T3	16		T4	1
valid_sources[0x37]	30218	1			T2	6		T3	38		T4	4
valid_sources[0x38]	31937	1			T2	1		T3	49		T4	6
valid_sources[0x39]	31398	1			T2	3		T3	60		T4	3
valid_sources[0x3a]	28378	1			T2	5		T3	23		T4	1
valid_sources[0x3b]	31329	1			T2	4		T3	51		T4	6
valid_sources[0x3c]	31071	1			T3	15		T4	2		T7	1
valid_sources[0x3d]	29996	1			T2	1		T3	35		T4	2
valid_sources[0x3e]	31853	1			T2	2		T3	9		T4	3
valid_sources[0x3f]	34645	1			T1	1		T2	2		T3	21
valid_sources[0x40]	29648	1			T2	3		T3	57		T4	3
valid_sources[0x41]	30135	1			T2	4		T3	54		T4	4
valid_sources[0x42]	29715	1			T2	1		T3	16		T4	3
valid_sources[0x43]	29505	1			T1	1		T2	4		T3	13
valid_sources[0x44]	30244	1			T1	1		T2	2		T3	17
valid_sources[0x45]	31234	1			T2	5		T3	32		T4	2
valid_sources[0x46]	33672	1			T1	3		T2	2		T3	32
valid_sources[0x47]	30431	1			T3	33		T4	7		T7	10
valid_sources[0x48]	28123	1			T2	4		T3	17		T4	2
valid_sources[0x49]	32588	1			T3	49		T4	2		T8	3
valid_sources[0x4a]	31483	1			T2	5		T3	75		T4	3
valid_sources[0x4b]	32260	1			T2	2		T3	33		T4	2
valid_sources[0x4c]	29985	1			T2	1		T3	28		T4	3
valid_sources[0x4d]	33537	1			T2	4		T3	3		T4	8
valid_sources[0x4e]	37474	1			T3	21		T4	3		T7	6
valid_sources[0x4f]	32494	1			T2	3		T3	69		T4	1
valid_sources[0x50]	29457	1			T2	1		T3	14		T4	4
valid_sources[0x51]	29307	1			T1	1		T2	2		T3	36
valid_sources[0x52]	30788	1			T2	3		T3	30		T4	3
valid_sources[0x53]	29608	1			T1	1		T2	4		T3	12
valid_sources[0x54]	30792	1			T2	4		T3	37		T4	1
valid_sources[0x55]	31014	1			T1	3		T2	1		T3	12
valid_sources[0x56]	34405	1			T3	12		T4	4		T7	1
valid_sources[0x57]	28495	1			T2	2		T3	37		T4	5
valid_sources[0x58]	35627	1			T2	3		T3	7		T4	1
valid_sources[0x59]	28981	1			T2	2		T3	8		T4	5
valid_sources[0x5a]	28748	1			T2	3		T3	74		T4	7
valid_sources[0x5b]	29104	1			T3	26		T4	2		T7	7
valid_sources[0x5c]	30863	1			T2	3		T3	56		T4	2
valid_sources[0x5d]	32211	1			T2	2		T3	27		T4	3
valid_sources[0x5e]	31999	1			T3	7		T4	4		T7	4
valid_sources[0x5f]	28446	1			T2	5		T3	28		T4	4
valid_sources[0x60]	30798	1			T2	7		T3	34		T4	5
valid_sources[0x61]	29149	1			T2	3		T3	62		T4	4
valid_sources[0x62]	30217	1			T2	5		T3	44		T4	6
valid_sources[0x63]	28929	1			T2	2		T3	59		T4	3
valid_sources[0x64]	28098	1			T2	2		T3	16		T4	8
valid_sources[0x65]	29892	1			T2	8		T3	12		T4	1
valid_sources[0x66]	29523	1			T2	3		T3	5		T4	4
valid_sources[0x67]	32633	1			T2	2		T3	57		T4	3
valid_sources[0x68]	29685	1			T2	1		T3	73		T4	3
valid_sources[0x69]	28629	1			T2	5		T3	33		T4	2
valid_sources[0x6a]	28802	1			T2	2		T3	43		T4	1
valid_sources[0x6b]	28449	1			T2	4		T3	37		T4	6
valid_sources[0x6c]	34056	1			T3	17		T4	3		T7	12
valid_sources[0x6d]	29512	1			T2	1		T3	80		T4	1
valid_sources[0x6e]	30260	1			T3	14		T4	5		T7	2
valid_sources[0x6f]	31957	1			T2	7		T3	17		T4	4
valid_sources[0x70]	36290	1			T2	4		T3	19		T4	5
valid_sources[0x71]	28971	1			T2	2		T3	65		T4	3
valid_sources[0x72]	30328	1			T2	1		T3	17		T4	2
valid_sources[0x73]	28095	1			T1	1		T2	7		T3	34
valid_sources[0x74]	32137	1			T2	4		T3	30		T4	1
valid_sources[0x75]	31570	1			T3	36		T4	4		T7	5
valid_sources[0x76]	28528	1			T2	6		T3	3		T4	4
valid_sources[0x77]	30807	1			T3	37		T4	4		T7	4
valid_sources[0x78]	29369	1			T1	1		T2	2		T3	24
valid_sources[0x79]	31811	1			T2	2		T3	16		T4	4
valid_sources[0x7a]	31114	1			T2	3		T3	52		T4	3
valid_sources[0x7b]	31083	1			T2	3		T3	12		T4	4
valid_sources[0x7c]	28862	1			T2	5		T3	38		T4	2
valid_sources[0x7d]	31647	1			T2	2		T3	59		T4	4
valid_sources[0x7e]	29766	1			T2	3		T3	36		T4	4
valid_sources[0x7f]	29438	1			T2	2		T3	56		T4	3
valid_sources[0x80]	30901	1			T2	3		T3	21		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1061015

1

T1

1

T2

23

T3

3968

values[0x0]

all_enables

biggest_size

1497151

1

T1

18

T2

18

T3

448

values[0x1]

all_enables

biggest_size

1472235

1

T1

17

T2

17

T3

441