Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3937045

1

T1

8

T2

582

T3

3884

full_word

4029355

1

T1

36

T2

58

T3

4857

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7966020	1			T1	44		T2	640		T3	8741
auto[TlIntgErrCmd]	119	1			T92	9		T95	5		T96	7
auto[TlIntgErrData]	127	1			T92	15		T95	10		T96	7
auto[TlIntgErrBoth]	134	1			T92	6		T95	5		T96	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4633130

1

T1

1

T2

587

T3

7847

auto[1]

3333270

1

T1

43

T2

53

T3

894

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3571918	1			T2	564		T3	3879		T4	3
auto[TlIntgErrNone]	partial	auto[1]	364781	1			T1	8		T2	18		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	1061050	1			T1	1		T2	23		T3	3968
auto[TlIntgErrNone]	full_word	auto[1]	2968271	1			T1	35		T2	35		T3	889
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T92	2		T95	3		T96	3
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T92	5		T95	2		T96	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T92	1		T96	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T92	1		T265	1		T266	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T92	6		T95	5		T96	3
auto[TlIntgErrData]	partial	auto[1]	63	1			T92	6		T95	4		T96	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T92	1		T95	1		T267	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T92	2		T96	1		T150	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T92	1		T95	1		T96	3
auto[TlIntgErrBoth]	partial	auto[1]	74	1			T92	5		T95	3		T96	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T111	1		T268	1		T263	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T95	1		T268	1		T264	2