Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	429973989	2411032	0	0
DepthKnown_A	429973989	429845697	0	0
RvalidKnown_A	429973989	429845697	0	0
WreadyKnown_A	429973989	429845697	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	2411032	0	0
T3	201097	832	0	0
T4	658440	832	0	0
T5	6529	1663	0	0
T6	173930	832	0	0
T7	5321	1663	0	0
T8	98111	0	0	0
T9	12289	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	394207	0	0	0
T13	0	2365	0	0
T14	0	24949	0	0
T15	0	832	0	0
T16	0	9981	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	429973989	2624140	0	0
DepthKnown_A	429973989	429845697	0	0
RvalidKnown_A	429973989	429845697	0	0
WreadyKnown_A	429973989	429845697	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	2624140	0	0
T3	201097	832	0	0
T4	658440	832	0	0
T5	6529	832	0	0
T6	173930	832	0	0
T7	5321	832	0	0
T8	98111	0	0	0
T9	12289	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	394207	0	0	0
T13	0	1600	0	0
T14	0	15808	0	0
T15	0	832	0	0
T16	0	7488	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	429973989	157020	0	0
DepthKnown_A	429973989	429845697	0	0
RvalidKnown_A	429973989	429845697	0	0
WreadyKnown_A	429973989	429845697	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	157020	0	0
T2	9648	18	0	0
T3	201097	0	0	0
T4	658440	0	0	0
T5	6529	0	0	0
T6	173930	0	0	0
T7	5321	0	0	0
T8	98111	148	0	0
T9	12289	0	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	0	713	0	0
T14	0	1849	0	0
T16	0	328	0	0
T22	0	100	0	0
T26	0	1488	0	0
T27	0	821	0	0
T39	0	128	0	0
T41	0	410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	429973989	344746	0	0
DepthKnown_A	429973989	429845697	0	0
RvalidKnown_A	429973989	429845697	0	0
WreadyKnown_A	429973989	429845697	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	344746	0	0
T2	9648	18	0	0
T3	201097	0	0	0
T4	658440	0	0	0
T5	6529	0	0	0
T6	173930	0	0	0
T7	5321	0	0	0
T8	98111	148	0	0
T9	12289	0	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	0	713	0	0
T14	0	1849	0	0
T16	0	328	0	0
T22	0	294	0	0
T26	0	1488	0	0
T27	0	821	0	0
T39	0	567	0	0
T41	0	410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	429973989	6635252	0	0
DepthKnown_A	429973989	429845697	0	0
RvalidKnown_A	429973989	429845697	0	0
WreadyKnown_A	429973989	429845697	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	6635252	0	0
T1	4167	44	0	0
T2	9648	622	0	0
T3	201097	7911	0	0
T4	658440	60	0	0
T5	6529	58	0	0
T6	173930	7843	0	0
T7	5321	102	0	0
T8	98111	1720	0	0
T9	12289	236	0	0
T10	1639	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	429973989	13743514	0	0
DepthKnown_A	429973989	429845697	0	0
RvalidKnown_A	429973989	429845697	0	0
WreadyKnown_A	429973989	429845697	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	13743514	0	0
T1	4167	44	0	0
T2	9648	622	0	0
T3	201097	7909	0	0
T4	658440	60	0	0
T5	6529	57	0	0
T6	173930	7843	0	0
T7	5321	102	0	0
T8	98111	1707	0	0
T9	12289	235	0	0
T10	1639	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429973989	429845697	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0